WO2014142039A1 - 論理演算素子 - Google Patents
論理演算素子 Download PDFInfo
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- WO2014142039A1 WO2014142039A1 PCT/JP2014/056079 JP2014056079W WO2014142039A1 WO 2014142039 A1 WO2014142039 A1 WO 2014142039A1 JP 2014056079 W JP2014056079 W JP 2014056079W WO 2014142039 A1 WO2014142039 A1 WO 2014142039A1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7613—Single electron transistors; Coulomb blockade devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/127—Quantum box structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
Definitions
- the present invention relates to a logical operation element having three or more gates.
- the inventors of the present invention have focused on gold nanoparticles as coulomb islands in single-electron devices in order to establish single-electron transistor manufacturing technology, and used STM (Scanning Tunneling Microscope) to make gold nanoparticles with a particle size of 1.8 nm. It has been clarified that the particles function as Coulomb islands at room temperature.
- STM Scnning Tunneling Microscope
- a technique for producing a nanogap electrode having a gap length of 5 nm at a high yield at a time using electroless plating has been established.
- the operation of a single electron transistor in which gold nanoparticles are introduced between nanogap electrodes by a chemical adsorption method has been reported (Non-Patent Documents 1 to 6).
- an object of the present invention is to provide a logical operation element capable of realizing a logical operation of three or more inputs with one unique device.
- One electrode and the other electrode provided to have a nanogap, Metal nanoparticles disposed insulatively between the one electrode and the other electrode; A plurality of gate electrodes for adjusting the charge of the metal nanoparticles; With A logic operation element, wherein a current flowing between the one electrode and the other electrode is controlled according to a voltage applied to three or more gate electrodes among the plurality of gate electrodes.
- the one electrode, the other electrode, and the two side gate electrodes are provided on the first insulating layer, A second insulating layer is provided on the first insulating layer so as to embed the one electrode, the other electrode, the two side gate electrodes, and the metal nanoparticles;
- the three or more gate electrodes include one side gate electrode, one bottom gate electrode, and one top gate electrode.
- the surface where the bottom gate electrode exists, the surface where the side gate electrode exists, and the surface where the top gate electrode exists are separated in the vertical direction,
- one electrode and the other electrode are provided so as to have a nanogap
- the metal nanoparticles are disposed between the electrodes
- the plurality of gate electrodes change the charge of the metal nanoparticles. Therefore, a current flowing between one electrode and the other electrode can be controlled in accordance with a voltage applied to three or more gate electrodes among the plurality of gate electrodes.
- three or more gate electrodes are composed of two side gates and one top gate, or when composed of one side gate, one top gate, and one bottom gate.
- the charge of the metal nanoparticles as Coulomb islands can be changed according to the voltage applied to the gate electrode, and various logical operations such as XOR and XNOR can be performed with one element.
- FIG. 2 is a cross-sectional view of a logical operation element different from FIG. 1. It is a figure which shows typically the process of installing the single electron island by the chemical bond which used the dithiol molecule, for example with respect to the electrode which has nanogap length. It is the figure which showed the truth table in 3 inputs, and also showed how to set the gate voltage for performing each logic operation. It is a figure which shows typically the waveform of the drain current which flows according to each gate voltage in a certain drain voltage.
- FIG. 1 shows typically the differential conductance when the drain voltage Vd and each gate voltage Vg1 , Vg2 , Vtop-gate are set to each value.
- the structure of the logic operation element which concerns on embodiment of this invention is shown, (A) is sectional drawing, (B) is a top view. It is the figure which showed the truth table in 4 inputs, and also showed how to set the gate voltage for performing each logic operation.
- 3 is a diagram showing an SEM image of the logical operation element fabricated in Example 1.
- FIG. 1 shows differential conductance characteristics when the side gate voltage and drain voltage are changed
- E shows differential conductance characteristics when the second side gate voltage and drain voltage are changed
- F shows top gate voltage and drain. It is a figure which shows the differential conductance characteristic at the time of changing a voltage.
- FIG. 3 is a diagram illustrating characteristics of a logical operation element manufactured in Example 1. It is a figure which shows the drain current dependence with respect to a drain voltage.
- (A), (B), and (C) are the Coulomb oscillation characteristics with respect to the gate voltages V g1 , V g2 , and V top-gate , respectively, and (D), (E), and (F) are with respect to the respective gate voltages. It is a figure which shows the Coulomb diamond characteristic.
- (A), (B), and (C) are diagrams showing results of repeated measurement of Coulomb oscillation characteristics with respect to gate voltages V g1 , V g2 , and V top-gate , respectively.
- 6 is a diagram illustrating characteristics of a logical operation element manufactured in Example 2.
- FIG. (A) is a figure which shows the operation result of the logic operation element in frequency 1Hz
- (B) is a figure which shows the operation result of the logic operation element in frequency 10Hz.
- Substrate 2 First insulating layer 3A, 3B, 4A, 4B: Metal layer 5A: Nanogap electrode (one electrode) 5B: Nanogap electrode (the other electrode) 5C, 5D: Gate electrode (side gate electrode) 6, 6A, 6B: Self-assembled monolayer 7: Metal nanoparticles 7A: Metal nanoparticles protected with alkanethiol 71: Insulating film 72: Metal nanoparticles with insulating film 8: Second insulating layer 9: Self Organized monomolecular mixed film (SAM mixed film) 9A: Alkanethiol 10: Logical operation element 11, 11B: Gate electrode (top gate electrode) 11A: Gate electrode (bottom gate electrode)
- SAM mixed film Self Organized monomolecular mixed film
- FIG. 1A and 1B show a configuration of a logical operation element according to an embodiment of the present invention.
- FIG. 1A is a cross-sectional view
- FIG. 1B is a plan view.
- the logic operation element 10 according to the embodiment of the present invention is insulated and arranged between one electrode 5A and the other electrode 5B arranged so as to have a nanogap, and one electrode 5A and the other electrode 5B.
- the metal nanoparticles 7 arranged on the side, side gate electrodes 5C and 5D arranged in a direction crossing the arrangement direction of the one electrode 5A and the other electrode 5B, the first insulating layer 2, and the one electrode 5A.
- the second insulating layer 8 provided to embed the self-assembled monolayer 6 and the metal nanoparticles 7 on the other electrode 5B and the third gate electrodes 5C and 5D, and the second insulating layer 8
- the top gate electrode 11 is disposed and disposed directly above the metal nanoparticles 7. , Comprising a.
- the nanogap length is a dimension of several nm, for example, 0.5 nm to 12 nm.
- a self-assembled monomolecular mixed film as an insulating film formed by a reaction between a self-assembled monomolecule (SAM) and an organic molecule is adsorbed.
- SAM self-assembled monomolecule
- a gate electrode is formed in a direction that intersects the arrangement direction of one electrode 5A and the other electrode 5B. You may call it.) 5C and 5D are provided.
- the substrate 1 various semiconductor substrates such as a Si substrate can be used.
- the first insulating layer 2 is formed of SiO 2 , Si 3 N 4 , Al 2 O 3 or the like.
- One electrode 5A and the other electrode 5B are formed of Au, Al, Ag, Cu, Ni, or the like.
- One electrode 5A and the other electrode 5B may be formed by sequentially laminating an adhesion layer and a metal layer.
- the adhesion layer is formed of Ti, Cr, Ni or the like
- the metal layer is formed of another or the same metal such as Au, Al, Ag, Cu, or Ni on the adhesion layer.
- the self-assembled monomolecular film 6 includes a first functional group chemically adsorbed on the metal atoms constituting the first electrode 5A and the second electrode 5B, and a second functional group bonded to the first functional group. Consists of.
- the first functional group is any group of a thiol group, a dithiocarbamate group, and a xanthate group.
- the second functional group is any group of an alkane, alkene, alkane or alkene in which part or all of the hydrogen molecule is substituted with fluorine, an amino group, a nitro group, or an amide group.
- the metal nanoparticles 7 are particles having a diameter of several nm, and gold, silver, copper, nickel, iron, cobalt, ruthenium, rhodium, palladium, iridium, platinum, or the like is used.
- molecules such as alkanethiol bonded to the linear portion of the molecule constituting the self-assembled monolayer 6 are bonded to the periphery.
- the second insulating layer 6 is formed of an inorganic insulator such as SiN, SiO, SiON, Si 2 O 3 , SiO 2 , Si 3 N 4 , Al 2 O 3 , or MgO.
- the inorganic insulator preferably has a stoichiometric composition, but may have a composition close to the stoichiometric composition.
- the top gate electrode 11 is provided on the second insulating layer 8 at a position directly above the metal nanoparticles 7 in plan view so as to straddle the one electrode 5A and the other electrode 5B. As shown in FIG. 1B, the top gate electrode 11 is arranged in a direction different from the arrangement direction of the electrodes 5A and 5B on the first insulating layer 2 and the arrangement direction of the side gate electrodes 5C and 5D. It is installed. This is to prevent the top gate electrode 11 and other electrodes 5A, 5B, 5C, 5D from forming capacitance.
- the metal nanoparticles 7 are insulated from the one electrode 5A and the other electrode 5B by the self-assembled monolayer 6 or the self-assembled mixed film around the metal nanoparticles 7 and the second insulating layer 8. As long as they are arranged.
- FIG. 2 is a cross-sectional view of a logical operation element 20 different from FIG.
- an inorganic or organic insulating film 71 is provided around the metal nanoparticles 7, and the metal nanoparticles 72 with an insulating film are connected to one electrode 5 ⁇ / b> A and the other electrode 5 ⁇ / b> B.
- the metal nanoparticles with the insulating film may be insulated from the one electrode 5A and the other electrode 5B by being disposed therebetween.
- the insulating film 71 does not need to be provided on the entire outer periphery of the metal nanoparticle 7, and one electrode 5A and the metal nanoparticle 7 are insulated by an insulating film of 0.3 nm to 10 nm, for example,
- the other electrode 5B may be insulated by an insulating film of 0.3 nm to 10 nm, for example.
- the metal nanoparticles 7 are disposed between the one electrode 5A and the other electrode 5B, and the insulating film 71 and the second insulating layer 8 are not distinguished, and the metal nanoparticles 7 and the one electrode are separated by the insulating layer.
- 5A and the other electrode 5B may be insulated.
- the metal nanoparticles 7 have the same gate capacitance between the two side gates and the top gate and the metal nanoparticles.
- the gate capacitance is determined by how much the electric flux converges from each electrode to the metal nanoparticles.
- the gap length of the nanogap electrodes 5A and 5B is narrow only in the portion where the metal nanoparticles 7 are present, the openings to the side gate electrodes 5C and 5D are widened, the openings to the metal nanoparticles 7 are wide and even the top. It is preferable that the gate electrode 11 is widened, and the metal nanoparticles 7 are not buried in the nanogap electrodes 5A and 5B by such a preferable form.
- the first insulating layer 2 is formed on the substrate 1.
- the nanogap electrodes 5A and 5B and the side gate electrodes 5C and 5D are formed by a molecular ruler electroless plating method.
- the metal layers 3A and 3B are formed on the first insulating layer 2 so as to have a gap wider than the nanogap so as to form a pair, and then the substrate 1 is applied to the electroless plating solution. Soak.
- the electroless plating solution is prepared by mixing a reducing agent and a surfactant into an electrolytic solution containing metal ions.
- the metal ions are reduced by the reducing agent, and the metal is deposited on the surfaces of the metal layers 3A and 3B to form the metal layer 4A and the metal layer 4B, and the metal layer 4A and the metal layer 4B.
- the surfactant contained in the electroless plating solution is chemically adsorbed on the metal layers 4A and 4B formed by the deposition.
- the surfactant controls the gap length (simply referred to as “gap length”) to nanometer size. Since the metal ions in the electrolytic solution are reduced by the reducing agent and the metal is deposited, such a method is classified as an electroless plating method.
- Metal layers 4A and 4B are formed on the metal layers 3A and 3B by plating, and a pair of electrodes 5A and 5B is obtained.
- the gap length is determined by an electroless plating method (hereinafter referred to as “molecular ruler electroless plating method”) using surfactant molecules as protective groups on the surfaces of the nanogap electrodes 5A and 5B as a molecular ruler. Is controlled by surfactant molecules.
- the nanogap electrodes 5A and 5B can be formed with high accuracy.
- the gate electrodes 5C and 5D can be formed simultaneously.
- the nanogap electrode is not limited to the one formed by the above-described method, and may be formed by electroless plating using iodine, for example, as disclosed in Non-Patent Document 3 by the present inventors.
- the metal nanoparticles 7 are chemically bonded between the nanogap electrodes 5A and 5B using ligand exchange of the gold nanoparticles 7 protected with alkanethiol by dithiol molecules. Thereby, the metal nanoparticle 7 is fixed to the self-assembled monolayer 6, for example.
- FIG. 3 is a diagram schematically showing a process of installing single-electron islands by chemical bonds using, for example, dithiol molecules, on the electrodes 5A and 5B having nanogap lengths.
- SAMs self-assembled monolayers
- FIG. 3 (B) by introducing alkanedithiol 9A, whether alkanedithiol is coordinated to the SAM deficient part or whether alkanethiol and alkanedithiol are exchanged, SAM and alkanethiol A SAM mixed film 9 is formed.
- the metal nanoparticles 7A protected with alkanethiol are introduced.
- a ligand of alkanethiol, which is a protective group of the metal nanoparticle 7, and alkanedithiol in the mixed self-assembled monolayer 6A, 6B of alkanethiol and alkanedithiol are chemisorbed on the self-assembled monomolecule.
- the self-assembled monolayers 6A and 6B are used between the electrodes 5A and 5B having the nanogap length, and the metal nanoparticles 7 are formed by chemical adsorption through the self-assembled monolayer mixed film. Introduced as a single-electron island.
- the substrate with the nanogap electrode on which the metal nanoparticles 7 are chemically adsorbed by the self-assembled monolayers 6A and 6B is cooled by using a catalytic CVD method, a plasma CVD method, a photo CVD method or a pulsed laser deposition (PLD) method.
- the second insulating layer 8 is deposited on the sample so that the temperature of the sample does not exceed a predetermined temperature.
- the gas may be pyrolyzed using an atomic layer epitaxy method or a thermal CVD method. In that case, it is necessary to sufficiently cool the sample stage.
- a resist is applied, a pattern of the gate electrode 11 is drawn by an electron beam lithography technique or optical lithography, and after development, one or two kinds of metal layers are formed to form the gate electrode 11. In that case, it is better to provide an adhesion layer.
- an external extraction electrode is formed in order to externally connect the nanogap electrodes 5A and 5B.
- a mask is formed on the resist by forming a resist on the second insulating layer 8, placing a mask on the resist, and exposing the resist.
- a via hole is formed in the second insulating layer 8. The self-assembled single molecule in the via hole is removed by ashing as necessary. Then, the via hole is filled with a metal to form an external extraction electrode.
- the electrode material may be copper as the initial electrode material.
- the initial electrode a copper electrode is formed by using an electron beam lithography method or an optical lithography method, and then the surface of the copper electrode is made of copper chloride.
- a gold chloride solution using ascorbic acid as a reducing agent is used as a plating solution, and the copper electrode surface is covered with gold.
- a surfactant alkyltrimethylammonium bromide C n H 2n + 1 [CH 3 ] 3 N + ⁇ Br ⁇ is mixed with an aqueous solution of gold chloride (III), and a reducing agent L (+)-ascorbic acid is added.
- a reducing agent L (+)-ascorbic acid is added.
- Autocatalytic electroless gold plating is performed on the gap electrode.
- a nanogap electrode having a gold surface is prepared by molecular ruler plating.
- the logical operation element 10 As described above, the logical operation element 10 according to the embodiment of the present invention can be manufactured.
- an inorganic insulating film such as Si 3 N 4 is formed by using a catalytic CVD method, a plasma CVD method, a photo CVD method, or a PLD method
- a sample is exposed to plasma or kinetic energy is high.
- the temperature of the substrate becomes high because particles sputter the sample surface or mainly improve the film quality. Since single-electron elements are easily destroyed by plasma, high-energy particles, heat, and the like on these substrates, it has been difficult to deposit an inorganic insulating film.
- the source source of the deposit is SAM and The element is destroyed by breaking the ligand molecules and breaking the nanoparticles. Even if the device is not destroyed, the nanoparticles present between the gaps move during the deposition of the inorganic insulator and do not function as a single-electron device.
- a nanoscale gold electrode used as a gold nanogap electrode has high fluidity to heat, the structure of the nanogap occurs when heat is applied, and the single-electron device is broken.
- An electrode pair can be formed by controlling the gap length by electroless plating, and such a nanogap electrode is stable to heat.
- the metal nanoparticles are covered with coordination molecules, and the nanogap electrode is covered with SAM, so that the electrode surface is not destroyed.
- Metal nanoparticles that act as single-electron islands are chemically fixed between the nanogaps by anchor molecules such as dithiol molecules.
- FIG. 4 is a diagram showing a truth table with three inputs, and also shows how to set a gate voltage for performing each logical operation.
- the logical operation element according to the embodiment of the present invention has a single-electron transistor structure. Although a single-electron transistor is a kind of FET (Field Effect Transistor), the electric charge to the single-electron island made of metal nanoparticles 7 is modulated by the gate voltage, and as a result, the current flows and does not flow. A so-called Coulomb oscillation phenomenon in which two states appear periodically is observed.
- FET Field Effect Transistor
- FIG. 5 schematically shows the waveform of the drain current flowing according to each gate voltage at a certain drain voltage.
- FIG. 6 shows the drain voltage V d and each gate voltage V g1 , V g2 , V top-gate . It is a figure which shows typically the differential conductance of the drain current I when it sets to a value.
- the magnitude of the differential conductance of the drain current I is shown to increase according to the number of meshes.
- the current waveform in the Coulomb oscillation characteristic is extrapolated by a straight line having a positive slope and a negative slope in the two voltage directions of the drain voltage Vd and each gate voltage, and the current value has a peak. Have.
- e is an elementary charge.
- the value of ⁇ V depends on the arrangement relationship between the metal nanoparticles 7 and one electrode 5A and the other electrode 5B, that is, the metal nanoparticles 7 and the source and drain electrodes, and the two side gate electrodes 5C and 5D and the top gate. It depends on the arrangement relationship with the electrode 11.
- the value of each gate voltage may be set as follows.
- the voltage difference corresponding to the input of the voltage “0” and the voltage “1” applied to the three gates becomes a voltage difference corresponding to ⁇ V / 2 (1/2 cycle).
- Adjust the drain voltage For example, a top gate voltage corresponding to an input of “1” is a gate voltage that takes a peak current of Coulomb oscillation, and a gate voltage corresponding to an input of “0” is a voltage value that is smaller by ⁇ V / 2.
- the top gate voltage is set to the input of “0”, and the side gate voltage of one side is set to the gate voltage corresponding to the input of “1”.
- the gate voltage corresponding to the input is set to a voltage value smaller by ⁇ V / 2.
- the top gate voltage and one side gate voltage are inputs of “0”, and the other side gate voltage is a gate voltage corresponding to the input of “1” with the gate voltage taking a peak current being “0”.
- the gate voltage corresponding to the input is set to a voltage value smaller by ⁇ V / 2.
- the input gate voltage is set so that the three gate voltages are gate voltages corresponding to the input of “1” and the output has a current peak value of “1”.
- the relationship between the input combination of the gate electrode and the output is the output of the exclusive OR XOR operation. Therefore, in the single-electron transistor, a logical operation can be realized by the Coulomb oscillation characteristic and the superposition phenomenon of charge induction on the single-electron island by a plurality of gate electrodes.
- each gate voltage may be set as follows. That is, in the XNOR operation, the drain voltage is adjusted so that the difference between the input voltages in the “0” and “1” states becomes a gate voltage difference corresponding to ⁇ V / 2, similar to XOR. Are set to the gate voltage corresponding to the input of “0” and the output has a current peak value of “1”. Then, the logical operation of XNOR can be realized by setting the gate voltage based on the same operating principle as XOR. This means that the voltage region in the right half of the one-cycle Coulomb oscillation diagram is used as the voltage applied to each gate electrode.
- XNOR exclusive OR operation
- the input voltage value of each gate voltage may be set to the gate voltage corresponding to the calculation A of the quarter cycle Coulomb oscillation in FIG. That is, for example, the drain voltage is adjusted so that the value obtained by dividing ⁇ V into four equal values on the positive and negative slopes of the peak current of the Coulomb oscillation, and the top gate voltage corresponding to the input of “0” is The voltage value on the negative slope of the peak current is set, and the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 4 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “0” input.
- the top gate corresponding to the input of “1” is set to the voltage value on the negative slope of the peak current so that the divided value becomes the same current value on the positive and negative slope of the peak current of Coulomb oscillation
- the voltage is set to a voltage value higher by ⁇ V / 4 than the set voltage value.
- the top gate voltage and one side gate voltage are input as “0”, and ⁇ V is set to four values as the value of the other side gate voltage corresponding to the input of “0”.
- ⁇ V is set to four values as the value of the other side gate voltage corresponding to the input of “0”.
- the gate voltage is set to a voltage value higher by ⁇ V / 4 than the set voltage value.
- the input gate voltage is set so that the three gate voltages are gate voltages corresponding to the input of “1” and the output has a current peak value of “1”. Then, the output is “1” only when the inputs to the three gate voltages are (0, 0, 0) and (1, 1, 1), otherwise the output is “0”.
- the logical operation element 10 performs the operation A.
- the gate voltage corresponding to operation C is set as follows. That is, for example, the top gate voltage corresponding to the input of “1” is divided into four equal parts of ⁇ V so that the positive current value of the peak current is the same on the positive and negative slopes of the peak current of the Coulomb oscillation. The voltage value on the slope is set, and the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “1” input.
- the top gate corresponding to the input of “0” is set to the voltage value on the positive slope of the peak current so that the divided value becomes the same current value on the positive and negative slope of the peak current of the Coulomb oscillation
- the voltage is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the top gate voltage and one side gate voltage are input as “0”, and ⁇ V is set to four as the value of the other side gate voltage corresponding to the input of “1”.
- ⁇ V is set to four as the value of the other side gate voltage corresponding to the input of “1”.
- ⁇ V / 4 is used as the voltage difference between the input “0” and the input “1” to adjust the drain voltage.
- the gate voltage corresponding to operation B is set as follows.
- a top gate voltage corresponding to an input of “1” a value obtained by dividing ⁇ V into four equal parts has the same current value on the positive and negative slopes of the peak current of the Coulomb oscillation. Is set to a value 3/4 times higher than ⁇ V, and the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value. .
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “1” input.
- a value that is 3/4 times higher than ⁇ V is set to the voltage value on the positive slope of the peak current so that the divided value becomes the same current value on the positive and negative slopes of the peak current of Coulomb oscillation.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the top gate voltage and one side gate voltage are input as “0”, and ⁇ V is set to four as the value of the other side gate voltage corresponding to the input of “1”.
- a value that is 3/4 times higher than ⁇ V with respect to the voltage value on the positive slope of the peak current is set so that the equally divided value becomes the same current value on the positive and negative slopes of the peak current of the Coulomb oscillation.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the gate voltage corresponding to operation D is set as follows. For example, as a top gate voltage corresponding to an input of “0”, a value obtained by dividing ⁇ V into four equal parts on the positive slope of the peak current so that the same current value is obtained on the positive and negative slopes of the peak current of the Coulomb oscillation. And the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 4 than the set voltage value. When "1" is input, the current value is the same as the same current value with a negative slope.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “0” input.
- ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “0” input.
- the top gate voltage and one side gate voltage are input as “0”, and ⁇ V is set to four values as the value of the other side gate voltage corresponding to the input of “0”.
- the voltage value on the positive slope of the peak current is set so that the equally divided values are the same on the positive and negative slopes of the peak current of the Coulomb oscillation, and the top corresponding to the input of “1”
- the gate voltage is set to a voltage value higher by ⁇ V / 4 than the set voltage value.
- the logical operation element 10 it is also possible to cause the logical operation element 10 to perform the following operation. That is, when ⁇ V / 3 is used as a voltage difference between input “0” and input “1” and two gate voltages having a voltage difference of ⁇ V / 3 are added, a positive slope before the current peak of Coulomb oscillation is obtained. The drain voltage is adjusted so that the same current value is shown in the middle of the negative slope after the peak.
- ⁇ V is divided into three equal parts on the positive slope of the peak current so that the same current value is obtained on the positive and negative slopes of the peak current of the Coulomb oscillation.
- the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 3 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- the top gate voltage and one side gate voltage are set to “0” inputs, and ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- the voltage value on the positive slope of the peak current is set so that the equally divided values are the same on the positive and negative slopes of the peak current of the Coulomb oscillation, and the top corresponding to the input of “1”
- the gate voltage is set to a voltage value higher by ⁇ V / 3 than the set voltage value.
- the gate voltage corresponding to operation F is set as follows. For example, as a top gate voltage corresponding to an input of “0”, ⁇ V is divided into three equal parts on the negative slope of the peak current so that the same current value is obtained on the positive and negative slopes of the peak current of Coulomb oscillation. And the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 3 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- the top gate voltage and one side gate voltage are set to “0” inputs, and ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- the gate voltage corresponding to operation G as follows.
- the top gate voltage corresponding to the input of “1” is set as follows. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the top gate voltage is set to the input of “0” determined previously, and the value of one side gate voltage corresponding to the input of “1” is set as follows. To do. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the other side gate voltage is set by setting the top gate voltage and one side gate voltage as “0” inputs, and setting the value of the other gate voltage corresponding to the “1” input as follows. To do. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the logical operation elements 10 and 20 shown in FIGS. 1 and 2 have a potential difference between High and Low, for example, a voltage difference between “0” and “1” is ⁇ V / n, and n is an integer of 2 or more. By setting these values, it is possible to realize a 3-input logical operation element.
- the number of gate electrodes is not necessarily three as shown in FIG. 1, and the number of gate electrodes may be four or more.
- the gate electrode is divided into a bottom gate electrode, a top gate electrode, and a side gate electrode according to the arrangement position.
- Each electrode may be made of any material as long as a predetermined voltage is applied.
- the three or more gate electrodes may be composed of two side gate electrodes and one top gate electrode.
- the three or more gate electrodes may be composed of two side gate electrodes and one bottom gate electrode.
- the three or more gate electrodes may be composed of two side gate electrodes, one top gate electrode, and one bottom gate electrode.
- gate electrodes for example, four gate electrodes, that is, any three of two side gate electrodes, one bottom gate electrode, and one top gate electrode are used for voltage input, and the rest One may be used as an electrode for voltage adjustment.
- the two side gate electrodes have symmetry with respect to the axis of arrangement of one electrode and the other electrode, so that either the bottom gate electrode or the top gate electrode is used.
- One of them is preferably an electrode for voltage adjustment.
- the voltage adjustment electrode can be set to 0 V, and the voltage applied to the other gate electrode can be set based on the voltage adjustment electrode.
- FIG. 7A and 7B show a 4-input logical operation element according to the embodiment of the present invention, in which FIG. 7A is a sectional view and FIG. 7B is a plan view.
- the logical operation element 30 according to the embodiment of the present invention includes one electrode 5A and the other electrode 5B arranged so as to have a nanogap, one electrode 5A, and the other electrode 5B.
- Metal nanoparticles 7 arranged insulatively, and a plurality of gate electrodes 5C, 5D, 11A, and 11B for adjusting the charge of the metal nanoparticles 7.
- the surface on which the bottom gate electrode 11A exists, the surface on which the side gate electrodes 5C and 5D exist, and the surface on which the top gate electrode 11A exists are separated in the vertical direction.
- the surface on which the bottom gate electrode 11A is present and the surface on which the top gate electrode 11B are present are separated from each other across the surface on which the side gate electrodes 5C and 5D are present.
- Metal nanoparticles 7 are embedded in the second insulating layer 8 on the bottom gate electrode 11A and below the top gate electrode 11B.
- the periphery is subjected to a process such as etching so that only a predetermined region of the conductive substrate 1 such as a Si substrate becomes high.
- a first insulating layer 2 is formed on the substrate 1 and the surface is planarized as necessary.
- one electrode 5A and the other electrode 5B are formed, and the metal nanoparticles 7 are arranged between the nano gaps on the predetermined region,
- the second insulating layer 8 is formed, and the top gate electrode 11B is formed.
- the raised portion of the substrate 1 can function as the bottom gate electrode 11A.
- FIG. 8 shows a truth table with four inputs, and also shows how to set a gate voltage for performing each logical operation.
- the operations H and I use ⁇ V / 2 (half cycle) as the voltage difference between the input “0” and the input “1” with respect to the logic operation element 30 and have two voltage differences of ⁇ V / 2.
- the drain voltage is adjusted so as to show the current peak of Coulomb oscillation. If the gate voltage is shifted by ⁇ V / 2 as shown in the coulomb oscillation characteristic of the half cycle of FIG. 8, it changes to “0”, “1”, “0”, “1”. Therefore, in operation H, a logical operation is performed in which the output is “1” only when the number of input “1” is an odd number, and the output is “0” in other cases.
- a logical operation is performed in which the output is “1” only when the number of inputs “1” is an even number, and the output is “0” otherwise.
- the operations J, K, L, and M use ⁇ V / 4 (quarter cycle) as the voltage difference between the input “0” and the input “1” with respect to the logic operation element 30, and the voltage difference of ⁇ V / 4.
- the drain voltage is adjusted so that the same current value is shown in the middle of the positive slope before the current peak of the coulomb oscillation and the negative slope after the peak when the two gate voltages having are added.
- the gate voltage is shifted by ⁇ V / 4 as shown in the coulomb oscillation characteristic of the quarter period of FIG. 4, it changes to “0”, “1”, “1”, “0”.
- a logical operation in which the output is “1” only when the number of input “1” is 1 or 2 and the output is “0” in other cases is performed.
- the operation K a logical operation is performed in which the output is “1” only when the number of “1” s at the input is 0, 1, and 4, and the output is “0” in other cases.
- the operation L a logical operation is performed in which the output is “1” only when the number of “1” s at the input is 0, 3, and 4, and the output is “0” in other cases.
- a logical operation is performed in which the output is “1” only when the number of input “1” is 2 or 3, and the output is “0” in other cases.
- the operations N, O, and P can also cause the logical operation element 30 to perform the following operations. That is, when ⁇ V / 3 is used as a voltage difference between input “0” and input “1” and two gate voltages having a voltage difference of ⁇ V / 3 are added, a positive slope before the current peak of Coulomb oscillation is obtained. The drain voltage is adjusted so that the same current value is shown in the middle of the negative slope after the peak.
- the output is “1” only when the number of “1” at the input is one, two, or four, otherwise the output is “0”.
- Perform operation N When the gate voltage corresponding to the operation O is set, the output is “1” only when the number of “1” s at the input is 0, 1, 3, and 4, and otherwise the output is “0”. ”Is performed.
- FIG. 9 is an SEM image of the logical operation element 10 manufactured in Example 1.
- a SiO 2 film is produced as a first insulating layer 2 on the Si substrate 1 by a thermal CVD method, gold nanogap electrodes 5A and 5B having a gap length of 9 nm are formed thereon, and a gold having a core diameter of 6.2 nm is formed. Nanoparticles 7 were placed between gold nanogap electrodes. Then, a passivation layer of SiN was formed as the second insulating layer 8 on the gold nanogap electrodes 5A and 5B and the SiO 2 film 2.
- the formation of the Si 3 N 4 passivation layer was performed as follows.
- the produced single-electron transistor was introduced into a vacuum chamber, and temperature control was performed so that the temperature of the single-electron transistor would not exceed 65 ° C. by water cooling.
- silane gas, ammonia gas and hydrogen gas were introduced into the vacuum chamber, and a SiN x layer was deposited by catalytic CVD.
- the sample temperature was cooled so as not to exceed 65 ° C. when the passivation layer of SiN x was formed.
- the passivation layer may be deposited at 170 ° C.
- the sample is cooled so that the temperature during the deposition is as low as possible, preferably 65 ° C. or lower.
- the thickness of the passivation layer of SiN x was measured by an ellipsometry method and a scanning electron microscope, both were 50 nm.
- a resist was applied to the sample, and an electrode pattern was drawn immediately above the gold nanogap portion by electron beam lithography. After development, a Ti layer 30 nm and an Au layer 70 nm were sequentially deposited by electron beam evaporation. Thereby, the top gate electrode 21 was disposed directly above the gold nanogap via the Si 3 N 4 layer as the second insulating layer 8.
- FIG. 10 is a diagram showing the drain current with respect to the drain voltage in the sample manufactured in Example 1.
- FIG. The measurement temperature was 9K.
- the horizontal axis represents the drain voltage V d (mV)
- the left vertical axis represents the drain current I d (pA)
- the right vertical axis represents the drain current I d (nA).
- the drain current before depositing SiN x as a passivation film is in the range of about ⁇ 100 pA, but the drain current after depositing SiN x is large in the range of ⁇ 400 pA, and the drain current I d flows.
- the width of the non-drain voltage Vd is also increased.
- the drain current is ⁇ 4 nA.
- FIG. 11 is a diagram showing a mapping (stability diagram) of differential conductance when the top gate voltage and the drain voltage are respectively swept.
- the horizontal axis represents the voltage (V) applied to the top gate
- the vertical axis represents the drain voltage Vd (V)
- the shade indicates the differential conductance of the drain current (A).
- the measurement temperature was 9K.
- a voltage region having a parallelogram shape called so-called coulomb diamond is observed due to current suppression (coulomb blockade) through the coulomb island between the drain and the source. This shows that it is operating as a single electron transistor. Moreover, it is confirmed that it is in agreement with the theoretical calculation value.
- FIG. 12 is a diagram showing the drain current dependency on the drain voltage.
- the horizontal axis is the drain voltage V d (V), and the vertical axis is the drain current I d (pA). From the figure, since there is a region where the drain current does not flow with respect to the increase or decrease of the drain voltage, the Coulomb steer case characteristic is clearly observed, and the sample manufactured in Example 1 operates as a single electron transistor. I understand that. This is also consistent with theoretical calculations.
- FIG. 13A shows the drain current dependency (Coulomb oscillation characteristics) on the first side gate voltage
- FIG. 13B shows the drain current dependency on the second side gate voltage (Coulomb oscillation characteristics)
- FIG. Drain current dependence on the top gate voltage (Coulomb oscillation characteristics)
- D is the differential conductance ( d I d / dV d ) characteristics when the first side gate voltage and drain voltage are changed
- E is the first 2 of the side gate voltage and the drain voltage differential conductance when changing the (dI d / dV d) characteristics
- the measurement temperature is 9K.
- the vertical axis represents the drain current I d (pA), and the vertical axes of (D) to (F) represent the drain voltage V d (V).
- the horizontal axis is the first side gate voltage V g1 (V), the horizontal axis of (B) and (E) is the second side gate voltage V g2 (V), and the horizontal axis of (C) and (F). Is the top gate voltage V top-gate (V).
- FIGS. 13D, 13E, and 13F show the Coulomb diamond characteristics corresponding to the respective gate voltages.
- the parallelograms are connected to each other sharing a vertex in the gate voltage direction.
- FIG. 14 is a diagram showing the differential conductance dependence on the voltage applied to any two gates, (A) is the differential conductance dependence on the first side gate voltage and the second side gate voltage, and (B) is The differential conductance dependence on the second gate voltage and the top gate voltage, (C) shows the differential conductance dependence on the first side gate voltage and the top gate voltage.
- the portion indicated by ⁇ corresponds to the peak current, and in the region indicated by ⁇ , current does not flow due to Coulomb blockade. Since the peak current indicated by ⁇ is observed as a collection of parallel lines with respect to any two gate voltages, it is expected that one device can perform a logical operation with three gates simultaneously.
- FIG. 15 is a diagram showing the characteristics of the logical operation element fabricated in Example 1.
- ⁇ 1V and 0.85V of V top-gate are respectively “
- FIG. 15 shows that the drain current is an XOR output according to the input of the pulse voltage waveforms of the first side gate voltage, the second side gate voltage, and the top gate voltage.
- the ON / OFF ratio was 10.
- the operating temperature was 9K.
- Example 2 the second insulating layer 8 was manufactured in the same manner as in Example 1 except that 50 nm Al 2 O 3 was formed by using a pulse laser deposition method.
- the measurement environment was 9K.
- FIG. 16 is a diagram showing the drain current dependency on the drain voltage.
- the horizontal axis is the drain voltage V d (V), and the vertical axis is the drain current I d (nA). From the figure, since there is a region where the drain current does not flow with respect to the increase or decrease of the drain voltage, the Coulomb steer case characteristics are clearly observed, and the sample manufactured in Example 2 operates as a single electron transistor. I understood that. It was also found to be consistent with the theoretical calculation.
- FIGS. 17A, 17B, and 17C show the Coulomb oscillation characteristics with respect to the gate voltages V g1 , V g2 , and V top-gate , respectively.
- (D), (E), and (F) are the respective values.
- Coulomb diamond characteristics with respect to gate voltage are shown.
- the vertical axis represents the drain current I d (nA)
- the vertical axes of (D) to (F) represent the drain voltage V d (V).
- the horizontal axis is the first side gate voltage V g1 (V), the horizontal axis of (B) and (E) is the second side gate voltage V g2 (V), the horizontal axis of (C) and (F) is the top
- the gate voltage is V top-gate (V).
- a peak current is observed in a region where no current flows and a slope having positive and negative slopes.
- FIGS. 17A, 17B, and 17C show the results of repeated measurement of the Coulomb oscillation characteristics with respect to the gate voltages V g1 , V g2 , and V top-gate , respectively.
- V d was 10 mV.
- the vertical and horizontal axes in the figure are the same as those in FIGS. 17A, 17B, and 17C.
- the figure shows that Coulomb oscillation can be observed stably.
- the characteristics of Coulomb diamond could be observed with good reproducibility.
- Example 1 Compared to Example 1, the drain current was not on the order of pA but on the order of nA. Moreover, compared with Example 1, the Coulomb vibration was more stable. In the single electron transistor, when the trap charge existing in the vicinity of the single electron island changes, the output current (drain) current is disturbed. When Al 2 O 3 is used as the passivation film, the variation in current is smaller than that when SiN x is used. Therefore, the Al 2 O 3 insulating film manufactured by the pulse laser deposition method is used for the passivation of a single electron transistor. As a layer, it is suitable from the viewpoint that the trap charge hardly changes. A film that is not limited to Al 2 O 3 , SiNx, and has a low trap charge change such as a high dielectric constant insulating layer such as a SiO 2 layer or HfOx is suitable.
- FIG. 19 is a diagram showing the characteristics of the logical operation element fabricated in Example 2.
- V top-gate of ⁇ 0.9V and 0.5V are set to each "0"
- 5V and -1V were values corresponding to inputs of "0" and "1", respectively.
- FIG. 19 shows that the drain current is an XOR output according to the input of the pulse voltage waveforms of the first side gate voltage, the second side gate voltage, and the top gate voltage.
- the ON / OFF ratio was 9.4.
- the operating temperature was 9K.
- the current value corresponding to the output “0” is about 0.1 nA
- the current corresponding to the output “1” is about 0.9 nA.
- the reason why the current value when the output is “0” is 0.1 nA is that a leak current flows between the source electrode and the drain electrode.
- the XOR characteristic is shown in FIG. 19, it was confirmed that the XNOR characteristic is shown by shifting the gate voltage by a half cycle as described above.
- a voltage difference of ⁇ V / 3 or ⁇ V / 4 is used instead of ⁇ V / 2
- various logical operations are possible as shown in the truth table shown in FIG.
- Example 2 Next, the frequency was increased to 1 Hz and 10 Hz, and the operation of the logical operation element produced in Example 2 was confirmed.
- 20A and 20B show the operation results of the logical operation elements at frequencies of 1 Hz and 10 Hz, respectively. It was confirmed that the characteristics of the logic operation element were maintained even when the frequency was increased.
- a logical operation element in which three or more gates of two side gates, top gates, and bottom gates are combined by applying a single electron transistor using metal nanoparticles or functional particles. Can be provided. Further, by combining the logic operation element according to the embodiment of the present invention with a CMOS circuit, a logic operation circuit having a higher degree of integration and a higher function is provided.
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Abstract
Description
[1] ナノギャップを有するように設けられた一方の電極及び他方の電極と、
前記一方の電極と前記他方の電極との間に絶縁して配置された金属ナノ粒子と、
前記金属ナノ粒子の電荷を調整するための複数のゲート電極と、
を備え、
前記複数のゲート電極のうち三つ以上のゲート電極に印加される電圧に従って前記一方の電極と前記他方の電極との間に流れる電流が制御される、論理演算素子。
[3] 前記三つ以上のゲート電極は、二つのサイドゲート電極と一つのボトムゲート電極で構成される、前記[1]に記載の論理演算素子。
[4] 前記三つ以上のゲート電極は、二つのサイドゲート電極と一つのトップゲート電極と一つのボトムゲート電極で構成される、前記[1]に記載の論理演算素子。
[5] 前記一方の電極、前記他方の電極及び前記二つのサイドゲート電極が第1絶縁層上に設けられ、
第2絶縁層が前記第1絶縁層上において、前記一方の電極、前記他方の電極、前記二つのサイドゲート電極及び前記金属ナノ粒子を埋設するように設けられ、
前記トップゲート電極が、前記第2絶縁層上で前記金属ナノ粒子の上に設けられている、前記[2]又は[4]に記載の論理演算素子。
[6] 前記三つ以上のゲート電極は、一つのサイドゲート電極と一つのボトムゲート電極と一つのトップゲート電極で構成され、
前記ボトムゲート電極が存在する面と、前記サイドゲート電極が存在する面と、前記トップゲート電極とが存在する面とが、上下方向に分離されており、
前記金属ナノ粒子が前記ボトムゲート電極上で前記トップゲート電極下であって絶縁層に埋設するように設けられている、前記[1]に記載の論理演算素子。
[8] 前記三つ以上のゲート電極に印加される電圧のHighとLowの入力に相当する電位差として、一周期分のクーロンオシレーションにおけるピーク電流を与えるゲート電圧と隣のピーク電流を与えるゲート電圧の電圧差ΔVを二等分、三等分又は四等分した或る一つの電圧区間の両端に相当する値が設定されている、前記[1]に記載の論理演算素子。
2:第1の絶縁層
3A,3B,4A,4B:金属層
5A:ナノギャップ電極(一方の電極)
5B:ナノギャップ電極(他方の電極)
5C,5D:ゲート電極(サイドゲート電極)
6,6A,6B:自己組織化単分子膜
7:金属ナノ粒子
7A:アルカンチオールで保護された金属ナノ粒子
71:絶縁膜
72:絶縁膜付き金属ナノ粒子
8:第2の絶縁層
9:自己組織化単分子混合膜(SAM混合膜)
9A:アルカンチオール
10:論理演算素子
11,11B:ゲート電極(トップゲート電極)
11A:ゲート電極(ボトムゲート電極)
図1は、本発明の実施形態に係る論理演算素子の構成を示しており、(A)は断面図、(B)は平面図である。本発明の実施形態に係る論理演算素子10は、ナノギャップを有するように配置された一方の電極5A及び他方の電極5Bと、一方の電極5A及び他方の電極5Bとの間に絶縁して配置される金属ナノ粒子7と、金属ナノ粒子7の電荷を調整するための複数のゲート電極5C,5D,11と、を備える。
第2の絶縁層6は、SiN、SiO、SiON、Si2O3、SiO2、Si3N4、Al2O3、MgOなど、無機絶縁物により形成される。無機絶縁物は化学量論組成のものが好ましいが、化学量論組成に近いものであってもよい。
次に、図1に示す論理演算素子10の製造方法について詳細に説明する。
先ず、基板1上に第1の絶縁層2を形成する。次に、分子定規無電解メッキ法によりナノギャップ電極5A,5Bと、サイドゲート電極5C,5Dを形成する。
1)無電解メッキによりギャップ長を制御して電極対を形成することができ、そのようなナノギャップ電極は熱に対して安定であること。
2)無機絶縁物を堆積する際、金属ナノ粒子が配位分子により覆われ、ナノギャップ電極がSAMで覆われていることから電極表面を破壊しないこと。
3)単電子島(「クーロン島」とも呼ばれる。)として働く金属ナノ粒子が、ナノギャップ間にアンカー分子、例えばジチオール分子によって化学的に固定したこと。
次に、本発明の実施形態に係る論理演算素子の動作原理について説明する。図4は、3入力における真理値表を示す図であり、各論理動作をさせるためのゲート電圧の設定の仕方を併せて示してある。本発明の実施形態に係る論理演算素子は、単電子トランジスタの構造を有している。単電子トランジスタはFET(Field Effect Transistor)の一種であるにも拘わらず、ゲート電圧によって金属ナノ粒子7からなる単電子島への電荷が変調し、その結果、電流が流れる状態と流れない状態の2つの状態が周期的に現れるという、所謂クーロンオシレーション現象が観察される。図5は或るドレイン電圧において、各ゲート電圧に応じて流れるドレイン電流の波形を模式的に示し、図6は、ドレイン電圧Vdと各ゲート電圧Vg1,Vg2,Vtop-gateを各値に設定したときのドレイン電流Iの微分コンダクタンスを模式的に示す図である。図6においては、ドレイン電流Iの微分コンダクタンスの大きさがメッシュの数に応じて大きくなるように示している。図5に示すように、クーロンオシレーション特性における電流波形は、ドレイン電圧Vdと各ゲート電圧の2つの電圧方向に正の傾きと負の傾きを有する直線で外挿され、電流値はピークを持つ。
3つのゲート電極のいずれか1つのゲート電圧を「1」の状態とし、残りの2つのゲート電圧を「0」の状態とすると、ピーク電流が流れ、出力は「1」となる。
3つのゲート電極のなかで、いずれか2つのゲート電圧を「1」の状態とし、残り1つのゲート電圧を「0」の状態とすると、ゲート電圧による単電子島への電荷誘起の重畳が起こり、1周期分のΔVを印加した状態となるため、出力は「0」の状態となる。
3つのゲート電圧を「1」の状態とすると、1.5周期分のΔVを印加したことと等しいので出力は「1」となる。
図4の論理対応表のXORの列では、上述した出力電流の結果を示している。出力結果で、「0」は電流が流れない状態又は小さい状態を示し、「1」は電流が流れる状態又は大きい状態を示している。
論理対応表の最下欄には、1周期分のクーロンオシレーション(横軸はゲート電圧、縦軸がドレイン電流)を示しており、黒丸(●)印は「0」の電流出力状態、白丸(〇)印は「1」の電流出力状態を示している。XOR動作では、ΔV/2の電位差を入力ゲート電圧の「0」と「1」の状態に相当する電位の差として用い、入力が「0」側で出力が「0」であることから、1周期分のクーロンオシレーションの左半分の電圧領域を各ゲート電極に印加する電圧として用いていることになる。
次に、4入力の論理演算素子について説明する。図7は、本発明の実施形態に係る4入力の論理演算素子を示し、(A)は断面図、(B)は平面図である。図7に示すように、本発明の実施形態に係る論理演算素子30は、ナノギャップを有するように配置された一方の電極5A及び他方の電極5Bと、一方の電極5Aと他方の電極5Bとの間に絶縁して配置される金属ナノ粒子7と、金属ナノ粒子7の電荷を調整するための複数のゲート電極5C,5D,11A,11Bと、を備える。
図8は4入力における真理値表を示し、各論理動作をさせるためのゲート電圧の設定の仕方についても併せて示した図である。
Claims (8)
- ナノギャップを有するように設けられた一方の電極及び他方の電極と、
前記一方の電極と前記他方の電極との間に絶縁して配置された金属ナノ粒子と、
前記金属ナノ粒子の電荷を調整するための複数のゲート電極と、
を備え、
前記複数のゲート電極のうち三つ以上のゲート電極に印加される電圧に従って前記一方の電極と前記他方の電極との間に流れる電流が制御される、論理演算素子。 - 前記三つ以上のゲート電極は、二つのサイドゲート電極と一つのトップゲート電極で構成される、請求項1に記載の論理演算素子。
- 前記三つ以上のゲート電極は、二つのサイドゲート電極と一つのボトムゲート電極で構成される、請求項1に記載の論理演算素子。
- 前記三つ以上のゲート電極は、二つのサイドゲート電極と一つのトップゲート電極と一つのボトムゲート電極で構成される、請求項1に記載の論理演算素子。
- 前記一方の電極、前記他方の電極及び前記二つのサイドゲート電極が第1絶縁層上に設けられ、
第2絶縁層が前記第1絶縁層上において、前記一方の電極、前記他方の電極、前記二つのサイドゲート電極及び前記金属ナノ粒子を埋設するように設けられ、
前記トップゲート電極が、前記第2絶縁層上で前記金属ナノ粒子の上に設けられている、請求項2又は4に記載の論理演算素子。 - 前記三つ以上のゲート電極は、一つのサイドゲート電極と一つのボトムゲート電極と一つのトップゲート電極で構成され、
前記ボトムゲート電極が存在する面と、前記サイドゲート電極が存在する面と、前記トップゲート電極とが存在する面とが、上下方向に分離されており、
前記金属ナノ粒子が前記ボトムゲート電極上で前記トップゲート電極下であって絶縁層に埋設するように設けられている、請求項1に記載の論理演算素子。 - 前記三つ以上のゲート電極に印加される電圧の入力と、前記一方の電極と前記他方の電極との間に前記金属ナノ粒子を介して流れる電流の出力との関係が、XOR又はXNORとなる、請求項1に記載の論理演算素子。
- 前記三つ以上のゲート電極に印加される電圧のHighとLowの入力に相当する電位差として、一周期分のクーロンオシレーションにおけるピーク電流を与えるゲート電圧と隣のピーク電流を与えるゲート電圧の電圧差ΔVを二等分、三等分又は四等分した或る一つの電圧区間の両端に相当する値が設定されている、請求項1に記載の論理演算素子。
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Y. YASUTAKE; K. KONO; M. KANEHARA; T. TERANISHI; M. R. BUITELAAR; C. G. SMITH; Y. MAJIMA, APPL. PHYS. LETT., vol. 91, 2007, pages 203107 |
Also Published As
Publication number | Publication date |
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KR102162267B1 (ko) | 2020-10-06 |
JP6352243B2 (ja) | 2018-07-04 |
JPWO2014142039A1 (ja) | 2017-02-16 |
EP2991118A1 (en) | 2016-03-02 |
KR20150130439A (ko) | 2015-11-23 |
EP2991118A4 (en) | 2017-01-25 |
US9825161B2 (en) | 2017-11-21 |
EP2991118B1 (en) | 2023-02-22 |
TW201503363A (zh) | 2015-01-16 |
TWI605585B (zh) | 2017-11-11 |
US20160027908A1 (en) | 2016-01-28 |
CN105144388A (zh) | 2015-12-09 |
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