WO2013129535A1 - ナノデバイス及びその製造方法 - Google Patents
ナノデバイス及びその製造方法 Download PDFInfo
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- WO2013129535A1 WO2013129535A1 PCT/JP2013/055261 JP2013055261W WO2013129535A1 WO 2013129535 A1 WO2013129535 A1 WO 2013129535A1 JP 2013055261 W JP2013055261 W JP 2013055261W WO 2013129535 A1 WO2013129535 A1 WO 2013129535A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
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- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Definitions
- the present invention relates to a nanodevice combined with an electronic device such as a diode, a tunnel element, or a MOS transistor, an integrated circuit thereof, and a method of manufacturing the nanodevice.
- Non-Patent Documents 1 to 5 There is a single-electron transistor as a nanodevice.
- the present inventors paid attention to gold nanoparticles as Coulomb islands in single-electron devices, and the gold nanoparticles having a particle diameter of 1.8 nm using STM are coulomb at room temperature. It has been elucidated that it functions as an island.
- a nanogap electrode having a gap length of 5 nm is produced at a high yield at a time using electroless plating.
- the operation of a single electron transistor in which gold nanoparticles are introduced between nanogap electrodes by a chemical adsorption method has been reported (Non-Patent Documents 1 to 5).
- the single-electron transistor fabricated in this way is composed of a nanogap electrode having a gap length of 5 nm or less and nanoparticles having an organic molecule as a ligand, and is limited to a prototype and can be integrated. There wasn't.
- an object of the present invention is to provide a nanodevice combined with an electronic device such as a diode, a tunnel element, or a MOS transistor, an integrated circuit thereof, and a method for manufacturing the nanodevice.
- a nanodevice of the present invention includes a first insulating layer, one electrode provided to have a nanogap on the first insulating layer, the other electrode, and one electrode. And a metal nanoparticle or functional molecule disposed between the first electrode and the other electrode, and a second insulating layer, the second electrode which is provided on the one electrode and the other electrode and embeds the metal nanoparticle or the functional molecule An insulating layer.
- one or more gate electrodes are provided on the first insulating layer in a direction intersecting the arrangement direction of the one electrode and the other electrode, and the gate electrode is covered with the second insulating layer.
- a gate electrode for applying a voltage to the metal nanoparticles is provided on the second insulating layer.
- the second insulating layer is made of any one of SiN, SiO, SiON, Si 2 O 3 , Si 3 N 4 , SiO 2 , Al 2 O 3 , and MgO.
- an insulating film is interposed between one electrode and the metal nanoparticle, and between the other electrode and the metal nanoparticle, and the insulating film is made of an inorganic material or an organic material.
- the integrated circuit of the present invention comprises the nanodevice and the electronic device of the present invention formed on a semiconductor substrate.
- a first insulating layer provided over a semiconductor substrate on which an electronic device is formed, one electrode and the other electrode provided with a nanogap on the first insulating layer, and one electrode And a metal nanoparticle or functional molecule disposed between the first electrode and the other electrode, and a second insulating layer, the second electrode which is provided on the one electrode and the other electrode and embeds the metal nanoparticle or the functional molecule
- one of the plurality of electrodes of the electronic device is connected to one of the electrodes through a via provided in the first insulating layer.
- metal nanoparticles or functional molecules are arranged on a substrate with an insulating layer provided with one electrode having a nanogap and the other electrode, and the one electrode, the other electrode and the insulating layer are provided.
- a metal nanoparticle or a functional molecule is embedded by forming a passivation film on the substrate.
- the passivation film is formed using any one of a catalytic CVD method, a plasma CVD method, a photo CVD method, a pulse laser deposition method, an atomic layer epitaxy method, and a thermal CVD method.
- the nanoparticles or functional molecules are provided as ligands between the nanogap electrodes and are covered with another insulating layer, so that the other insulating layer functions as a passivation film. Therefore, the gate electrode can be provided on the metal nanoparticle or the functional molecule on the passivation layer, and the nanodevice can be integrated. Further, by providing another insulating film on the gate electrode and opening a via hole as appropriate, integration can be achieved by constructing an electrode for wiring.
- the nanogap electrode can be manufactured by providing a seed electrode on a substrate by lithography and mixing a surfactant with electroless plating to control the nanogap length. Therefore, a diode, a tunnel element, and a MOS transistor can be fabricated almost simultaneously with the fabrication of the nanogap electrode. Therefore, three-dimensional integration of devices can be achieved.
- the single-electron element as a nanodevice concerning the 1st Embodiment of this invention is shown typically, (A) is sectional drawing, (B) is a top view. (A) to (C) are diagrams schematically showing a step of installing a single electron island by chemical bonding using, for example, a dithiol molecule with respect to an electrode having a nanogap length.
- the single-electron element as a nanodevice concerning the 2nd Embodiment of this invention is shown typically, (A) is sectional drawing, (B) is a top view. It is sectional drawing of the integrated circuit which concerns on the 3rd Embodiment of this invention.
- FIG. 5 is a plan view of the integrated circuit shown in FIG. 4.
- FIG. 5 is a plan view of the integrated circuit shown in FIG. 4.
- FIG. 6 is a circuit diagram of the integrated circuit shown in FIGS. 4 and 5. It is sectional drawing of the single electronic element as a nanodevice concerning the 4th Embodiment of this invention. It is sectional drawing of the molecular element as a nanodevice concerning the 5th Embodiment of this invention.
- 1 is a plan view of a single electron transistor fabricated in Example 1.
- FIG. 1 is a cross-sectional view of a single electron transistor manufactured in Example 1.
- FIG. FIG. 6 is a graph showing drain current-side gate voltage dependency with respect to Example 1. It is a figure which shows the mapping of a differential conductance at the time of sweeping a drain voltage and a side gate voltage regarding Example 1.
- FIG. 6 is a plan view of a single electron transistor fabricated in Example 2.
- FIG. 6 is a cross-sectional view of a single electron transistor fabricated in Example 2.
- FIG. 6 is a diagram showing drain current-top gate voltage dependence obtained when the top gate voltage is swept in the single electron transistor fabricated in Example 2. It is a figure which shows the mapping of a differential conductance at the time of sweeping a drain voltage and a side gate voltage regarding Example 2.
- FIG. It is a figure which shows the drain current with respect to drain voltage regarding Example 2.
- the drain current depends on the top gate voltage, that is, the so-called Coulomb oscillation characteristics.
- (A) is the measurement temperature of 9K and 80K
- (B) is the case of 160K and 220K. It is a figure which shows the mapping of differential conductance regarding Example 2
- (A), (B), (C), (D) is a case where measurement temperature is 40K, 80K, 160K, and 220K, respectively.
- (A) and (D) are the characteristics of the drain current with respect to the drain voltage
- (B) and (E) are the characteristics of the drain current with respect to the voltage applied to the side gate
- (C) and (C F) shows dI / dV (nS) with respect to the side gate voltage and the drain voltage.
- FIG. 10 is a diagram showing characteristics of a gate to which a voltage is applied in one side gate, the other side gate, and a top gate in Example 3, and (A) to (C) show one side gate and the other side, respectively.
- (D) to (F) are the characteristics of drain current with respect to the voltage applied to one side gate, the other side gate, and the top gate, and the drain voltage with respect to the drain voltage with respect to the drain voltage. dV is shown.
- 4 is an SEM image of a single electron transistor being produced as Example 4.
- FIG. Regarding Example 4 (A) and (B) show the dependency of the drain current on the voltage applied to the first side gate electrode and the dependency of the drain current on the voltage applied to the second side gate electrode.
- FIG. 6 is an SEM image of a single electron transistor being produced as Example 5.
- FIG. Regarding Example 5 (A), (B), and (C) show the dependence of the drain current on the voltage applied to the first side gate electrode, and the dependence of the drain current on the voltage applied to the second side gate electrode.
- FIG. 4 is a diagram showing dI / dV (differential conductance) with respect to the second side gate voltage and the drain voltage
- FIG. 4D is a diagram showing the dependency of the drain current on the voltage applied to the second side gate electrode.
- Example 6 show the dependence of the drain current on the voltage applied to the top gate electrode, the first side gate electrode, and the second side gate electrode, respectively (D ) Shows dI / dV (differential conductance) with respect to the top gate voltage and drain voltage, and (E) shows dI / dV (differential conductance) with respect to the first side gate voltage and drain voltage.
- Substrate 2 First insulating layer 3A, 3B, 4A, 4B: Metal layer 5A: Nanogap electrode (one electrode) 5B: Nanogap electrode (the other electrode) 5C, 5D: Gate electrode (side gate electrode) 6, 6A, 6B: Self-assembled monomolecular film 7: Metal nanoparticles 8: Second insulating layer 9: Self-assembled monomolecular mixed film (SAM mixed film) 9A: Alkanethiol 10, 20: Single electron device 21: Gate electrode (top gate electrode) 30, 60: Integrated circuit 40, 62: MOSFET 50, 61: Single electronic device 31: Substrate 41: Source 42: Drain 43: First insulating layer 43A: Lower portion of the first insulating layer 43B: Upper portion of the first insulating layer 44: Gate electrodes 45, 46, 48 49: Via 51: Source electrode 52: Drain electrode 53: Metal nanoparticle 54: Second insulating layer 55: Gate electrode 70, 80: Nanodevice 71: Insulating film
- an inorganic insulating film such as SiN is formed using a catalytic CVD method, a plasma CVD method, a photo CVD method, or a PLD method
- the sample is generally exposed to plasma or particles with high kinetic energy are present on the surface of the sample.
- the temperature of the substrate is increased to improve the film quality. Since single-electron elements are easily destroyed by plasma, high-energy particles, heat, and the like on these substrates, it has been difficult to deposit an inorganic insulating film.
- an inorganic insulating film is deposited on nanoparticles covered with organic materials such as self-assembled monolayer (SAM) or nanoparticles covered with ligand molecules
- SAM self-assembled monolayer
- ligand molecules covered with ligand molecules
- the source source of the deposit breaks the SAM and the ligand molecule, and breaks the device by breaking the nanoparticles. Even if the device is not destroyed, the nanoparticles present between the gaps move during the deposition of the inorganic insulator and do not function as a single-electron device.
- a nanoscale gold electrode used as a gold nanogap electrode has high fluidity to heat, the structure of the nanogap occurs when heat is applied, and the single-electron device is broken.
- An electrode pair can be formed by controlling the gap length by electroless plating, and such a nanogap electrode is stable to heat.
- the metal nanoparticles are covered with coordination molecules, and the nanogap electrode is covered with SAM, so that the electrode surface is not destroyed.
- Metal nanoparticles that act as single-electron islands are chemically fixed between the nanogaps by anchor molecules such as dithiol molecules.
- Non-Patent Document 6 a functional molecule having a functional group as shown in Chemical Formula 1 (Non-Patent Document 6) is used, ohmic contact can be realized and the function of the functional molecule can be easily expressed.
- an oligothiophene molecule m is a natural number
- the functional group to be brought into ohmic contact may be a functional molecule structure that exists only on one side and does not make ohmic contact on the other side. In this case, the entry / exit of electric charges to / from the functional molecule easily occurs on the ohmic contact side, and the electric potential is applied to the electrode as it is on the other conductive path side.
- the anchor portion has a ⁇ -conjugated system as shown in Chemical Formula 1, for example.
- a structure where there is an overlap of wave functions with the surface is preferred for ohmic contact.
- the overlap of the wave function of the ⁇ -conjugated system as in Chemical Formula 1 at the anchor site and the ⁇ -conjugated system at the molecular functional site determines the conductivity of the functional molecule.
- the conductivity in the molecule is increased.
- the above-described molecules are designed to have a planar structure.
- the conductivity within the molecule including the functional site is lowered.
- FIG. 1A is a cross-sectional view schematically showing a single electronic device according to the first embodiment of the present invention
- FIG. 1B is a plan view of the single electronic device.
- the single-electron element 10 as a nanodevice according to the first embodiment has a nanogap length on the substrate 1, the first insulating layer 2 provided on the substrate 1, and the first insulating layer 2.
- a self-assembled monolayer 6 Adsorbed on one electrode 5A and the other electrode 5B provided on the electrode, a self-assembled monolayer 6 as an insulating film provided on the one electrode 5A and the other electrode 5B, and the self-assembled monolayer 6 Then, the self-assembled monolayer 6 on the metal nanoparticles 7 arranged between the one electrode 5A and the other electrode 5B, the first insulating layer 2, the one electrode 5A, and the other electrode 5B. And a second insulating layer 8 provided so as to embed the metal nanoparticles 7.
- the nanogap length is a dimension of several nm, for example, 2 nm to 12 nm.
- a self-assembled monomolecular mixed film formed by the reaction of self-assembled monomolecules and organic molecules is adsorbed and provided as an insulating film.
- a gate electrode (referred to as a side gate electrode) is formed on the first insulating layer 2 in a direction intersecting the arrangement direction of the one electrode 5A and the other electrode 5B, specifically in a direction orthogonal thereto.
- 5C and 5D are provided.
- the substrate 1 various semiconductor substrates such as a Si substrate are used.
- the first insulating layer 2 is formed of SiO 2 , Si 3 N 4 or the like.
- One electrode 5A and the other electrode 5B are formed of Au, Al, Ag, Cu or the like.
- One metal 5A and the other metal 5B may be formed by sequentially laminating an adhesion layer and a metal layer.
- the adhesion layer is formed of Ti, Cr, Ni or the like
- the metal layer is formed of another metal such as Au, Al, Ag, or Cu on the adhesion layer.
- the self-assembled monomolecular film 6 includes a first functional group chemically adsorbed on the metal atoms constituting the first electrode 5A and the second electrode 5B, and a second functional group bonded to the first functional group. Consists of.
- the first functional group is any group of a thiol group, a dithiocarbamate group, and a xanthate group.
- the second functional group is any group of an alkane, alkene, alkane or alkene in which part or all of the hydrogen molecule is substituted with fluorine, an amino group, a nitro group, or an amide group.
- the metal nanoparticles 7 are particles having a diameter of several nm, and gold, silver, copper, nickel, iron, cobalt, ruthenium, rhodium, palladium, iridium, platinum, or the like is used.
- molecules such as alkanethiol bonded to the linear portion of the molecule constituting the self-assembled monolayer 6 are bonded to the periphery.
- the second insulating layer 6 is formed of an inorganic insulator such as SiN, SiO, SiON, Si 2 O 3 , SiO 2 , Si 3 N 4 , Al 2 O 3 , or MgO.
- the inorganic insulator preferably has a stoichiometric composition, but may have a composition close to the stoichiometric composition.
- the first insulating layer 2 is formed on the substrate 1.
- the nanogap electrodes 5A and 5B and the side gate electrodes 5C and 5D are formed by a molecular ruler electroless plating method.
- the metal layers 3A and 3B are formed on the first insulating layer 2 so as to have a gap wider than the nanogap so as to form a pair, and then the substrate 1 is applied to the electroless plating solution. Soak.
- the inorganic electrolytic plating solution is prepared by mixing a reducing agent and a surfactant into an electrolytic solution containing metal ions.
- metal ions are reduced by the reducing agent, and the metal is deposited on the surfaces of the metal layers 3A and 3B to form the metal layer 4A and the metal layer 4B, and the metal layer 4A and the metal layer 4B.
- the surfactant contained in the electroless plating solution is chemically adsorbed on the metal layers 4A and 4B formed by the deposition.
- the surfactant controls the gap length (simply called “gap length”) to nanometer size. Since the metal ions in the electrolytic solution are reduced by the reducing agent and the metal is deposited, such a method is classified as an electroless plating method.
- Metal layers 4A and 4B are formed on the metal layers 3A and 3B by plating, and a pair of electrodes 5A and 5B is obtained.
- the gap length is set by the electroless plating method (hereinafter referred to as “molecular ruler electroless plating method”) using a surfactant molecule as a molecular ruler on the surfaces of the nanogap electrodes 5A and 5B. Controlled by surfactant molecules.
- the nanogap electrodes 5A and 5B can be formed with high accuracy.
- the gate electrodes 5C and 5D can be formed simultaneously.
- the metal nanoparticles 7 are chemically bonded between the nanogap electrodes 5A and 5B using ligand exchange of the gold nanoparticles 7 protected with alkanethiol by dithiol molecules. Thereby, the metal nanoparticles 7 are fixed to the self-assembled monolayer 6, for example.
- FIG. 2 is a diagram schematically showing a single-electron island installation process by chemical bonding using, for example, dithiol molecules with respect to the electrodes 5A and 5B having nanogap lengths.
- SAMs self-assembled monolayers
- FIG. 2 (B) depending on whether alkanedithiol is coordinated to the SAM deficient part by introducing alkanedithiol 9A or alkanethiol and alkanedithiol are exchanged, A SAM mixed film 9 is formed as an insulating film.
- the metal nanoparticles 7A protected with alkanethiol are introduced.
- a ligand of alkanethiol which is a protective group of the metal nanoparticle 7, and alkanedithiol in the mixed self-assembled monolayer 6A, 6B of alkanethiol and alkanedithiol.
- the metal nanoparticles 7 are chemisorbed on the self-assembled single molecules.
- the metal nanoparticles 7 are formed by chemical adsorption using the self-assembled monolayers 6A and 6B between the electrodes 5A and 5B having the nanogap length and interposing the SAM mixed film 9 as an insulating film. Is introduced as a single-electron island.
- the substrate with the nanogap electrode on which the metal nanoparticles 7 are chemically adsorbed by the self-assembled monolayers 6A and 6B is cooled by using a catalytic CVD method, a plasma CVD method, a photo CVD method or a pulsed laser deposition (PLD) method.
- the second insulating layer 8 is deposited on the sample so that the temperature of the sample does not exceed a predetermined temperature.
- the gas may be pyrolyzed using an atomic layer epitaxy method or a thermal CVD method. In that case, it is necessary to sufficiently cool the sample stage.
- an external extraction electrode is formed.
- a mask pattern is formed on the resist by forming a resist on the second insulating layer 8, placing a mask on the resist, and exposing the resist.
- a via hole is formed in the second insulating layer 8. The self-assembled single molecule in the via hole is removed by ashing as necessary.
- An external extraction electrode is formed by filling the via hole with metal.
- the single electronic element 10 as the nanodevice according to the first embodiment can be manufactured.
- FIG. 3A is a cross-sectional view schematically showing a single electronic element as a nanodevice according to the second embodiment
- FIG. 3B is a plan view of the single electronic element as a nanodevice.
- the single-electron element 20 as a nanodevice according to the second embodiment has a substrate 1, a first insulating layer 2 provided on the substrate 1, and a nanogap length on the first insulating layer 2.
- One electrode 5A and the other electrode 5B provided, the self-assembled monolayer 6 provided on the one electrode 5A and the other electrode 5B, and the one electrode 5A adsorbed on the self-assembled monolayer 6
- the metal nanoparticles 7 disposed between the other electrode 5B and the self-assembled monolayer 6 and the metal nanoparticles 7 are embedded on the first insulating film 2, one electrode 5A and the other electrode 5B.
- a second insulating layer 8 provided in such a manner, and a gate electrode 21 provided on the second insulating layer 8 directly above the metal nanoparticles 7 and straddling the one electrode 5A and the other electrode 5B, Consists of.
- the second insulating layer 8 is deposited in the same manner as the single electronic device 10 of the first embodiment, and then a resist is applied,
- the gate electrode 21 is formed by drawing a pattern of the gate electrode 21 by a beam lithography technique or optical lithography, and forming one or two kinds of metal layers after development. In that case, it is better to provide an adhesion layer.
- the electrode material may be copper as the initial electrode material.
- the initial electrode a copper electrode is formed by using an electron beam lithography method or an optical lithography method, and then the surface of the copper electrode is made of copper chloride. Thereafter, a gold chloride solution using ascorbic acid as a reducing agent is used as a plating solution, and the copper electrode surface is covered with gold.
- a surfactant alkyltrimethylammonium bromide C n H 2n + 1 [CH 3 ] 3 N + ⁇ Br ⁇ is mixed with an aqueous solution of gold chloride (III), and the reducing agent L (+)-ascorbic acid is added.
- autocatalytic electroless gold plating is performed on the gap electrode.
- a nanogap electrode having a gold surface is prepared by molecular ruler plating.
- This integrated circuit is formed by forming an electronic device, for example, a diode, a tunnel element, a MOS transistor, etc. on a semiconductor substrate and then producing a single electronic element as a nanodevice according to the first and second embodiments. It is.
- FIG. 4 is a cross-sectional view of an integrated circuit according to the third embodiment of the present invention
- FIG. 5 is a plan view of the integrated circuit shown in FIG.
- the MOSFET 40 is provided on the Si substrate 31, and the single electronic element 50 as a nano device is provided at a position not overlapping the MOSFET 40 in plan view.
- FIG. 6 is a circuit diagram of the integrated circuit 30 shown in FIGS.
- a circuit 60 shown in FIG. 6 is called a universal literal gate circuit in which a single electronic element 61 and a MOSFET 62 are connected in series (see Non-Patent Document 5).
- a source 41 and a drain 42 which are reversely conductive with the substrate 31 are provided by partially diffusing impurities at intervals in a part of the substrate 31, for example, a p-type Si substrate.
- a source 41 and a drain 42 can be formed by providing a mask over the substrate 31 and diffusing impurities by thermal diffusion or ion implantation.
- the first insulating layer 43 is provided on the source 41, the drain 42, and the substrate 31, and the gate electrode 44 is provided at a predetermined height from the substrate 31 in the first insulating layer 43.
- the gate electrode 44 of the MOSFET 40 is formed on the lower part 43A of the first insulating layer 43 by an electron beam evaporation method or the like.
- the upper first insulating layer 43B may be formed on the gate electrode 44 and the lower portion 43A of the first insulating layer 43.
- a via 46 is formed by providing a contact hole through the first insulating layer 43 so as to penetrate the source 41 and filling the electrode material.
- the lower end of the via 46 connected to the source 41 becomes the source electrode.
- only the lower portion of the via 45 may be formed by providing a contact hole penetrating the drain 42 with the first insulating layer 43 and filling the electrode material.
- the single electronic device 50 according to the first and second embodiments described above is provided on the first insulating layer 43. That is, the source electrode 51 and the drain electrode 52 are provided on the first insulating layer 43 so as to have a nanogap, and the self-assembled monomolecular film (not shown) is interposed on the source electrode 51 and the drain electrode 52 so that the metal nano Particles 53 are provided as ligands. The method has already been described. At this time, the upper end of the via 46 is made to be one end of the drain electrode 52.
- the second insulating layer 54 is provided on the first insulating layer 43 and on the source electrode 51 and the drain electrode 52 of the single-electron element 50, and the second insulating layer 54 is a self-organized single layer. A molecular film and metal nanoparticles 53 are embedded.
- the gate electrode 55 of the single electron element 50 is provided on the second insulating layer 54 and above the metal nanoparticles 53. At this time, the gate electrode 55 is formed not to be parallel to the arrangement direction of the source electrode and the drain electrode of the MOSFET 40 or the single electron element 50 but to intersect, if possible, orthogonally. This is to reduce the parasitic capacitance.
- the source 41 of the MOSFET 40 and the drain electrode 52 of the single-electron element 50 are connected via the via 46 by filling the contact hole of the first insulating layer 43 with the electrode material.
- the lower end side of 46 functions as the source electrode 47.
- a MOSFET 40 and a single electronic element 50 are connected in series.
- Each gate electrode is arranged separately in the vertical direction in a direction intersecting with the arrangement direction of the source and drain.
- the gate electrode 44 of the MOSFET 40 is wired by a via 48 formed by filling the contact hole formed in the upper first insulating layer 43B and the second insulating layer 54 with an electrode material, and is externally provided on the second insulating layer 54. It can be taken out as a wiring for connection.
- a drain electrode of the MOSFET 40 is formed by a via 45 penetrating through the first and second insulating layers 43 and 54.
- the source electrode 51 of the single electronic element 50 is connected to the wiring on the second insulating layer 54 through the via 49.
- the drain electrode 52 of the single-electron element 50 and the MOSFET 40 source electrode 47 are connected via a via 46 provided in the first insulating layer 43.
- an electronic device such as MOSFT 40 is formed on the semiconductor substrate 31, the electronic device is covered with the first insulating layer 43, and the via 46 is formed in the first insulating layer 43.
- the single electronic device 50 is formed on the first insulating layer 43, and one control electrode of the single electronic device 50 and one control electrode of the electronic device 40 are connected to each other. Wiring is connected by vias 46.
- one control electrode of the single electronic device 50 is a drain electrode
- one control electrode of the electronic device 40 is a source electrode, but the reverse configuration may be used.
- the other control electrodes of the single electronic device 50 and the other electrodes of the electronic device 40 are formed on the second insulating layer 43 by vias 45, 48, 49 provided in the first and second insulating layers 43, 54, respectively. Can be wired. Thereby, the electric signal of each element can be input and output.
- the nanodevice is a single electron element, and the metal nanoparticle 7 and the nanogap electrode 5A, although the case where the SAM mixed film 9 made of a self-assembled monomolecular film and alkanethiol is provided between 5B and 5B has been described, the following form may be adopted.
- FIG. 7 is a cross-sectional view of a single-electron element as a nanodevice according to the fourth embodiment of the present invention.
- a part or all of the metal nanoparticles 7 are covered with an insulating film 71 of several to several tens of nanometers.
- the nanogap electrode 5A and the metal nanoparticle 7 are connected via an insulating film 71, and the metal nanoparticle 7 and the nanogap electrode 5B are connected via an insulating film 71.
- a tunnel current flows between the nanogap electrode 5A and the nanogap electrode 5B via the metal nanoparticles 7 due to the thin insulating film 71.
- FIG. 8 is a cross-sectional view of a molecular element as a nanodevice according to the fifth embodiment of the present invention.
- the nanodevice 80 is not a metal nanoparticle 7 but a functional molecule 81. That is, the functional molecule 81 is disposed between the nanogap electrode 5A and the nanogap electrode 5B. At this time, the nanogap electrodes 5A and 5B and the functional molecule 81 are insulated.
- the functional molecule 81 include molecules and oligomers having a ⁇ -conjugated skeleton. Such a molecular element can also be produced by the same method as that of the already described single electron element.
- FIG. 9 is a plan view of the single electron transistor fabricated in Example 1, and FIG. 10 is a cross-sectional view thereof.
- a single electron transistor as the single electronic element 10 according to the first embodiment was manufactured as follows.
- a SiO 2 film is produced as a first insulating layer 2 on the Si substrate 1 by a thermal CVD method, gold nanogap electrodes 5A and 5B are formed thereon, and octanethiol and decane as self-assembled monomolecular films.
- Gold nanoparticles 7 were disposed between the gold nanogap electrodes using a mixed film of dithiols.
- a SiN passivation layer was formed as the second insulating layer 8 on the single-electron transistor thus manufactured, that is, on the gold nanogap electrodes 5A and 5B and the SiO 2 film 2.
- the formation of the SiN passivation layer was performed as follows.
- the produced single-electron transistor was introduced into a vacuum chamber, and temperature control was performed so that the temperature of the single-electron transistor would not exceed 65 ° C. by water cooling.
- silane gas, ammonia gas and hydrogen gas were introduced into the vacuum chamber, and a SiN layer was deposited by catalytic CVD.
- the passivation layer of SiN was cooled so as not to exceed 65 ° C.
- the passivation layer may be deposited at 180 ° C. or lower, but the sample is cooled so that the temperature during the deposition is as low as possible, preferably 65 ° C. or lower.
- FIG. 11 is a diagram showing the drain current-side gate voltage dependency. The horizontal axis is the voltage Vg1 (V) applied to the first side gate, and the vertical axis is the drain current (A). FIG. 11 shows that the drain current can be modulated by the side gate voltage.
- FIG. 12 is a diagram showing the mapping of differential conductance when the drain voltage and the side gate voltage are swept, respectively.
- the horizontal axis represents the voltage Vg1 (V) applied to the first side gate
- the vertical axis represents the drain voltage Vd (V)
- the shade indicates the differential conductance of the drain current (A).
- the measurement temperature was 9K. It was found that a parallelogram-shaped voltage region called so-called Coulomb diamond due to suppression of the drain-source current was observed. From this, it was found that the device produced in Example 1 was operating as a single electron transistor.
- FIG. 13 shows characteristics of the sample manufactured in Example 1, (A) shows the drain current Id when the drain voltage Vd is applied, and (B) shows the drain with respect to the voltage Vg1 applied to the first side gate. It is a figure which shows the electric current Id.
- the horizontal axis is the drain voltage Vd (V)
- the left vertical axis is the drain current Id (nA) when SiNx is deposited as the passivation film
- the right vertical axis is the SiNx depositing as the passivation film. This is the previous drain current Id (pA).
- the horizontal axis is the voltage Vg1 (V) applied to the first side gate
- the left vertical axis is the drain current Id (pA) when SiNx is deposited as a passivation film
- the right vertical axis is A drain current Id (pA) before depositing SiNx as a passivation film.
- the measurement temperature was 9K.
- FIG. 13A shows that the drain current is increased by depositing SiNx.
- the relative dielectric constant of the deposited SiNx was 7.5 according to the capacitance measurement when an AC voltage was applied to the capacitance in which the SiNx was sandwiched between the opposing electrodes.
- the Coulomb blockade effect could be confirmed.
- FIG. 14 is a plan view of the single electron transistor fabricated in Example 2, and FIG. 15 is a cross-sectional view thereof.
- the gold nanoparticle 7 is disposed between the gold nanogap electrodes 5A and 5B, and the SiN passivation layer is formed as the second insulating layer 8 on the upper portion, thereby the single electron transistor.
- a resist was applied on the single electron transistor, and an electrode pattern was drawn immediately above the gold nanogap portion by electron beam lithography. After development, a Ti layer 30 nm and an Au layer 70 nm were sequentially deposited by electron beam evaporation. As a result, the top gate electrode 21 was disposed directly above the gold nanogap via the SiN layer as the second insulating layer 8.
- FIG. 16 shows the measurement result of the drain current-top gate voltage dependency.
- the horizontal axis represents the voltage (V) of the top gate electrode, and the vertical axis represents the drain current Is (A). As shown in FIG. 16, it was found that the drain current can be modulated by the side gate voltage.
- FIG. 17 is a diagram showing the mapping of differential conductance when the drain voltage and the side gate voltage are respectively swept.
- the horizontal axis represents the voltage (V) applied to the top gate
- the vertical axis represents the drain voltage Vd (V)
- the shade indicates the differential conductance of the drain current (A).
- the measurement temperature was 9K.
- a voltage region of a parallelogram called so-called Coulomb diamond caused by suppression of the drain-source current is observed. From this, it can be seen that the device manufactured in Example 2 operates as a single electron transistor.
- FIG. 18 is a diagram showing the drain current with respect to the drain voltage in the sample produced in Example 2.
- FIG. The measurement temperature was 9K.
- the horizontal axis represents the drain voltage Vd (mV)
- the left vertical axis represents the drain current Id (pA)
- the right vertical axis represents the drain current Id (nA).
- the drain current before depositing SiNx as a passivation film is in the range of about ⁇ 100 pA, but the drain current after depositing SiNx is large in the range of ⁇ 400 pA, and the drain voltage at which the drain current Id does not flow.
- the width of Vd is also increased.
- the drain current is ⁇ 4 nA.
- Example 2 provided with a top gate, Coulomb diamond is clearer than Example 1.
- FIG. 19 shows the so-called Coulomb oscillation characteristics of the drain current depending on the top gate voltage.
- FIG. 19A shows the case where the measurement temperature is 9K and 80K
- FIG. 19B shows the case where the measurement temperature is 160K and 220K.
- the drain current repeatedly increases and decreases due to the insertion of the gate voltage.
- the zero current region is clearly observed in the gate voltage region of ⁇ 1.5 to 1.2V. It can be seen that as the measurement temperature increases to 80K, 160K, and 220K, the minimum value of the current when the gate voltage is inserted gradually increases.
- FIG. 20 is a diagram showing the differential conductance mapping, and (A), (B), (C), and (D) are cases where the measured temperatures are 40K, 80K, 160K, and 220K, respectively.
- the horizontal axis is the gate voltage, and the vertical axis is the drain voltage.
- Example 3 differs from Example 2 in that AlOx is deposited at room temperature as a passivation film and a top gate electrode is provided thereon.
- a pulsed laser deposition method was used for the deposition of AlOx.
- As the top gate a two-layer structure of a Ti layer and an Au layer is formed by using the EBL method.
- FIGS. 21A and 21D show the characteristics of the drain current with respect to the drain voltage.
- FIGS. 21B and 21E show the characteristics of the drain current with respect to the voltage applied to the side gate.
- FIGS. It represents dI / dV (nS) with respect to the side gate voltage and the drain voltage.
- (A) to (C) are characteristics before Al 2 O 3 is deposited, and (D) to (F) are characteristics after Al 2 O 3 is deposited.
- the measurement temperature was 9K. It can be seen that the current value is higher than when SiNx is deposited as the passivation film.
- the gate capacitance is e / ⁇ V (e is an elementary charge).
- FIG. 22 is a diagram showing characteristics when a gate to which a voltage is applied is one side gate, the other side gate, and a top gate.
- the measurement temperature was 9K.
- (A) to (C) are the drain current characteristics (Coulomb oscillation) with respect to the voltage applied to one side gate, the other side gate, and the top gate, respectively.
- (D) to (F) It is dI / dV (nS) (stability diagram) with respect to the drain voltage with respect to the voltage applied to the side gate, the other side gate, and the top gate, and the drain voltage. It was found that stable oscillation occurs as compared with the case where SiNx is used as the passivation film.
- FIG. 23 is an SEM image of a single-electron transistor being manufactured as Example 4. As shown in the SEM image of FIG. 23, after the gold nanoparticles 7 are disposed through the insulating film 6 at substantially the center of the top, bottom, left, and right in the plan view of the nanogap between the one electrode 5A and the other electrode 5B. Then, SiNx was deposited as a passivation film.
- FIG. 24 relates to Example 4,
- (A) and (B) show the dependency of the drain current on the voltage applied to the first side gate electrode and the dependency of the drain current on the voltage applied to the second side gate electrode, respectively. Both are measurements on samples before depositing SiNx.
- (C) shows the dependence of drain current on the voltage applied to the second side gate electrode, and
- (D) shows dI / dV (differential conductance) with respect to the second side gate voltage and drain voltage.
- (C) and (D) are measurements on the sample after depositing SiNx. In either case, the measurement temperature was 9K.
- the gate capacitance of the second side gate electrode 5D is slightly larger than that of the first side gate electrode 5C. However, unlike Example 5 described later, this is not a large difference. From this, it is considered that the gold nanoparticle 7 is located substantially at the center in the vertical direction of the nanogap in the SEM image, that is, substantially on the central axis of the one electrode 5A and the other electrode 5B. After passivation, Coulomb oscillation is observed for one period, and it can be seen that the gate capacitance is increased.
- Example 4 since the gold nanoparticle 7 is positioned at the center of the nanogap, the nanogap electrodes 5a and 5B have a high effect of surrounding the gold nanoparticle 7, and are deposited without being destroyed during the passivation process. It is thought.
- FIG. 25 is an SEM image of a single-electron transistor being manufactured as Example 5.
- the gold nanoparticles 7 are disposed with an insulating film interposed between the one electrode 5A and the other electrode 5B in the plan view of the nanogap on the left and right in the center. Later, SiNx was deposited as a passivation film. Other details are the same as in the other embodiments.
- FIG. 26 relates to the fifth embodiment.
- (A), (B), and (C) show the dependence of the drain current on the voltage applied to the first side gate electrode and the voltage applied to the second side gate electrode, respectively. It is a figure which shows dI / dV (differential conductance) with respect to the dependence of drain current, 2nd side gate voltage, and drain voltage, and all are the measurements in the sample before depositing SiNx.
- (D) is a figure which shows the dependence of the drain current with respect to the voltage applied to a 2nd side gate electrode, and is a measurement result in the sample after depositing SiNx. In either case, the measurement temperature was 9K.
- FIG. 26 shows the characteristics before and after passivation.
- the current increases gently between -4V and 4V.
- the peak of the maximum value of current is observed in the vicinity of ⁇ 3.5 V and 4.5 V, respectively, and one cycle of Coulomb oscillation is observed.
- the gold nanoparticle 7 is located in the vicinity of the second side gate electrode 5D, and the nanogap length is slightly larger than the nanoparticle, so that the Coulomb oscillation by the first side gate is also slightly observed.
- the current is constant after passivation. This indicates that the nanoparticles were destroyed by passivation, and a conduction path was formed between the electrodes due to the destruction of the core gold.
- Example 4 and Example 5 were compared, the following was found.
- the conductive path due to the destruction of the Au nanoparticles 7 due to passivation is likely to occur when the Au nanoparticles 7 are positioned downward in cross-sectional view between the nanogap electrodes, that is, located near the SiO 2 substrate.
- Au nanoparticles 7 are destroyed by passivation, gold as the core when gold nanoparticles 7 to SiO 2 is close to that as the support surface of SiO 2 surface, electrically connected to the transmission path is formed between the electrodes Sometimes.
- the Au nanoparticles 7 are in the center or upper side in a cross-sectional view, even if the Au nanoparticles are destroyed, they adhere to the surface of the nanogap electrode but there is no support surface, so that a conduction path is difficult to form.
- the gold nanoparticle 7 is placed on the insulating film on the lower side in the center of the left and right in the plan view of the nanogap between the one electrode 5A and the other electrode 5B. Then, SiNx was deposited as a passivation film. Thereafter, a top gate was disposed on the passivation film directly above the metal nanoparticles. Other details are the same as in the other embodiments.
- FIG. 27 relates to Example 6, and (A), (B), and (C) show the dependency of the drain current on the voltage applied to the top gate electrode, the first side gate electrode, and the second side gate electrode, respectively. , (D) shows dI / dV (differential conductance) with respect to the top gate voltage and the drain voltage, and (E) shows dI / dV (differential conductance) with respect to the first side gate voltage and the drain voltage.
- the measurement temperature was 9K.
- FIG. 27 confirms the coulomb oscillations of the top gate, the first side gate, and the second side gate after passivation, and the Coulomb oscillations of the top gate and the first side gate. From the Coulomb oscillation interval, the gate capacitance is the largest at the first side gate, and the gate capacitance becomes smaller in the order of the top gate and the second side gate. Since the gate capacity of the first side gate is larger than that of the top gate, the nanoparticles (Coulomb island) are located near the first side gate in the vicinity of the substrate of the nanogap electrode. For this reason, it is considered that the gate capacitance of the first side gate is larger than the gate capacitance of the top gate.
- the gap length is expected to be slightly larger than the particle size of the nanoparticles, and the first side gate is larger than the second side gate 2. It is suggested that gold nanoparticles exist at a position close to the substrate side and a position close to the substrate side. Thus, by comparing the gate capacitance, the shape of the nanogap electrode and the position of the nanoparticles existing between the nanogap can be known.
- metal nanoparticles or functional molecules are disposed between nanogap electrodes, and an insulating film is interposed between the metal nanoparticles and the nanogap electrodes, or these may be inorganic insulating layers. Can be covered. Therefore, a three-dimensionally integrated single unit is provided by providing a top gate electrode on the inorganic insulating layer, providing another transistor, or connecting to various electronic elements such as a CMOS circuit formed on a semiconductor substrate by wiring. Logic circuit elements including electronic transistors, memories, and sensor circuits can be manufactured.
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Abstract
Description
上記構成において、金属ナノ粒子に電圧を印加するためのゲート電極が、第2の絶縁層上に設けられている。
上記構成において、第2の絶縁層は、SiN、SiO、SiON、Si2O3、Si3N4、SiO2、Al2O3、MgOの何れかでなる。
上記構成において、一方の電極と金属ナノ粒子との間、他方の電極と金属ナノ粒子との間には絶縁膜が介在されており、絶縁膜が、無機材料又は有機材料からなる。
特に、パッシベーション膜を形成する際、絶縁層付き基板を冷却する。
特に、パッシベーション膜は、触媒CVD法、プラズマCVD法、光CVD法、パルスレーザー堆積法、原子層エピタキシー法、熱CVD法の何れかを用いて形成する。
2:第1の絶縁層
3A,3B,4A,4B:金属層
5A:ナノギャップ電極(一方の電極)
5B:ナノギャップ電極(他方の電極)
5C,5D:ゲート電極(サイドゲート電極)
6,6A,6B:自己組織化単分子膜
7:金属ナノ粒子
8:第2の絶縁層
9:自己組織化単分子混合膜(SAM混合膜)
9A:アルカンチオール
10,20:単電子素子
21:ゲート電極(トップゲート電極)
30,60:集積回路
40,62:MOSFET
50,61:単電子素子
31:基板
41:ソース
42:ドレイン
43:第1の絶縁層
43A:第1の絶縁層の下部
43B:第1の絶縁層の上部
44:ゲート電極
45,46,48,49:ビア
51:ソース電極
52:ドレイン電極
53:金属ナノ粒子
54:第2の絶縁層
55:ゲート電極
70,80:ナノデバイス
71:絶縁膜
81:機能分子
1)無電解メッキによりギャップ長を制御して電極対を形成することができ、そのようなナノギャップ電極は熱に対して安定であること。
2)無機絶縁物を堆積する際、金属ナノ粒子が配位分子により覆われ、ナノギャップ電極がSAMで覆われていることから電極表面を破壊しないこと。
3)単電子島(「クーロン島」とも呼ばれる。)として働く金属ナノ粒子が、ナノギャップ間にアンカー分子、例えばジチオール分子によって化学的に固定したこと。
図1(A)は本発明の第1の実施形態に係る単電子素子を模式的に示す断面図であり、(B)は単電子素子の平面である。第1の実施形態に係るナノデバイスとしての単電子素子10は、基板1と、基板1上に設けられた第1の絶縁層2と、第1の絶縁層2上にナノギャップ長を有するように設けられた一方の電極5A及び他方の電極5Bと、一方の電極5A及び他方の電極5Bに設けられた絶縁膜としての自己組織化単分子膜6と、自己組織化単分子膜6に吸着して一方の電極5Aと他方の電極5Bとの間に配置された金属ナノ粒子7と、第1の絶縁層2、一方の電極5A、他方の電極5B上で、自己組織化単分子膜6及び金属ナノ粒子7を埋設するように設けられた第2の絶縁層8と、からなる。
第1の絶縁層2は、SiO2 、Si3N4などにより形成される。
一方の電極5A及び他方の電極5Bは、Au、Al、Ag、Cuなどにより形成される。一方の金属5A及び他方の金属5Bは、密着層と金属層とを順に積層することにより形成されてもよい。ここで、密着層はTi、Cr、Niなどで形成され、金属層は密着層上にAu、Al、Ag、Cuなどの別の金属で形成される。
第2の絶縁層6は、SiN、SiO、SiON、Si2O3 、SiO2 、Si3N4 、Al2O3 、MgOなど、無機絶縁物により形成される。無機絶縁物は化学量論組成のものが好ましいが、化学量論組成に近いものであってもよい。
先ず、基板1上に第1の絶縁層2を形成する。
次に、分子定規無電解メッキ法によりナノギャップ電極5A,5Bと、サイドゲート電極5C,5Dを形成する。
第2の実施形態に係るナノデバイスとしての単電子素子20について説明する。図3(A)は第2の実施形態に係るナノデバイスとしての単電子素子を模式的に示す断面図であり、(B)はナノデバイスとしての単電子素子の平面図である。
次に、本発明の第3の実施形態に係る集積回路について説明する。この集積回路は、半導体基板上に電子デバイス、例えば、ダイオード、トンネル素子、MOSトランジスタなどを形成したあと、第1及び第2の実施形態に係るナノデバイスとしての単電子素子を作製して成るものである。
図7は、本発明の第4の実施形態に係るナノデバイスとしての単電子素子の断面図である。第4の実施形態では、ナノデバイス70が、第1乃至第3の実施形態とは異なり、金属ナノ粒子7の一部又は全部が数~数十nmの絶縁膜71で覆われている。ナノギャップ電極5Aと金属ナノ粒子7との間は絶縁膜71を介在して接続され、金属ナノ粒子7とナノギャップ電極5Bとの間は絶縁膜71を介在して接続されている。
図8は、本発明の第5の実施形態に係るナノデバイスとしての分子素子の断面図である。第5の実施形態では、ナノデバイス80が、第1乃至4の実施形態とは異なり、金属ナノ粒子7ではなく、機能分子81としている。すなわち、ナノギャップ電極5Aとナノギャップ電極5Bとの間に、機能分子81が配置される。その際、ナノギャップ電極5A,5Bと機能分子81とは絶縁されている。機能分子81としてはπ共役系骨格を有する分子、オリゴマーが挙げられる。このような分子素子も、既に説明した単電子素子の場合と同様な手法により、作製することができる。
図12は、ドレイン電圧及びサイドゲート電圧をそれぞれ掃引した際の、微分コンダクタンスのマッピングを示す図である。横軸は第1のサイドゲートに印加する電圧Vg1(V)であり、縦軸はドレイン電圧Vd(V)であり、濃淡がドレイン電流(A)の微分コンダクタンスを示す。測定温度は9Kとした。ドレイン・ソース間電流の抑制に起因した、いわゆるクーロンダイヤモンドと呼ばれる平行四辺形状の電圧領域が観察されていることが分かった。このことから実施例1で作製した素子が単電子トランジスタとして動作していることが分かった。
Claims (11)
- 第1の絶縁層と、
上記第1の絶縁層上にナノギャップを有するように設けられた一方の電極と他方の電極と、
上記一方の電極と上記他方の電極との間に配置された金属ナノ粒子と、
上記第1の絶縁層、上記一方の電極及び上記他方の電極の上に設けられ、上記金属ナノ粒子を埋設する第2の絶縁層と、
を備える、ナノデバイス。 - 第1の絶縁層と、
上記第1の絶縁層上にナノギャップを有するように設けられた一方の電極と他方の電極と、
上記一方の電極と上記他方の電極との間に配置された機能分子と、
上記第1の絶縁層、上記一方の電極及び上記他方の電極の上に設けられ、上記機能分子を埋設する第2の絶縁層と、
を備える、ナノデバイス。 - 前記第1の絶縁層上に、前記一方の電極と前記他方の電極との配置方向に対して交差する方向に一又は複数のゲート電極を備え、
上記ゲート電極が前記第2の絶縁層によって被覆されている、請求項1又は2に記載のナノデバイス。 - 前記金属ナノ粒子に電圧を印加するためのゲート電極が、前記第2の絶縁層上に設けられている、請求項1又は2に記載のナノデバイス。
- 前記第2の絶縁層は、SiN、SiO、SiON、Si3N4、SiO2、Al2O3、MgOの何れかでなる、請求項1又は2に記載のナノデバイス。
- 前記一方の電極と前記金属ナノ粒子との間、前記他方の電極と前記金属ナノ粒子との間には絶縁膜が介在されており、上記絶縁膜が、無機材料又は有機材料からなる、請求項1に記載のナノデバイス。
- 請求項1乃至6の何れかに記載のナノデバイスと電子デバイスとが半導体基板上に形成されてなる、集積回路。
- 電子デバイスが形成された半導体基板上に設けられた第1の絶縁層と、
上記第1の絶縁層上にナノギャップを有するように設けられた一方の電極と他方の電極と、
上記一方の電極と上記他方の電極との間に配置された金属ナノ粒子又は機能分子と、
上記第1の絶縁層、上記一方の電極及び上記他方の電極の上に設けられ、上記金属ナノ粒子又は機能分子を埋設する第2の絶縁層と、
を備え、
上記電子デバイスの複数の電極のうち一つが、前記第1の絶縁層に設けたビアを介して上記一方の電極に接続されている、集積回路。 - ナノギャップを有する一方の電極及び他方の電極を設けた絶縁層付き基板に金属ナノ粒子又は機能分子を配置し、
上記一方の電極、上記他方の電極及び上記絶縁層付き基板の上にパッシベーション膜を形成することで金属ナノ粒子又は機能分子を埋設する、ナノデバイスの製造方法。 - 前記パッシベーション膜を形成する際、前記絶縁層付き基板を冷却する、請求項9に記載のナノデバイスの製造方法。
- 前記パッシベーション膜は、触媒CVD法、プラズマCVD法、光CVD法、パルスレーザー堆積法、原子層エピタキシー法、熱CVD法の何れかを用いて形成する、請求項9に記載のナノデバイスの製造方法。
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US9595604B2 (en) | 2013-03-09 | 2017-03-14 | Japan Science And Technology Agency | Electronic element |
WO2016031836A1 (ja) * | 2014-08-29 | 2016-03-03 | 国立研究開発法人科学技術振興機構 | ナノデバイス |
JPWO2016031836A1 (ja) * | 2014-08-29 | 2017-08-17 | 国立研究開発法人科学技術振興機構 | ナノデバイス |
US10170547B2 (en) | 2014-08-29 | 2019-01-01 | Japan Science And Technology Agency | Nanodevice |
Also Published As
Publication number | Publication date |
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CN104303313B (zh) | 2017-06-13 |
JP5674220B2 (ja) | 2015-02-25 |
CN104303313A (zh) | 2015-01-21 |
EP2822040B1 (en) | 2017-01-04 |
US20150014624A1 (en) | 2015-01-15 |
EP2822040A4 (en) | 2015-11-11 |
EP2822040A1 (en) | 2015-01-07 |
KR20140138787A (ko) | 2014-12-04 |
TW201344882A (zh) | 2013-11-01 |
TWI591801B (zh) | 2017-07-11 |
JPWO2013129535A1 (ja) | 2015-07-30 |
KR101985347B1 (ko) | 2019-06-03 |
US9240561B2 (en) | 2016-01-19 |
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