WO2016031836A1 - ナノデバイス - Google Patents
ナノデバイス Download PDFInfo
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- WO2016031836A1 WO2016031836A1 PCT/JP2015/073917 JP2015073917W WO2016031836A1 WO 2016031836 A1 WO2016031836 A1 WO 2016031836A1 JP 2015073917 W JP2015073917 W JP 2015073917W WO 2016031836 A1 WO2016031836 A1 WO 2016031836A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
Definitions
- the present invention relates to a nanodevice in which nanoparticles are provided between nanogap electrodes and the charge state of the nanoparticles is controlled.
- a device composed of a pair of electrodes facing each other so as to have a nanogap and arranging nanoparticles and molecules in the nanogap has a switching function and a memory function, and thus is promising as a new device.
- the present inventors assembled a single-electron transistor (SET) by introducing chemically synthesized gold nanoparticles into a nano-gap electrode produced by electroless gold plating, and operated at room temperature. (Non-patent Document 1).
- Non-Patent Document 4 reports a single-electron memory operation in a transistor having a structure in which a poly-Si ultrathin thin wire and a gate electrode cross each other through an oxide film.
- Poly-Si has a structure in which crystal grains of several nm are spread, and when a gate voltage is applied, the poly-Si crystal grains are filled with electrons, a percolation path is connected, and current flows between the source and drain. Begins to flow. Further, when a high voltage is applied as the gate voltage, electrons are trapped in the accumulation dots, and the conductance of the current path is changed by the Coulomb repulsion between the electrons, resulting in a memory effect.
- an object of the present invention is to provide a nanodevice capable of controlling the charge state of nanoparticles.
- a voltage applied to the floating gate is between a peak state voltage and a bottom state voltage of Coulomb oscillation.
- a gate voltage that provides a peak current in one cycle of coulomb oscillation and a gate voltage that provides an adjacent peak current The nanodevice according to [1], wherein values corresponding to both ends of a certain voltage section obtained by dividing the potential difference ⁇ V into two equal parts, three equal parts, or four equal parts are set.
- the plurality of gate electrodes include one or more side gate electrodes on the same surface as the nanogap electrode.
- the nanogap electrode and the nanoparticles are covered with an insulating layer,
- a control gate electrode is provided at a position facing the nanoparticles with the floating gate electrode interposed therebetween,
- the one electrode and the other electrode are arranged with the nanoparticles interposed therebetween, As the plurality of gate electrodes, the side gate electrode and the floating gate electrode are arranged across the nanoparticles, The nanodevice according to [1], wherein a control gate electrode is disposed so as to face the nanoparticles with the floating gate electrode interposed therebetween. [10] The nanodevice according to [9], wherein the one electrode, the other electrode, the side gate electrode, the floating gate electrode, and the control gate electrode are arranged on the same plane.
- the charge state of the nanoparticles can be arbitrarily controlled, and a multi-value memory can be configured with one nanodevice.
- a logic operation element that can be rewritten by one nanodevice can be configured. Therefore, according to the present invention, application to a power-saving single-electron flash memory and a logical operation element is expected.
- the drain voltage V d and the gate voltage V g1, V g2, V top -gate is a diagram schematically showing a differential conductance of the drain current I when set to each value.
- the first side gate voltage V G1 (V) is a diagram showing a drain current V D (mV) and differential conductance mapping (Stability diagram) when the second side gate voltage V G2 (V) is swept, respectively.
- FIG. 6A is a diagram illustrating the Coulomb oscillation characteristics, where FIG. 5A is the drain current I DS (pA) dependence on the voltage applied to the first side gate when the second side gate is set to 0 V, and FIG. The drain current I DS (pA) dependence on the voltage applied to the second side gate when is set to 0V is shown. It is the figure which expanded the origin vicinity of FIG. 11 (A). Voltage V G1 applied to the first side gate 25 mV, a diagram obtained by extracting the case of 95mV. Is a view showing a Coulomb oscillation characteristics in after the measurement shown in FIG.
- (A) is the drain current I DS (pA) dependence on the voltage applied to the first side gate when the second side gate to 0V
- (B) shows the drain current I DS (pA) dependence on the voltage applied to the second side gate when the first side gate is set to 0V. It is the figure which performed charge forming with the 1st side gate, and measured the Coulomb oscillation characteristic with the 2nd side gate voltage. The input dependence of the pulse width of the second side gate voltage is shown.
- (A), (B), and (C) show the cases where the pulse width is 5 seconds, 0.5 seconds, and 0.05 seconds, respectively.
- FIG. 1 It is a figure which shows the time dependence of the drain current at the time of performing charge forming with a side gate, a solid line shows the drain current of a nanodevice, and a broken line shows a side gate voltage.
- A), (B), (C) is a figure which respectively shows the Coulomb diamond characteristic with respect to three gate voltages in the nanodevice of FIG. It is a figure showing that a pulse train is applied with respect to three gate voltages, and a nano device shows XOR operation.
- the drain current V D (mV) and the differential conductance mapping when the first side gate voltage V FG (V) and the second side gate voltage V CG (V) are respectively swept ( It is a figure which shows a stability diagram.
- nanodevices prepared in Example 4 is a diagram showing a Coulomb oscillation when the gate electrode of the second input was swept independently, switch off in a state in which 0V is being applied to the (A) is, V FG
- the I DS -V CG characteristics when the floating gate electrode is in a floating state are shown
- (B) is a diagram showing the I DS -V FG characteristics when the voltage V CG is 0V.
- the nanodevice produced in Example 4 it is a figure which shows the time dependence of an electric current when the voltage of the charge forming of a floating electrode is set to 30mV, 45mV, and 100mV as a floating gate.
- (B) is the figure which plotted the differential value of the drain current after 20V pulse application to a control gate on the two-dimensional plane of a drain voltage and a side gate voltage. It is a figure which shows the change of the drain current accompanying the repeated input of a write signal and an erase signal.
- FIG. 2 shows one embodiment of the nanodevice shown in FIG. 1, (A) is a cross-sectional view, and (B) is a plan view.
- the nanodevice 10 includes a substrate 1, an insulating layer 2, a nanogap electrode 5 provided on the insulating layer 2, and a self-assembled monolayer 6 provided on the nanogap electrode 5.
- Metal nanoparticles 7 provided between the nano gaps with the self-assembled monolayer 6 interposed therebetween, and a plurality of gate electrodes provided on the insulating layer 2 so as to intersect the arrangement direction of the nano gap electrodes 5 9 (9A, 9B).
- the plurality of gate electrodes 9 are all side gate electrodes, and one of the side gate electrodes 9B functions as a floating gate electrode.
- the nanogap electrode 5 (5A, 5B) is composed of seed electrodes 3A, 3B composed of one or more layers and plating electrodes 4A, 4B.
- the at least one side gate electrode 9A among the plurality of gate electrodes 9 is connected by wiring so that a gate voltage can be applied. As shown in FIG. 1, one end of a switch 11 is connected to the other side gate electrode 9B, and a floating voltage Vf can be applied to the floating electrode so as to have a certain potential.
- the number of gate electrodes 9 is set by a combination of side gate electrodes 9A and 9B and a top gate electrode 9C provided on the insulating layer 2 so as to intersect with the arrangement direction of the nanogap electrodes.
- the numbers of the side gate electrodes 9A and 9B and the top gate electrode 9C are appropriately set according to the use of the nanodevice 10A.
- the second insulating layer 8 is formed on the nanogap electrode 5, the metal nanoparticles 7, and the side gate electrodes 9 ⁇ / b> A and 9 ⁇ / b> B, and the top gate is formed on the second insulating layer 8.
- An electrode 9C is formed.
- the bottom gate electrode 9D is formed on the substrate 1, and a potential can be applied by the substrate 1.
- at least one of the plurality of gate electrodes 9 is used as a floating gate electrode.
- the drain current becomes a different value. Therefore, as shown in FIG. 4B, by setting the gate voltage within a certain range of, for example, 1 (V) to 4 (V), a drain current corresponding to the range flows. Therefore, a plurality of states can be held according to the value of the floating gate voltage Vf.
- the nanodevice according to the embodiment of the present invention includes an input gate used as a signal input terminal among the plurality of gates 9 and a control gate for applying a floating voltage for performing a rewrite operation. By applying a voltage to the control gate, the charge state of the nanoparticles is changed and the operation of the single electron transistor is reversed.
- Various logic operation processes such as XOR and XNOR are realized by using three input gates, for example.
- e is an elementary charge.
- the value of ⁇ V depends on the arrangement relationship between the metal nanoparticles and one electrode and the other electrode, and also the arrangement relationship between the two side gate electrodes and the top gate electrode and / or the bottom gate electrode. Therefore, the value of ⁇ V is dependent on the arrangement of the three gate electrodes, each three gate electrodes, the value of ⁇ V which corresponds to one cycle of the Coulomb oscillation of the drain current I d is different.
- the bottom column of the logical correspondence table shows the Coulomb oscillation for one cycle (the horizontal axis is the gate voltage, the vertical axis is the drain current), and the black circle ( ⁇ ) indicates the current output state of “0”, the white circle ( ⁇ ) indicates a current output state of “1”.
- a potential difference of ⁇ V / 2 is used as a potential difference corresponding to a state of “0” and “1” of the input gate voltage, and the input is “0” side and the output is “0”.
- the voltage region in the left half of the Coulomb oscillation for the period is used as a voltage to be applied to each gate electrode.
- the top gate voltage and one side gate voltage are input as “0”, and ⁇ V is set to four values as the value of the other side gate voltage corresponding to the input of “0”.
- ⁇ V is set to four values as the value of the other side gate voltage corresponding to the input of “0”.
- the gate voltage is set to a voltage value higher by ⁇ V / 4 than the set voltage value.
- the input gate voltage is set so that the three gate voltages are gate voltages corresponding to the input of “1” and the output has a current peak value of “1”. Then, the output becomes “1” only when the inputs to the three gates are (0, 0, 0) and (1, 1, 1), otherwise the output becomes “0”, and the operation A Processing is done.
- the gate voltage corresponding to operation C is set as follows. That is, for example, the top gate voltage corresponding to the input of “1” is divided into four equal parts of ⁇ V so that the positive current value of the peak current is the same on the positive and negative slopes of the peak current of the Coulomb oscillation. The voltage value on the slope is set, and the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set to be equal to four as the value of the one side gate voltage corresponding to the “1” input.
- a value that is 3/4 times higher than ⁇ V is set to the voltage value on the positive slope of the peak current so that the divided value becomes the same current value on the positive and negative slopes of the peak current of Coulomb oscillation.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 4 than the set voltage value.
- the top gate voltage and one side gate voltage are set to “0” input, the value of the other side gate voltage corresponding to the input “1” is set, and ⁇ V is divided into four equal parts.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower than the set voltage value by ⁇ V / 4.
- the gate voltage corresponding to operation D is set as follows. For example, as a top gate voltage corresponding to an input of “0”, a value obtained by dividing ⁇ V into four equal parts on the positive slope of the peak current so that the same current value is obtained on the positive and negative slopes of the peak current of the Coulomb oscillation. And the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 4 than the set voltage value. When "1" is input, the current value is the same as the same current value with a negative slope.
- the following operations can also be performed on nanodevices. That is, when ⁇ V / 3 is used as a voltage difference between input “0” and input “1” and two gate voltages having a voltage difference of ⁇ V / 3 are added, a positive slope before the current peak of Coulomb oscillation is obtained. The drain voltage is adjusted so that the same current value is shown in the middle of the negative slope after the peak.
- the top gate voltage and one side gate voltage are set to “0” inputs, and ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- the voltage value on the positive slope of the peak current is set so that the equally divided values are the same on the positive and negative slopes of the peak current of the Coulomb oscillation, and the top corresponding to the input of “1”
- the gate voltage is set to a voltage value higher by ⁇ V / 3 than the set voltage value.
- the gate voltage corresponding to operation F is set as follows. For example, as a top gate voltage corresponding to an input of “0”, the value obtained by dividing ⁇ V into three equal parts has the same current value on the positive and negative slopes of the peak current of the Coulomb oscillation, on the negative slope of the peak current. The voltage value is set, and the top gate voltage corresponding to the input of “1” is set to a voltage value higher by ⁇ V / 3 than the set voltage value.
- the top gate voltage is set to the previously determined “0” input, and ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- ⁇ V is set as the third value as the value of the one side gate voltage corresponding to the “0” input.
- the top gate voltage and one side gate voltage are set to “0” inputs, and ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- ⁇ V is set to three as the value of the other side gate voltage corresponding to the “0” input.
- the gate voltage corresponding to operation G as follows.
- the top gate voltage corresponding to the input of “1” is set as follows. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the top gate voltage is set to the input of “0” determined previously, and the value of one side gate voltage corresponding to the input of “1” is set as follows. To do. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the other side gate voltage is set by setting the top gate voltage and one side gate voltage as “0” inputs, and setting the value of the other gate voltage corresponding to the “1” input as follows. To do. ⁇ V is divided into three equal parts so that the value obtained by dividing ⁇ V into three equal parts has the same value on the positive and negative slopes of the peak current of the Coulomb oscillation, and is set to a value on the positive slope of the peak current.
- the top gate voltage corresponding to the input of “0” is set to a voltage value lower by ⁇ V / 3 than the set value.
- the potential difference between High and Low for example, the voltage difference between “0” and “1” is ⁇ V / n, and n is set to an integer of 2 or more to set 3 Input logical operation processing can be realized.
- the nanodevice according to the embodiment of the present invention performs various logical operation processes, the remaining gate electrode that is not used as a three-input gate electrode among the plurality of gate electrodes is used as a floating gate electrode, similarly to the inversion process in XOR.
- the floating gate electrode is shifted to the + side or the ⁇ side by the magnitude of the voltage half the peak-to-peak voltage of the Coulomb oscillation of the floating gate electrode, and the switch is turned off to induce charge in the floating gate. This induced charge reverses the charge state of the metal nanoparticles.
- Such a floating gate realizes a logic operation element that can be rewritten by a nanodevice.
- the voltage applied to the floating gate does not need to be a voltage half the peak-to-peak voltage of Coulomb oscillation, and may be a voltage necessary to invert the charge state of the metal nanoparticles.
- the factors that determine the voltage applied to the floating gate are as follows: first, the arrangement relationship between the metal nanoparticles and the nanogap electrode, second, the arrangement relationship between the metal nanoparticles and each gate electrode, and third, the floating gate of the gate. Whether the top gate is used or the bottom gate is used, and fourth, the thickness of the second insulating layer and the dielectric constant for providing the top gate are given. The influence of at least one of these factors receive.
- First step A first insulating layer 2 is formed on a semiconductor substrate 1. In order to form the bottom gate electrode 9D, the semiconductor substrate 1 is etched to leave a portion to be the bottom gate electrode 9D.
- Second step An adhesion layer that partially constitutes the seed electrodes 3A and 3B is formed on the first insulating layer 2.
- Third step An electrode pair and a side electrode pair are formed by an electroless plating method, and then the gap length is narrowed so that the gap length becomes a predetermined value by a molecular ruler electroless plating method as necessary.
- the nanogap electrode 5 having the seed electrodes 3A and 3B and the plating electrodes 4A and 4B is formed. Further, side gate electrodes 9A and 9B are formed during the second step and the third step.
- Cat-CVD Catalytic Chemical Vapor Deposition
- a nanodevice 20 according to an embodiment of the present invention includes a nanogap electrode 5 in which one electrode 5A and the other electrode 5B are provided so as to have a nanogap, and metal nanoparticles 7 provided between the nanogap, A plurality of gate electrodes 9, and at least one of the plurality of gate electrodes 9 functions as a floating gate electrode 9B.
- one electrode 5A corresponds to the source electrode
- the other electrode 5B corresponds to the drain electrode.
- the nanodevice 20 according to the embodiment of the present invention further includes a control gate 12 as shown in FIG.
- the control gate electrode 12 can be regarded as a kind of the gate electrode 9.
- the control gate electrode 12 is used to change the charge state of the floating gate electrode 9B by applying a voltage, thereby controlling the charge state of the metal nanoparticles 7.
- the charge state of the floating gate electrode 9B is controlled by turning on / off the switch 11, whereas in the form shown in FIG. 8, the charge state of the floating gate electrode 9B is transferred to the floating gate electrode 12.
- the pulse voltage is controlled.
- the pulse width and voltage of the pulse voltage for changing the charge state of the floating gate electrode depend on the structure and material of the floating gate electrode, the control gate electrode, the source electrode, the drain electrode, and the back gate electrode made of the Si substrate. , Depending on the capacitance and the resistance when a voltage is applied.
- the floating gate electrode has a capacitance between each of the control gate electrode, source electrode, drain electrode, and back gate electrode. When a pulse voltage is applied to the control gate electrode, each capacitance A potential difference corresponding to From the electrode having the lowest resistance to the floating gate electrode, a charge that makes the potential difference with the electrode zero flows from the electrode to the floating gate electrode, and as a result, a charge is induced in the floating gate electrode. Become.
- Ti and Au were deposited on the developed substrate by electron beam deposition.
- An initial gold nanogap electrode having a gap length of 25 nm was produced by immersing the substrate in ZDMAC (manufactured by Nippon Zeon) and lifting off the resist. Thereafter, a contact pad for taking an electrical contact between the prober and the nanogap electrode was produced by photolithography and deposition of Ti and Au.
- FIG. 11 is a diagram showing the Coulomb oscillation characteristics, where (A) shows the drain current I DS (pA) dependence on the voltage applied to the first side gate when the second side gate is set to 0 V, and (B) shows The drain current I DS (pA) dependence on the voltage applied to the second side gate when the first side gate is set to 0V is shown.
- the drain voltage V D was 5 mV. It was found that periodic Coulomb oscillation was observed corresponding to the gate capacities C G1 and C G2 of the side gate electrodes with respect to Coulomb Island. From this point onward, V G1 is used as a floating gate voltage to adjust the charge state on the nanoparticles in a non-contact manner, and V G2 serves as a signal input terminal for observing Coulomb oscillation.
- FIG. 14 is a diagram showing the Coulomb oscillation characteristics after the measurement shown in FIG. 13, and FIG. 14A shows the drain current I DS () with respect to the voltage applied to the first side gate when the second side gate is set to 0V. pA) dependence, (B) shows the drain current I DS (pA) dependence on the voltage applied to the second side gate when the first side gate is set to 0V.
- the drain voltage V D was 5 mV.
- the first gate voltage V G1 30 mV becomes the High state
- V G1 100 mV becomes the Low state.
- the voltage applied to at least one of the gate electrodes is changed by the half period of the Coulomb oscillation, and the charge state of the metal nanoparticles is reversed by bringing the gate electrode into a floating state.
- the operation of the nanodevice 10 can be rewritten by using the gate electrode as a floating electrode.
- Example 2 Another embodiment relating to the nanodevice 10 shown in FIG. 2 will be described.
- the gold nanogap electrode 5 and the two side gate electrodes 9A and 9B were manufactured by the same manufacturing method as in Example 1.
- a self-assembled monolayer 6 and gold nanoparticles 7 were introduced into the gold nanogap electrode 5 by the following procedure. First, the electrode was immersed in an ethanol solution of 1 mM octanethiol molecules for 24 hours and rinsed with ethanol. Thereafter, the electrode was immersed in an ethanol solution of 500 mM decanedithiol molecules for 24 hours, and the decanedithiol molecules were inserted into the octanethiol monomolecular film.
- FIG. 17 is a diagram showing the time dependence of the drain current when charge forming is performed by the side gate, where the solid line indicates the drain current of the nanodevice, and the broken line indicates the side gate voltage.
- the measurement temperature was 9K.
- the drain current-gate voltage dependency of this element is shown in FIG.
- the charge forming voltage Vf was increased stepwise by 1V from 0V to 4V, the drain current increased stepwise.
- the nanodevice operates as a multi-valued memory by charge forming. After about 300 seconds, the drain current value is almost 12 hours after the voltage application probe is retracted while the charge forming voltage Vf is kept at 4 V and the side gate electrode is left floating.
- FIG. 21A shows the I DS -V CG characteristics when the switch is turned off with 0 V applied to V FG and the floating gate electrode is brought into a floating state.
- FIG. 21B shows the voltage V CG set to 0 V. I D -V FG characteristics are shown. Coulomb oscillation corresponding to the stability diagrams of FIGS. 21 to 20 is clearly observed. It was found that ⁇ V on the floating gate electrode side was 150 mV, and ⁇ V on the control gate side was 730 mV.
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Abstract
Description
[1]ナノサイズのギャップを有するように一方の電極と他方の電極とが配置されて成るナノギャップ電極と、
上記ナノギャップ電極間に設けられるナノ粒子と、
複数のゲート電極と、を備え、
上記複数のゲート電極のうち少なくとも一つをフローティングゲート電極として用い、前記ナノ粒子の電荷状態を制御する、ナノデバイス。
[2]前記フローティングゲートに加える電圧は、クーロンオシレーションのピーク状態とボトム状態の電圧の間とする、前記[1]に記載のナノデバイス。
[3]前記フローティングゲートに加える電圧が、複数の階層に分かれることにより、前記一方の電極と前記他方の電極との間に流れる電流を段階的に異ならせる、前記[1]に記載のナノデバイス。
[4]前記フローティングゲートに加える電圧は、クーロンオシレーション特性のうち緩やかな傾き又は急峻な傾きの何れかを用いる、前記[3]に記載のナノデバイス。
[5]前記複数のゲート電極に印加される電圧のHighとLowの入力に相当する電位差として、一周期分のクーロンオシレーションにおけるピーク電流を与えるゲート電圧と、隣のピーク電流を与えるゲート電圧の電位差ΔVの二等分、三等分又は四等分した或る一つの電圧区間の両端に相当する値が設定される、前記[1]に記載のナノデバイス。
[6]前記複数のゲート電極は、前記ナノギャップ電極と同一の面に有る一又は複数のサイドゲート電極からなる、前記[1]乃至[5]の何れかに記載のナノデバイス。
[7]前記ナノギャップ電極と前記ナノ粒子が絶縁層により覆われており、
前記複数のゲート電極は、サイドゲート電極及びトップゲート電極からなる、前記[1]乃至[5]の何れかに記載のナノデバイス。
[8]さらに、前記フローティングゲート電極を挟んで前記ナノ粒子と対向する位置に、コントロールゲート電極を備えており、
前記コントロールゲート電極に電圧を印加することにより、前記フローティングゲート電極の電荷状態を変化させ、前記ナノ粒子の電荷状態を制御する、前記[1]に記載のナノデバイス。
[9]前記一方の電極と前記他方の電極とが前記ナノ粒子を挟んで配置されており、
前記複数のゲート電極として、前記サイドゲート電極と前記フローティングゲート電極とが前記ナノ粒子を挟んで配置されており、
前記フローティングゲート電極を挟んで、前記ナノ粒子と対向するようにコントロールゲート電極が配置されている、前記[1]に記載のナノデバイス。
[10]前記一方の電極、前記他方の電極、前記サイドゲート電極、前記フローティングゲート電極及び前記コントロールゲート電極が、同一面上に配置されている、前記[9]に記載のナノデバイス。
1:基板(半導体基板)
2:第1の絶縁層(絶縁層)
3A,3B:種電極(イニシャル電極)
4A,4B:メッキ電極
5:ナノギャップ電極
5A:一方の電極(ソース電極)
5B:他方の電極(ドレイン電極)
6:自己組織化単分子膜
7:金属ナノ粒子(金ナノ粒子)
8:第2の絶縁層(別の絶縁層)
9:ゲート電極
9A:サイドゲート電極
9B:サイドゲート電極(フローティングゲート電極)
9C:トップゲート電極
9D:ボトムゲート電極
11:スイッチ
12:コントロールゲート電極
本発明の実施形態に係るナノデバイスでは、フローティングゲート電極にフローティング電圧Vfを印加した後に、スイッチをOFFしても、フローティングゲートに蓄えられた電荷で、金属ナノ粒子の電荷の状態を記憶させておくことができる。後述する実施例で示すように、現状で12時間以上のリテンション特性が得られている。
本発明の実施形態に係るナノデバイスは、フローティングゲート電極に加える電圧により、金属ナノ粒子の電荷状態を段階的に異ならせることができ、その結果として、ナノギャップ電極間に流れる電流を段階的に異ならせることができる。よって、任意のゲート電圧を設定することにより、金属ナノ粒子の電荷状態を段階的に異ならせ、多数の状態を一つのメモリで表せ、多値メモリとして用いることができる。
本実施形態に係るナノデバイスでは、スイッチをON/OFFすることにより、フローティング状態を得ている。このスイッチの動作によって単電子トランジスタのメモリ動作に影響を与えない。
本発明の実施形態に係るナノデバイスでは、複数のゲート9のうち、信号入力端子として用いる入力ゲートと、書き換え動作を行うフローティング電圧を印加するためのコントロールゲートと、を備える。コントロールゲートに電圧を印加することでナノ粒子の電荷状態を換え、単電子トランジスタの動作を反転させる。入力ゲートを例えば3入力とすることにより、XOR,XNORなどの各種論理演算処理が実現される。
3つの入力ゲートを有するナノデバイスに対して排他的論理和(XOR:exclusive or)の動作をさせる場合には、各ゲート電圧の値を次のように設定すればよい。XOR動作では、3つの入力ゲートに印加される「0」の電圧と「1」の電圧の入力に相当する電圧の差が、ΔV/2(2分の1周期)に相当する電圧差となるようにドレイン電圧を調整する。そして、例えば「1」の入力に相当するトップゲート電圧を、クーロンオシレーションのピーク電流をとるゲート電圧とし、「0」の入力に相当するゲート電圧をΔV/2だけ小さい電圧値とする。トップゲート電圧は先に決めた「0」の入力にして、次に、一方のサイドゲート電圧は、ピーク電流をとるサイドゲート電圧を「1」の入力に相当するゲート電圧とし、「0」の入力に相当するゲート電圧をΔV/2だけ小さい電圧値とする。トップゲート電圧と一方のサイドゲート電圧を「0」の入力にして、さらに、他方のサイドゲート電圧は、ピーク電流をとるゲート電圧を「1」の入力に相当するゲート電圧とし、「0」の入力に相当するゲート電圧をΔV/2だけ小さい電圧値とする。その際、3つのゲート電圧が共に「1」の入力に相当するゲート電圧で、出力が「1」の電流ピーク値をとるように、入力のゲート電圧を設定する。
3つのゲート電極のいずれか1つのゲート電圧を「1」の状態とし、残りの2つのゲート電圧を「0」の状態とすると、ピーク電流が流れ、出力は「1」となる。
3つのゲート電極のなかで、いずれか2つのゲート電圧を「1」の状態とし、残り1つのゲート電圧を「0」の状態とすると、ゲート電圧による単電子島への電荷誘起の重畳が起こり、1周期分のΔVを印加した状態となるため、出力は「0」の状態となる。
3つのゲート電圧を「1」の状態とすると、1.5周期分のΔVを印加したことと等しいので出力は「1」となる。
図5の論理対応表のXORの列では、上述した出力電流の結果を示す。出力結果で、「0」は電流が流れない状態又は小さい状態を示し、「1」は電流が流れる状態又は大きい状態を示す。
論理対応表の最下欄には、1周期分のクーロンオシレーション(横軸はゲート電圧、縦軸がドレイン電流)を示しており、黒丸(●)印は「0」の電流出力状態、白丸(〇)印は「1」の電流出力状態を示している。XOR動作では、ΔV/2の電位差を入力ゲート電圧の「0」と「1」の状態に相当する電位の差として用い、入力が「0」側で出力が「0」であることから、1周期分のクーロンオシレーションの左半分の電圧領域を各ゲート電極に印加する電圧として用いている。
ナノデバイスに対して排他的論理和の否定(XNOR:exclusive not OR)の動作をさせる場合について説明する。この場合、各ゲート電圧の値を次のように設定すればよい。すなわち、XNOR動作では、XORと同様に「0」と「1」の状態の入力電圧の差が、ΔV/2に相当するゲート電圧差となるようにドレイン電圧を調整するが、3つのゲート電圧が共に「0」の入力に相当するゲート電圧で、出力が「1」の電流ピーク値をとるように、入力のゲート電圧を設定する。すると、XORと同様な動作原理により、このゲート電圧の設定で、XNORの論理演算を実現することができる。このことは、1周期分のクーロンオシレーションの図の右半分の電圧領域を各ゲート電極に印加する電圧として用いていることになる。
本発明の実施形態に係るナノデバイスが各種論理演算処理を行うため、XORでの反転処理と同様、複数のゲート電極のうち3入力のゲート電極として用いていない残りのゲート電極をフローティングゲート電極として用い、フローティングゲート電極のクーロンオシレーションのピークtoピークの電圧の半分の電圧の大きさ分+側又は-側にシフトさせ、スイッチをOFFとして、フローティングゲートに電荷を誘起する。この誘起した電荷によって金属ナノ粒子の電荷状態が反転する。このようなフローティングゲートにより、ナノデバイスによって書き換え可能な論理演算素子が実現される。
本発明の各実施形態に係るナノデバイスの作製方法について、図3に示すナノデバイスを例にとって説明する。
第1ステップ:半導体基板1上に第1の絶縁層2を形成する。なお、ボトムゲート電極9Dを形成するためには、半導体基板1をエッチングしてボトムゲート電極9Dとする部分を残しておく。
第2ステップ:第1の絶縁層2上に、種電極3A,3Bを部分的に構成する密着層を形成する。
第3ステップ:無電解メッキ法により電極対とサイド電極の対とを形成し、その後必要に応じて分子定規無電解メッキ法によりギャップ長が所定の値になるようにギャップ長を狭める。第2ステップ及び第3ステップにより、種電極3A,3Bとメッキ電極4A,4Bとを有するナノギャップ電極5が形成される。また、第2ステップ及び第3ステップの際にサイドゲート電極9A,9Bが形成される。
第4ステップ:図3に一点破線で示すように、保護分子で覆われた金属ナノ粒子7をナノギャップ間に導入し、Cat-CVD(Catalytic Chemical Vapor Deposition,触媒化学気相成長)法や光CVD法等を用いて第2の絶縁層8を形成する。その上でトップゲート電極9Cを形成する。
図8は、本発明の実施形態に係るナノデバイスの一形態を示し、(A)は断面図、(B)は平面図である。本発明の実施形態に係るナノデバイス20は、ナノギャップを有するように一方の電極5Aと他方の電極5Bとを設けて成るナノギャップ電極5と、ナノギャップ間に設けられる金属ナノ粒子7と、複数のゲート電極9と、を備えており、複数のゲート電極9の少なくとも一つをフローティングゲート電極9Bとして機能させる。例えば、一方の電極5Aがソース電極に対応し、他方の電極5Bがドレイン電極に対応する。本発明の実施形態に係るナノデバイス20は、さらに、図8に示すように、コントロールゲート12を備えている。コントロールゲート電極12は、ゲート電極9の一種とみなすことができる。
実施例1として、図2に示すナノデバイス10を次の要領で作製した。
最初に、金ナノギャップ電極5を電子ビーム描画法(EBL:Electron Beam Lithography)により作製した。第1の絶縁層2としてSiO2膜が形成された半導体基板1のSi基板に対して、アセトン、エタノールによる超音波洗浄を行った。オゾン洗浄を行った後に、ポジ型レジストZEP-520aとZEP-a(共に日本ゼオン製)を1:2で混合した溶液をスピンコートにより塗布した。レジストを塗布した基板を180℃2分間ベーキングした後、この基板にEBL描画を行い、ZEP-520(日本ゼオン製)により現像を行った。現像後の基板に、電子ビーム蒸着によりTiとAuを蒸着した。基板をZDMAC(日本ゼオン製)に浸漬し、レジストをリフトオフすることにより、ギャップ長25nmの初期金ナノギャップ電極を作製した。その後、プローバーとナノギャップ電極の電気的な接点を取るためのコンタクトパッドをフォトリソグラフィー、TiとAuの蒸着により作製した。
図2に示すナノデバイス10に関する別の実施例を説明する。実施例1と同様な作製手法で、金ナノギャップ電極5および2つのサイドゲート電極9A,9Bを作製した。この金ナノギャップ電極5に以下の手順で自己組織化単分子膜6と金ナノ粒子7を導入した。まず、オクタンチオール分子1mMのエタノール溶液に電極を24時間浸漬させ、エタノールでリンスをした。その後、デカンジチオール分子500mMのエタノール溶液に電極を24時間浸漬させ、デカンジチオール分子をオクタンチオール単分子膜内に挿入した。これにより、オクタンチオールとデカンジチオールの混合した自己組織化単分子膜6を形成する。さらにエタノールでリンスした後、化学合成により作製したデカンチオール保護金ナノ粒子7のトルエン溶液に16時間浸漬させる。直径6.2nmの金ナノ粒子を、自己組織化単分子膜6中のデカンジチオール分子により金ナノギャップ電極5間に化学吸着させる。この素子にフローティングゲート電極を設け、電荷フォーミングにより素子をON/OFFできるようにした。これにより、実施例2としてのナノデバイス10を作製した。
3入力のXOR、XNORなどの論理回路動作に必要な、図3に示す3つの入力ゲートを有するナノデバイス10Aの実施例を説明する。まず実施例2と同様の作製手法で、2つの入力ゲートを有するナノデバイスを作製した。ナノデバイス動作確認後、Cat-CVD法を用いて第2の絶縁層8となるSi3N4層を50nmナノデバイス上に堆積させた。堆積プロセス時の基板温度は65℃程度とした。最後に、Si3N4層上にトップゲート電極9Cを設けた。金ナノギャップ電極5とサイドゲート電極9A,9Bを作製した時と同じ条件でEBLの重ね露光と電極蒸着を行い、金属ナノ粒子7の直上にトップゲート電極9Cを作製した。これにより、実施例3としてのナノデバイス10Aを作製した。
実施例1と似通った作製方法で2つの入力ゲートを有する単電子トランジスタを作製した。実施例1と同様な作製方法で、金ナノギャップ電極5および2つのサイドゲート電極9を作製した。この金ナノギャップ電極に以下の手順で自己組織化単分子膜6と金ナノ粒子7を導入した。まず、ヘキサンチオール分子0.1mMのエタノール溶液に電極を15時間浸漬させ、エタノールでリンスをした。これにより、ヘキサンチオールの自己組織化単分子膜6を形成する。さらにエタノールでリンスした後、化学合成により作製したオクタンチオールとデカンジチオールが混合した保護基を有する金ナノ粒子7のトルエン溶液に0.5時間浸漬させる。直径8.2nmの金ナノ粒子を、金ナノ粒子7中のデカンジチオール分子により金ナノギャップ電極5間に化学吸着させる。この素子にフローティングゲート電極を設け、電荷フォーミングにより素子をON/OFFできるようにした。これにより、実施例4としてのナノデバイス10を作製した。
実施例5として、図8に示すコントロールゲート電極12を備えたナノデバイス20を次の要領で作成した。SiO2層を設けたSi基板上に、電子線描画法及び電子線蒸着法を用いて、ナノギャップ電極5、フローティングゲート電極9B、コントロールゲート電極12及びサイドゲート電極9Aを有する電極構造体を作製した。作製した電極構造体を、エタノール溶媒で濃度1mMのオクタンチオール溶液に12時間浸漬し、オクタンチオール自己組織化単分子膜を電極構造体の表面に作製した。その後、エタノール溶媒で濃度1mMのデカンジチオール溶液に12時間浸漬することでオクタンチオール分子を部分的にデカンジチオールに置換した混合自己組織化単分子膜の作製を行った。この試料をトルエン溶媒のAuナノ粒子溶液に浸漬することで、ナノギャップ電極間にAuナノ粒子を導入しナノデバイス20としてのフローティングゲート電極付き単電子トランジスタの作製を行った。図23は、実施例5で作製したナノデバイスのSEM像及び測定回路を示す図である。
Claims (10)
- ナノサイズのギャップを有するように一方の電極と他方の電極とが配置されて成るナノギャップ電極と、
上記ナノギャップ電極間に設けられるナノ粒子と、
複数のゲート電極と、を備え、
上記複数のゲート電極のうち少なくとも一つをフローティングゲート電極として用い、前記ナノ粒子の電荷状態を制御する、ナノデバイス。 - 前記フローティングゲートに加える電圧は、クーロンオシレーションのピーク状態とボトム状態の電圧の間とする、請求項1に記載のナノデバイス。
- 前記フローティングゲートに加える電圧が、複数の階層に分かれることにより、前記一方の電極と前記他方の電極との間に流れる電流を段階的に異ならせる、請求項1に記載のナノデバイス。
- 前記フローティングゲートに加える電圧は、クーロンオシレーション特性のうち緩やかな傾き又は急峻な傾きの何れかを用いる、請求項3に記載のナノデバイス。
- 前記複数のゲート電極に印加される電圧のHighとLowの入力に相当する電位差として、一周期分のクーロンオシレーションにおけるピーク電流を与えるゲート電圧と隣のピーク電流を与えるゲート電圧との電位差ΔVの二等分、三等分又は四等分した或る一つの電圧区間の両端に相当する値が設定される、請求項1に記載のナノデバイス。
- 前記複数のゲート電極は、前記ナノギャップ電極と同一の面に有る一又は複数のサイドゲート電極からなる、請求項1乃至5の何れかに記載のナノデバイス。
- 前記ナノギャップ電極と前記ナノ粒子が絶縁層により覆われており、
前記複数のゲート電極は、サイドゲート電極及びトップゲート電極からなる、請求項1乃至5の何れかに記載のナノデバイス。 - さらに、前記フローティングゲート電極を挟んで前記ナノ粒子と対向する位置に、コントロールゲート電極を備えており、
前記コントロールゲート電極に電圧を印加することにより、前記フローティングゲート電極の電荷状態を変化させ、前記ナノ粒子の電荷状態を制御する、請求項1に記載のナノデバイス。 - 前記一方の電極と前記他方の電極とが前記ナノ粒子を挟んで配置されており、
前記複数のゲート電極として、前記サイドゲート電極と前記フローティングゲート電極とが前記ナノ粒子を挟んで配置されており、
前記フローティングゲート電極を挟んで、前記ナノ粒子と対向するようにコントロールゲート電極が配置されている、請求項1に記載のナノデバイス。 - 前記一方の電極、前記他方の電極、前記サイドゲート電極、前記フローティングゲート電極及び前記コントロールゲート電極が、同一面上に配置されている、請求項9に記載のナノデバイス。
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