WO2014088201A1 - 발광 다이오드 및 그것의 어플리케이션 - Google Patents
발광 다이오드 및 그것의 어플리케이션 Download PDFInfo
- Publication number
- WO2014088201A1 WO2014088201A1 PCT/KR2013/009395 KR2013009395W WO2014088201A1 WO 2014088201 A1 WO2014088201 A1 WO 2014088201A1 KR 2013009395 W KR2013009395 W KR 2013009395W WO 2014088201 A1 WO2014088201 A1 WO 2014088201A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor layer
- layer
- transparent substrate
- conductive semiconductor
- light emitting
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05118—Zinc [Zn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05169—Platinum [Pt] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/0518—Molybdenum [Mo] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05559—Shape in side view non conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Definitions
- the present invention relates to light emitting diodes and their applications, and more particularly to flip chip type light emitting diodes having improved directivity angles and their applications.
- GaN-based LEDs Since the development of gallium nitride (GaN) -based light emitting diodes, GaN-based LEDs have been used in a variety of applications, including color LED display devices, LED traffic signals, backlight units, and lighting devices.
- GaN gallium nitride
- a gallium nitride-based light emitting diode is generally formed by growing epi layers on a substrate such as sapphire, and includes an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed therebetween. Meanwhile, an N-electrode pad is formed on the N-type semiconductor layer, and a P-electrode pad is formed on the P-type semiconductor layer.
- the light emitting diode is electrically connected to and driven by an external power source through electrode pads. At this time, current flows from the P-electrode pad to the N-electrode pad via the semiconductor layers.
- a flip chip type light emitting diode is used to prevent light loss caused by the P-electrode pad and to improve heat dissipation efficiency. Since the flip chip type light emitting diode emits light through the growth substrate, light loss caused by the P-electrode pad can be reduced compared to the light emitting diode having a horizontal structure emitting light through the epi layer. Furthermore, since the light emitting diode having a horizontal structure must transfer heat through a growth substrate such as a sapphire substrate, heat radiation efficiency is low. In contrast, the flip chip type light emitting diode transmits heat through the electrode pads, and thus has high heat dissipation efficiency.
- a light emitting diode having a vertical structure for removing a growth substrate such as sapphire from the epi layer has been developed.
- the light emitting diode having the vertical structure may prevent light loss due to total internal reflection by texturing the exposed surface of the semiconductor layer.
- the directing angle of the light source is an important concern.
- the light emitting diode of the flip-chip structure generally has a direction angle of about 120 degrees
- the light emitting diode of the vertical structure generally has a direction angle smaller than about 120 degrees by surface texturing. Accordingly, efforts have been made to increase the directing angle of light by using a molding part at a package level or by using a separately manufactured secondary lens.
- LEDs having different directivity angle characteristics depending on the direction may be required.
- the directing angle of the LEDs is large in a direction orthogonal to the rolling direction of the fluorescent lamp.
- An object of the present invention is to provide a flip chip type light emitting diode suitable for a backlight unit or a surface lighting device and an application thereof.
- Another object of the present invention is to provide a flip chip type light emitting diode which can improve light extraction efficiency by increasing reflectance.
- Another object of the present invention is to provide a flip chip type light emitting diode having improved current spreading performance.
- Another object of the present invention is to provide a light emitting diode having a different orientation angle characteristic according to a direction and a lighting device employing the same.
- Another object of the present invention is to provide a flip chip type light emitting diode having an improved luminous efficiency and a lighting device having the same.
- a light emitting diode comprising: a transparent substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- light generated in the active layer is emitted to the outside of the transparent substrate through the second surface of the transparent substrate.
- the light emitting diode has a directing angle of 140 degrees or more in at least one axial direction.
- the light emitting diode according to the present embodiments has a relatively wide direct angle of 140 degrees or more without using a lens-shaped molding member or a secondary lens. Therefore, it is suitable for illuminating devices, such as a backlight unit and a surface illuminating device.
- the light emitting diode according to the present embodiments may be directly applied to an application without performing a separate packaging process. Furthermore, the light emitting diode may be used without or in combination with a secondary lens.
- the light emitting diode may further include a conformal coating layer covering the second surface of the transparent substrate. Light emitted from the second surface is emitted to the outside of the conformal coating layer through the conformal coating layer.
- the conformal coating layer may contain phosphors and thus may wavelength convert at least some of the light generated in the active layer.
- the sum of the thicknesses of the transparent substrate and the conformal coating layer may have a value within the range of 225 ⁇ m to 600 ⁇ m. Further, the thickness of the transparent substrate may have a value within the range of 150 ⁇ m 400 ⁇ m. In addition, the thickness of the conformal coating may have a value within the range of 20 ⁇ m to 200 ⁇ m.
- the thickness of the transparent substrate may have a value in the range of 225 ⁇ m to 400 ⁇ m.
- a flip chip light emitting diode having a directivity angle of 140 degrees or more can be provided regardless of the presence or absence of a conformal coating layer.
- the thickness of the transparent substrate exceeds 400 ⁇ m, it is difficult to separate the substrate into individual light emitting diode chips.
- the light emitting diode may further include a plurality of mesas spaced apart from each other on the first conductivity type semiconductor layer. Each mesa includes the active layer and the second conductive semiconductor layer.
- the light emitting diodes may include: reflective electrodes positioned on the plurality of mesas and ohmic contact with a second conductive semiconductor layer; And openings covering the plurality of mesas and the first conductivity type semiconductor layer, the openings being located in the upper region of each mesa and exposing the reflective electrodes, ohmic contacting the first conductivity type semiconductor layer, and the plurality of mesas. It may further include a current spreading layer insulated from them. The first pad may be electrically connected to the current spreading layer, and the second pad may be electrically connected to the reflective electrodes through the openings.
- the current spreading layer covers the plurality of mesas and the first conductivity type semiconductor layer, the current spreading performance is improved through the current spreading layer.
- the first conductivity type semiconductor layer may be continuous.
- the plurality of mesas may have an elongated shape extending in parallel to each other in one direction. Openings of the current spreading layer may be located at the same end side of the plurality of mesas. Therefore, a pad connecting the reflective electrodes exposed to the openings of the current spreading layer can be easily formed.
- the current spreading layer may include a reflective metal such as Al. Accordingly, in addition to the light reflection by the reflective electrodes, the light reflection by the current spreading layer can be obtained, and thus, the light traveling through the plurality of mesas sidewalls and the first conductivity type semiconductor layer can be reflected.
- the reflective electrodes may each include a reflective metal layer and a barrier metal layer. Further, the barrier metal layer may cover the top and side surfaces of the reflective metal layer. As a result, the reflective metal layer can be prevented from being exposed to the outside, and deterioration of the reflective metal layer can be prevented.
- the light emitting diode includes: an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes; And a second pad disposed on the upper insulating layer and connected to the reflective electrodes exposed through the openings of the upper insulating layer.
- first pad and the second pad may be formed in the same shape and size, and thus flip chip bonding may be easily performed.
- the light emitting diode may further include a lower insulating layer positioned between the plurality of mesas and the current spreading layer to insulate the current spreading layer from the plurality of mesas.
- the lower insulating layer may have openings positioned in the upper mesas and exposing the reflective electrodes.
- each of the openings of the current spreading layer may have a wider width than the openings of the lower insulating layer so that all of the openings of the lower insulating layer are exposed. That is, sidewalls of the openings of the current spreading layer are located on the lower insulating layer.
- the light emitting diode may further include an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes. The upper insulating layer may cover sidewalls of the openings of the current spreading layer.
- the lower insulating layer may be a reflective dielectric layer, such as a distributed Bragg reflector (DBR).
- DBR distributed Bragg reflector
- a light emitting diode includes: a transparent substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- the light generated in the active layer is emitted to the outside through the second surface of the transparent substrate, the thickness of the transparent substrate has a value in the range of 225 ⁇ m to 400 ⁇ m.
- a light emitting diode comprising: a transparent substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; A second pad electrically connected to the second conductive semiconductor layer; And a conformal coating layer covering the transparent substrate.
- the light generated in the active layer is emitted to the outside through the conformal coating layer, the sum of the thickness of the transparent substrate and the conformal coating has a value in the range of 225 ⁇ m to 600 ⁇ m.
- the thickness of the transparent substrate may have a value within the range of 150 ⁇ m 400 ⁇ m.
- the thickness of the conformal coating may have a value within the range of 20 ⁇ m to 200 ⁇ m.
- An illumination module comprises a plurality of light emitting diodes, at least one light emitting diode having a first side, a second side and a side connecting the first side and the second side Board; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- light generated in the active layer is emitted to the outside of the transparent substrate through the second surface of the transparent substrate.
- the at least one light emitting diode has a directing angle of at least 140 degrees in at least one axial direction.
- the thickness of the transparent substrate may have a value within the range of 225 ⁇ m to 400 ⁇ m.
- the at least one light emitting diode may further include a conformal coating layer covering the second surface of the transparent substrate.
- the sum of the thicknesses of the transparent substrate and the conformal coating may have a value within the range of 225 ⁇ m to 600 ⁇ m.
- the thickness of the conformal coating may have a value within the range of 20 ⁇ m to 200 ⁇ m.
- a lighting device comprising a lighting module.
- the lighting module has a plurality of light emitting diodes including at least one light emitting diode as described above.
- a backlight unit includes a plurality of light emitting diodes, wherein at least one light emitting diode has a first surface, a second surface, and a side surface connecting the first surface and the second surface. Board; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- light generated in the active layer is emitted to the outside of the transparent substrate through the second surface of the transparent substrate.
- the at least one light emitting diode has a directing angle of at least 140 degrees in at least one axial direction.
- the thickness of the transparent substrate may have a value within the range of 225 ⁇ m to 400 ⁇ m.
- the at least one light emitting diode may further include a conformal coating layer covering the second surface of the transparent substrate, the sum of the thickness of the transparent substrate and the conformal coating has a value within the range of 225 ⁇ m to 600 ⁇ m Can have.
- the thickness of the conformal coating may have a value within the range of 20 ⁇ m to 200 ⁇ m.
- a light emitting diode comprising: a transparent substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- the light generated in the active layer is emitted to the outside of the transparent substrate through the second surface of the transparent substrate, the transparent substrate has a polygonal shape having at least one acute angle.
- the light extraction efficiency of the light emitting diode is improved, and the directivity angle characteristic of the light emitting diode can be adjusted. Therefore, it is possible to provide a light emitting diode having different directivity angle characteristics depending on the direction.
- the transparent substrate may have a thickness in the range of 100 ⁇ m to 400 ⁇ m.
- the polygonal shape having at least one acute angle may be a triangular shape, a parallelogram shape, or a pentagonal shape.
- the transparent substrate may be a sapphire substrate.
- the transparent substrate may have a parallelogram shape, and the side surface of the transparent substrate may be formed of an m plane group. Since the side surface of the transparent substrate is composed of the m surface group, the wafer can be scribed along the crystal surface of the m surface group, thereby preventing damage such as chipping during division into individual light emitting diodes.
- the light emitting diode may further include a reflective electrode positioned on the second conductive semiconductor layer to reflect light generated by the active layer.
- the light efficiency can be improved by reflecting light by the reflective electrode.
- the active layer and the second conductive semiconductor layer may be located in the upper region of the first conductive semiconductor layer so that the upper surface of the first conductive semiconductor layer is exposed along the edge of the substrate.
- the light emitting diode may further include a current spreading layer connecting the first pad and the first conductive semiconductor layer, wherein the first pad and the second pad are disposed on the second conductive semiconductor layer. Can be located. Accordingly, it is possible to reduce the height difference between the first pad and the second pad, thereby facilitating flip chip bonding.
- the current spreading layer may include a reflective metal. In addition to the reflective electrode, light can be reflected by the current spreading layer, thereby further increasing the light efficiency of the light emitting diode.
- the light emitting diode may further include a lower insulating layer that insulates the current spreading layer from the reflective electrode.
- the lower insulating layer may have openings exposing the first conductive semiconductor layer, and the current spreading layer may be connected to the first conductive semiconductor layer through the openings.
- each of the openings may be disposed in an elongated shape along edges of the substrate.
- the openings may be farther away from the at least one acute angle than the other angles. Accordingly, concentration of current in the acute angle portion can be alleviated.
- the openings may include a plurality of holes spaced apart from each other along an edge of the substrate.
- the spacing between the holes may increase as the at least one acute angle portion approaches. Accordingly, concentration of current in the acute angle portion can be alleviated.
- the side surface of the light emitting diode may be inclined such that the first surface has a larger area than the second surface.
- the inclined side further improves the light extraction efficiency.
- the light emitting diode may further include a conformal coating covering the second surface of the substrate.
- the sum of the thicknesses of the transparent substrate and the conformal coating may have a value within the range of 225 ⁇ m to 600 ⁇ m, thereby increasing the directing angle of the light.
- an illumination device comprising a plurality of light emitting diodes.
- At least one of the light emitting diodes includes: a transparent substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first conductivity type semiconductor layer on the first surface of the transparent substrate; A second conductivity type semiconductor layer on the first conductivity type semiconductor layer; An active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; A first pad electrically connected to the first conductive semiconductor layer; And a second pad electrically connected to the second conductivity type semiconductor layer.
- the light generated in the active layer is emitted to the outside of the transparent substrate through the second surface of the transparent substrate, the transparent substrate has a polygonal shape having at least one acute angle.
- a light emitting diode includes: a first conductivity type semiconductor layer disposed on a first surface of a substrate having a first surface and a second surface opposite to the first surface; A mesa having an active layer and a second conductive semiconductor layer sequentially stacked on the first conductive semiconductor layer, the planar shape is a polygon having an acute angle and an obtuse angle, and the first conductive semiconductor layer is exposed to the outside thereof.
- Mesa A lower portion covering the mesa and having a plurality of first openings exposing the first conductive semiconductor layer adjacent to outer sides of the mesa and a second opening exposing an upper surface of the second conductive semiconductor layer.
- the distance between the first openings adjacent to the acute angle of the mesa is greater than the distance between the first openings adjacent to the obtuse angle of the mesa.
- a flip chip type light emitting diode having a relatively wide orientation angle is provided. Therefore, it can be used suitably for a backlight unit or a surface illuminating device.
- the light emitting diodes having the wide directivity are arranged, the number of use of the light emitting diodes may be reduced or the backlight unit or the lighting module may be slimmed.
- a substrate having at least one acute angle it is possible to provide a flip chip type light emitting diode having improved luminous efficiency and having different directivity angle characteristics depending on the direction. Furthermore, by adopting such a light emitting diode, it is possible to provide a lighting device capable of illuminating a large area while reducing light loss.
- FIG. 1 to 5 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, (a) is a cross-sectional view taken along the cutting line A-A in (b) in each of the drawings.
- FIG. 6 is a plan view for explaining a modification of the mesa structure.
- FIG. 7 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
- FIG. 8 is a cross-sectional view for describing a light emitting diode according to still another embodiment of the present invention.
- 9 to 12 are graphs showing directivity of light emitting diodes at various substrate thicknesses.
- 13 is a graph showing the directivity angles of light emitting diodes according to the thickness of the substrate.
- 18 is a graph showing the directivity angles of light emitting diodes with conformal coating according to substrate thickness.
- 19 is a schematic cross-sectional view illustrating a light emitting diode module employing conventional light emitting diodes and a light emitting diode module employing light emitting diodes according to the present invention.
- FIG. 1 to 5 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, (a) is a cross-sectional view taken along the cutting line A-A in (b) in each of the drawings.
- a first conductivity type semiconductor layer 23 is formed on a substrate 21, and an active layer 25 and a second conductivity type semiconductor layer (on the first conductivity type semiconductor layer 23). 27) is located.
- the substrate 21 is a substrate for growing a gallium nitride-based semiconductor layer, and may be, for example, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, an indium gallium nitride substrate, an aluminum gallium nitride substrate, an aluminum nitride substrate, a gallium oxide substrate, or the like. In particular, it may be a sapphire substrate.
- the first conductive semiconductor layer 23 may be a nitride based semiconductor layer and may be a layer doped with n-type impurities.
- the first conductive semiconductor layer 23 may be a layer doped with Si in an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer.
- the first conductivity type semiconductor layer 23 may be a GaN layer doped with Si.
- the second conductivity-type semiconductor layer 27 is a nitride-based semiconductor layer and may be a layer doped with a p-type impurities.
- the second conductive semiconductor layer 27 may be doped with Mg or Zn in an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer. It may be a layer.
- the second conductivity-type semiconductor layer 27 may be a GaN layer doped with Mg.
- the active layer 25 may include a well layer of an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer, or a single quantum well structure or It may have a multi-quantum well structure.
- the active layer 25 may have a single quantum well structure of an InGaN, GaN or AlGaN layer, or a multi-quantum well structure in which layers such as InGaN / GaN, GaN / AlGaN or AlGaN / AlGaN are stacked.
- the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 may be formed using metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques.
- MOCVD metalorganic chemical vapor deposition
- MBE molecular beam epitaxy
- a plurality of mesas M spaced apart from each other may be formed on the first conductive semiconductor layer 23, and the plurality of mesas M may be the active layer 25 and the second conductive semiconductor layer 27, respectively. It may include.
- the active layer 25 is positioned between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27.
- the reflective electrodes 30 are located on the plurality of mesas M, respectively.
- the plurality of mesas M may include an epitaxial layer including the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 on the first surface of the substrate 21. After growing using a vapor phase growth method or the like, the second conductive semiconductor layer 27 and the active layer 25 may be patterned to expose the first conductive semiconductor layer 23. Sides of the plurality of mesas M may be formed to be inclined by using a technique such as photoresist reflow. The inclined profile of the mesa (M) side improves the extraction efficiency of the light generated in the active layer 25.
- the plurality of mesas M may have an elongated shape extending in parallel to each other in one direction as shown. This shape simplifies forming a plurality of mesas M of the same shape in the plurality of chip regions on the substrate 21.
- the reflective electrodes 30 may be formed on each mesa M after the plurality of mesas M are formed, but is not limited thereto.
- the second conductive semiconductor layer 27 may be grown and mesas. It may be formed in advance on the second conductivity-type semiconductor layer 27 before forming (M).
- the reflective electrode 30 covers most of the upper surface of the mesa M, and has a shape substantially the same as the planar shape of the mesa M.
- the reflective electrodes 30 may include a reflective layer 28 and may further include a barrier layer 29.
- the barrier layer 29 may cover the top and side surfaces of the reflective layer 28.
- barrier layer 29 can be formed to cover the top and side surfaces of reflective layer 28.
- the reflective layer 28 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, TiO / Ag layer.
- the barrier layer 29 may be formed of Ni, Cr, Ti, Pt, or a composite layer thereof, and prevents the metal material of the reflective layer from being diffused or contaminated.
- an edge of the first conductivity type semiconductor layer 23 may also be etched. Accordingly, the upper surface of the substrate 21 may be exposed. Side surfaces of the first conductive semiconductor layer 23 may also be formed to be inclined.
- the plurality of mesas M may be formed so as to be limitedly positioned inside the upper region of the first conductivity-type semiconductor layer 23. That is, the plurality of mesas M may be located in an island shape on the upper region of the first conductivity type semiconductor layer 23.
- mesas M extending in one direction may be formed to reach the upper edge of the first conductivity-type semiconductor layer 23. That is, the one side edge of the bottom surface of the plurality of mesas M coincides with the one side edge of the first conductivity type semiconductor layer 23. Accordingly, an upper surface of the first conductivity type semiconductor layer 23 is partitioned by the plurality of mesas M.
- a lower insulating layer 31 covering the plurality of mesas M and the first conductive semiconductor layer 23 is formed.
- the lower insulating layer 31 has openings 31a and 31b to allow electrical connection to the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 in a specific region.
- the lower insulating layer 31 may have openings 31a exposing the first conductivity type semiconductor layer 23 and openings 31b exposing the reflective electrodes 30.
- the openings 31a may be positioned near the edge between the mesas M and the edge of the substrate 21, and may have an elongated shape extending along the mesas M.
- the openings 31b are limited to the upper portion of the mesa M, and may be positioned to the same end side of the mesas.
- the lower insulating layer 31 may be formed of an oxide film such as SiO 2 , a nitride film such as SiNx, or an insulating film of MgF 2 using a technique such as chemical vapor deposition (CVD).
- the lower insulating layer 31 may be formed as a single layer, but is not limited thereto and may be formed as a multilayer.
- the lower insulating layer 31 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately stacked.
- DBR distributed Bragg reflector
- an insulating reflective layer having a high reflectance can be formed by laminating layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5 .
- a current spreading layer 33 is formed on the lower insulating layer 31.
- the current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23.
- the current spreading layer 33 has openings 33a located in the upper region of each mesa M and exposing the reflective electrodes 30.
- the current spreading layer 33 may be in ohmic contact with the first conductivity type semiconductor layer 23 through the openings 31a of the lower insulating layer 31. Meanwhile, the current spreading layer 33 is insulated from the plurality of mesas M and the reflective electrodes 30 by the lower insulating layer 31.
- the openings 33a of the current spreading layer 33 have a larger area than the openings 31b of the lower insulating layer 31, respectively, to prevent the current spreading layer 33 from connecting to the reflective electrodes 30. Have Thus, sidewalls of the openings 33a are located on the lower insulating layer 31.
- the current spreading layer 33 is formed over almost the entire area of the substrate 31 except for the openings 33a. Therefore, the current can be easily distributed through the current spreading layer 33.
- the current spreading layer 33 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni.
- a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer.
- the current spreading layer 33 may have, for example, a multilayer structure of Ti / Al / Ti / Ni / Au.
- an upper insulating layer 35 is formed on the current spreading layer 33.
- the upper insulating layer 35 has openings 35b exposing the current spreading layer 33 and openings 35b exposing the reflective electrodes 30.
- the opening 35a may have an elongated shape in a direction perpendicular to the longitudinal direction of the mesa M, and has a relatively large area compared to the openings 35b.
- the openings 35b expose the reflective electrodes 30 exposed through the openings 33a of the current spreading layer 33 and the openings 31b of the lower insulating layer 31.
- the openings 35b may have a smaller area than the openings 33a of the current spreading layer 33, and may have a larger area than the openings 31b of the lower insulating layer 31. Accordingly, sidewalls of the openings 33a of the current spreading layer 33 may be covered by the upper insulating layer 35.
- the upper insulating layer 35 may be formed using an oxide insulating layer, a nitride insulating layer, or a polymer such as polyimide, teflon, parylene, or the like.
- a first pad 37a and a second pad 37b are formed on the upper insulating layer 35.
- the first pad 37a connects to the current spreading layer 33 through the opening 35a of the upper insulating layer 35
- the second pad 37b connects the openings 35b of the upper insulating layer 35. It is connected to the reflective electrodes 30 through.
- the first pad 37a and the second pad 37b may be connected to bumps or used as pads for SMT in order to mount a light emitting diode to a submount, package, or printed circuit board.
- the first and second pads 37a and 37b may be formed together in the same process, for example, using photo and etching techniques or lift off techniques.
- the first and second pads 37a and 37b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au.
- the light emitting diode is completed by dividing the substrate 21 into individual light emitting diode chip units.
- the substrate 21 may be deformed to have a thinner thickness through a thinning process before being divided into individual LED chips.
- the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a first pad 37a, and a second pad 37b. It may include reflective electrodes 30, current spreading layer 33, lower insulating layer 31, upper insulating layer 35 and mesas (M).
- the substrate 21 may be a growth substrate for growing the gallium nitride-based epi layers, such as sapphire, silicon carbide, and gallium nitride substrate.
- the substrate 21 may include a first surface 21a, a second surface 21b, and a side surface 21c.
- the first surface 21a is a surface on which semiconductor layers are grown
- the second surface 21b is a surface on which light generated in the active layer 25 is emitted to the outside.
- the side surface 21c connects the first surface 21a and the second surface 21b.
- the side surface 21c of the substrate 21 may be a surface perpendicular to the first surface 21a and the second surface 21b, but is not limited thereto and may be an inclined surface.
- the substrate 21 may have an inclined side surface 21d such that the first surface 21a has a larger area than the second surface 21b, as shown by the dotted line 21d shown in FIG. 7.
- the thickness t1 of the substrate 21 may have a value within the range of 225 ⁇ m to 400 ⁇ m.
- the first conductive semiconductor layer 23 is located on the first surface 21a of the substrate 21.
- the first conductive semiconductor layer 23 is continuous, and the active layer 25 and the second conductive semiconductor layer 27 are positioned on the first conductive semiconductor layer 23.
- the plurality of mesas M may be spaced apart from each other on the first conductivity type semiconductor layer 23.
- the mesas M include the active layer 25 and the second conductivity-type semiconductor layer 27 as described with reference to FIG. 1 and have an elongated shape extending toward one side.
- the mesas M may be a stacked structure of a gallium nitride compound semiconductor.
- Mesas M may be located within the upper region of the first conductivity-type semiconductor layer 23, as shown in FIG. On the contrary, as shown in FIG.
- the mesas M may extend to one edge of the upper surface of the first conductivity-type semiconductor layer 23 in one direction, and thus the first conductivity-type semiconductor layer ( The upper surface of 23 may be partitioned into a plurality of regions. Accordingly, it is possible to alleviate the concentration of the current near the edge of the mesas (M) to further enhance the current distribution performance.
- the reflective electrodes 30 are respectively positioned on the plurality of mesas M to make ohmic contact with the second conductive semiconductor layer 27.
- the reflective electrodes 300 may include a reflective layer 28 and a barrier layer 29, and the barrier layer 29 may cover the top and side surfaces of the reflective layer 28.
- the current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23.
- the current spreading layer 33 has openings 33a positioned in the upper region of each mesa M and exposing the reflective electrodes 30.
- the current spreading layer 33 may cover the entire area of the mesa M except for a part of the upper area of the mesa M in which the openings 33a are formed. It can cover the whole area.
- the current spreading layer 33 is also in ohmic contact with the first conductivity type semiconductor layer 23 and insulated from the plurality of mesas M.
- the current spreading layer 33 may include a reflective metal such as Al.
- the current spreading layer 33 may be insulated from the plurality of mesas M by the lower insulating layer 31.
- the lower insulating layer 31 may be positioned between the plurality of mesas M and the current spreading layer 33 to insulate the current spreading layer 33 from the plurality of mesas M.
- the lower insulating layer 31 may have openings 31b disposed in the upper region of each mesa M to expose the reflective electrodes 30, and may expose the first conductivity-type semiconductor layer 23. It may have openings 31a.
- the current spreading layer 33 may be connected to the first conductivity type semiconductor layer 23 through the openings 31a.
- the openings 31b of the lower insulating layer 31 have a smaller area than the openings 33a of the current spreading layer 33 and are all exposed by the openings 33a.
- the upper insulating layer 35 covers at least a portion of the current spreading layer 33.
- the upper insulating layer 35 has openings 35b exposing the reflective electrodes 30.
- the upper insulating layer 35 may have an opening 35a exposing the current spreading layer 33.
- the upper insulating layer 35 may cover sidewalls of the openings 33a of the current spreading layer 33.
- the first pad 37a may be positioned on the current spreading layer 33, and may be connected to the current spreading layer 33 through, for example, an opening 35a of the upper insulating layer 35.
- the first pad 37a is electrically connected to the first conductive semiconductor layer 23 through the current spreading layer 33.
- the second pad 37b is connected to the reflective electrodes 30 exposed through the openings 35b and electrically connected to the second conductive semiconductor layer 27 through the reflective electrodes 30. .
- the directivity angle of the light emitting diode 100 can be increased to 140 degrees or more.
- the current spreading layer 33 covers almost the entire area of the first conductivity-type semiconductor layer 23 between the mesas M and the mesas M, the current easily flows through the current spreading layer 33. Can be dispersed.
- the current spreading layer 23 includes a reflective metal layer such as Al, or the lower insulating layer is formed as an insulating reflecting layer so that the light not reflected by the reflecting electrodes 30 is reflected by the current spreading layer 23 or the lower insulating layer.
- the layer 31 can be used for reflection to improve the light extraction efficiency.
- FIG. 8 is a cross-sectional view for describing a light emitting diode 200 according to another embodiment of the present invention.
- the light emitting diode 200 is generally similar to the light emitting diode 100 of FIG. 7, but there is a difference in that the conformal coating 50 is positioned on the substrate 21.
- the conformal coating 50 may cover the second surface 21b of the substrate 21 with a uniform thickness and may also cover the side surface 21c.
- the conformal coating 50 may include a wavelength converting material such as a phosphor.
- the sum of the thickness t1 of the substrate 21 and the thickness t2 of the conformal coating 50 may be 225 ⁇ m or more and 600 ⁇ m or less.
- the thickness t2 of the conformal coating 50 may have a value in the range of 20 ⁇ m to 200 ⁇ m.
- the thickness t1 of the substrate 21 may be changed according to the thickness t2 of the conformal coating, and may have a value within a range of 150 ⁇ m to 400 ⁇ m, for example.
- the directivity angle of the light emitting diode 200 may be increased to 140 degrees or more.
- 9 to 12 are graphs showing directivity of light emitting diodes at various substrate thicknesses.
- the solid line represents the directivity characteristic in the first axis (x-axis) direction
- the dotted line represents the directivity characteristic in the second axis (y-axis) direction orthogonal to the first axis.
- a sapphire substrate was used as the substrate 21, and light emitting diodes as described in FIG. 7 were manufactured by varying the thickness of the sapphire substrate 21.
- the size of the light emitting diode was 1 mm x 1 mm, and the thicknesses of the sapphire substrate 21 were approximately 80 ⁇ m, 150 ⁇ m, 250 ⁇ m and 400 ⁇ m.
- FIG. 13 is a graph illustrating the directivity angles of light emitting diodes according to the thickness of the substrate of FIGS. 9 to 12.
- 'Orientation angle' refers to the angle range in which a light beam of 1/2 or more of the maximum light beam appears.
- 'Orientation angle' corresponds to the angular length from the minimum angle to the maximum angle where the normalized intensity becomes 0.5 in the directed distribution graph.
- the orientation angle increases to about 140 degrees, and the orientation angle is large when the thickness t1 of the substrate 21 is 250 ⁇ m or more. There was no change.
- the orientation angle can be maintained at 140 degrees without applying another transparent film on the substrate 21, and the thickness t1 is increased beyond that. Even if it is made, a big change in orientation angle does not occur.
- 14 to 17 are graphs showing directivity of light emitting diodes 200 having conformal coatings at various substrate thicknesses t1.
- the solid line represents the directivity characteristic in the first axis (x-axis) direction
- the dotted line represents the directivity characteristic in the second axis (y-axis) direction orthogonal to the first axis.
- light emitting diodes are manufactured by varying the thickness t1 of the sapphire substrate 21, and a condenser having the same thickness t2 of about 75 ⁇ m on each substrate 21.
- the formal coating 50 was applied to fabricate the light emitting diodes 200 as shown in FIG. 8.
- FIG. 18 is a graph illustrating directing angles of the light emitting diodes 200 having the conformal coating 50 according to the substrate thickness t1 of FIGS. 14 to 17.
- the orientation angle increases to about 143 degrees, and when the thickness t1 of the substrate 21 is 150 ⁇ m or more, the orientation angle is large. There was no change. Therefore, when the sum of the thickness t1 of the substrate 21 and the thickness t2 of the conformal coating 50 is 225 ⁇ m or more, the orientation angle is saturated to a value of 140 degrees or more.
- the light emitting diode 200 having a directivity angle of 140 degrees or more can be provided.
- the light emitting diode 200 having a directivity angle of 140 degrees or more may be provided even when the thickness of the substrate 21 is about 225 ⁇ m without the conformal coating 50.
- FIG. 19 is a schematic cross-sectional view illustrating a light emitting diode module 300a employing conventional light emitting diodes 10 and light emitting diode modules 300b and 300c employing light emitting diodes 100 according to the present invention.
- the light emitting diode modules 300a, 300b, and 300c are used as backlight units for backlighting the liquid crystal display panel 400.
- the conventional light emitting diode 10 has a directivity angle ⁇ 1 of approximately 120 degrees, whereas the light emitting diode 100 of the present invention has a directivity angle ⁇ 2 of approximately 140 degrees or more.
- the distance between the light emitting diode module and the liquid crystal display panel 400 may be expressed as d, the pitch of the light emitting diodes p, and the directivity angle of the light emitting diodes ⁇ .
- the pitch p represents the width of a region where one light emitting diode irradiates the liquid crystal display panel 400, and is represented by the following equation (1).
- the pitch p1 of the conventional light emitting diode module 300a and the pitch p2 of the light emitting diode module 300b according to the present invention are represented by the following equations (2) and (3), respectively.
- the orientation angle ( ⁇ 2) of the LED 100 is to the following formula (4) is satisfied since larger than the directivity angle ( ⁇ 1) of the conventional light-emitting diode (10) ⁇ 2/2 is smaller than 90 degrees .
- the light emitting diode module 300b according to the present invention may arrange the light emitting diodes 100 at a wider distance than the conventional light emitting diode module 300a. Therefore, the number of light emitting diodes 100 used in the light emitting diode module 300b may be reduced.
- the light emitting diode module 300c of the present invention is closer to the liquid crystal display panel 400 than the light emitting diode module 300a. It can be arranged, thus making it possible to slim down the backlight unit and further the liquid crystal display.
- the light emitting diode modules 300a, 300b, and 300c are used as backlight units, but the light emitting diode modules 300a, 300b, and 300c may be used as lighting modules used in lighting devices.
- the lighting modules 300a, 300b, and 300c may irradiate the diffuser plate 400 of the illumination device.
- the illumination module 300a, 300b, and 300c may irradiate the diffuser plate having the same area with a smaller number of light emitting diodes. , Or closer to the diffuser plate.
- 20 to 24 are diagrams for describing a method of manufacturing a light emitting diode according to an exemplary embodiment of the present invention, in which (a) is a sectional view taken along a cut line A-A in (b).
- a first conductivity type semiconductor layer 123 is formed on a substrate 121, and an active layer 125 and a second conductivity type semiconductor layer (1) are formed on the first conductivity type semiconductor layer 123. 127 is located.
- the substrate 121 is a substrate for growing a gallium nitride based semiconductor layer, for example, may be a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate, and in particular, may be a sapphire substrate.
- the substrate 121 will be provided in the form of a large area wafer capable of manufacturing a plurality of light emitting diodes, but FIG. 20 shows only the substrate portion of the final light emitting diode after being separated into individual light emitting diodes.
- the substrate 121 may have a parallelogram shape having an acute angle, for example, a rhombus shape, but is not limited thereto.
- the substrate 121 may have various polygonal shapes such as a triangle, a pentagon, and the like having an acute angle.
- the first conductive semiconductor layer 123 may be a nitride based semiconductor layer and may be a layer doped with n-type impurities.
- the first conductivity type semiconductor layer 123 may be a layer doped with Si in an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer.
- the first conductivity type semiconductor layer 123 may be a GaN layer doped with Si.
- the second conductivity-type semiconductor layer 127 may be a nitride-based semiconductor layer and may be a layer doped with p-type impurities.
- the second conductive semiconductor layer 127 may be doped with Mg or Zn in an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer. It may be a layer.
- the second conductivity-type semiconductor layer 27 may be a GaN layer doped with Mg.
- the active layer 125 may include a well layer of an In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) layer, or a single quantum well structure or It may have a multi-quantum well structure.
- the active layer 125 may have a single quantum well structure of an InGaN, GaN or AlGaN layer, or a multi-quantum well structure in which layers such as InGaN / GaN, GaN / AlGaN or AlGaN / AlGaN are stacked.
- the first conductive semiconductor layer 123, the active layer 125, and the second conductive semiconductor layer 127 may be formed using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques.
- MOCVD metal organic chemical vapor deposition
- MBE molecular beam epitaxy
- a mesa is formed on the first conductive semiconductor layer 123, and a portion of the first conductive semiconductor layer 123 is exposed along an edge of the mesa. As shown in FIG. 20, the top surface of the first conductive semiconductor layer 123 may be exposed along the edge of the substrate 121 of the final light emitting diode, and the active layer 125 and the second conductive semiconductor layer 127 may be exposed. ) May be located within the upper region of the first conductivity type semiconductor layer 123.
- the mesa may be formed on the first surface of the substrate 121.
- the organic layer may include a semiconductor stacked structure 126 including a first conductive semiconductor layer 123, an active layer 125, and a second conductive semiconductor layer 127. After growing using a vapor phase growth method or the like, the second conductive semiconductor layer 127 and the active layer 125 may be formed by patterning the first conductive semiconductor layer 123.
- the side of the mesa may be formed to be inclined by using a technique such as photoresist reflow. The inclined profile of the mesa side improves the extraction efficiency of the light generated in the active layer 125.
- the planar shape of the mesa is similar to the planar shape of the substrate 121.
- the planar shape of the mesa has at least one acute angle like the planar shape of the substrate 121.
- the planar shape of the mesa may be a quadrangle having a pair of obtuse angles facing each other and a pair of acute angles facing each other.
- the obtuse angles may have the same value as each other, and the acute angles may have the same value as each other.
- the planar shape of the mesa may be a rhombus shape or a diamond shape.
- One side of the mesa may be disposed perpendicular to the flat zone of the substrate 121.
- the substrate 121 is a sapphire substrate
- one side of the mesa may be aligned with the m-plane.
- the planar shape of the semiconductor stacked structure 126 may also have a shape similar to that of the mesa.
- the reflective electrode 130 is formed on the second conductivity type semiconductor layer 127.
- the reflective electrode 130 may be formed on the mesa after the mesa is formed, but is not limited thereto, and the second conductive semiconductor layer 127 may be formed before the second conductive semiconductor layer 127 is grown and the mesa is formed. 127 may be formed in advance.
- the reflective electrode 130 covers most of the upper surface of the second conductivity-type semiconductor layer and has a shape substantially the same as a planar shape of the mesa.
- the reflective electrode 130 may include a reflective layer 128 and further include a barrier layer 129.
- the barrier layer 129 may cover the top and side surfaces of the reflective layer 128.
- barrier layer 129 may be formed to cover the top and side surfaces of reflective layer 128.
- the reflective layer 128 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, TiO / Ag layer.
- the barrier layer 129 may be formed of Ni, Cr, Ti, Pt, or a composite layer thereof to prevent the metal material of the reflective layer 128 from being diffused or contaminated.
- an upper edge of the substrate 121 may be exposed by additionally etching the edges of the exposed first conductive semiconductor layer 123.
- the side surface of the first conductivity-type semiconductor layer 123 may also be formed to be inclined.
- a lower insulating layer 131 is formed to cover the first conductivity-type semiconductor layer 123 and the reflective electrode 130.
- the lower insulating layer 131 has openings 131a and 131b for allowing electrical connection to the first conductive semiconductor layer 123 and the second conductive semiconductor layer 127 in a specific region.
- the lower insulating layer 131 may have openings 131a exposing the first conductivity type semiconductor layer 123 and openings 131b exposing the reflective electrode 130.
- the opening 131a may be positioned near the edge of the substrate 121 around the reflective electrode 130 and may have an elongated shape extending along the edge of the substrate 121.
- the openings 131a are formed to be farther from each other at the acute angle than at the obtuse portion, as shown in FIG. 21.
- the distance between the openings 131a near the acute portion may be greater than or equal to the current spreading length, and the distance between the openings 131a near the obtuse portion may be equal to or less than the current spreading length.
- the current spreading length means the length from the p electrode edge to where the current density is reduced by 1 / e when the driving current is drawn into the device.
- the opening 131b is limited to the upper portion of the reflective electrode 130, and may be disposed to be near the acute angle of the substrate 121.
- the opening 131b may have, for example, a planar shape of triangle or trapezoid.
- the lower insulating layer 131 may be formed of an oxide film such as SiO 2 , a nitride film such as SiNx, or an insulating film of MgF 2 using a technique such as chemical vapor deposition (CVD).
- the lower insulating layer 131 may be formed as a single layer, but is not limited thereto and may be formed as a multilayer.
- the lower insulating layer 131 may be formed of a distributed Bragg reflector (DBR) in which the low refractive material layer and the high refractive material layer are alternately stacked.
- DBR distributed Bragg reflector
- an insulating reflective layer having a high reflectance can be formed by laminating layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5 .
- the opening 131a exposing the first conductivity type semiconductor layer 123 has an elongated shape and is formed along the edge of the substrate 121, but the present invention is not limited thereto.
- a plurality of holes 131c exposing the first conductivity type semiconductor layer 123 may be arranged along the edge of the substrate 121.
- the plurality of holes 131c may be disposed to be farther from each other as they become closer to the acute angle from the obtuse portion, thereby alleviating current concentration.
- an interval between the holes 131c at both sides having the acute angle may be greater than an interval between the holes 131c at both sides having the acute angle.
- an interval between the holes 131c at both sides having the acute angle may be
- the distance between the current spreading length or more and the holes 131c on both sides of the obtuse portion may be less than or equal to the current spreading length.
- the shapes of the holes 131c may be polygonal, circular, or semicircular.
- a current spreading layer 133 is formed on the lower insulating layer 131.
- the current spreading layer 133 covers the reflective electrode 130 and the first conductive semiconductor layer 123.
- the current spreading layer 133 has an opening 133a positioned in the upper region of the reflective electrode 130 and exposing the reflective electrode 130.
- the current spreading layer 133 may be in ohmic contact with the first conductive semiconductor layer 123 through the openings 131a of the lower insulating layer 131. Meanwhile, the current spreading layer 133 is insulated from the reflective electrode 130 by the lower insulating layer 131.
- the openings 133a of the current spreading layer 133 have a larger area than the openings 131b of the lower insulating layer 131, respectively, to prevent the current spreading layer 133 from connecting to the reflective electrode 130. Therefore, the sidewall of the opening 133a is positioned on the lower insulating layer 131.
- the current spreading layer 133 is formed over almost the entire area of the substrate 131 except for the opening 133a. Therefore, the current may be easily distributed through the current spreading layer 133.
- the current spreading layer 133 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni.
- a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer.
- the current spreading layer 133 may have a multilayer structure of, for example, Ti / Al / Ti / Ni / Au.
- an upper insulating layer 135 is formed on the current spreading layer 133.
- the upper insulating layer 135 has an opening 135b exposing the current spreading layer 133 and an opening 135b exposing the reflective electrode 130.
- the opening 135a and the opening 135b may be disposed to face each other, and as shown in FIG. 23A, may be disposed near acute portions of the substrate 121.
- the opening 135b exposes the reflective electrode 130 exposed through the opening 133a of the current spreading layer 133 and the opening 131b of the lower insulating layer 131.
- the opening 135b has a narrower area than the openings 133a of the current spreading layer 133.
- the opening 135b may have a smaller area than the opening 131b of the lower insulating layer 131, but is not limited thereto and may have a larger area.
- the opening 135a may have an inverted trapezoidal shape, and the opening 135b may have a trapezoidal shape.
- the upper insulating layer 135 may be formed using an oxide insulating layer, a nitride insulating layer, or a polymer such as polyimide, teflon, parylene, or the like.
- a first pad 137a and a second pad 137b are formed on the upper insulating layer 135.
- the first pad 137a is connected to the current spreading layer 133 through the opening 135a of the upper insulating layer 135, and the second pad 137b is connected to the opening 135b of the upper insulating layer 135. It is connected to the reflective electrode 130.
- the first pad 137a is connected to the first conductive semiconductor layer 123 through the current dispersion layer 133
- the second pad 137b is connected to the second conductive semiconductor through the reflective electrode 130. May be connected to layer 127.
- the first pad 137a and the second pad 137b may be connected to bumps or used as pads for Surface Mounting Technology (SMT) for mounting the light emitting diodes to a submount, package, or printed circuit board.
- SMT Surface Mounting Technology
- the first and second pads 137a and 137b may be formed together in the same process, for example, using photo and etching techniques or lift off techniques.
- the first and second pads 137a and 137b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au.
- the first and second pads 137a and 137b may further include a pad barrier layer covering the high conductivity metal layer.
- the barrier metal layer prevents diffusion of metal atoms such as tin (Sn) during bonding or soldering to prevent an increase in specific resistance of the first and second pads 137a and 137b.
- the pad barrier layer may be formed of Cr, Ni, Ti, W, TiW, Mo, Pt, or a composite layer thereof.
- the light emitting diode is completed by dividing the substrate 121 into individual light emitting diode chip units.
- the substrate 121 may be divided into individual light emitting diode chip units having a parallelogram shape by scribing along the m plane group. Accordingly, a light emitting diode in which side surfaces of the substrate 121 are formed in an m plane group may be provided.
- the substrate 121 may be deformed to have a thinner thickness through a thinning process before being divided into individual LED chips.
- the thickness of the substrate 121 may exceed 100 ⁇ m, and in particular, may be 225 ⁇ m or more and 400 ⁇ m or less.
- a conformal coating (50 in FIG. 27) covering the substrate 121 of the individual light emitting diode chip may be further formed.
- the conformal coating 150 may be formed before or after dividing the substrate 121 into chips.
- the light emitting diode 100a may include a substrate 121, a first conductive semiconductor layer 123, an active layer 125, a second conductive semiconductor layer 127, and a first pad 137a.
- the second pad 137b may include the reflective electrode 130, the current spreading layer 133, the lower insulating layer 131, and the upper insulating layer 135.
- the substrate 121 may be a growth substrate for growing the gallium nitride-based epi layers, such as sapphire, silicon carbide, and gallium nitride substrate.
- the substrate 121 may include a first surface 121a, a second surface 121b, and a side surface 121c.
- the first surface 121a is a surface on which semiconductor layers are grown
- the second surface 121b is a surface on which light generated by the active layer 125 is emitted to the outside.
- the side surface 121c connects the first surface 121a and the second surface 121b.
- the side surface 121c of the substrate 121 may be a surface perpendicular to the first surface 121a and the second surface 121b, but is not limited thereto and may be an inclined surface.
- the substrate 121 may have an inclined side surface 121d such that the first surface 121a has a larger area than the second surface 121b, as shown by the dotted line 121d shown in FIG. 26.
- the substrate 121 may have a polygonal shape having at least one acute angle.
- the first surface 121a and the second surface 121b may have a polygonal shape such as a parallelogram, a triangle, or a pentagon, as described with reference to FIG. 20. Since the substrate 121 has an acute angle, the extraction efficiency of light through the acute part is improved, and the directivity angle of the light at the acute part may be increased.
- the thickness of the substrate 121 may exceed 100 ⁇ m, and in particular, may have a value within the range of 225 ⁇ m to 400 ⁇ m. As the thickness of the substrate 121 is thicker, the directing angle of the light may be increased. When the thickness of the substrate 121 is 225 ⁇ m or more, the directing angle of the light may be substantially constant.
- the first conductive semiconductor layer 123 is positioned on the first surface 121a of the substrate 121.
- the first conductive semiconductor layer 123 may cover the entire surface of the first surface 121a of the substrate 121, but is not limited thereto and may expose the first surface 121a along the edge of the substrate 121.
- the first conductivity-type semiconductor layer 123 may be located within the upper region of the substrate 121.
- a mesa including an active layer 125 and a second conductive semiconductor layer 127 is positioned on the first conductive semiconductor layer 123.
- the active layer 125 and the second conductivity-type semiconductor layer 127 are limited to the upper region of the first conductivity-type semiconductor layer 127. Therefore, some regions of the first conductivity-type semiconductor layer 127 may be exposed, particularly along the edge of the substrate 121.
- the reflective electrode 130 makes ohmic contact with the second conductivity type semiconductor layer 127.
- the reflective electrodes 130 may include a reflective layer 128 and a barrier layer 129, and the barrier layer 129 may cover the top and side surfaces of the reflective layer 128.
- the current spreading layer 133 covers the reflective electrode 130 and the first conductive semiconductor layer 123.
- the current spreading layer 133 has an opening 133a positioned in the upper region of the reflective electrode 130 and exposing the reflective electrode 130.
- the current spreading layer 133 may cover the entire region of the reflective electrode 130 except for a portion of the upper region of the reflective electrode 130 having the opening 133a formed therein, and may also cover the first conductive semiconductor layer 123. Can cover the entire area).
- the current spreading layer 133 is also ohmic contacted to the first conductivity type semiconductor layer 123 and insulated from the reflective electrode 130.
- the current spreading layer 133 may be insulated from the reflective electrode 130 by the lower insulating layer 131.
- the lower insulating layer 131 may be positioned between the reflective electrode 130 and the current spreading layer 133 to insulate the current spreading layer 133 from the reflective electrode 130.
- the lower insulating layer 131 may be formed in the upper region of the reflective electrode 130 to have an opening 131b exposing the reflective electrode 130, and the openings exposing the first conductive semiconductor layer 123. 131a.
- the openings 131b of the lower insulating layer 131 have a smaller area than the openings 133a of the current spreading layer 133, and are all exposed by the openings 133a.
- the current spreading layer 133 may be connected to the first conductivity type semiconductor layer 123 through the openings 131a.
- the openings 131a may be positioned along the edges of the substrate 121 as described with reference to FIG. 21, and may be farther away from the acute portion than in the obtuse portion. Accordingly, the luminous efficiency can be improved by preventing the current from being concentrated at the sharp corners.
- the lower insulating layer 131 may have holes 131c as described with reference to FIG. 25 instead of the openings 131a.
- the upper insulating layer 135 covers at least a portion of the current spreading layer 133.
- the upper insulating layer 135 has an opening 135a exposing the current spreading layer 133 and an opening 135b exposing the reflective electrode 130.
- the opening 135a and the opening 135b may be located near the acute parts to face each other.
- the upper insulating layer 135 may cover the sidewall of the opening 133a of the current spreading layer 133, and the opening 135b may be located in the opening 133a.
- the first pad 137a may be positioned on the current spreading layer 133, and may be connected to the current spreading layer 133 through the opening 135a of the upper insulating layer 135, for example.
- the first pad 137a is electrically connected to the first conductive semiconductor layer 123 through the current spreading layer 133.
- the second pad 137b is connected to the reflective electrode 130 exposed through the opening 135b and electrically connected to the second conductive semiconductor layer 127 through the reflective electrode 130.
- the light extraction efficiency can be improved by making the substrate 121 have a polygonal shape having at least one acute angle, such as a parallelogram shape or a triangular shape. Furthermore, since the luminous flux emitted through the acute angle increases, the direct angle characteristic of the light emitting diode may be adjusted using the acute angle.
- the directivity angle of light can be increased by setting the thickness of the substrate 121 to 100 ⁇ m or more.
- the current spreading layer 123 includes a reflective metal layer such as Al, or the lower insulating layer is formed as an insulating reflecting layer so that the light that is not reflected by the reflecting electrodes 130 is scattered by the current spreading layer 123 or the lower insulating layer.
- the layer 131 may be reflected to improve light extraction efficiency.
- FIG. 27 is a cross-sectional view for describing a light emitting diode 200a according to another embodiment of the present invention.
- the light emitting diode 200a is generally similar to the light emitting diode 100a of FIG. 26, but there is a difference in that the conformal coating 150 is positioned on the substrate 121.
- the conformal coating 150 may cover the second surface 121b of the substrate 121 and may cover the side surface 121c with a uniform thickness.
- the conformal coating 150 may include a wavelength converting material such as a phosphor.
- the sum of the thickness of the substrate 121 and the thickness of the conformal coating 150 may be 225 ⁇ m or more and 600 ⁇ m or less.
- the thickness of conformal coating 150 may have a value within the range of 20 ⁇ m to 200 ⁇ m.
- the thickness of the substrate 121 may be changed according to the thickness of the conformal coating, and may have, for example, a value within a range of 100 ⁇ m to 400 ⁇ m.
- the directivity angle of the light emitting diode 200a may be increased to 140 degrees or more.
- FIG. 28 is a schematic plan view for explaining light extraction characteristics according to a substrate shape.
- (a) is a view showing a path of light propagation in the conventional rectangular substrate 111
- (b) is a view of the light in the diamond-shaped substrate 121 having an acute angle according to an embodiment of the present invention
- a part of the light generated at a specific position Lp of the active layer enters the substrate 111 and then repeats total internal reflection on the side surfaces of the substrate 111.
- the light travels a considerable distance inside the substrate 111, and thus light loss occurs in the substrate 111.
- the thickness of the substrate 111 becomes thicker, more internal total reflection occurs at the side of the substrate 111 and thus light loss is increased.
- the direction angle along the direction is constant without large difference.
- the diamond-shaped substrate 121 As shown in FIG. 28 (b), a part of the light generated at the specific position Lp of the active layer enters the substrate 121, and then the substrate 121 is removed. After total internal reflection at the sides, the angle of incidence of light is generally reduced near the acute angle and emitted to the outside. Therefore, by employing the diamond substrate 121, the light extraction efficiency is improved as compared with the case where the conventional substrate 111 is adopted. Moreover, since the light extraction efficiency is increased at the acute angle portion, the directing angle of the light at the acute angle portion increases compared to the obtuse portion. Therefore, it is possible to provide a light emitting diode having different orientation angle characteristics depending on the direction.
- the substrate 111 of the light emitting diode manufactured according to the prior art has a rectangular shape of 300 ⁇ m ⁇ 1000 ⁇ m, and the thickness thereof is approximately 250 ⁇ m.
- the substrate 121 had a length of 1 mm between the acute parts and a length of about 0.58 mm between the obtuse parts.
- the light emitting diode according to the related art has a substantially similar direction angle distribution R-X along the x-axis (short axis) direction and a direction angle distribution R-Y along the y-axis (long axis) direction.
- the light emitting diode according to the embodiment of the present invention has a direction angle distribution DY in the y-axis direction passing through the acute angles relative to the direction angle distribution DX in the x-axis direction passing through the obtuse portions. It appears large.
- a light emitting diode having different orientation angle characteristics in the x-axis direction and the y-axis direction.
- Such a light emitting diode may be particularly useful for lighting devices that require different directivity angle characteristics depending on the direction, such as LED fluorescent lamps.
- a plurality of light emitting diodes may be arranged in a line such that the y-axis direction having a wide direction angle is orthogonal to the length direction of the LED fluorescent lamp, thereby illuminating a large area while reducing light loss in the fluorescent lamp. have.
Abstract
Description
Claims (50)
- 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 상기 투명 기판 외부로 방출되고,적어도 일축 방향으로 140도 이상의 지향각을 갖는 발광 다이오드.
- 청구항 1에 있어서,상기 투명 기판의 제2면을 덮는 컨포멀 코팅층을 더 포함하고,상기 제2면에서 방출된 광은 상기 컨포멀 코팅층을 통해 상기 컨포멀 코팅층의 외부로 방출되는 발광 다이오드.
- 청구항 2에 있어서,상기 투명 기판과 상기 컨포멀 코팅층의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 발광 다이오드.
- 청구항 3에 있어서,상기 투명 기판의 두께는 150㎛ 내지 400㎛ 범위 내의 값을 갖는 발광 다이오드.
- 청구항 3에 있어서,상기 컨포멀 코팅의 두께는 20㎛ 내지 200㎛ 범위 내의 값을 갖는 발광 다이오드.
- 청구항 1에 있어서,상기 투명 기판의 두께는 225㎛ 내지 400㎛ 범위 내의 값을 갖는 발광 다이오드.
- 청구항 1 내지 청구항 6의 어느 한 항에 있어서,상기 제1 도전형 반도체층 상에 서로 이격되어 배치된 복수의 메사들을 더 포함하되,상기 각 메사는 상기 활성층 및 상기 제2 도전형 반도체층을 포함하는 발광 다이오드.
- 청구항 7에 있어서,각각 상기 복수의 메사들 상에 위치하여 제2 도전형 반도체층에 오믹 콘택하는 반사 전극들; 및상기 복수의 메사들 및 상기 제1 도전형 반도체층을 덮되, 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 가지며, 상기 제1 도전형 반도체층에 오믹콘택하고 상기 복수의 메사들로부터 절연된 전류 분산층을 더 포함하고,상기 제1 패드는 상기 전류 분산층에 전기적으로 연결되고,상기 제2 패드는 상기 개구부들을 통해 상기 반사 전극들에 전기적으로 연결된 발광 다이오드.
- 청구항 8에 있어서,상기 복수의 메사들은 일측 방향으로 서로 평행하게 연장하는 기다란 형상을 갖는 발광 다이오드.
- 청구항 8에 있어서,상기 전류 분산층은 반사 금속을 포함하는 발광 다이오드.
- 청구항 8에 있어서,상기 반사 전극들은 각각 반사 금속층과 장벽 금속층을 포함하되, 상기 장벽 금속층이 상기 반사 금속층의 상면 및 측면을 덮는 발광 다이오드.
- 청구항 8에 있어서,상기 전류분산층의 적어도 일부를 덮되, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층을 더 포함하고,상기 제2 패드는 상기 상부 절연층의 개구부들을 통해 노출된 반사 전극들에 접속하는 발광 다이오드.
- 청구항 8에 있어서,상기 복수의 메사들과 상기 전류 분산층 사이에 위치하여 상기 전류 분산층을 상기 복수의 메사들로부터 절연시키는 하부 절연층을 더 포함하되,상기 하부 절연층은 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 갖는 발광 다이오드.
- 청구항 13에 있어서,상기 전류 분산층의 개구부들은 각각 상기 하부 절연층의 개구부들이 모두 노출되도록 상기 하부 절연층의 개구부들보다 더 넓은 폭을 갖는 발광 다이오드.
- 청구항 14에 있어서,상기 전류분산층의 적어도 일부를 덮고, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층을 더 포함하되,상기 상부 절연층은 상기 전류 분산층의 개구부들의 측벽들을 덮는 발광 다이오드.
- 청구항 13에 있어서,상기 하부 절연층은 반사성 유전층인 발광 다이오드.
- 청구항 1에 있어서,상기 제1면의 폭이 제2면의 폭보다 더 넓은 면적을 갖도록 상기 측면이 경사진 발광 다이오드.
- 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 외부로 방출되고,상기 투명 기판의 두께는 225㎛ 내지 400㎛ 범위 내의 값을 갖는 발광 다이오드.
- 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드;상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드; 및상기 투명 기판을 덮는 컨포멀 코팅층을 포함하고,상기 활성층에서 생성된 광은 상기 컨포멀 코팅층을 통해 외부로 방출되고,상기 투명 기판 및 상기 컨포멀 코팅의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 발광 다이오드.
- 청구항 19에 있어서,상기 투명 기판의 두께는 150㎛ 내지 400㎛ 범위 내의 값을 갖는 발광 다이오드.
- 복수의 발광 다이오드들을 포함하는 조명 모듈에 있어서,적어도 하나의 발광 다이오드가,상기 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 상기 투명 기판 외부로 방출되고,상기 적어도 하나의 발광 다이오드는 적어도 일축 방향으로 140도 이상의 지향각을 갖는 조명 모듈.
- 청구항 21에 있어서,상기 투명 기판의 두께는 225㎛ 내지 400㎛ 범위 내의 값을 갖는 조명 모듈.
- 청구항 21에 있어서,상기 적어도 하나의 발광 다이오드는 상기 투명 기판의 제2면을 덮는 컨포멀 코팅층을 더 포함하고,상기 투명 기판 및 상기 컨포멀 코팅의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 조명 모듈.
- 청구항 21 내지 청구항 23의 어느 한 항에 기재된 조명 모듈을 포함하는 조명 장치.
- 복수의 발광 다이오드들을 포함하는 백라이트 유닛에 있어서,적어도 하나의 발광 다이오드가,상기 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 상기 투명 기판 외부로 방출되고,상기 적어도 하나의 발광 다이오드는 적어도 일축 방향으로 140도 이상의 지향각을 갖는, 백라이트 유닛.
- 청구항 25에 있어서,상기 투명 기판의 두께는 225㎛ 내지 400㎛ 범위 내의 값을 갖는 백라이트 유닛.
- 청구항 25에 있어서,상기 적어도 하나의 발광 다이오드는 상기 투명 기판의 제2면을 덮는 컨포멀 코팅층을 더 포함하고,상기 투명 기판 및 상기 컨포멀 코팅의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 백라이트 유닛.
- 청구항 27에 있어서,상기 컨포멀 코팅의 두께는 20㎛ 내지 200㎛ 범위 내의 값을 갖는 백라이트 유닛.
- 제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 상기 투명 기판 외부로 방출되고,상기 투명기판은 적어도 하나의 예각을 갖는 다각형 형상인 발광 다이오드.
- 청구항 29에 있어서,상기 투명 기판은 100㎛ 내지 400㎛ 범위 내의 두께를 갖는 발광 다이오드.
- 청구항 30에 있어서,상기 적어도 하나의 예각을 갖는 다각형 형상은 삼각형 형상, 평행사변형 형상 또는 5각형 형상인 발광 다이오드.
- 청구항 29에 있어서,상기 투명 기판은 사파이어 기판인 발광 다이오드.
- 청구항 32에 있어서,상기 투명 기판은 평행사변형 형상을 갖고, 상기 투명 기판의 측면은 m면 군으로 이루어진 발광 다이오드.
- 청구항 29에 있어서, 상기 제2 도전형 반도체층 상에 위치하여 상기 활성층에서 생성된 광을 반사시키는 반사 전극을 더 포함하는 발광 다이오드.
- 청구항 29 내지 청구항 34의 어느 한 항에 있어서,상기 제1 도전형 반도체층의 상부면이 상기 기판의 가장자리를 따라 노출되도록 상기 활성층 및 상기 제2 도전형 반도체층이 상기 제1 도전형 반도체층의 상부 영역 내에 한정되어 위치하는 발광 다이오드.
- 청구항 35에 있어서,상기 제1 패드와 상기 제1 도전형 반도체층을 연결하는 전류 분산층을 더 포함하고,상기 제1 패드 및 제2 패드는 상기 제2 도전형 반도체층 상부에 위치하는 발광 다이오드.
- 청구항 36에 있어서,상기 전류 분산층은 반사 금속을 포함하는 발광 다이오드.
- 청구항 36에 있어서,상기 전류 분산층을 상기 반사 전극으로부터 절연시키는 하부 절연층을 더 포함하되,상기 하부 절연층은 상기 제1 도전형 반도체층을 노출시키는 개구부들을 갖고,상기 전류 분산층은 상기 개구부들을 통해 상기 제1 도전형 반도체층에 접속하는 발광 다이오드.
- 청구항 38에 있어서,상기 개구부들은 각각 상기 기판의 가장자리들을 따라 기다란 형상으로 배치되고,상기 개구부들은 다른 각부들에 비해 상기 적어도 하나의 예각부에서 더 멀리 떨어져 있는 발광 다이오드.
- 청구항 38에 있어서,상기 개구부들은 상기 기판의 가장자리를 따라 서로 이격되어 위치하는 복수의 홀들을 포함하고,상기 홀들 사이의 간격은 상기 적어도 하나의 예각부에 가까울수록 커지는 발광 다이오드.
- 청구항 29에 있어서,상기 제1면이 제2면보다 더 넓은 면적을 갖도록 상기 측면이 경사진 발광 다이오드.
- 청구항 29에 있어서,상기 기판의 제2면을 덮는 컨포멀 코팅을 더 포함하는 발광 다이오드.
- 청구항 42에 있어서,상기 투명 기판 및 상기 컨포멀 코팅의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 발광 다이오드.
- 복수의 발광 다이오드들을 포함하는 조명 장치에 있어서,적어도 하나의 발광 다이오드가,제1면, 제2면 및 상기 제1면과 제2면을 연결하는 측면을 갖는 투명 기판;상기 투명 기판의 제1면 상에 위치하는 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 위치하는 제2 도전형 반도체층;상기 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 위치하는 활성층;상기 제1 도전형 반도체층에 전기적으로 접속된 제1 패드; 및상기 제2 도전형 반도체층에 전기적으로 접속된 제2 패드를 포함하고,상기 활성층에서 생성된 광은 상기 투명 기판의 제2면을 통해 상기 투명 기판 외부로 방출되고,상기 투명기판은 적어도 하나의 예각을 갖는 다각형 형상인 조명 장치.
- 청구항 44에 있어서,상기 투명 기판은 100㎛ 내지 400㎛ 범위 내의 두께를 갖는 조명 장치.
- 청구항 44에 있어서,상기 적어도 하나의 예각을 갖는 다각형 형상은 삼각형 형상, 평행사변형 형상 또는 5각형 형상인 조명 장치.
- 청구항 46에 있어서,상기 투명 기판은 평행사변형 형상을 갖고, 상기 투명 기판의 측면은 m면 군으로 이루어진 조명 장치.
- 청구항 47에 있어서,상기 적어도 하나의 발광 다이오드는 상기 투명 기판의 제2면을 덮는 컨포멀 코팅을 더 포함하고,상기 투명 기판 및 상기 컨포멀 코팅의 두께의 합은 225㎛ 내지 600㎛ 범위 내의 값을 갖는 조명 장치.
- 제1면과 상기 제1면의 반대면인 제2면을 갖는 기판의 제1면 상에 배치된 제1 도전형 반도체층;상기 제1 도전형 반도체층 상에 차례로 적층된 활성층과 제2 도전형 반도체층을 갖는 메사로서, 그 평면형상이 예각과 둔각을 갖는 다각형이고, 그 외측에 상기 제1 도전형 반도체층이 노출되는 메사;상기 메사를 덮고, 상기 메사의 외측변들에 인접하여 상기 제1 도전형 반도체층을 노출시키는 복수개의 제1 개구부들과 상기 제2 도전형 반도체층의 상부면을 노출시키는 제2 개구부를 갖는 하부 절연층;상기 제1 개구부들을 통해 상기 제1 도전형 반도체층에 전기적으로 접속하는 제1 패드; 및상기 제2 개구부를 통해 상기 제2 도전형 반도체층에 전기적으로 접속하는 제2 패드를 포함하고,상기 메사의 예각을 중심으로 이에 인접하는 제1 개구부들 사이의 거리는 상기 메사의 둔각을 중심으로 이에 인접하는 제1 개구부들 사이의 거리에 비해 큰 발광 다이오드.
- 청구항 49에 있어서,상기 메사의 예각을 중심으로 이에 인접하는 제1 개구부들 사이의 거리는 전류 스프레딩 길이 이상이고,상기 메사의 둔각을 중심으로 이에 인접하는 제1 개구부들 사이의 거리는 전류 스프레딩 길이 이하인 발광 다이오드.
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201380072266.0A CN105074941B (zh) | 2012-12-06 | 2013-10-22 | 发光二极管、照明模块、照明设备和背光单元 |
CN201910265288.8A CN109979925B (zh) | 2012-12-06 | 2013-10-22 | 发光二极管 |
DE112013005849.9T DE112013005849T5 (de) | 2012-12-06 | 2013-10-22 | Lichtemittierende Diode und Anwendung dafür |
CN201910834913.6A CN110600593B (zh) | 2012-12-06 | 2013-10-22 | 发光二极管 |
US14/733,787 US9608171B2 (en) | 2012-12-06 | 2015-06-08 | Light-emitting diode and application therefor |
US14/745,271 US9536924B2 (en) | 2012-12-06 | 2015-06-19 | Light-emitting diode and application therefor |
US14/745,284 US9548425B2 (en) | 2012-12-06 | 2015-06-19 | Light-emitting diode and application therefor |
US15/470,811 US10497836B2 (en) | 2012-12-06 | 2017-03-27 | Light-emitting diode and application therefor |
US16/660,460 US10749080B2 (en) | 2012-12-06 | 2019-10-22 | Light-emitting diode and application therefor |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2012-0140991 | 2012-12-06 | ||
KR1020120140991A KR102013364B1 (ko) | 2012-12-06 | 2012-12-06 | 발광 다이오드 및 그것의 어플리케이션 |
KR10-2012-0155783 | 2012-12-28 | ||
KR1020120155783A KR102071036B1 (ko) | 2012-12-28 | 2012-12-28 | 발광 다이오드 및 그것을 채택하는 조명 장치 |
KR1020130011453A KR101984932B1 (ko) | 2013-01-31 | 2013-01-31 | 예각과 둔각을 가지는 다각형의 발광다이오드 및 이를 포함하는 조명모듈 |
KR10-2013-0011453 | 2013-01-31 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/733,787 Continuation-In-Part US9608171B2 (en) | 2012-12-06 | 2015-06-08 | Light-emitting diode and application therefor |
US14/733,787 Continuation US9608171B2 (en) | 2012-12-06 | 2015-06-08 | Light-emitting diode and application therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014088201A1 true WO2014088201A1 (ko) | 2014-06-12 |
Family
ID=50883597
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2013/009395 WO2014088201A1 (ko) | 2012-12-06 | 2013-10-22 | 발광 다이오드 및 그것의 어플리케이션 |
Country Status (4)
Country | Link |
---|---|
US (4) | US9608171B2 (ko) |
CN (3) | CN109979925B (ko) |
DE (2) | DE202013012758U1 (ko) |
WO (1) | WO2014088201A1 (ko) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109979925B (zh) * | 2012-12-06 | 2024-03-01 | 首尔伟傲世有限公司 | 发光二极管 |
WO2014182104A1 (ko) * | 2013-05-09 | 2014-11-13 | 서울반도체 주식회사 | 광원 모듈 및 이를 구비한 백라이트 유닛 |
WO2015016561A1 (en) * | 2013-07-29 | 2015-02-05 | Seoul Viosys Co., Ltd. | Light emitting diode, method of fabricating the same and led module having the same |
US9847457B2 (en) | 2013-07-29 | 2017-12-19 | Seoul Viosys Co., Ltd. | Light emitting diode, method of fabricating the same and LED module having the same |
US9608168B2 (en) * | 2014-06-13 | 2017-03-28 | Seoul Viosys Co., Ltd. | Light emitting diode |
US10297719B2 (en) * | 2015-08-27 | 2019-05-21 | Mikro Mesa Technology Co., Ltd. | Micro-light emitting diode (micro-LED) device |
US10854785B2 (en) | 2015-10-01 | 2020-12-01 | Sensor Electronic Technology, Inc. | Contact configuration for optoelectronic device |
US10707379B2 (en) | 2015-10-01 | 2020-07-07 | Sensor Electronic Technology, Inc. | Configuration for optoelectronic device |
JP6361645B2 (ja) * | 2015-12-22 | 2018-07-25 | 日亜化学工業株式会社 | 発光装置 |
FR3050872B1 (fr) * | 2016-04-27 | 2019-06-14 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Diode electroluminescente comprenant au moins une couche intermediaire de plus grand gap disposee dans au moins une couche barriere de la zone active |
DE102016112587A1 (de) * | 2016-07-08 | 2018-01-11 | Osram Opto Semiconductors Gmbh | Strahlungsemittierender Halbleiterchip |
DE112018001504T5 (de) * | 2017-03-23 | 2020-03-12 | Seoul Semiconductor Co., Ltd. | Bildschirmgerät und verfahren zur herstellung desselben |
US10746387B2 (en) | 2017-03-31 | 2020-08-18 | Mind Head Llc | Low voltage security lighting systems for perimeter fences having tactical glare capabilities |
KR102601417B1 (ko) * | 2017-09-28 | 2023-11-14 | 서울바이오시스 주식회사 | 발광 다이오드 칩 |
US11282981B2 (en) * | 2017-11-27 | 2022-03-22 | Seoul Viosys Co., Ltd. | Passivation covered light emitting unit stack |
DE102017129226A1 (de) | 2017-12-08 | 2019-06-13 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und anzeigevorrichtung |
US10418510B1 (en) * | 2017-12-22 | 2019-09-17 | Facebook Technologies, Llc | Mesa shaped micro light emitting diode with electroless plated N-contact |
EP4297105A3 (en) * | 2017-12-22 | 2024-04-24 | Seoul Viosys Co., Ltd. | Chip scale package light emitting diode |
US10325889B1 (en) | 2018-01-12 | 2019-06-18 | Mikro Mesa Technology Co., Ltd. | Display device including LED devices with selective activation function |
CN108461583B (zh) * | 2018-02-05 | 2019-11-08 | 广东省半导体产业技术研究院 | 一种紫外led芯片的制作方法 |
US10784407B2 (en) | 2018-04-23 | 2020-09-22 | Asahi Kasei Kabushiki Kaisha | Nitride semiconductor light emitting element and nitride semiconductor light emitting device |
KR102565148B1 (ko) * | 2018-06-27 | 2023-08-18 | 서울바이오시스 주식회사 | 플립칩형 발광 다이오드 칩 및 그것을 포함하는 발광 장치 |
DE102018117018A1 (de) * | 2018-07-13 | 2020-01-16 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauelement mit einer silberhaltigen stromaufweitungsstruktur und optoelektronische vorrichtung |
FR3087579B1 (fr) * | 2018-10-22 | 2022-08-12 | Aledia | Dispositif optoelectronique a diodes electroluminescentes a extraction de lumiere amelioree |
JP6915029B2 (ja) * | 2018-11-30 | 2021-08-04 | シャープ株式会社 | マイクロ発光素子及び画像表示素子 |
US11362073B2 (en) * | 2019-02-08 | 2022-06-14 | Seoul Viosys Co., Ltd. | Light emitting device including multiple transparent electrodes for display and display apparatus having the same |
CN111341895A (zh) * | 2020-03-10 | 2020-06-26 | 淄博职业学院 | 一种发光二极管 |
CN114242875B (zh) * | 2021-12-06 | 2023-09-01 | 华引芯(武汉)科技有限公司 | 发光器件及其制作方法、照明装置及显示装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002026392A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体発光素子とその製造方法、及び半導体発光装置 |
JP2006108161A (ja) * | 2004-09-30 | 2006-04-20 | Toyoda Gosei Co Ltd | 半導体発光素子 |
KR20070065093A (ko) * | 2005-12-19 | 2007-06-22 | 주식회사 대우일렉트로닉스 | 유기 발광 소자 패널 |
WO2010074288A1 (ja) * | 2008-12-28 | 2010-07-01 | 有限会社Mtec | 高電圧駆動の発光ダイオードモジュール |
US20120228655A1 (en) * | 2011-03-08 | 2012-09-13 | Opto Tech Corporation | Light emitting diode with large viewing angle and fabricating method thereof |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3557011B2 (ja) * | 1995-03-30 | 2004-08-25 | 株式会社東芝 | 半導体発光素子、及びその製造方法 |
US6784463B2 (en) * | 1997-06-03 | 2004-08-31 | Lumileds Lighting U.S., Llc | III-Phospide and III-Arsenide flip chip light-emitting devices |
EP1928034A3 (en) | 1997-12-15 | 2008-06-18 | Philips Lumileds Lighting Company LLC | Light emitting device |
JP2004101587A (ja) * | 2002-09-05 | 2004-04-02 | Nec Corp | レンズ駆動装置 |
US7064353B2 (en) * | 2004-05-26 | 2006-06-20 | Philips Lumileds Lighting Company, Llc | LED chip with integrated fast switching diode for ESD protection |
JP2006012916A (ja) * | 2004-06-22 | 2006-01-12 | Toyoda Gosei Co Ltd | 発光素子 |
US7534633B2 (en) * | 2004-07-02 | 2009-05-19 | Cree, Inc. | LED with substrate modifications for enhanced light extraction and method of making same |
KR20060030350A (ko) * | 2004-10-05 | 2006-04-10 | 삼성전자주식회사 | 백색광 발생 유닛, 이를 갖는 백라이트 어셈블리 및 이를갖는 액정표시장치 |
KR20060077801A (ko) | 2004-12-31 | 2006-07-05 | 엘지전자 주식회사 | 고출력 발광 다이오드 및 그의 제조 방법 |
TWI389337B (zh) * | 2005-05-12 | 2013-03-11 | Panasonic Corp | 發光裝置與使用其之顯示裝置及照明裝置,以及發光裝置之製造方法 |
JP4802314B2 (ja) * | 2006-01-24 | 2011-10-26 | シャープ株式会社 | 窒化物半導体発光素子とその製造方法 |
KR100833309B1 (ko) * | 2006-04-04 | 2008-05-28 | 삼성전기주식회사 | 질화물계 반도체 발광소자 |
EP2023412A1 (en) * | 2006-05-02 | 2009-02-11 | Mitsubishi Chemical Corporation | Semiconductor light-emitting device |
TWI344709B (en) * | 2007-06-14 | 2011-07-01 | Epistar Corp | Light emitting device |
EP2381495B1 (en) | 2008-12-19 | 2017-04-26 | Samsung Electronics Co., Ltd. | Light emitting device package |
CN101881400A (zh) * | 2009-05-05 | 2010-11-10 | 厦门市信达光电科技有限公司 | Led路灯光源模组 |
JPWO2011071100A1 (ja) | 2009-12-11 | 2013-04-22 | 豊田合成株式会社 | 半導体発光素子、半導体発光素子を用いた発光装置および電子機器 |
KR101654340B1 (ko) * | 2009-12-28 | 2016-09-06 | 서울바이오시스 주식회사 | 발광 다이오드 |
KR101579220B1 (ko) | 2010-03-26 | 2015-12-23 | 주식회사 솔라코 컴퍼니 | 엘이디 조명모듈 및 이를 이용한 조명램프 |
KR101125335B1 (ko) * | 2010-04-15 | 2012-03-27 | 엘지이노텍 주식회사 | 발광소자, 발광소자 제조방법 및 발광소자 패키지 |
KR101795053B1 (ko) * | 2010-08-26 | 2017-11-07 | 엘지이노텍 주식회사 | 발광 소자, 발광 소자 패키지, 라이트 유닛 |
KR101746004B1 (ko) * | 2010-10-29 | 2017-06-27 | 엘지이노텍 주식회사 | 발광소자 |
KR20120053571A (ko) | 2010-11-18 | 2012-05-29 | 서울옵토디바이스주식회사 | 복수의 메사 구조체를 갖는 발광 다이오드 칩 |
CN102544250B (zh) * | 2010-12-27 | 2014-05-07 | 同方光电科技有限公司 | 一种GaN基发光二极管的制作方法 |
KR20120079363A (ko) * | 2011-01-04 | 2012-07-12 | 삼성전자주식회사 | 광원용 렌즈, 이를 갖는 광원 모듈 및 백라이트 어셈블리 |
US9166126B2 (en) * | 2011-01-31 | 2015-10-20 | Cree, Inc. | Conformally coated light emitting devices and methods for providing the same |
CN102339913B (zh) * | 2011-09-30 | 2013-06-19 | 映瑞光电科技(上海)有限公司 | 高压led器件及其制造方法 |
CN106252491A (zh) * | 2012-05-29 | 2016-12-21 | 晶元光电股份有限公司 | 发光装置 |
CN109979925B (zh) * | 2012-12-06 | 2024-03-01 | 首尔伟傲世有限公司 | 发光二极管 |
-
2013
- 2013-10-22 CN CN201910265288.8A patent/CN109979925B/zh active Active
- 2013-10-22 CN CN201380072266.0A patent/CN105074941B/zh active Active
- 2013-10-22 CN CN201910834913.6A patent/CN110600593B/zh active Active
- 2013-10-22 WO PCT/KR2013/009395 patent/WO2014088201A1/ko active Application Filing
- 2013-10-22 DE DE202013012758.9U patent/DE202013012758U1/de not_active Expired - Lifetime
- 2013-10-22 DE DE112013005849.9T patent/DE112013005849T5/de active Pending
-
2015
- 2015-06-08 US US14/733,787 patent/US9608171B2/en active Active
- 2015-06-19 US US14/745,284 patent/US9548425B2/en active Active
-
2017
- 2017-03-27 US US15/470,811 patent/US10497836B2/en active Active
-
2019
- 2019-10-22 US US16/660,460 patent/US10749080B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002026392A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体発光素子とその製造方法、及び半導体発光装置 |
JP2006108161A (ja) * | 2004-09-30 | 2006-04-20 | Toyoda Gosei Co Ltd | 半導体発光素子 |
KR20070065093A (ko) * | 2005-12-19 | 2007-06-22 | 주식회사 대우일렉트로닉스 | 유기 발광 소자 패널 |
WO2010074288A1 (ja) * | 2008-12-28 | 2010-07-01 | 有限会社Mtec | 高電圧駆動の発光ダイオードモジュール |
US20120228655A1 (en) * | 2011-03-08 | 2012-09-13 | Opto Tech Corporation | Light emitting diode with large viewing angle and fabricating method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN105074941B (zh) | 2019-10-08 |
CN109979925B (zh) | 2024-03-01 |
CN110600593B (zh) | 2023-01-03 |
US20150270442A1 (en) | 2015-09-24 |
US20150287888A1 (en) | 2015-10-08 |
CN110600593A (zh) | 2019-12-20 |
US20200098949A1 (en) | 2020-03-26 |
DE112013005849T5 (de) | 2015-08-20 |
CN109979925A (zh) | 2019-07-05 |
DE202013012758U1 (de) | 2019-04-29 |
US9608171B2 (en) | 2017-03-28 |
CN105074941A (zh) | 2015-11-18 |
US9548425B2 (en) | 2017-01-17 |
US20170200864A1 (en) | 2017-07-13 |
US10749080B2 (en) | 2020-08-18 |
US10497836B2 (en) | 2019-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2014088201A1 (ko) | 발광 다이오드 및 그것의 어플리케이션 | |
WO2020141845A1 (ko) | 발광 소자 패키지 및 이를 포함한 표시 장치 | |
WO2014098510A1 (en) | Light emitting diode and method of fabricating the same | |
WO2016021919A1 (ko) | 발광 다이오드 및 그 제조 방법 | |
WO2016064134A2 (en) | Light emitting device and method of fabricating the same | |
WO2017030396A1 (ko) | 발광 소자, 이 소자를 포함하는 발광 소자 패키지 및 이 패키지를 포함하는 발광 장치 | |
WO2016133292A1 (ko) | 광 추출 효율이 향상된 발광 소자 | |
WO2016204482A1 (ko) | 복수의 파장변환부를 포함하는 발광 소자 및 그 제조 방법 | |
WO2017138707A1 (ko) | 고출력 발광 다이오드 및 그것을 갖는 발광 모듈 | |
WO2015133685A1 (en) | Backlight module with mjt led and backlight unit incluing the same | |
WO2018044102A1 (ko) | 칩 스케일 패키지 발광 다이오드 | |
WO2019045505A1 (ko) | 반도체 소자 및 이를 포함하는 헤드 램프 | |
WO2016117905A1 (ko) | 광원 모듈 및 조명 장치 | |
WO2017135763A1 (ko) | 발광소자 및 이를 포함하는 발광소자 패키지 | |
WO2010038976A2 (en) | Semiconductor light emitting device and method of manufacturing the same | |
WO2016032193A1 (ko) | 발광 소자 및 이의 제조 방법 | |
WO2017034212A1 (ko) | 발광소자 및 이를 구비한 발광 소자 패키지 | |
WO2013183888A1 (ko) | 발광소자 | |
WO2019039769A1 (ko) | 분포 브래그 반사기를 가지는 발광 다이오드 | |
WO2016148424A1 (ko) | 금속 벌크를 포함하는 발광 소자 | |
WO2017039208A1 (ko) | Zno 투명 전극을 갖는 발광 소자 및 그것을 제조하는 방법 | |
WO2021133124A1 (ko) | Led 디스플레이 장치 | |
WO2015147518A1 (ko) | 렌즈, 이를 포함하는 발광소자 모듈 | |
WO2013162337A1 (en) | Light emitting device and light emitting device package | |
WO2020241993A1 (ko) | 수직형 발광 다이오드 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201380072266.0 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13859683 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112013005849 Country of ref document: DE Ref document number: 1120130058499 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13859683 Country of ref document: EP Kind code of ref document: A1 |