CN110600593A - 照明模块 - Google Patents

照明模块 Download PDF

Info

Publication number
CN110600593A
CN110600593A CN201910834913.6A CN201910834913A CN110600593A CN 110600593 A CN110600593 A CN 110600593A CN 201910834913 A CN201910834913 A CN 201910834913A CN 110600593 A CN110600593 A CN 110600593A
Authority
CN
China
Prior art keywords
layer
type semiconductor
conductive type
semiconductor layer
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910834913.6A
Other languages
English (en)
Other versions
CN110600593B (zh
Inventor
蔡钟炫
李俊燮
卢元英
姜珉佑
张锺敏
金贤儿
徐大雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seoul Viosys Co Ltd
Original Assignee
Seoul Viosys Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120140991A external-priority patent/KR102013364B1/ko
Priority claimed from KR1020120155783A external-priority patent/KR102071036B1/ko
Priority claimed from KR1020130011453A external-priority patent/KR101984932B1/ko
Application filed by Seoul Viosys Co Ltd filed Critical Seoul Viosys Co Ltd
Publication of CN110600593A publication Critical patent/CN110600593A/zh
Application granted granted Critical
Publication of CN110600593B publication Critical patent/CN110600593B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/405Reflective materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05118Zinc [Zn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518Molybdenum [Mo] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05558Shape in side view conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05559Shape in side view non conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/06102Disposition the bonding areas being at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

本发明提供一种发光二极管。所述发光二极管包含:透明衬底,具有第一表面、第二表面以及侧表面;第一导电型半导体层,位于所述透明衬底的所述第一表面上;第二导电型半导体层,位于所述第一导电型半导体层上;作用层,位于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,由所述作用层产生的光通过所述透明衬底的所述第二表面发射到所述透明衬底外部,并且所述发光二极管在至少一个轴向方向上具有至少140度的光束角。因此,可以提供一种适合于背光单元或表面照明设备的发光二极管。

Description

照明模块
本发明是2013年10月22日所提出的申请号为201380072266.0、发明名称为《发光二极管、照明模块、照明设备和背光单元》的发明专利申请的分案申请。
技术领域
本发明涉及一种发光二极管,并且更具体地说,涉及一种具有改良的光束角的倒装芯片型发光二极管。
背景技术
已开发氮化镓(GaN)类发光二极管,且GaN类LED已经广泛地用于各种应用中,包括全色LED显示器、LED交通标志牌、背光单元、照明装置等等。
一般来说,氮化镓类发光二极管通过使外延层在例如蓝宝石衬底等衬底上生长来形成,并且包含N型半导体层、P型半导体层以及插入其间的作用层。另一方面,将N-电极衬垫形成于N型半导体层上并且将P-电极衬垫形成于P型半导体层上。发光二极管通过电极衬垫电连接到外部电源并由此进行操作。这里,电流通过半导体层从P-电极衬垫流动到N-电极衬垫。
另一方面,倒装芯片型发光二极管用于防止P-电极衬垫的光损失,同时提高热耗散效率。倒装芯片型发光二极管发光穿过生长衬底,并因此相比于发光穿过其外延层的垂直型发光二极管,可以减少P-电极衬垫的光损失。此外,侧向型发光二极管被配置成将热通过例如蓝宝石衬底等生长衬底排放并因此具有低的热耗散效率。相反,倒装芯片型发光二极管通过电极衬垫排放热并因此具有高的热耗散效率。
此外,垂直型发光二极管通过从外延层去除例如蓝宝石衬底等生长衬底来构造以提高光提取效率。具体地说,垂直型发光二极管可以通过将半导体层的暴露的表面纹理化来防止光因全内反射而损失。
另一方面,在特定应用中,具体地说,在需要光照射在如背光单元或薄片照明设备中的广泛区域上的应用中,光束角是一个重要的问题。
一般来说,常规的倒装芯片型发光二极管具有约120°的光束角,并且典型的垂直型发光二极管因表面纹理化而具有小于约120°的光束角。因此,在现有技术中,使用模制构件或另外的二级透镜来在封装级下增加光束角。
另一方面,例如LED荧光灯等照明设备可能需要根据方向具有不同光束角的LED。当多个LED安装在细长荧光灯形状的照明设备内部时,LED宜在与荧光灯的纵向方向正交的方向上具有大的光束角。
发明内容
技术问题
本发明的实施例提供一种适合于背光单元或薄片照明设备的倒装芯片型发光二极管以及其应用。
本发明的实施例提供一种通过改善反射率而提高光提取效率的倒装芯片型发光二极管。
本发明的实施例提供一种具有提高的电流扩展性能的倒装芯片型发光二极管。
本发明的实施例提供一种根据方向具有不同光束角的发光二极管以及包括所述发光二极管的照明设备。
本发明的实施例提供一种具有提高的发光效率的倒装芯片型发光二极管以及包括所述发光二极管的照明设备。
技术解决方案
根据本发明的一个方面,发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,放置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出。此外,发光二极管在其至少一个轴向方向上具有140°或超过140°的光束角。
不同于典型的发光二极管,根据本发明的实施例的发光二极管在未使用透镜形状的模制构件或二级透镜下具有140°或超过140°的相对较宽的光束角。因此,根据本发明的实施例的发光二极管适合于包含薄片照明设备在内的照明设备。根据本发明的实施例的发光二极管可以不用另一包装工艺而直接用于各种应用。此外,发光二极管可在无二级透镜下使用,或可在二级透镜耦接后连同一起使用。
在一些实施例中,发光二极管可还包含覆盖透明衬底的第二表面的保形涂层。穿过第二表面发射的光穿过保形涂层放出。保形涂层可以含有磷光体并因此可以将作用层中产生的至少一部分光的波长转换。
透明衬底与保形涂层的总厚度可以在225微米到600微米范围内。此外,透明衬底的厚度可以是150微米到400微米。此外,保形涂层的厚度可以是20微米到200微米。
在一些实施例中,透明衬底的厚度可以是225微米到400微米。因为透明衬底具有225微米到400微米的厚度,所以可以提供一种无论是否存在保形涂层,都具有140°或超过140°的光束角的倒装芯片型发光二极管。如果透明衬底的厚度超出400微米,那么难以将衬底分割成个别的发光二极管芯片。
发光二极管可以在第一导电型半导体层上包含多个彼此分隔开的凸台。每一凸台包含作用层和第二导电型半导体层。
发光二极管可以还包含:反射电极,分别置于所述多个凸台上并与所述第二导电型半导体层形成欧姆接触;以及电流扩展层,覆盖所述多个凸台和所述第一导电型半导体层并具有分别置于所述多个凸台的上部区域中同时使所述反射电极暴露的开口,所述电流扩展层与第一导电型半导体层形成欧姆接触并与多个凸台隔绝。通过所述开口,第一衬垫可以电连接到电流扩展层并且第二衬垫可以电连接到反射电极。
因为电流扩展层覆盖多个凸台和第一导电型半导体层,所以发光二极管通过电流扩展层具有提高的电流扩展性能。
第一导电型半导体层可以为连续的。此外,多个凸台可以具有在一个方向上延伸的细长形状并可以彼此平行安置。电流扩展层的开口可以被放置成偏向多个凸台的同一末端。因此,可以容易地形成将通过电流扩展层的开口暴露的反射电极彼此连接的衬垫。
电流扩展层可以包含例如Al等反射金属。在此结构下,除反射电极的光反射外,可以通过电流扩展层提供光反射,从而由此可以反射穿过多个凸台的侧壁和第一导电型半导体层的光。
另一方面,每一反射电极可以包含反射金属层和阻挡金属层。此外,阻挡金属层可以覆盖反射金属层的上表面和侧表面。在此结构下,可以通过防止反射金属层暴露于外部,来防止反射金属层退化。
发光二极管可以还包含:上部绝缘层,覆盖所述电流扩展层的至少一部分并包含使所述反射电极暴露的开口;以及第二衬垫,置于所述上部绝缘层上并电连接到通过上部绝缘层的开口暴露的反射电极。
第一衬垫和第二衬垫可以具有相同形状和相同尺寸,由此有助于倒装芯片粘结。
发光二极管可以还包含下部绝缘层,所述下部绝缘层置于多个凸台与电流扩展层之间并将电流扩展层与多个凸台隔绝。下部绝缘层可以包含开口,所述开口分别置于凸台的上部区域中并使反射电极暴露。
此外,电流扩展层的每一开口可以具有比下部绝缘层的开口大的宽度,从而允许下部绝缘层的对应开口通过其被完全地暴露。也就是说,电流扩展层的侧壁可以置于下部绝缘层上。此外,发光二极管可以还包含上部绝缘层,所述上部绝缘层覆盖电流扩展层的至少一部分并包含使反射电极暴露的开口。上部绝缘层可以覆盖电流扩展层的开口的侧壁。
下部绝缘层可以是反射介电层,例如分布式布拉格反射器(DBR)。
根据本发明的另一个方面,发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,放置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出,并且透明衬底具有225μm到400微米的厚度。
根据本发明的另一个方面,发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;第二衬垫,电连接到所述第二导电型半导体层;以及覆盖透明衬底的保形涂层。此外,在作用层中产生的光穿过保形涂层放出,并且透明衬底与保形涂层的总厚度可以在225微米到600微米范围内。
此外,透明衬底的厚度可以是150微米到400微米。此外,保形涂层的厚度可以是20微米到200微米。
根据本发明的又一个方面,照明模块包含多个发光二极管,至少一个所述发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出。此外,至少一个发光二极管在其至少一个轴向方向上具有140°或超过140°的光束角。
透明衬底具有225微米到400微米的厚度。
至少一个发光二极管可还包含覆盖透明衬底的第二表面的保形涂层。透明衬底与保形涂层的总厚度可以在225微米到600微米范围内。这里,保形涂层的厚度可以是20微米到200微米。
根据本发明的又一个方面,提供一种包含所述照明模块的照明设备。所述照明模块包含多个发光二极管,至少一个所述发光二极管具有与上述相同的结构。
根据本发明的又一个方面,背光单元包含多个发光二极管,至少一个所述发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出。此外,至少一个发光二极管在其至少一个轴向方向上具有140°或超过140°的光束角。
透明衬底可以具有225微米到400微米的厚度。
至少一个发光二极管可以还包含覆盖透明衬底的第二表面的保形涂层,并且透明衬底与保形涂层的总厚度可以在225微米到600微米范围内。此外,保形涂层的厚度可以是20微米到200微米。
根据本发明的又一个方面,发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出,并且透明衬底具有包含至少一个锐角的多边形形状。
因为靠近锐角部分放出的光的量增加,所以发光二极管具有提高的光提取效率并允许其光束角进行调节。因此,可以提供根据方向具有不同光束角的发光二极管。
透明衬底可以具有100微米到400微米的厚度。此外,包含至少一个锐角的多边形形状可以是三角形形状、平行四边形形状或五边形形状。此外,透明衬底可以是蓝宝石衬底。此外,透明衬底可以具有平行四边形并且透明衬底的侧表面可以由一组m型平面构成。因为透明衬底的侧表面由此群m型平面构成,所以可以沿着此群m型平面的晶体平面进行晶片划线,由此防止在衬底分成个别的发光二极管期间发生例如碎裂等破坏。
发光二极管可以还包含置于第二导电型半导体层上并反射作用层中产生的光的反射电极。发光二极管允许光被反射电极反射,由此提高了发光效率。
另一方面,作用层和第二导电型半导体层可以限制性地置于第一导电型半导体层的上部区域内,使得第一导电型半导体层的上表面沿着衬底的边缘暴露。
发光二极管可以还包含将第一衬垫连接到第一导电型半导体层的电流扩展层,并且第一衬垫和第二衬垫可以置于第二导电型半导体层上面。此结构可以减少第一衬垫与第二衬垫之间的高度差异,由此有助于倒装芯片粘结。
电流扩展层可以包含反射金属。在发光二极管中,光被反射电极和电流扩展层反射,由此进一步提高了发光二极管的发光效率。
发光二极管可以还包含将电流扩展层与反射电极隔绝的下部绝缘层。所述下部绝缘层包含使第一导电型半导体层暴露的开口并且电流扩展层可以通过下部绝缘层的开口连接到第一导电型半导体层。
在一些实施例中,开口可以分别沿着衬底的边缘呈细长形状安置。此外,与其它角度部分相比,在至少一个锐角部分上开口可以彼此分隔得更远。在此结构下,发光二极管可以防止电流集聚在锐角部分。
在其它实施例中,开口可以包含沿着衬底的边缘彼此分隔开的多个孔洞。孔洞之间的距离可以随着孔洞接近至少一个锐角部分而增加。在此结构下,可以减轻锐角部分的电流集聚。
发光二极管可以经形成以具有倾斜的侧表面,使得第一表面具有比第二表面大的面积。发光二极管的倾斜侧表面进一步提高了光提取效率。
在一些实施例中,发光二极管可以还包含覆盖衬底的第二表面的保形涂层。透明衬底与保形涂层的总厚度可以在225微米到600微米范围内,从而发光二极管具有增加的光束角。
根据本发明的又一个方面,提供一种包含多个发光二极管的照明设备。在发光二极管中,至少一个发光二极管包含:透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;第一导电型半导体层,置于所述透明衬底的第一表面上;第二导电型半导体层,置于所述第一导电型半导体层上;作用层,置于所述第一导电型半导体层与所述第二导电型半导体层之间;第一衬垫,电连接到所述第一导电型半导体层;以及第二衬垫,电连接到所述第二导电型半导体层。此外,在作用层中产生的光经由透明衬底的第二表面穿过透明衬底放出,并且透明衬底具有包含至少一个锐角的多边形形状。
根据本发明的又一个方面,发光二极管包含:第一导电型半导体层,置于具有第一表面和与第一表面相对的第二表面的衬底的第一表面上;凸台,包含依序堆叠在第一导电型半导体层上的作用层和第二导电型半导体层,所述凸台在平面图中具有包含锐角和钝角的多边形形状并且使第一导电型半导体层暴露于其外部;下部绝缘层,覆盖凸台并包含多个与凸台外侧相邻放置并使第一导电型半导体层暴露的第一开口和使第二导电型半导体层的上表面暴露的第二开口;第一衬垫,通过第一开口电连接到第一导电型半导体层;以及第二衬垫,通过第二开口电连接到第二导电型半导体层。此外,靠近凸台的锐角放置的第一开口之间的距离超过靠近凸台的钝角放置的第一开口之间的距离。在此结构下,发光二极管可以防止电流集聚。
有利作用
根据本发明的实施例,倒装芯片型发光二极管具有相对较宽的光束角。因此,倒装芯片型发光二极管可以适用于背光单元或薄片照明设备中。具体地说,在具有宽光束角的发光二极管的配置中,可以减少发光二极管的数目或实现背光单元或照明模块的细长结构。
根据本发明的实施例,倒装芯片型发光二极管通过提高反射率而具有提高的光提取效率,并具有提高的电流扩展性能。
根据本发明的实施例,倒装芯片型发光二极管采取一种包含至少一个锐角部分的衬底,由此提高了发光效率同时显示根据方向不同的光束角。此外,照明设备采用此类发光二极管,由此实现了广泛区域的照射同时减少光损失。
附图说明
图1(a)到图5(a)、图1(b)到图5(b)为说明一种制造根据本发明的一个实施例的发光二极管的方法的图,其中图1(a)到图5(a)展示平面图并且图1(b)到图5(b)展示沿着线A-A获取的截面图。
图6为凸台结构的修改的平面图。
图7为根据本发明的一个实施例的发光二极管的截面图。
图8为根据本发明的另一个实施例的发光二极管的截面图。
图9到图12为描绘视衬底厚度而定的发光二极管的光束角特征的图。
图13为描绘发光二极管的光束角与衬底厚度之间的关系的图。
图14到图17为描绘视衬底厚度而定的每一个具有保形涂层的发光二极管的光束角特征的图。
图18为描绘每一个具有保形涂层的发光二极管的光束角与衬底厚度之间的关系的图。
图19(a)、图19(b)及图19(c)展示采用典型发光二极管的发光二极管模块和采用根据本发明的发光二极管的发光二极管模块的示意性截面图。
图20(a)到图24(a)、图20(b)到图24(b)为说明制造根据本发明的一个实施例的发光二极管的方法的图,其中图20(a)到图24(a)展示平面图并且图20(b)到图24(b)展示沿着线A-A获取的截面图。
图25为说明制造根据本发明的一个实施例的发光二极管的方法的图。
图26描述根据本发明的一个实施例的发光二极管100a的结构。
图27是根据本发明的又一个实施例的发光二极管200a的截面图。
图28(a)及图28(b)展示说明视衬底形状而定的光提取特征的示意平面图。
图29是描绘通过典型方法构造的倒装芯片型发光二极管和通过根据本发明的一个实施例的方法构造的倒装芯片型发光二极管的光束角的图。
具体实施方式
下文中,将参考附图来更详细地描述本发明的实施例。以下实施例是通过实例提供,从而将本发明的精神完全传达给本发明所涉及的领域的技术人员。因此,本发明不限于本文中所揭露的实施例并且还可以用不同形式实现。在附图中,元件的宽度、长度、厚度等等可能出于清楚和描述的目的而被放大。贯穿本说明书,相似的参考数字指代具有相同或类似功能的相似元件。
首先,将描述一种制造发光二极管的方法,以帮助理解根据本发明的一个实施例的倒装芯片型发光二极管的结构。
图1(a)到图5(a)、图1(b)到图5(b)为说明一种制造根据本发明的一个实施例的发光二极管的方法的图,其中图1(a)到图5(a)展示平面图并且图1(b)到图5(b)展示沿着线A-A获取的截面图。
首先,参看图1(a)及图1(b),第一导电型半导体层23形成于衬底21上,并且作用层25和第二导电型半导体层27置于第一导电型半导体层23上。衬底21为用于GaN类半导体层生长的衬底并且可以是例如蓝宝石衬底、碳化硅衬底、氮化镓衬底、氮化铟镓衬底、氮化铝镓衬底、氮化铝衬底、氧化镓衬底等等。具体地说,衬底可以是蓝宝石衬底。
第一导电型半导体层23可以是掺杂有n型杂质的氮化物类半导体层。在一个实施例中,第一导电型半导体层23可以是掺杂有Si的InxAlyGa1-x-yN层(0≤x≤1,0≤y≤1,0≤x+y≤1)。举例来说,第一导电型半导体层23可以是掺杂Si的GaN层。第二导电型半导体层27可以是掺杂有p型杂质的氮化物类半导体层。在一个实施例中,第二导电型半导体层27可以是掺杂有Mg或Zn的InxAlyGa1-x-yN层(0≤x≤1,0≤y≤1,0≤x+y≤1)。举例来说,第二导电型半导体层27可以是掺杂Mg的GaN层。作用层25可以包含InxAlyGa1-x-yN(0≤x≤1,0≤y≤1,0≤x+y≤1)的阱层并且可以具有单量子阱结构或多量子阱结构。在一个实施例中,作用层25可以具有InGaN、GaN或AlGaN层的单量子阱结构或InGaN/GaN层、GaN/AlGaN层或AlGaN/AlGaN层的多量子阱结构。
第一导电型半导体层23、作用层25和第二导电型半导体层27可以通过金属有机化学气相沉积(MOCVD)或分子束外延法(MBE)形成。
多个凸台M可以彼此分隔地形成于第一导电型半导体层23上,并且每一凸台M可以包含作用层25和第二导电型半导体层27。作用层25置于第一导电型半导体层23与第二导电型半导体层27之间。另一方面,反射电极30置于每一凸台M上。
多个凸台M可以通过利用金属有机化学气相沉积等等使包含第一导电型半导体层23、作用层25和第二导电型半导体层27的外延层在衬底21的第一表面上生长,接着将第二导电型半导体层27和作用层25图案化,从而暴露第一导电型半导体层23来形成。多个凸台M可以使用光阻回流技术形成以具有倾斜的侧表面。凸台M的侧表面的倾斜型态提高了在作用层25中产生的光的提取效率。
如所示,多个凸台M可以具有在一个方向上延伸的细长形状并彼此平行安置。此类形状简化了具有相同形状的多个凸台M在衬底21上的多个芯片区域中的形成。
另一方面,反射电极30可以在多个凸台M形成后形成于相应凸台M上,但不限于此。或者,反射电极可以在形成凸台M前、在使第二导电型半导体层27生长后形成于第二导电型半导体层27上。反射电极30覆盖凸台M的上表面的大部分区域并且在平面图中具有与凸台M形状相同的形状。
反射电极30包含反射层28并且可以还包含阻挡层29。阻挡层29可以覆盖反射层28的上表面和侧表面。举例来说,阻挡层29可以通过形成反射层28的图案,接着在其上形成阻挡层29来形成以覆盖反射层28的上表面和侧表面。举例来说,反射层28可以通过Ag、Ag合金、Ni/Ag、NiZn/Ag或TiO/Ag层的沉积和图案化来形成。另一方面,阻挡层29可以由Ni、Cr、Ti、Pt或其组合形成并防止金属材料在反射层中扩散或污染。
在形成多个凸台M后,还可以蚀刻第一导电型半导体层23的边缘。结果,可以暴露衬底21的上表面。第一导电型半导体层23还可以经形成以具有倾斜的侧表面。
如图1(a)及图1(b)所示,多个凸台M可以限制性地放置在第一导电型半导体层23的上部区域内。具体来说,多个凸台M可以呈岛形状放置于第一导电型半导体层23的上部区域上。或者,凸台M可以在一个方向上延伸以达到第一导电型半导体层23的上表面的边缘,如图6所示。也就是说,多个凸台M的下表面在一个方向上的边缘可以与第一导电型半导体层23在所述一个方向上的边缘重合。在此结构下,第一导电型半导体层23的上表面被多个凸台M分割。
参看图2(a)及图2(b),下部绝缘层31经形成以覆盖多个凸台M和第一导电型半导体层23。下部绝缘层31包含开口31a、31b以允许在穿过其的特定区域中电连接到第一导电型半导体层23和第二导电型半导体层27。举例来说,下部绝缘层31可以包含使第一导电型半导体层23暴露的开口31a和使反射电极30暴露的开口31b。
开口31a可以置于凸台M与衬底21的靠近边缘之间,并且可以具有沿着凸台M延伸的细长形状。另一方面,开口31b限制性地置于凸台M的上部区域中以偏向凸台的同一末端。
下部绝缘层31可以由例如SiO2等氧化物、例如SiNx等氮化物或例如MgF2等绝缘材料通过化学气相沉积(CVD)等等形成。下部绝缘层31可以由单一层或多个层构成。此外,下部绝缘层31可以形成为分布式布拉格反射器(DBR),其中低折射率材料层和高折射率材料层交替堆叠在彼此之上。举例来说,具有高反射性的绝缘反射层可以通过堆叠例如SiO2/TiO2层或SiO2/Nb2O5层来形成。
参看图3(a)及图3(b),电流扩展层33形成于下部绝缘层31上。电流扩展层33覆盖多个凸台M和第一导电型半导体层23。此外,电流扩展层33包含开口33a,所述开口分别置于凸台M的上部区域中并使反射电极30暴露。电流扩展层33可以通过下部绝缘层31的开口31a与第一导电型半导体层23形成欧姆接触。电流扩展层33通过下部绝缘层31与多个凸台M和反射电极30隔绝。
电流扩展层33的每一开口33a具有比下部绝缘层31的开口31b大的面积以防止电流扩展层33连接到反射电极30。因此,开口33a具有置于下部绝缘层31上的侧壁。
除了开口33a外,电流扩展层33实质上在衬底21的整个上表面上形成。因此,电流可以容易地通过电流扩展层33扩展。电流扩展层33可以包含高反射金属层,例如Al层,并且高反射金属层可以形成于例如Ti、Cr或Ni层等粘结层上。此外,具有Ni、Cr、Au等等单一层或复合层结构的保护层可以形成于高反射金属层上。电流扩展层33可以具有例如Ti/Al/Ti/Ni/Au的多层结构。
参看图4(a)及图4(b),上部绝缘层35形成于电流扩展层33上。上部绝缘层35包含使电流扩展层33暴露的开口35a和使反射电极30暴露的开口35b。开口35a可以在相对于凸台M的纵向方向的垂直方向上具有细长形状,并具有比开口35b大的面积。开口35b使反射电极30暴露,其是通过电流扩展层33的开口33a和下部绝缘层31的开口31b暴露。开口35b具有比电流扩展层33的开口33a狭窄的面积和比下部绝缘层31的开口31b大的面积。因此,电流扩展层33的开口33a的侧壁可以被上部绝缘层35覆盖。
上部绝缘层35可以由氧化物绝缘层、氮化物绝缘层或例如聚酰亚胺、铁氟龙、聚对二甲苯基等聚合物形成。
参看图5(a)及图5(b),第一衬垫37a和第二衬垫37b形成于上部绝缘层35上。第一衬垫37a通过上部绝缘层35的开口35a连接到电流扩展层33,并且第二衬垫37b通过上部绝缘层35的开口35b连接到反射电极30。第一衬垫37a和第二衬垫37b可以用作连接用于将发光二极管安装在底座、包装或印刷电路板上的凸块的衬垫或用于SMT的衬垫。
第一衬垫37a和第二衬垫37b可以同时通过例如光刻法和蚀刻工艺或剥离工艺等相同工艺形成。第一衬垫37a和第二衬垫37b可以包含由例如Ti、Cr、Ni等形成的粘结层和由Al、Cu、Ag、Au等形成的高导电性金属层。
随后,衬底21被分成个别的发光二极管芯片,由此提供成品发光二极管芯片。此时,衬底21可以经受薄化工艺(thinning process),以在分成个别发光二极管芯片之前具有较薄的厚度。
下文中,将参考图7详细地描述根据本发明的一个实施例的发光二极管100的结构。
所述发光二极管包含衬底21、第一导电型半导体层23、作用层25、第二导电型半导体层27、第一衬垫37a以及第二衬垫37b,并且可以还包含反射电极30、电流扩展层33、下部绝缘层31、上部绝缘层35以及凸台M。
衬底21可以是用于氮化镓类外延层生长的生长衬底,例如蓝宝石衬底、碳化硅衬底或氮化镓衬底。衬底21可以包含第一表面21a、第二表面21b以及侧表面21c。第一表面21a是半导体层在上面生长的平面,并且第二表面21b是在作用层25中产生的光放到外部所通过的平面。侧表面21c将第一表面21a连接到第二表面21b。衬底21的侧表面21c可以垂直于第一表面21a和第二表面21b,但不限于此。或者,衬底的侧表面21d可以相对于其倾斜。举例来说,如图7中的虚线所指示,衬底21可以具有倾斜的侧表面21d,使得第一表面21a具有比第二表面21b大的面积。在此实施例中,衬底21可以具有225微米到400微米的厚度t1。
第一导电型半导体层23置于衬底21的第一表面21a上。第一导电型半导体层23是连续的,并且作用层25和第二导电型半导体层27置于第一导电型半导体层23上。具体地说,多个凸台M彼此分隔开置于第一导电型半导体层23上。如参考图1(a)及图1(b)所说明,凸台M包括作用层25和第二导电型半导体27并具有朝向一侧延伸的细长形状。此处,凸台M由氮化镓化合物半导体层的堆叠形成。如图1(a)及图1(b)所示,凸台M可以限制性地置于第一导电型半导体层23的上部区域内。或者,如图6中所示,凸台M可以延伸到第一导电型半导体层23的上表面在一个方向上的边缘,从而第一导电型半导体层23的上表面可以分成多个区域。在此结构下,发光二极管可以减轻靠近凸台M的拐角处的电流集聚,由此进一步提高了电流扩展性能。
反射电极30分别置于多个凸台M上以与第二导电型半导体层27形成欧姆接触。如参考图1(a)及图1(b)所说明,反射电极30可以包含反射层28和阻挡层29,并且阻挡层29可以覆盖反射层28的上表面和侧表面。
电流扩展层33覆盖多个凸台M和第一导电型半导体层23。电流扩展层33具有开口33a,所述开口分别置于相应凸台M的上部区域中,使得通过其使反射电极30暴露。电流扩展层33可以覆盖凸台M的整个区域,除了其中形成开口33a的凸台M的上部区域的一些区域,并且也可以覆盖第一导电型半导体层23的整个区域。电流扩展层33还与第一导电型半导体层23形成欧姆接触,并与多个凸台M隔绝。电流扩展层33可以包含例如Al等反射金属。
电流扩展层33可以通过下部绝缘层31与多个凸台M隔绝。举例来说,下部绝缘层31可以插入多个凸台M与电流扩展层33之间,以将电流扩展层33与多个凸台M隔绝。此外,下部绝缘层31可以具有开口31b,所述开口置于相应凸台M的上部区域内,使得通过其使反射电极30暴露;以及开口31a,通过所述开口使第一导电型半导体层23暴露。电流扩展层33可以通过开口31a连接到第一导电型半导体层23。下部绝缘层31的开口31b具有比电流扩展层33的开口33a小的面积,并且通过开口33a被完全地暴露。
上部绝缘层35覆盖电流扩展层33的至少一部分。上部绝缘层35具有开口35b,所述开口使反射电极30暴露。此外,上部绝缘层35可以具有开口35a,所述开口使电流扩展层33暴露。上部绝缘层35可以覆盖电流扩展层33的开口33a的侧壁。
第一衬垫37a可以置于电流扩展层33上并且例如可以通过上部绝缘层35的开口35a连接到电流扩展层33。第一衬垫37a通过电流扩展层33电连接到第一导电型半导体层23。此外,第二衬垫37b连接到通过开口35b暴露的反射电极30并通过反射电极30电连接到第二导电型半导体层27。
根据此实施例,因为衬底21具有225微米或超过225微米的厚度t1,所以发光二极管100的光束角可以增加到140°或超过140°。此外,因为电流扩展层33覆盖凸台M并实质上覆盖凸台M之间的第一导电型半导体层23的整个区域,所以电流可以容易地通过电流扩展层33扩展。
此外,电流扩展层33包含例如Al层等反射金属层,或下部绝缘层作为绝缘反射层而形成,从而未被反射电极30反射的光可以被电流扩展层33或下部绝缘层31反射,由此提高了光提取效率。
图8是根据本发明的另一个实施例的发光二极管200的截面图。
除了保形涂层50置于衬底21上外,根据此实施例的发光二极管200大体上类似于图7的发光二极管100。保形涂层50均匀地覆盖衬底21的第二表面21b并且也可以覆盖其侧表面21c。保形涂层50可以含有例如磷光体等波长转换材料。
此外,衬底21的厚度t1与保形涂层50的厚度t2的总和可以在225微米到600微米范围内。举例来说,保形涂层50可以具有20微米到200微米的厚度t2。此外,衬底21的厚度t1可以视保形涂层的厚度t2而变化,例如可以在150微米到400微米范围内。
当衬底21的厚度与保形涂层50的厚度的总和t1+t2大于或等于225微米时,发光二极管200的光束角可以增加到140°或超过140°。
图9到图12为描绘视衬底厚度而定的发光二极管的光束角特征的图。在每个图中,实线指示在第一轴线(x轴)上的光束角特征,并且虚线指示在与第一轴线正交的第二轴线(y轴)上的光束角特征。
作为衬底21,使用蓝宝石衬底,并且用不同厚度的蓝宝石衬底21制造具有如图7中所示的结构的发光二极管。发光二极管具有1毫米×1毫米的尺寸并且蓝宝石衬底21分别具有约80微米、150微米、250微米以及400微米的厚度。
参看图9到图12,可以证实光束分布随着衬底21的厚度从80微米增加到250微米而加宽。但是,当衬底21的厚度从250微米增加到400微米时,光束分布无显著差异。
图13是描绘图9到图12的发光二极管的光束角与衬底厚度之间的关系的图。术语“光束角”意谓其中显示1/2或超过1/2的最大光通量的光通量的角范围。“光束角”对应于在光束分布图中正规化强度变成0.5的从最小角到最大角的角度。
参看图13,随着衬底21的厚度t1增加到250微米,光束角增加到约140°并且当衬底21的厚度t1为250微米或超过250微米时,光束角未显著改变。
因此,当衬底21的厚度t1设定成250微米时,在衬底21上无其它透明膜下光束角可以维持在140°,并且甚至当衬底的厚度t1增加时光束角也未显著改变。
图14到图17为描绘视各种衬底厚度t1而定,每一个具有保形涂层的发光二极管200的光束角特征的图。在每个图中,实线指示在第一轴线(x轴)上的光束角特征,并且虚线指示在与第一轴线正交的第二轴线(y轴)上的光束角特征。
如参考图9到图12所描述,使用具有不同厚度t1的蓝宝石衬底21并且在每一衬底21上形成保形涂层50到约75微米的厚度t2,由此制造发光二极管200,如图8中所示。
参看图14到图17,可以证实光束分布随着衬底21的厚度从80微米增加到150微米而显著改变。此外,随着衬底21的厚度从150微米增加到400微米,尽管光通量倾向于稍微减少接近0°,但光束分布未显著改变。
图18是描绘图14到图17的发光二极管200的光束角与衬底厚度t1之间的关系的图,每一发光二极管都包含保形涂层50。
参看图18,随着衬底21的厚度t1增加到150微米,光束角增加到约143°,并且当衬底21的厚度t1为150微米或超过150微米时,光束角未显著改变。因此,可以看出,当衬底21的厚度t1与保形涂层50的厚度t2的总和达到225微米或超过225微米时,光束角最终达到140°或超过140°的值。
因此,当衬底21的厚度与保形涂层50的厚度的总和设定成225微米或超过225微米时,发光二极管200可以具有140°或超过140°的光束角。
从实验结果预期,在无保形涂层50下即使当衬底21具有约225微米的厚度时,也将提供具有140°或超过140°的光束角的发光二极管200。
图19(a)、图19(b)及图19(c)展示采用典型发光二极管10的发光二极管模块300a和采用根据本发明的发光二极管100的发光二极管模块300b、300c的截面示意图。此处,发光二极管模块300a、300b、300c将通过实例展示为用于照射液晶显示面板400的背光单元中。
参看图19(a)、图19(b)及图19(c),典型发光二极管10具有约120°的光束角θ1,而根据本发明的发光二极管100具有约140°或超过140°的光束角θ2
发光二极管模块与液晶显示面板400之间的距离可以由d表示,发光二极管的间距可以由p表示,并且发光二极管的光束角可以由θ表示。另一方面,当发光二极管被配置成防止其光束角彼此重叠时,间距p指示单一发光二极管所照射的液晶显示面板400的一个区域的宽度并由以下等式1表示。
等式1
p=2·d·tan(θ/2)
因此,典型发光二极管模块300a的间距p1和根据本发明的发光二极管模块300b的间距p2由等式2和等式3表示。
等式2
p1=2·d1·tan(θ1/2)
等式3
p2=2·d2·tan(θ2/2)
此处,因为发光二极管100的光束角θ2超过发光二极管10的光束角θ1并且θ2/2小于90°,所以建立以下等式4。
等式4
tan(θ1/2)<tan(θ2/2)
因此,如果等式2和等式3中d1=d2,那么建立以下等式5。
等式5
p2>p1(当d1=d2时)
也就是说,当图19(a)和图19(b)中所示的发光二极管模块300a、300b与液晶显示面板400分隔相同距离(d1=d2)并照射液晶显示面板400的相同区域时,根据本发明的发光二极管模块300b允许发光二极管100以比典型发光二极管模块300a更宽的间隔配置。因此,可以减少发光二极管模块300b中发光二极管100的数目。
另一方面,如图19(a)和图19(c)中所示,当典型发光二极管模块300a的发光二极管10的间距p1与根据本发明的发光二极管模块的发光二极管100的间距p3相同时,建立以下等式6。
等式6
d3<d1(当p1=p3时)
也就是说,当发光二极管模块300、300c包括相同数目的发光二极管时,根据本发明的发光二极管模块300c可以比发光二极管模块300a放置得更接近液晶显示面板400,由此实现了背光单元和液晶显示器的厚度的减少。
本文中,虽然发光二极管模块300a、300b、300c展示为用于背光单元中,但发光二极管模块300a、300b、300c还可以用作照明设备的照明模块。在此情况下,发光二极管模块300a、300b、300c可以照射照明设备的漫射板(相当于液晶显示面板400),并且如上所述,根据本发明的发光模块可以使用较少数目的发光二极管照射漫射板的相同区域,或允许发光二极管比典型发光模块放置得更接近漫射板。
然后,将描述一种制造发光二极管的方法以帮助理解根据本发明的另一个实施例的倒装芯片型发光二极管的结构。
图20(a)到图24(a)、图20(b)到图24(b)为说明制造根据本发明的一个实施例的发光二极管的方法的图,其中图20(a)到图24(a)展示平面图并且图20(b)到图24(b)展示沿着线A-A获取的截面图。
首先,参看图20(a)及图20(b),第一导电型半导体层123形成于衬底121上,并且作用层125和第二导电型半导体层127置于第一导电型半导体层123上。衬底121是用于氮化镓类半导体层生长的衬底并且可以是例如蓝宝石衬底、碳化硅衬底或氮化镓衬底。具体地说,衬底121可以是蓝宝石衬底。虽然衬底可以呈能够提供多个发光二极管的大的晶片形式提供,但图20(a)及图20(b)展示个别分离的最终发光二极管之一的衬底的一部分。在最终发光二极管中,衬底121可以具有含有锐角的平行四边形形状,例如菱形形状,但不限于此。或者,衬底可以具有含有锐角的多种多边形形状任一个,例如三角形形状、五边形形状等等。
第一导电型半导体层123可以是掺杂有n型杂质的氮化物类半导体层。在一个实施例中,第一导电型半导体层123可以是掺杂有Si的InxAlyGa1-x-yN层(0≤x≤1,0≤y≤1,0≤x+y≤1)。举例来说,第一导电型半导体层123可以是掺杂Si的GaN层。第二导电型半导体层127可以是掺杂有p型杂质的氮化物类半导体层。在一个实施例中,第二导电型半导体层127可以是掺杂有Mg或Zn的InxAlyGa1-x-yN层(0≤x≤1,0≤y≤1,0≤x+y≤1)。举例来说,第二导电型半导体层127可以是掺杂Mg的GaN层。作用层125可以包含InxAlyGa1-x-yN(0≤x≤1,0≤y≤1,0≤x+y≤1)的阱层并且可以具有单量子阱结构或多量子阱结构。在一个实施例中,作用层125可以具有InGaN、GaN或AlGaN层的单量子阱结构或InGaN/GaN层、GaN/AlGaN层或AlGaN/AlGaN层的多量子阱结构。
第一导电型半导体层123、作用层125和第二导电型半导体层127可以通过金属有机化学气相沉积(MOCVD)或分子束外延法(MBE)形成。
凸台可以形成于第一导电型半导体层123上并且第一导电型半导体层123的一些区域沿着凸台的边缘暴露。如图20(a)及图20(b)所示,第一导电型半导体层123的上表面可以沿着最终发光二极管的衬底121的边缘暴露,并且作用层125和第二导电型半导体层127可以限制性地置于第一导电型半导体层123的上部区域内。
凸台可以通过利用金属有机化学气相沉积等使包含第一导电型半导体层123、作用层125和第二导电型半导体层127的半导体堆叠结构126在衬底121的第一表面上生长,随后将第二导电型半导体层127和作用层125图案化从而暴露第一导电型半导体层123来形成。凸台可以使用光阻回流技术形成以具有倾斜的侧表面。凸台的侧表面的倾斜型态提高了在作用层125中产生的光的提取效率。此外,凸台具有在平面图中类似于衬底121的形状的形状。举例来说,凸台具有在平面图中类似于衬底121的至少一个锐角。在平面图中凸台可以具有包含一对彼此面对的钝角和一对彼此面对的锐角的四边形形状。钝角可以具有相同的值并且锐角可以具有相同的值。凸台的此类平面形状可以是菱形形状或菱形形状。
凸台的一个侧表面可以垂直于衬底121的平坦区域。在一个实施例中,当衬底121是蓝宝石衬底时,凸台的一个侧表面可以对准在m-型平面上。半导体堆叠结构126的平面形状也可以类似于凸台的平面形状。
另一方面,反射电极130形成于第二导电型半导体层127上。反射电极130可以在形成凸台之后形成于凸台上,但不限于此。或者,反射电极可以在形成凸台之前在第二导电型半导体层127生长之后形成于第二导电型半导体层127上。反射电极130覆盖第二导电型半导体层的上表面的大部分区域并且在平面图中具有实质上与凸台的形状相同的形状。
反射电极130包含反射层128并且可以还包含阻挡层129。阻挡层129可以覆盖反射层128的上表面和侧表面。举例来说,阻挡层129可以通过形成反射层128的图案,接着在其上形成阻挡层129来形成以覆盖反射层128的上表面和侧表面。举例来说,反射层128可以通过Ag、Ag合金、Ni/Ag、NiZn/Ag或TiO/Ag层的沉积和图案化来形成。另一方面,阻挡层129可以由Ni、Cr、Ti、Pt或其组合形成并防止金属材料在反射层128中扩散或污染。
在形成凸台之后,第一导电型半导体层123的边缘还可以经蚀刻以暴露衬底121的上表面。此处,第一导电型半导体层123还可以经形成以具有倾斜的侧表面。
参看图21(a)及图21(b),下部绝缘层131经形成以覆盖第一导电型半导体层123和反射电极130。下部绝缘层131包含开口131a、131b以允许在穿过其的特定区域中电连接到第一导电型半导体层123和第二导电型半导体层127。举例来说,下部绝缘层131可以包含使第一导电型半导体层123暴露的开口131a和使反射电极130暴露的开口131b。
开口131a可以在反射电极130周围靠近衬底121的边缘放置,并且可以具有沿着衬底121的边缘延伸的细长形状。如图21(a)及图21(b)中所示,与钝角部分相比,开口131a在锐角部分彼此分隔更远。在此结构下,可以防止在锐角部分附近电流集聚。在一个实施例中,靠近锐角部分的开口131a之间的距离可以大于或等于电流扩展长度,并且靠近钝角部分的开口131a之间的距离小于或等于电流扩展长度(current spreading length)。电流扩展长度意谓从p型电极的边缘到在施加驱动电流时电流密度减少到1/e的位置的长度。
另一方面,开口131b限制性地置于反射电极130的上部区域中并且可以偏向衬底121的锐角部分。在一个实施例中,开口131b可以具有三角形形状或梯形形状。
下部绝缘层131可以由例如SiO2等氧化物、例如SiNx等氮化物或例如MgF2等绝缘材料通过化学气相沉积(CVD)等等形成。下部绝缘层131可以由单一层或多个层构成。此外,下部绝缘层131可以形成为分布式布拉格反射器(DBR),其中低折射率材料层和高折射率材料层交替堆叠在彼此之上。举例来说,具有高反射性的绝缘反射层可以通过堆叠例如SiO2/TiO2层或SiO2/Nb2O5层来形成。
在此实施例中,使第一导电型半导体层123暴露的开口131a具有细长形状并且沿着衬底121的边缘形成。但是,应了解本发明并不限于此。举例来说,如图25中所示,使第一导电型半导体层123暴露的多个孔洞131c可以沿着衬底121的边缘配置。在此情况下,多个孔洞131c可以被配置成在孔洞从钝角部分接近锐角部分时彼此分隔得更远,由此缓解了电流集聚。此外,锐角部分的相对侧的孔洞131c之间的距离可以超过钝角部分相对侧的孔洞131c之间的距离。在一个实施例中,锐角部分相对侧的孔洞131c之间的距离可以大于或等于电流扩展长度,并且钝角部分相对侧的孔洞131c之间的距离可以小于或等于电流扩展长度。孔洞131c可以具有多边形形状、圆形形状或半圆形形状。
参看图22(a)及图22(b),电流扩展层133形成于下部绝缘层131上。电流扩展层133覆盖反射电极130和第一导电型半导体层123。此外,电流扩展层133包含开口133a,所述开口置于反射电极130的上部区域中并使反射电极130暴露。电流扩展层133可以通过下部绝缘层131的开口131a与第一导电型半导体层123形成欧姆接触。电流扩展层133通过下部绝缘层131与反射电极130隔绝。
电流扩展层133的开口133a具有比下部绝缘层131的开口131b大的区域,以防止电流扩展层133连接到反射电极130。因此,开口133a具有置于下部绝缘层131上的侧壁。
除了开口133a外,电流扩展层133实质上在衬底131的整个上表面上形成。因此,电流可以容易地通过电流扩展层133扩散。电流扩展层133可以包含高反射金属层,例如Al层,并且高反射金属层可以形成于例如Ti、Cr或Ni层等粘结层上。此外,具有Ni、Cr、Au等等单一层或复合层结构的保护层可以形成于高反射金属层上。电流扩展层133可以具有例如Ti/Al/Ti/Ni/Au的多层结构。
参看图23(a)及图23(b),上部绝缘层135形成于电流扩展层133上。上部绝缘层135包含使电流扩展层133暴露的开口135a和使反射电极130暴露的开口135b。开口135a和开口135b可以彼此面对面安置,并且可以安置在衬底121的锐角部分附近,如图23(a)中所示。此外,开口135b使反射电极130暴露,其是通过电流扩展层133的开口133a和下部绝缘层131的开口131b暴露。开口135b具有比电流扩展层133的开口133a狭窄的面积。因此,电流扩展层133的开口133a的侧壁可以被上部绝缘层135覆盖。另一方面,开口135b可以具有比下部绝缘层131的开口131b小的面积。或者,开口可以具有比下部绝缘层的开口大的面积。开口135a可以具有颠倒的梯形形状并且开口135b可以具有梯形形状。
上部绝缘层135可以使用氧化物绝缘层、氮化物绝缘层或例如聚酰亚胺、铁氟龙、聚对二甲苯基等聚合物形成。
参看图24(a)及图24(b),第一衬垫137a和第二衬垫137b形成于上部绝缘层135上。第一衬垫137a通过上部绝缘层135的开口135a连接到电流扩展层133,并且第二衬垫137b通过上部绝缘层135的开口135b连接到反射电极130。结果,第一衬垫137a可以通过电流扩展层133连接到第一导电型半导体层123,并且第二衬垫137b可以通过反射电极130连接到第二导电型半导体层127。第一衬垫137a和第二衬垫137b可以用作连接用于将发光二极管安装在底座、包装或印刷电路板上的凸块的衬垫或用于SMT(Surface Mounting Technology)的衬垫。
第一衬垫137a和第二衬垫137b可以同时通过例如光刻法和蚀刻工艺或剥离工艺等相同工艺形成。第一衬垫137a和第二衬垫137b每一个都可以包含由例如Ti、Cr、Ni等等形成的粘结层和由Al、Cu、Ag、Au等等形成的高导电性金属层。此外,第一衬垫137a和第二衬垫137b每一个可以还包含覆盖高导电性金属层的衬垫阻挡层。阻挡金属层防止例如锡(Sn)等金属元素在粘结或焊接的过程中扩散,由此防止第一衬垫137a和第二衬垫137b的比电阻增加。衬垫阻挡层可以由Cr、Ni、Ti、W、TiW、Mo、Pt或其组合形成。
随后,衬底121被分成个别的发光二极管芯片,由此提供成品发光二极管芯片。举例来说,衬底121可以通过沿着一组m型平面划线来分成具有平行四边形形状的个别发光二极管芯片。结果,可以提供包含衬底121的发光二极管,其侧表面由所述组的m型平面构成。
另一方面,衬底121可以经受薄化工艺(thinning process)以在分成个别的发光二极管芯片之前具有更薄的厚度。此处,衬底121的厚度可以超过100微米,具体地说为225微米到400微米。
另一方面,可以进一步形成保形涂层(参见图27的保形涂层150)以覆盖个别发光二极管芯片的衬底121。保形涂层150可以在衬底121分成个别芯片之前或之后形成。
下文中,将参考图26描述根据本发明的一个实施例的发光二极管100a的结构。
参看图26,发光二极管100a包含衬底121、第一导电型半导体层123、作用层125、第二导电型半导体层127、第一衬垫137a以及第二衬垫137b,并且可以包含反射电极130、电流扩展层133、下部绝缘层131以及上部绝缘层135。
衬底121可以是用于氮化镓类外延层生长的生长衬底,例如蓝宝石衬底、碳化硅衬底或氮化镓衬底。衬底121可以包含第一表面121a、第二表面121b以及侧表面121c。第一表面121a是半导体层在上面生长的平面,并且第二表面121b是在作用层125中产生的光放到外部所通过的平面。侧表面121c将第一表面121a连接到第二表面121b。衬底121的侧表面121c可以垂直于第一表面121a和第二表面121b,但不限于此。或者,衬底的侧表面121d可以相对于其倾斜。举例来说,如通过图26中的虚线指示,衬底121可以具有倾斜的侧表面121d,使得第一表面121a具有比第二表面121b大的面积。
此外,衬底121可以具有包含至少一个锐角的多边形形状。举例来说,第一表面121a和第二表面121b可以具有多边形形状,例如平行四边形形状、三角形形状、五边形形状等等,如图20(a)及图20(b)中所示。因为衬底121包含锐角,所以发光二极管通过锐角部分提高了光提取效率,同时在锐角部分增加光束角。
在此实施例中,衬底121的厚度可以超过100微米,尤其在225微米到400微米范围内。光束角可以随着衬底121的厚度增加而增加,并且当衬底121具有225μm或超过225μm的厚度时,光束角可以一般维持恒定。
第一导电型半导体层123置于衬底121的第一表面121a上。第一导电型半导体层123可以覆盖衬底121的第一表面121a的整个表面,但不限于此。或者,第一导电型半导体层123可以限制性地置于衬底121的上部区域内,从而允许第一表面121a沿着衬底121的边缘暴露。
包含作用层125和第二导电型半导体层127的凸台置于第一导电型半导体层123上。具体地说,作用层125和第二导电型半导体层127限制性地置于第一导电型半导体层123的上部区域内,如参考图20(a)及图20(b)所描述。因此,第一导电型半导体层123的一些区域可以尤其沿着衬底121的边缘暴露。
反射电极130与第二导电型半导体层127形成欧姆接触。如参考图20(a)及图20(b)所描述,反射电极130包括反射层128和阻挡层129,所述阻挡层129可以覆盖反射层128的上表面和侧表面。
电流扩展层133覆盖反射电极130和第一导电型半导体层123。电流扩展层133具有开口133a,所述开口置于反射电极130的上部区域中,使得通过其使反射电极130暴露。电流扩展层133可以覆盖反射电极130的整个区域,除了其中形成开口133a的反射电极130的上部区域的一部分,并且也可以覆盖第一导电型半导体层123的整个区域。
电流扩展层133也与第一导电型半导体层123形成欧姆接触,并且与反射电极130隔绝。举例来说,电流扩展层133可以通过下部绝缘层131与反射电极130隔绝。下部绝缘层131置于反射电极130与电流扩展层133之间以将电流扩展层133与反射电极130隔绝。
此外,下部绝缘层131可以具有开口131b,所述开口置于反射电极130的上部区域内,使得通过其使反射电极130暴露;以及开口131a,所述开口通过其使第一导电型半导体层123暴露。下部绝缘层131的开口131b具有比电流扩展层133的开口133a小的面积,并且通过开口133a被完全地暴露。
另一方面,电流扩展层133可以通过开口131a连接到第一导电型半导体层123。此处,如参考图21(a)及图21(b)所描述,开口131a可以沿着衬底121的边缘放置并且与钝角部分相比,在锐角部分可以彼此分隔得更远。在此结构下,发光二极管可以防止电流集聚在锐角部分,由此提高了发光效率。此外,如参考图25所描述,下部绝缘层131可以包含孔洞131c代替开口131a。
上部绝缘层135覆盖电流扩展层133的至少一部分。此外,上部绝缘层135具有使电流扩展层133暴露的开口135a和使反射电极130暴露的开口135b。开口135a和开口135b可以靠近锐角部分彼此面对面放置。此外,上部绝缘层135可以覆盖电流扩展层133的开口133a的侧壁,并且开口135b可以置于开口133a内。
第一衬垫137a可以置于电流扩展层133上并且例如可以通过上部绝缘层135的开口135a连接到电流扩展层133。第一衬垫137a通过电流扩展层133电连接到第一导电型半导体层123。此外,第二衬垫137b连接到通过开口135b暴露的反射电极130并通过反射电极130电连接到第二导电型半导体层127。
根据此实施例,衬底121具有包含至少一个锐角的多边形形状,例如平行四边形形状或三角形形状,由此提高了光提取效率。此外,通过锐角部分的光通量增加,从而可以使用锐角部分调整发光二极管的光束角。
此外,根据此实施例,衬底121具有100微米或超过100微米的厚度,由此提高了光束角。
此外,电流扩展层123包含例如Al层等反射金属层,或下部绝缘层作为绝缘反射层而形成,从而未被反射电极130反射的光可以被电流扩展层123或下部绝缘层131反射,由此提高了光提取效率。
图27是根据本发明的又一个实施例的发光二极管200a的截面图。
除了保形涂层150置于衬底121上外,根据此实施例的发光二极管200a大体上类似于图26的发光二极管100a。保形涂层150均匀地覆盖衬底121的第二表面121b并且也可以覆盖侧表面121c。保形涂层150可以含有例如磷光体等波长转换材料。
此外,衬底121的厚度与保形涂层150的厚度的总和可以是225微米到600微米。举例来说,保形涂层150可以具有20微米到200微米的厚度。此外,衬底121的厚度可以视保形涂层的厚度而变化,例如可以在100微米到400微米范围内。当衬底121的厚度与保形涂层150的厚度的总和大于或等于225微米时,发光二极管200a的光束角可以增加到140°或超过140°。
图28(a)及图28(b)展示说明视衬底形状而定的光提取特征的示意平面图。此处,图28(a)展示在具有矩形形状的典型衬底111中光的行进通道,并且图28(b)展示在根据本发明的一个实施例,具有包含锐角的菱形形状的衬底121中光的行进通道。
参看图28(a),在作用层中特定位置Lp产生的一些光进入衬底111并且在衬底111的内侧表面上重复全反射。结果,光在衬底111内行进很大距离,由此引起光在衬底111内损失。因为衬底111的厚度增加,所以光在衬底111的侧表面上的全反射变得更严重,由此增加了光损失。此外,因为从衬底111的部分发射的光具有类似的特征,所以根据方向的光束角不存在很大差异。
相反,在具有如图28(b)中所示的菱形形状的衬底121中,在作用层中特定位置Lp产生的一些光进入衬底121,被衬底121的内侧表面全部反射,并随后靠近锐角部分,以减小入射角的光放到外部。因此,相比于典型衬底111,具有菱形形状的衬底121提供了提高的光提取效率。此外,因为光提取效率在锐角部分增加,所以相比于钝角部分,在锐角部分光束角增加。因此,可以提供视方向而定具有不同光束角的发光二极管。
图29是描绘通过典型方法构造的倒装芯片型发光二极管和通过根据本发明的一个实施例的方法构造的倒装芯片型发光二极管的光束角的图。在通过典型方法构造的发光二极管中,衬底111具有300微米×1000微米的矩形形状和约250微米的厚度。在通过根据实施例的方法构造的倒装芯片型发光二极管中,衬底121的锐角部分之间的距离是1毫米并且其钝角部分之间的距离是约0.58毫米。
参看图29,对于典型发光二极管,在x轴(短轴)方向上的光束角分布R-X大体上类似于在y轴(长轴)方向上的光束角分布R-Y。相反,对于根据本发明的实施例的发光二极管,在x轴方向上穿过锐角部分的光束角分布D-X超过在y轴方向上穿过钝角部分的光束角分布D-Y。
因此,根据本发明的实施例,可以提供一种根据x轴方向和y轴方向显示不同光束角特征的发光二极管。此类发光二极管可以有利地用于例如LED荧光灯等视方向而定,需要不同光束角特征的照明设备中。举例来说,多个发光二极管可以线性配置以垂直于具有宽光束角的LED荧光灯的纵向方向,由此实现大面积的照射,同时减少荧光灯内的光损失。
虽然上文已经描述了本发明的各种实施例和特征,但应了解本发明并不限于此。此外,某一实施例的个别结构、元件或特征不限于所述某一实施例并可以在不脱离本发明的精神和范围下施加至其它实施例。

Claims (1)

1.一种照明模块,包括多个发光二极管,所述发光二极管中的至少一个包括:
透明衬底,具有第一表面、第二表面以及将所述第一表面与所述第二表面连接的侧表面;
第一导电型半导体层,置于所述透明衬底的所述第一表面上;
第二导电型半导体层,置于所述第一导电型半导体层上;
作用层,放置于所述第一导电型半导体层与所述第二导电型半导体层之间;
第一衬垫,电连接到所述第一导电型半导体层;
第二衬垫,电连接到所述第二导电型半导体层;以及
电流扩展层,与所述第一导电型半导体层的边缘接触,并形成在所述第二导电型半导体层上方的区域的一部分上,
其中至少一个所述发光二极管还包括覆盖所述透明衬底的所述第二表面的保形涂层,并且所述透明衬底和所述保形涂层的总厚度范围为225微米至600微米。
CN201910834913.6A 2012-12-06 2013-10-22 发光二极管 Active CN110600593B (zh)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
KR10-2012-0140991 2012-12-06
KR1020120140991A KR102013364B1 (ko) 2012-12-06 2012-12-06 발광 다이오드 및 그것의 어플리케이션
KR1020120155783A KR102071036B1 (ko) 2012-12-28 2012-12-28 발광 다이오드 및 그것을 채택하는 조명 장치
KR10-2012-0155783 2012-12-28
KR10-2013-0011453 2013-01-31
KR1020130011453A KR101984932B1 (ko) 2013-01-31 2013-01-31 예각과 둔각을 가지는 다각형의 발광다이오드 및 이를 포함하는 조명모듈
CN201380072266.0A CN105074941B (zh) 2012-12-06 2013-10-22 发光二极管、照明模块、照明设备和背光单元
PCT/KR2013/009395 WO2014088201A1 (ko) 2012-12-06 2013-10-22 발광 다이오드 및 그것의 어플리케이션

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201380072266.0A Division CN105074941B (zh) 2012-12-06 2013-10-22 发光二极管、照明模块、照明设备和背光单元

Publications (2)

Publication Number Publication Date
CN110600593A true CN110600593A (zh) 2019-12-20
CN110600593B CN110600593B (zh) 2023-01-03

Family

ID=50883597

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201910834913.6A Active CN110600593B (zh) 2012-12-06 2013-10-22 发光二极管
CN201380072266.0A Active CN105074941B (zh) 2012-12-06 2013-10-22 发光二极管、照明模块、照明设备和背光单元
CN201910265288.8A Active CN109979925B (zh) 2012-12-06 2013-10-22 发光二极管

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN201380072266.0A Active CN105074941B (zh) 2012-12-06 2013-10-22 发光二极管、照明模块、照明设备和背光单元
CN201910265288.8A Active CN109979925B (zh) 2012-12-06 2013-10-22 发光二极管

Country Status (4)

Country Link
US (4) US9608171B2 (zh)
CN (3) CN110600593B (zh)
DE (2) DE112013005849T5 (zh)
WO (1) WO2014088201A1 (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110600593B (zh) * 2012-12-06 2023-01-03 首尔伟傲世有限公司 发光二极管
WO2014182104A1 (ko) * 2013-05-09 2014-11-13 서울반도체 주식회사 광원 모듈 및 이를 구비한 백라이트 유닛
US9847457B2 (en) * 2013-07-29 2017-12-19 Seoul Viosys Co., Ltd. Light emitting diode, method of fabricating the same and LED module having the same
WO2015016561A1 (en) * 2013-07-29 2015-02-05 Seoul Viosys Co., Ltd. Light emitting diode, method of fabricating the same and led module having the same
US9608168B2 (en) * 2014-06-13 2017-03-28 Seoul Viosys Co., Ltd. Light emitting diode
US10297719B2 (en) * 2015-08-27 2019-05-21 Mikro Mesa Technology Co., Ltd. Micro-light emitting diode (micro-LED) device
US10707379B2 (en) 2015-10-01 2020-07-07 Sensor Electronic Technology, Inc. Configuration for optoelectronic device
US10854785B2 (en) 2015-10-01 2020-12-01 Sensor Electronic Technology, Inc. Contact configuration for optoelectronic device
JP6361645B2 (ja) * 2015-12-22 2018-07-25 日亜化学工業株式会社 発光装置
FR3050872B1 (fr) * 2016-04-27 2019-06-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Diode electroluminescente comprenant au moins une couche intermediaire de plus grand gap disposee dans au moins une couche barriere de la zone active
DE102016112587A1 (de) * 2016-07-08 2018-01-11 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterchip
US11018285B2 (en) * 2017-03-23 2021-05-25 Seoul Semiconductor Co., Ltd. Display device and manufacturing method thereof
US10746387B2 (en) 2017-03-31 2020-08-18 Mind Head Llc Low voltage security lighting systems for perimeter fences having tactical glare capabilities
KR102601417B1 (ko) * 2017-09-28 2023-11-14 서울바이오시스 주식회사 발광 다이오드 칩
US11282981B2 (en) * 2017-11-27 2022-03-22 Seoul Viosys Co., Ltd. Passivation covered light emitting unit stack
DE102017129226A1 (de) * 2017-12-08 2019-06-13 Osram Opto Semiconductors Gmbh Optoelektronisches bauelement und anzeigevorrichtung
CN110192287B (zh) * 2017-12-22 2022-10-28 首尔伟傲世有限公司 芯片级封装发光二极管
US10418510B1 (en) * 2017-12-22 2019-09-17 Facebook Technologies, Llc Mesa shaped micro light emitting diode with electroless plated N-contact
US10325889B1 (en) 2018-01-12 2019-06-18 Mikro Mesa Technology Co., Ltd. Display device including LED devices with selective activation function
CN108461583B (zh) * 2018-02-05 2019-11-08 广东省半导体产业技术研究院 一种紫外led芯片的制作方法
US10784407B2 (en) 2018-04-23 2020-09-22 Asahi Kasei Kabushiki Kaisha Nitride semiconductor light emitting element and nitride semiconductor light emitting device
KR102565148B1 (ko) * 2018-06-27 2023-08-18 서울바이오시스 주식회사 플립칩형 발광 다이오드 칩 및 그것을 포함하는 발광 장치
DE102018117018A1 (de) * 2018-07-13 2020-01-16 Osram Opto Semiconductors Gmbh Optoelektronisches halbleiterbauelement mit einer silberhaltigen stromaufweitungsstruktur und optoelektronische vorrichtung
JP6915029B2 (ja) * 2018-11-30 2021-08-04 シャープ株式会社 マイクロ発光素子及び画像表示素子
US11362073B2 (en) * 2019-02-08 2022-06-14 Seoul Viosys Co., Ltd. Light emitting device including multiple transparent electrodes for display and display apparatus having the same
CN111341895A (zh) * 2020-03-10 2020-06-26 淄博职业学院 一种发光二极管
CN114242875B (zh) * 2021-12-06 2023-09-01 华引芯(武汉)科技有限公司 发光器件及其制作方法、照明装置及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864171A (en) * 1995-03-30 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor optoelectric device and method of manufacturing the same
US20120193648A1 (en) * 2011-01-31 2012-08-02 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
CN102683530A (zh) * 2011-03-08 2012-09-19 光磊科技股份有限公司 具有宽视角的发光二极管及其制造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784463B2 (en) * 1997-06-03 2004-08-31 Lumileds Lighting U.S., Llc III-Phospide and III-Arsenide flip chip light-emitting devices
EP1928034A3 (en) 1997-12-15 2008-06-18 Philips Lumileds Lighting Company LLC Light emitting device
JP4024994B2 (ja) * 2000-06-30 2007-12-19 株式会社東芝 半導体発光素子
JP2004101587A (ja) * 2002-09-05 2004-04-02 Nec Corp レンズ駆動装置
US7064353B2 (en) * 2004-05-26 2006-06-20 Philips Lumileds Lighting Company, Llc LED chip with integrated fast switching diode for ESD protection
JP2006012916A (ja) * 2004-06-22 2006-01-12 Toyoda Gosei Co Ltd 発光素子
US7534633B2 (en) * 2004-07-02 2009-05-19 Cree, Inc. LED with substrate modifications for enhanced light extraction and method of making same
JP4450199B2 (ja) * 2004-09-30 2010-04-14 豊田合成株式会社 半導体発光素子
KR20060030350A (ko) * 2004-10-05 2006-04-10 삼성전자주식회사 백색광 발생 유닛, 이를 갖는 백라이트 어셈블리 및 이를갖는 액정표시장치
KR20060077801A (ko) 2004-12-31 2006-07-05 엘지전자 주식회사 고출력 발광 다이오드 및 그의 제조 방법
TWI389337B (zh) * 2005-05-12 2013-03-11 Panasonic Corp 發光裝置與使用其之顯示裝置及照明裝置,以及發光裝置之製造方法
KR100773935B1 (ko) * 2005-12-19 2007-11-06 주식회사 대우일렉트로닉스 유기 발광 소자 패널
JP4802314B2 (ja) * 2006-01-24 2011-10-26 シャープ株式会社 窒化物半導体発光素子とその製造方法
KR100833309B1 (ko) * 2006-04-04 2008-05-28 삼성전기주식회사 질화물계 반도체 발광소자
CN101512783B (zh) * 2006-05-02 2011-07-27 三菱化学株式会社 半导体发光元件
TWI344709B (en) * 2007-06-14 2011-07-01 Epistar Corp Light emitting device
CN102257646A (zh) 2008-12-19 2011-11-23 三星Led株式会社 发光器件封装、背光单元、显示器件和发光器件
WO2010074288A1 (ja) * 2008-12-28 2010-07-01 有限会社Mtec 高電圧駆動の発光ダイオードモジュール
CN101881400A (zh) * 2009-05-05 2010-11-10 厦门市信达光电科技有限公司 Led路灯光源模组
WO2011071100A1 (ja) 2009-12-11 2011-06-16 昭和電工株式会社 半導体発光素子、半導体発光素子を用いた発光装置および電子機器
KR101654340B1 (ko) * 2009-12-28 2016-09-06 서울바이오시스 주식회사 발광 다이오드
KR101579220B1 (ko) 2010-03-26 2015-12-23 주식회사 솔라코 컴퍼니 엘이디 조명모듈 및 이를 이용한 조명램프
KR101125335B1 (ko) * 2010-04-15 2012-03-27 엘지이노텍 주식회사 발광소자, 발광소자 제조방법 및 발광소자 패키지
KR101795053B1 (ko) * 2010-08-26 2017-11-07 엘지이노텍 주식회사 발광 소자, 발광 소자 패키지, 라이트 유닛
KR101746004B1 (ko) * 2010-10-29 2017-06-27 엘지이노텍 주식회사 발광소자
KR20120053571A (ko) 2010-11-18 2012-05-29 서울옵토디바이스주식회사 복수의 메사 구조체를 갖는 발광 다이오드 칩
CN102544250B (zh) * 2010-12-27 2014-05-07 同方光电科技有限公司 一种GaN基发光二极管的制作方法
KR20120079363A (ko) * 2011-01-04 2012-07-12 삼성전자주식회사 광원용 렌즈, 이를 갖는 광원 모듈 및 백라이트 어셈블리
CN102339913B (zh) * 2011-09-30 2013-06-19 映瑞光电科技(上海)有限公司 高压led器件及其制造方法
CN203277380U (zh) * 2012-05-29 2013-11-06 璨圆光电股份有限公司 发光组件及其发光装置
CN110600593B (zh) * 2012-12-06 2023-01-03 首尔伟傲世有限公司 发光二极管

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864171A (en) * 1995-03-30 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor optoelectric device and method of manufacturing the same
US20120193648A1 (en) * 2011-01-31 2012-08-02 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
CN102683530A (zh) * 2011-03-08 2012-09-19 光磊科技股份有限公司 具有宽视角的发光二极管及其制造方法

Also Published As

Publication number Publication date
US10497836B2 (en) 2019-12-03
CN105074941A (zh) 2015-11-18
US10749080B2 (en) 2020-08-18
CN109979925B (zh) 2024-03-01
US9548425B2 (en) 2017-01-17
CN110600593B (zh) 2023-01-03
US20150270442A1 (en) 2015-09-24
WO2014088201A1 (ko) 2014-06-12
CN105074941B (zh) 2019-10-08
US20170200864A1 (en) 2017-07-13
DE202013012758U1 (de) 2019-04-29
US20150287888A1 (en) 2015-10-08
US9608171B2 (en) 2017-03-28
US20200098949A1 (en) 2020-03-26
DE112013005849T5 (de) 2015-08-20
CN109979925A (zh) 2019-07-05

Similar Documents

Publication Publication Date Title
US10749080B2 (en) Light-emitting diode and application therefor
US10749075B2 (en) Semiconductor light-emitting device
US10784406B2 (en) Light emitting diode, method of fabricating the same and led module having the same
TWI616004B (zh) 半導體發光元件
KR102013364B1 (ko) 발광 다이오드 및 그것의 어플리케이션
US20130134867A1 (en) Light emitting diode with improved light extraction efficiency
US9536924B2 (en) Light-emitting diode and application therefor
KR20160025456A (ko) 발광 다이오드 및 그 제조 방법
US11764332B2 (en) Semiconductor light-emitting device
CN110120450B (zh) 发光元件
KR20140117791A (ko) 발광 다이오드 및 그것을 제조하는 방법
KR102071036B1 (ko) 발광 다이오드 및 그것을 채택하는 조명 장치
KR20120087036A (ko) 발광 소자 및 발광 소자 패키지
KR101781217B1 (ko) 발광 소자 및 발광 소자 패키지
US20240136472A1 (en) Semiconductor light-emitting device
KR20120087035A (ko) 발광 소자 및 발광 소자 패키지
TWI804437B (zh) 發光元件
KR102563266B1 (ko) 발광소자 및 이를 구비한 광원 모듈
KR101786081B1 (ko) 발광 소자 및 발광 소자 패키지
KR20110067312A (ko) 발광 다이오드

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant