WO2014082469A1 - 合成结构的高压器件及启动电路 - Google Patents

合成结构的高压器件及启动电路 Download PDF

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WO2014082469A1
WO2014082469A1 PCT/CN2013/081159 CN2013081159W WO2014082469A1 WO 2014082469 A1 WO2014082469 A1 WO 2014082469A1 CN 2013081159 W CN2013081159 W CN 2013081159W WO 2014082469 A1 WO2014082469 A1 WO 2014082469A1
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voltage
module
chip
drain
negative threshold
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PCT/CN2013/081159
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English (en)
French (fr)
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李照华
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深圳市明微电子股份有限公司
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Priority to EP13840111.2A priority Critical patent/EP2765604A4/en
Priority to US14/357,492 priority patent/US9385186B2/en
Publication of WO2014082469A1 publication Critical patent/WO2014082469A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Definitions

  • the present invention relates to the field of semiconductor device technology, and in particular, to a high voltage device and a startup circuit of a composite structure.
  • the controller chip requires a startup circuit to provide the voltage required to turn it on.
  • the startup circuit is connected from the output of the rectifier bridge to the power supply of the controller.
  • the output of the rectifier bridge charges the bypass capacitor of the controller chip through a large resistor.
  • the controller starts and the system starts to work normally.
  • the startup is completed, the energy required at the power supply is mainly supplied to the controller chip by the auxiliary winding.
  • the resistance of the startup circuit still consumes a certain amount of power, which seriously affects the overall efficiency of the system.
  • One way to solve this problem is to reduce the startup current of the controller chip and increase the starting resistor value.
  • Another method is to integrate the startup circuit inside the controller chip. After the controller chip is started and the system is working normally, the startup circuit is turned off to remove the influence of the startup circuit on the overall efficiency of the switching power supply system.
  • the controller chip integrates the startup circuit internally, and the process must complete the conversion from high voltage to low voltage to supply power to the controller chip. It inevitably increases the chip area, how to effectively reduce the controller chip area without affecting the controller chip. Start-up requirements, which are key issues that must be addressed in the internal integrated startup circuit. In the power chip in which the high-voltage power MOS is also integrated inside the controller chip, the problem is more prominent, and the area of the chip is large, resulting in an increase in the cost of the chip.
  • the object of the present invention is to solve at least one of the above technical drawbacks, in particular, by synthesizing a high voltage device structure, effectively saving the area of the chip and reducing the cost of the chip.
  • the embodiment of the invention provides a high-voltage device with a synthetic structure, including a high-voltage power MOS tube (referred to as a HVNMOS tube) and a JFET tube.
  • a high-voltage power MOS tube referred to as a HVNMOS tube
  • a JFET tube a high-voltage power MOS tube
  • the high voltage power MOS transistor HVNMOS includes a drain, a source, a gate and a substrate, and the conductive channel is a P-type well region Pwell between the source and the drain;
  • the JFET tube includes a drain, a source, a gate and a substrate, and the conductive channel is an N-type well region Nwell between the source and the drain;
  • the high voltage power MOS transistor HVNMOS and the JFET transistor share the same drain (also referred to as a drain terminal or a drain terminal).
  • the drain uses an N-type double diffusion process.
  • the substrate further includes a buried layer Bury P and a deep N-type well region Deep Nwell is used to increase the withstand voltage and reliability of the device.
  • the embodiment of the present invention further provides a starting circuit of the high voltage device adopting the above synthetic structure, the starting circuit includes a negative threshold switching tube, an enabling module, an anti-backflow module and a voltage detecting module, wherein the negative threshold switching tube adopts the above a high voltage device of a synthetic structure;
  • the drain, the source and the gate of the JFET device in the high-voltage device of the above synthetic structure are respectively the input end, the output end and the control end of the negative threshold switch tube;
  • the high-voltage input signal is connected to the input end of the negative threshold switch tube, and the output end of the negative threshold switch tube is connected to the input end of the anti-backflow module, and the control end of the negative threshold switch tube is connected to the output end of the enable module, and the input of the enable module is enabled.
  • the output end of the voltage detecting module is terminated, and the input end of the voltage detecting module and the power end of the chip are connected to the output end of the anti-backflow module;
  • the high voltage input signal is connected to the input end of the negative threshold switch tube, and supplies energy to the power supply terminal VDD of the chip through a negative threshold switch tube.
  • the voltage detection module detects the voltage value of the power supply terminal VDD of the chip, when the power supply terminal VDD When the voltage value reaches the predetermined working voltage of the chip, the chip starts, and the voltage detecting module outputs an enable signal EN;
  • the enabling module receives the enable signal EN such that the negative threshold switch is turned off, and the negative threshold switch is turned off;
  • the anti-backflow module enables a single conduction between the input end of the negative threshold switch and the power supply terminal VDD of the chip to prevent the current of the power supply terminal VDD from flowing back to the input end of the switch.
  • the above solution proposed by the embodiment of the present invention effectively saves the area of the chip and reduces the cost of the chip by the synthesized high-voltage device structure.
  • the startup circuit is turned off after the chip works normally, which not only greatly reduces the difficulty of realizing the low-power system, improves the conversion efficiency of the power system, and can effectively save circuit components (starting resistance) and improve The degree of integration.
  • the above solution proposed by the present invention has little modification to the existing circuit system, does not affect the compatibility of the system, and is simple and efficient to implement.
  • HVNMOS high voltage power tube
  • FIG. 2 is a schematic cross-sectional view of a high voltage start device JFET
  • FIG. 3 is a cross-sectional view showing the structure of a high voltage device synthesized in accordance with an embodiment of the present invention
  • Figure 4 is a schematic view showing the comparison of the area of the chip layout before and after the use of the structure
  • FIG. 5 is a functional block diagram of a startup circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a specific startup circuit according to an embodiment of the present invention.
  • P-substrate in the text and in the drawing denotes a P-type substrate layer
  • Pwell denotes a P-type well region
  • P denotes a P-type buried layer
  • Deep Nwell denotes a deep N-type well region
  • Nwell denotes an N-type well region
  • LV Nwell represents the low-voltage N-type well region
  • P+ represents the P-type high-concentration implant
  • N+ represents the N-type high-concentration implant
  • Sub represents the substrate connection end
  • Source represents the source end of the device
  • Drain represents the drain end of the device
  • Gate represents the gate of the device.
  • HVNMOS denotes a high voltage power MOS transistor
  • JFET denotes a junction field effect transistor
  • J-Source denotes a source terminal of a junction FET
  • J-Gate denotes a gate of a junction FET
  • LV-MOS denotes a low voltage MOS device .
  • an embodiment of the present invention provides a high voltage device of a composite structure, including a high voltage power MOS transistor HVNMOS and a JFET tube.
  • the high voltage power MOS transistor HVNMOS includes a drain, a source, a gate and a substrate, and the conductive channel is a P-type well region Pwell between the source and the drain;
  • the JFET tube includes a drain, a source, a gate and a substrate, and the conductive channel is an N-type well region Nwell between the source and the drain;
  • the high voltage power MOS transistor HVNMOS and the JFET transistor share the same drain, and the drain adopts an N-type double diffusion process.
  • the substrate further includes a buried layer Bury P and a deep N-type well region Deep Nwell is used to increase the withstand voltage and reliability of the device.
  • the high voltage power MOS transistor HVNMOS in the present invention generally refers to a power MOS transistor having a withstand voltage of 700 V or more.
  • HVNMOS high voltage power MOS transistor
  • HVNMOS high voltage power MOS transistor
  • a conductive channel is a P-type well region between the source and the drain.
  • Its structure is similar to that of a normal low-voltage MOS transistor, except that the drain uses an N-type double-diffusion process and adds a buried layer of Bury.
  • P and deep N-well region Deep Nwell their role is mainly to improve the withstand voltage value and reliability of the device, reducing the impact of parasitic devices on the device.
  • the high voltage power MOS transistor HVNMOS is of an enhanced structure, that is, when the voltage Vgs between the gate and the source of the high voltage power MOS transistor HVNMOS is greater than a certain threshold, the HVNMOS transistor is turned on, and electrons pass from the source to the drain through the conductive channel. Extremely forming current; when Vgs When the threshold is less than the threshold, the HVNMOS transistor is turned off.
  • FIG. 2 is a schematic cross-sectional view of a high-voltage start-up device JFET, including drain Drain, source source, gate Gate, and substrate Sub.
  • the structure is similar to that of the high-voltage power transistor HVNMOS structure, and there is also a buried layer Bury.
  • P and deep N-well region Deep Nwell their role is to improve the withstand voltage and reliability of the device and reduce the impact of parasitic devices on the device.
  • the difference is that the conductive channel is the N-type well region Nwell between the source and the drain.
  • the high-voltage JFET has the characteristics of negative threshold turn-off and high voltage withstand voltage
  • the drain and source of the JFET can be directly connected to the high-voltage input signal and the medium-low voltage circuit inside the chip, and the startup circuit can be integrated inside the chip with a little simple control. It has been proved by experiments that this method achieves good performance in actual chip design and is a practical solution.
  • a high-voltage JFET device can be fabricated by expanding the N-well below the pole and expanding the source and gate of the JFET.
  • FIG. 3 comprises two parts.
  • the left side is a high voltage power MOS tube HVNMOS structure
  • the right side is a JFET structure required for a startup circuit, and they share a drain terminal Drain, which is effective.
  • the high voltage JFET is in an on state, charging the capacitor of the power supply terminal of the controller chip, and the high voltage power MOS transistor HVNMOS is kept off; once the controller chip reaches its startup voltage, the internal logic of the chip The high voltage JFET is turned off, at which time the turn-on and turn-off of the high voltage power MOS transistor HVNMOS is determined by the controller chip according to the operating state, so the high voltage work MOS rate tube HVNMOS and the high voltage
  • the drain sharing of the JFET has no effect on its own operation.
  • the startup circuit is turned off after the chip is started, the influence of the startup circuit on the system efficiency is also reduced, which is beneficial to improving the working efficiency of the system.
  • the high-voltage power MOS transistor HVNMOS has a large on-current, and the layout area is large, and a plurality of high-voltage power MOS transistors HVNMOS are connected in parallel. Since the drain is shared, the JFET can also be made large, so the startup circuit provides The current is large and the controller chip can be quickly started.
  • Figure 4 shows a comparison of the area of the chip layout before and after the use of the structure. If the high voltage power MOS transistor HVNMOS and the low voltage module (abbreviated as LV-MOS) are consistent, the structure of the present invention is greatly reduced by using the structure of the present invention (ie, The area of the shadow area) effectively saves the area of the chip. In today's pursuit of high performance, high integration and low cost, reducing chip area is an important factor in reducing chip cost.
  • the embodiment of the invention further provides a starting circuit of the high voltage device using the above synthetic structure, comprising a negative threshold switching tube, an enabling module, an anti-backflow module and a voltage detecting module, wherein the negative threshold switching tube adopts the high voltage of the above synthetic structure Device.
  • the drain, source and gate of the JFET device in the high voltage device of the above synthetic structure are respectively the input terminal, the output terminal and the control terminal of the negative threshold switching transistor.
  • the high-voltage input signal is connected to the input end of the negative threshold switch tube, and the output end of the negative threshold switch tube is connected to the input end of the anti-backflow module, and the control end of the negative threshold switch tube is connected to the output end of the enable module, and the input terminal of the enable module is connected.
  • the output end of the voltage detecting module, the input end of the voltage detecting module and the power end of the chip are connected to the output end of the anti-backflow module.
  • the high voltage input terminal of the startup circuit supplies energy to the power supply terminal VDD of the chip through the negative threshold switch tube, and the voltage detection module detects the voltage value of the power supply terminal VDD of the chip.
  • the voltage detection module detects the voltage value of the power supply terminal VDD of the chip.
  • the voltage detection module outputs an enable signal EN;
  • the enable module receives the enable signal EN, so that the negative threshold switch is turned off, and the negative threshold switch is turned off;
  • the anti-backflow module enables a single conduction between the input of the negative threshold switch and the power supply terminal VDD of the chip.
  • FIG. 5 it is a functional block diagram of a startup circuit proposed by the present invention.
  • the circuit of the present invention consists of a negative threshold switch 10, an enable module 13, an anti-backflow module 11 and a voltage detection module 12.
  • the high voltage input signal supplies energy to the power supply terminal VDD of the chip through the negative threshold switch 10, and the voltage detection module 12 detects the voltage value of the power supply terminal VDD of the chip.
  • the voltage detecting module 12 outputs an enable signal EN;
  • the enable module 13 receives the enable signal EN, so that the negative threshold switch is turned off, and the negative threshold switch 10 is turned off;
  • the anti-backflow module 11 makes a single conduction between the input end of the negative threshold switch and the power supply terminal VDD of the chip.
  • the voltage at the input terminal of the negative threshold switch 10 is prevented from decreasing, the current of the power supply terminal VDD flows back to the input terminal of the negative threshold switch.
  • FIG. 6 is an example of a specific circuit implementation of the present invention
  • the negative threshold switch 10 includes a JFET device JFET0.
  • the high voltage input signal is connected to the drain terminal D of the JFET0.
  • the source terminal S of the JFET device JFET0 is connected to the input terminal of the anti-backflow module, and the gate G of the JFET device JFET0 is connected to the output terminal VG of the enable module 13.
  • the anti-backflow module 11 includes a diode D1.
  • the anode of the diode D1 is an input end of the anti-backflow module 11;
  • the cathode of the diode D1 is an output end of the anti-backflow module 11, and is connected to the power terminal VDD of the controller chip and the input end of the voltage detecting module 12. .
  • the voltage detecting module 12 includes a resistor R1, a resistor R2, a hysteresis comparator COM1, and a bandgap reference circuit BG1.
  • the input end of the voltage detecting module 12 is the power terminal VDD of the controller chip, and is connected to the first end of the resistor R1.
  • the second end of the resistor R1 and the first end of the resistor R2 are connected to the inverting input terminal of the hysteresis voltage comparator COM1.
  • VC the second end of the resistor R2 is grounded.
  • the voltages of the first positive phase reference input VRH and the second positive phase reference input VRL of the hysteresis voltage comparator COM1 may be generated by a bandgap reference circuit.
  • the output terminal of the hysteresis voltage comparator COM1 is the output terminal of the voltage detecting module 12, and outputs an enable signal EN.
  • the enable module 13 includes an inverter INV1, an inverter INV2, a PMOS transistor M1, and an NMOS transistor M2.
  • the input terminal of the inverter INV1 and the input terminal of the inverter INV2 are connected in common as an output terminal of the enable terminal 13 to the output terminal of the voltage detecting module 12.
  • the output end of the inverter INV1 is connected to the gate of the PMOS transistor M1, the source end of the PMOS transistor M1 is connected to the power supply terminal VDD of the controller chip, and the drain terminal of the PMOS transistor M1 and the drain terminal of the NMOS transistor M2 serve as the output of the enable module 13.
  • the terminal is connected to the gate G of the JFET device JFET0.
  • the output terminal of the inverter INV2 is connected to the gate of the NMOS transistor M2, and the source terminal of the NMOS transistor M2 is grounded.
  • the VDD voltage value of the power supply terminal of the chip is zero level, and the resistors R1, R2 and a voltage comparator form the power supply voltage detecting module 12 of the chip.
  • the threshold voltage is negative, so the JFET device JFET0 is turned on, the voltage of VDD starts to rise, and the voltage VC shown in the figure also rises.
  • VC is greater than >VRH, the hysteresis voltage comparator output enable signal EN goes from high level. Turning it to a low level, the enable signal turns on the NMOS transistor M2 through the inverters INV1 and INV2, respectively, and turns off the PMOS transistor M1.
  • the gate of the JFET device JFET0 is pulled low, and the JFET device JFET0 is turned off, at this time, the negative threshold switch
  • the gate source voltage of the tube is negative, and the negative threshold switch is turned off.
  • the JFET device JFET0 and the high voltage power MOS transistor (HVNMOS transistor) share the drain, when the high voltage power MOS transistor (HVNMOS transistor) is used as the switching device of the controller chip, the drain voltage has a high and low level switching, in order to prevent When the JFET0 drain terminal voltage is reduced, the VDD current flows back to the drain terminal D of the JFET0 JFET0. Therefore, the anti-backflow module is added to the circuit. When the drain voltage of the JFET device JFET0 is reduced, the current of the power supply terminal VDD is prevented from flowing back. JFET device JFET0 drain terminal for single-pass.
  • the negative threshold switching tube includes, but is not limited to, a depletion type field effect transistor, a junction field effect transistor, and the like, and an N-type device having a negative opening voltage threshold;
  • the voltage detecting module includes but is not limited to using a voltage dividing resistor.
  • the voltage comparator is implemented;
  • the enabling module includes, but is not limited to, a circuit implementation using an inverter and a MOS transistor, as long as the gate-source voltage of the negative threshold switching device can be made negative, the negative threshold switching device can be turned off.
  • the startup circuit has a startup current flowing in the startup process, and the startup circuit is turned off after the chip works normally, which not only greatly reduces the low power consumption.
  • the difficulty of the system implementation improves the conversion efficiency of the power system and saves circuit components (starting resistors).
  • the above solution proposed by the present invention has little modification to the existing circuit system, does not affect the compatibility of the system, and is simple and efficient to implement.

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Abstract

提供了一种合成结构的高压器件，包括高压功率MOS管HVNMOS和JFET管，所述高压功率MOS管HVNMOS包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的P型阱区Pwell；所述JFET管包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的N型阱区Nwell；所述高压功率MOS管HVNMOS和所述JFET管共用相同的漏极，所述漏极采用N型双扩散工艺。还提供了一种采用上述合成结构的高压器件的启动电路。由此，通过合成的高压器件结构，有效的节省了芯片的面积，降低芯片的成本。

Description

合成结构的高压器件及启动电路 技术领域
本发明涉及半导体器件技术领域，具体而言，本发明涉及合成结构的高压器件及启动电路。
 背景技术
在AC/DC开关电源应用领域中，控制器芯片需要一个启动电路为其提供开启所需要的电压，在传统应用中，启动电路是从整流桥输出端串接大电阻到控制器的电源端，整流桥输出端通过大电阻给控制器芯片的旁路电容充电，当其达到启动电压之后，控制器启动，系统开始正常工作。当启动完成之后，电源端所需能量主要是靠辅助绕组给控制器芯片提供。控制器芯片正常工作之后，启动电路的电阻仍然消耗一定的功率，严重的影响了系统的整体效率。解决这个问题的一种方法是降低控制器芯片的启动电流，加大启动电阻值。但由于启动电阻较大，启动电流相应的减小，从而延长了启动时间。另外的一个方法是在控制器芯片内部集成启动电路，在控制器芯片启动完成，系统正常工作之后，关闭启动电路，去除启动电路对开关电源系统整体效率的影响。
控制器芯片内部集成启动电路，其过程要完成从高压到低压的转换才能向控制器芯片供电，其不可避免的加大芯片的面积，如何有效减少控制器芯片面积而又不影响控制器芯片的启动要求，这是内部集成启动电路的面临必须要解决的关键问题。在控制器芯片内部也集成高压功率MOS的电源芯片中，其问题更加突出，芯片的面积很大，导致芯片成本增加。
此外，由于现代开关电源对于降低功耗的要求与日俱增，而且绿色开关电源是所有应用所必需的，而不仅是过去所指的手持式和电池供电系统，因此在保护环境生态的大前提下，降低电力线供电系统及电池供电系统的能耗都是必不可少的，对中国来说，这更可以带来特别的优点：降低燃煤发电站的负荷。这就不仅要求电源芯片控制核心具备低功耗特性，而且还要求它具备一些能进一步降低系统功耗的特性。
因此，有必要提出有效的技术方案，解决现有技术中开关电源芯片设计的难题。
 技术问题
本发明的目的旨在至少解决上述技术缺陷之一，特别是通过合成的高压器件结构，有效的节省了芯片的面积，降低芯片的成本。
 技术解决方案
本发明实施例提出了一种合成结构的高压器件，包括高压功率MOS管（简称HVNMOS管）和JFET管，
所述高压功率MOS管HVNMOS包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的P型阱区Pwell；
所述JFET管包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的N型阱区Nwell；
所述高压功率MOS管HVNMOS和所述JFET管共用相同的漏极（也称漏极端或漏端）。所述漏极采用N型双扩散工艺。
进一步而言，所述衬底上还包括掩埋层Bury P和深N型阱区Deep Nwell，用于提高器件的耐压值和可靠性。
本发明实施例还提出了一种采用上述合成结构的高压器件的启动电路，所述启动电路包括负阈值开关管、使能模块、防倒灌模块以及电压检测模块，其中，负阈值开关管采用上述合成结构的高压器件；
上述合成结构的高压器件中的JFET器件的漏极、源极和栅极分别为所述负阈值开关管的输入端、输出端和控制端；
高压输入信号接入所述负阈值开关管的输入端，负阈值开关管的输出端接防倒灌模块的输入端，负阈值开关管的控制端接使能模块的输出端，使能模块的输入端接电压检测模块的输出端，电压检测模块的输入端和芯片的电源端共接于防倒灌模块的输出端；
所述高压输入信号接入所述负阈值开关管的输入端，通过负阈值开关管向芯片的电源端VDD提供能量，所述电压检测模块检测芯片的电源端VDD的电压值，当电源端VDD的电压值达到芯片预定工作电压时，所述芯片启动，同时所述电压检测模块输出使能信号EN；
所述使能模块接收所述使能信号EN，使得所述负阈值开关管截止，关闭所述负阈值开关管；
所述防倒灌模块使得所述负阈值开关管的输入端与芯片的电源端VDD之间单向导通，防止电源端VDD的电流倒流回开关管的输入端。
 有益效果
本发明实施例提出的上述方案，通过合成的高压器件结构，有效的节省了芯片的面积，降低芯片的成本。采用本发明提出的高压器件结构，芯片正常工作后启动电路关闭，这不仅大大降低了低功耗系统实现的难度，提高了电源系统的转换效率，同时能有效节省电路元件（启动电阻），提高了集成度。此外，本发明提出的上述方案，对现有的电路系统的改动很小，不会影响系统的兼容性，而且实现简单、高效。
本发明附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本发明的实践了解到。
 附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为高压功率管HVNMOS的剖面示意图；
图2为高压启动器件JFET的剖面示意图；
图3为本发明实施例合成的高压器件结构的剖面示意图；
图4为采用本结构前后芯片版图面积的对比示意图；
图5为本发明实施例启动电路的功能框图；
图6为本发明实施例具体启动电路示意图。
 本发明的实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
文中及附图中的P-substrate表示P型衬底层，Pwell表示P型阱区；Bury P表示P型埋层；Deep Nwell表示深N型阱区；Nwell表示N型阱区；LV Nwell表示低压N型阱区；P+表示P型高浓度注入，N+表示N型高浓度注入，Sub表示衬底连接端，Source表示器件的源端，Drain表示器件的漏端，Gate表示器件的栅极；HVNMOS表示高压功率MOS管，JFET表示结型场效应管；J-Source表示结型场效应管的源端；J-Gate表示结型场效应管的栅极；LV-MOS表示低压MOS器件。
为了实现本发明之目的，本发明实施例提出了一种合成结构的高压器件，包括高压功率MOS管HVNMOS和JFET管，
所述高压功率MOS管HVNMOS包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的P型阱区Pwell；
所述JFET管包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的N型阱区Nwell；
所述高压功率MOS管HVNMOS和所述JFET管共用相同的漏极，所述漏极采用N型双扩散工艺。
进一步而言，衬底上还包括掩埋层Bury P和深N型阱区Deep Nwell，用于提高器件的耐压值和可靠性。
本发明中的高压功率MOS管HVNMOS通常指的是耐高压为700V以上的功率MOS管。
下面结合附图，对本发明提出的上述结构作详细说明。
本发明依据目前高压700V工艺的特点，结合高压功率器件与器件JFET的结构特点，提出一种优化的可行的器件结构，将其应用到小功率的开关电源控制器芯片上，实现了高集成、高性能和低成本的控制器芯片。
图1为高压功率MOS管HVNMOS的剖面示意图，包含漏极Drain、源极Source、栅极Gate和衬底Sub共4个端口，导电沟道为源极和漏极之间的P型阱区Pwell。其结构与正常的低压MOS管结构相似，区别在于漏极采用N型双扩散工艺，并增加了掩埋层Bury P和深N型阱区Deep Nwell，它们的作用主要是提高器件的耐压值和可靠性，降低寄生器件对器件的影响。
该高压功率MOS管HVNMOS为增强型结构，即当高压功率MOS管HVNMOS的栅极与源极之间的电压Vgs大于某个阈值的时候HVNMOS管导通，电子从源极经导电沟道到达漏极形成电流；当Vgs 小于阈值的时候HVNMOS管截止。
图2为高压启动器件JFET的剖面示意图，包含漏极Drain、源极Source、栅极Gate和衬底Sub共4个端口，其结构与高压功率管HVNMOS结构图1相似，也有掩埋层Bury P和深N型阱区Deep Nwell，它们的作用主要是提高器件的耐压值和可靠性，降低寄生器件对器件的影响。区别在于导电沟道为源极和漏极之间的N型阱区Nwell。当初始的栅源电压差为零时，高压JFET是导通的，栅源电压之间需要较大的负阈值电压才能使其截止。
由于高压JFET具有负阈值关闭和耐高压的特性，可直接将JFET的漏极与源极分别连接高压输入信号和芯片内部的中低压电路，稍加简单控制即可实现在芯片内部集成启动电路，经实验证明此方法在实际芯片设计中获得很好的性能，是一种切实可行的方案。
通过对比高压JFET与高压功率MOS管HVNMOS的工艺结构（图1和图2）发现，它们的结构非常的相似，漏极结构相同，因此完全可以共享一个漏极，只需将高压功率管HVNMOS漏极下面的N阱向外再扩展一下，同时再引出JFET的源极和栅极，即可制造出一个高压JFET器件。
通过前面的深入分析，本发明提出的结构的剖面图如图3所示，包含两部分，左边为高压功率MOS管HVNMOS结构，右边为启动电路所需的JFET结构，它们共享漏端Drain，有效的减少由于启动电路带来的芯片面积。
在实际运用中，在控制器芯片启动之前，高压JFET处于导通状态，给控制器芯片电源端的电容充电，而高压功率MOS管HVNMOS保持截止；一旦控制器芯片达到其启动电压之后，芯片内部逻辑就将高压JFET截止，此时高压功率MOS管HVNMOS的导通和截止由控制器芯片根据工作状态决定，因此高压功MOS率管HVNMOS和高压 JFET的漏极共享对其本身工作互不相影响。同时，由于启动电路在芯片启动之后就关闭，所以还减少了启动电路对系统效率的影响，有利于提高系统的工作效率。
另外，通常高压功率MOS管HVNMOS的导通电流较大，版图面积很大，由多个高压功率MOS管HVNMOS并联而成，由于共用漏极，所以JFET也可以做很大，故启动电路提供的电流很大，可以快速启动控制器芯片。
图4显示了采用本结构前后芯片版图面积的对比示意图，若高压功率MOS管HVNMOS和低压模块（简称为LV-MOS）保持一致，采用本发明的结构使启动电路部分面积大大的缩减了（即阴影部分面积），有效的节省了芯片的面积。在追求芯片高性能、高集成度和低成本的今天，减少芯片面积是降低芯片成本的一个重要因素。
本发明实施例还提出了一种使用上述合成结构的高压器件的启动电路，包括负阈值开关管、使能模块、防倒灌模块以及电压检测模块，其中，负阈值开关管采用上述合成结构的高压器件。
上述合成结构的高压器件中的JFET器件的漏极、源极和栅极分别为负阈值开关管的输入端、输出端和控制端。
高压输入信号接入负阈值开关管的输入端，负阈值开关管的输出端接防倒灌模块的输入端，负阈值开关管的控制端接使能模块的输出端，使能模块的输入端接电压检测模块的输出端，电压检测模块的输入端和芯片的电源端共接于防倒灌模块的输出端。
启动电路的高电压输入端通过负阈值开关管向芯片的电源端VDD提供能量，电压检测模块检测芯片的电源端VDD的电压值，当电源端VDD的电压值达到芯片预定工作电压时，芯片启动，同时电压检测模块输出使能信号EN；
使能模块接收使能信号EN，使得负阈值开关管截止，关闭负阈值开关管；
防倒灌模块使得负阈值开关管的输入端与芯片的电源端VDD之间单向导通。
如图5所示，为本发明提出的启动电路的功能框图。本发明电路由一个负阈值开关管10、使能模块13、防倒灌模块11和电压检测模块12组成。所高电压输入信号通过负阈值开关管10向芯片的电源端VDD提供能量，电压检测模块12检测芯片的电源端VDD的电压值，当芯片的电源端VDD的电压值达到芯片预定工作电压时，芯片启动，同时电压检测模块12输出使能信号EN；
使能模块13接收使能信号EN，使得负阈值开关管截止，关闭负阈值开关管10；
防倒灌模块11使得负阈值开关管的输入端与芯片的电源端VDD之间单向导通。防止负阈值开关管10输入端电压降低时，电源端VDD的电流倒流回负阈值开关管的输入端。
进一步而言，图6是本发明的一个具体电路实现的举例，负阈值开关管10包括JFET器件JFET0。高压输入信号接入JFET0的漏端D，JFET器件JFET0的源端S接防倒灌模块的输入端，JFET器件JFET0的栅极G接使能模块13的输出端VG。
防倒灌模块11包括二极管D1，二极管D1的阳极是防倒灌模块11的输入端；二极管D1的阴极是防倒灌模块11的输出端，接控制器芯片的电源端VDD和电压检测模块12的输入端。
电压检测模块12包括电阻R1、电阻R2、迟滞比较器COM1及带隙基准电路BG1。电压检测模块12的输入端是控制器芯片的电源端VDD，接电阻R1的第一端，电阻R1的第二端、电阻R2的第一端共接于迟滞电压比较器COM1的反相输入端VC，电阻R2的第二端接地。迟滞电压比较器COM1的第一正相基准输入端VRH和第二正相基准输入端VRL的电压可由带隙基准电路产生。迟滞电压比较器COM1的输出端为电压检测模块12的输出端，输出使能信号EN。
使能模块13包括反相器INV1、反相器INV2、PMOS管M1及NMOS管M2。反相器INV1的输入端与反相器INV2的输入端共接作为使能模块13的输入端接电压检测模块12的输出端。反相器INV1的输出端接PMOS管M1的栅极，PMOS管M1的源端接控制器芯片的电源端VDD，PMOS管M1的漏端与NMOS管M2的漏端作为使能模块13的输出端且连接到JFET器件JFET0的栅极G。反相器INV2的输出端接NMOS管M2的栅极，NMOS管M2的源端接地。
控制器芯片启动之初，芯片的电源端VDD电压值为零电平，电阻R1，R2和一个电压比较器形成了芯片的供电电压检测模块12，芯片刚上电时，因为负阈值开关管的阈值电压为负值，所以JFET器件JFET0导通，VDD的电压开始上升，图中所示的电压VC也跟随上升，当VC大于>VRH时，迟滞电压比较器输出使能信号EN从高电平翻转为低电平，该使能信号通过反相器INV1和INV2分别打开NMOS管M2，关闭PMOS管M1，那么，JFET器件JFET0的栅极被拉低，JFET器件JFET0关闭，此时负阈值开关管的栅源电压为负，负阈值开关管被关闭。同时由于JFET器件JFET0与高压功率MOS管（HVNMOS管）共用了漏极，当高压功率MOS管（HVNMOS管）作为控制器芯片的开关器件时，漏极电压会有高低电平的切换，为了防止JFET器件JFET0漏端电压降低时，VDD电流倒流回JFET器件JFET0的漏端D，所以电路中加入了防倒灌模块，当JFET器件JFET0的漏端电压降低时，防止了电源端VDD的电流倒流回JFET器件JFET0漏端，实现单向导通。
显然，上述具体电路中，负阈值开关管包括但不限于耗尽型场效应管、结型场效应管等开启电压阈值为负值的N型器件；电压检测模块包括但不限于使用分压电阻和电压比较器实现；使能模块包括但不限于使用反相器和MOS管的电路实现，只要能令负阈值开关管器件的栅源电压为负，关闭负阈值开关管器件即可。
本发明实施例提出的上述方案，通过在启动电路中引入负阈值开关管，使得启动电路在启动的过程中才有启动电流流入，芯片正常工作后启动电路关闭，这不仅大大降低了低功耗系统实现的难度，提高了电源系统的转换效率，同时能有效节省电路元件（启动电阻）。此外，本发明提出的上述方案，对现有的电路系统的改动很小，不会影响系统的兼容性，而且实现简单、高效。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。
因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (6)

  1. 一种合成结构的高压器件，其特征在于，包括高压功率MOS管HVNMOS和JFET管，
    所述高压功率MOS管HVNMOS包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的P型阱区；
    所述JFET管包括漏极、源极、栅极和衬底，导电沟道为源极和漏极之间的N型阱区；
    所述高压功率MOS管HVNMOS和所述JFET管共用相同的漏极，所述漏极采用N型双扩散工艺。
  2. 如权利要求1所述的合成结构的高压器件，其特征在于，所述衬底上还包括掩埋层和深N型阱区，用于提高器件的耐压值和可靠性。
  3. 一种启动电路，其特征在于，包括负阈值开关管、使能模块、防倒灌模块以及电压检测模块，所述负阈值开关管采用如权利要求1或2所述的合成结构的高压器件，所述合成结构的高压器件中的JFET器件的漏极、源极和栅极分别为所述负阈值开关管的输入端、输出端和控制端；
    高压输入信号接入所述负阈值开关管的输入端，所述负阈值开关管的输出端接所述防倒灌模块的输入端，所述负阈值开关管的控制端接所述使能模块的输出端，所述使能模块的输入端接所述电压检测模块的输出端，所述电压检测模块的输入端和芯片的电源端共接于所述防倒灌模块的输出端，所述高压输入信号接入所述负阈值开关管的输入端，通过所述负阈值开关管向所述芯片的电源端提供能量，所述电压检测模块检测所述芯片的电源端的电压值，当所述电源端的电压值达到芯片预定工作电压时，所述芯片启动，同时所述电压检测模块输出使能信号；
    所述使能模块接收所述使能信号，使得所述负阈值开关管截止，关闭所述负阈值开关管；
    所述防倒灌模块使得所述负阈值开关管的输入端与所述芯片的电源端之间单向导通，防止所述电源端的电流倒流回所述负阈值开关管的输入端。
  4. 如权利要求3所述的启动电路，其特征在于，所述防倒灌模块包括二极管D1，所述二极管D1的阳极是所述防倒灌模块的输入端，所述二极管D1的阴极是所述防倒灌模块的输出端。
  5. 如权利要求3所述的启动电路，其特征在于，所述电压检测模块包括电阻R1、电阻R2、迟滞比较器及带隙基准电路；所述电压检测模块的输入端接所述电阻R1的第一端，所述电阻R1的第二端、所述电阻R2的第一端共接于所述迟滞电压比较器的反相输入端，所述电阻R2的第二端接地，所述迟滞电压比较器的第一正相基准输入端和第二正相基准输入端的电压由所述带隙基准电路产生，所述迟滞电压比较器的输出端为所述电压检测模块的输出端，输出所述使能信号。
  6. 如权利要求3所述的启动电路，其特征在于，所述使能模块包括反相器INV1、反相器INV2、PMOS管M1及NMOS管M2；所述反相器INV1的输入端与所述反相器INV2的输入端共接作为所述使能模块的输入端，所述反相器INV1的输出端接所述PMOS管M1的栅极，所述PMOS管M1的源端接所述芯片的电源端，所述PMOS管M1的漏端与所述NMOS管M2的漏端作为所述使能模块的输出端且连接到所述JFET器件的栅极，所述反相器INV2的输出端接所述NMOS管M2的栅极，所述NMOS管M2的源端接地。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124878A (zh) * 2014-07-23 2014-10-29 上海晶丰明源半导体有限公司 供电模块、开关电源芯片以及开关电源系统
CN112636741A (zh) * 2020-12-29 2021-04-09 成都极米科技股份有限公司 一种电平转换电路及终端设备

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000626B (zh) 2012-11-28 2015-08-26 深圳市明微电子股份有限公司 合成结构的高压器件及启动电路
CN103441145B (zh) * 2013-08-02 2016-04-13 无锡华润上华半导体有限公司 半导体器件及其形成方法、启动电路及开关电源
CN104900695B (zh) * 2014-03-03 2018-04-10 无锡华润上华科技有限公司 功率结型场效应管及其制造方法
CN103928464B (zh) 2014-04-18 2015-08-12 杭州士兰微电子股份有限公司 复合器件及开关电源
CN103887961B (zh) * 2014-04-18 2015-06-10 杭州士兰微电子股份有限公司 开关电源及其控制器
CN105336779B (zh) * 2014-08-05 2018-06-29 中芯国际集成电路制造(上海)有限公司 Ldmos器件及其形成方法
KR101975630B1 (ko) * 2015-04-03 2019-08-29 매그나칩 반도체 유한회사 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
CN105679820B (zh) * 2016-03-16 2018-08-21 上海华虹宏力半导体制造有限公司 Jfet及其制造方法
CN105871211A (zh) * 2016-05-20 2016-08-17 南京超闪通讯科技有限公司 一种芯片外电源转换电路及应用
WO2017201709A1 (zh) * 2016-05-26 2017-11-30 中山港科半导体科技有限公司 一种坚固的功率半导体场效应晶体管结构
CN108615729B (zh) * 2016-12-09 2020-12-01 无锡市晶源微电子有限公司 开关器件
TWI636573B (zh) * 2016-12-16 2018-09-21 通嘉科技股份有限公司 具有高壓啟動單元的垂直雙擴散金氧半功率元件
TWI683437B (zh) * 2016-12-30 2020-01-21 新唐科技股份有限公司 高壓半導體裝置
CN110445099B (zh) * 2019-08-06 2020-10-23 苏州赛芯电子科技有限公司 一种集成电池保护电路的半导体结构及其制造工艺
CN112289787B (zh) * 2020-09-17 2024-01-26 南京通华芯微电子有限公司 一种具有多种控制功能的mos器件
CN112886837B (zh) * 2021-03-03 2022-08-30 昂宝电子（上海）有限公司 开关电源及其控制芯片
CN117134603B (zh) * 2023-10-26 2024-03-22 成都市硅海武林科技有限公司 一种基于jfet的高压启动电路、电源转换器及电源芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200979884Y (zh) * 2006-11-24 2007-11-21 杭州士兰微电子股份有限公司 一种复合型的场效应晶体管结构
US20100301412A1 (en) * 2009-05-29 2010-12-02 Power Integrations, Inc. Power integrated circuit device with incorporated sense FET
US20110080213A1 (en) * 2009-10-06 2011-04-07 Sung-Nien Tang Semiconductor device and method for operating the same
CN103000626A (zh) * 2012-11-28 2013-03-27 深圳市明微电子股份有限公司 合成结构的高压器件及启动电路
CN203055909U (zh) * 2012-11-28 2013-07-10 深圳市明微电子股份有限公司 一种合成结构的高压器件

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386136A (en) * 1991-05-06 1995-01-31 Siliconix Incorporated Lightly-doped drain MOSFET with improved breakdown characteristics
JP4213776B2 (ja) * 1997-11-28 2009-01-21 光照 木村 Ｍｏｓゲートショットキートンネルトランジスタおよびこれを用いた集積回路
JP2009259972A (ja) * 2008-04-15 2009-11-05 Panasonic Corp 半導体装置、及び該半導体装置を用いたエネルギー伝達装置
DE102008024090A1 (de) * 2008-05-17 2009-11-26 Moeller Gmbh Schaltregler mit PWM-Regler
US7939863B2 (en) * 2008-08-07 2011-05-10 Texas Instruments Incorporated Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
JP5487852B2 (ja) * 2008-09-30 2014-05-14 サンケン電気株式会社 半導体装置
TWI365591B (en) * 2008-12-26 2012-06-01 Richtek Technology Corp Power transistor chip with built-in junction field effect transistor and application circuit thereof
US9184097B2 (en) * 2009-03-12 2015-11-10 System General Corporation Semiconductor devices and formation methods thereof
US8169801B2 (en) * 2009-05-28 2012-05-01 Monolithic Power Systems, Inc. Voltage converters with integrated low power leaker device and associated methods
US8475451B2 (en) * 2010-06-08 2013-07-02 Kwangwoon University Industry-Academic Collaboration Foundation Medical plasma generator and endoscope using the same
US8772871B2 (en) * 2010-08-20 2014-07-08 Freescale Semiconductor, Inc. Partially depleted dielectric resurf LDMOS
JP5985293B2 (ja) * 2011-10-04 2016-09-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200979884Y (zh) * 2006-11-24 2007-11-21 杭州士兰微电子股份有限公司 一种复合型的场效应晶体管结构
US20100301412A1 (en) * 2009-05-29 2010-12-02 Power Integrations, Inc. Power integrated circuit device with incorporated sense FET
US20110080213A1 (en) * 2009-10-06 2011-04-07 Sung-Nien Tang Semiconductor device and method for operating the same
CN103000626A (zh) * 2012-11-28 2013-03-27 深圳市明微电子股份有限公司 合成结构的高压器件及启动电路
CN203055909U (zh) * 2012-11-28 2013-07-10 深圳市明微电子股份有限公司 一种合成结构的高压器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2765604A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124878A (zh) * 2014-07-23 2014-10-29 上海晶丰明源半导体有限公司 供电模块、开关电源芯片以及开关电源系统
CN112636741A (zh) * 2020-12-29 2021-04-09 成都极米科技股份有限公司 一种电平转换电路及终端设备
CN112636741B (zh) * 2020-12-29 2023-05-23 成都极米科技股份有限公司 一种电平转换电路及终端设备

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