WO2013071842A1 - 一种应用于功率因数校正器中的高压大电流驱动电路 - Google Patents

一种应用于功率因数校正器中的高压大电流驱动电路 Download PDF

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WO2013071842A1
WO2013071842A1 PCT/CN2012/084379 CN2012084379W WO2013071842A1 WO 2013071842 A1 WO2013071842 A1 WO 2013071842A1 CN 2012084379 W CN2012084379 W CN 2012084379W WO 2013071842 A1 WO2013071842 A1 WO 2013071842A1
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high voltage
transistor
circuit
current
terminal
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PCT/CN2012/084379
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English (en)
French (fr)
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代国定
陈跃
马晓辉
韩辉
马任月
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无锡华润上华科技有限公司
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Priority to US14/358,566 priority Critical patent/US9190897B2/en
Priority to EP12850584.9A priority patent/EP2782233B1/en
Publication of WO2013071842A1 publication Critical patent/WO2013071842A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/615—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors in a Darlington configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Definitions

  • the invention belongs to the technical field of circuits and relates to an analog integrated circuit, in particular to a high voltage and high current driving circuit applied in a power factor corrector, which can be used for output stage driving in an active power factor correction controller.
  • switching power supplies are used in large quantities because of their high power conversion efficiency.
  • semiconductor switching devices are an indispensable basic component, and at the same time, switching power supply operating frequency Continuous improvement has led to a wide range of changes in the electronic component industry.
  • Research on semiconductor switching devices is also important, especially for power MOSFETs and IGBTs. Due to the special process and construction of power devices, it is necessary to design power devices. Drive circuit.
  • the invention can effectively solve the protection problem of the higher voltage driving circuit, and at the same time improve the defects of the finite current and sink current of the traditional driving circuit, reduce the static power consumption of the driving circuit, reduce the total harmonic distortion, and ensure the reliability of the driving circuit. And security.
  • the high voltage and high current driving circuit applied to the power factor corrector includes a current mirror circuit, a high voltage pre-modulation circuit, a level shift circuit, a dead time control circuit, and a large current output stage.
  • the current mirror circuit uses a current source circuit composed of a resistor and a triode and a current sink circuit to convert the start current I start and the input signal I bias generated by the reference current source into an input signal of the high voltage pre-modulation circuit, and convert the start current I start The input signal of the level shifting circuit;
  • the high voltage pre-modulation circuit uses a high voltage LDMOS tube to isolate and a breakdown voltage regulation characteristic of the Zener diode under the bias of the current mirror circuit, and a high input power supply voltage VDD Converted to a relatively low voltage to ensure that the drive circuit operates within a safe voltage range while generating an input voltage V CLAMP of the level shift circuit;
  • the level shift circuit utilizes current under the output of the high voltage pre-modulation circuit
  • the biasing function of the mirror circuit controls the
  • the second logic switch signal S2 generates an output drive signal GATE_DRIVER having a large source current and sink current capability to drive the turn-on and turn-off of the peripheral power device.
  • the current mirror circuit includes transistors Q3, Q4, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14 and resistors R1, R2, R3, R4, R7; the transistor Q13 and the transistor Q14 constitute the first a current mirror circuit; wherein the transistors Q3, Q4, Q6, Q7, Q8, Q9, Q10, Q11, Q12 and the resistors R1, R2, R3, R4, R7 form a second current mirror circuit; the input end of the first current mirror circuit Connected to the output terminal I bias of the external reference current source, the first current mirror circuit is used to provide a bias current for the high voltage pre-modulation circuit when the current is working normally; the second current mirror circuit is provided for the high voltage pre-modulation circuit and the level shift circuit Bias current.
  • the high voltage pre-modulation circuit includes the LDMOS transistor LDMOS1, the LDMOS transistor LDMOS2, the Zener diode D4, D5, D6, and the transistor Q5; the LDMOS transistor LDMOS1 and the LDMOS transistor LDMOS2 form a third current mirror circuit, wherein the LDMOS transistor LDMOS1 acts as a high voltage
  • the first high-voltage isolation tube of the pre-modulation circuit, the LDMOS tube LDMOS2 serves as the gate bias tube of the LDMOS tube LDMOS1
  • the Zener diode D6 serves as the gate clamp protection of the third current mirror circuit, and the series connection of the Zener diodes D4 and D5
  • the first high voltage pre-modulation circuit, the transistor Q5 acts as the second high voltage isolation tube of the high voltage pre-modulation circuit.
  • the gate and the drain of the LDMOS transistor LDMOS2 in the third current mirror circuit are connected together, and are connected to the collector output terminal of the transistor Q13 in the first current mirror circuit, the LDMOS transistor LDMOS1 and the LDMOS transistor LDMOS2.
  • the source is connected to the input power supply VDD
  • the clamp diode D6 is connected between the gate and the source of the third current mirror circuit LDMOS transistor LDMOS1 and the LDMOS transistor LDMOS2.
  • the drain terminal of the LDMOS transistor LDMOS1 is connected to the clamp diode D4.
  • the N terminal of the series D5 is connected to the base of the transistor Q5 and the collector output of the transistor Q7 of the second current mirror circuit, and a high voltage pre-modulation signal V CLAMP is generated at the emitter of the transistor Q5.
  • the level shifting circuit comprises a high voltage PMOS transistor PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, a high voltage NMOS transistor M3, M4, M5 and an inverter INV1; the source terminals of the high voltage PMOS transistors PMOS1, PMOS2, and PMOS5 are connected to a common power supply.
  • V CLAMP is connected to the output end of the high voltage pre-modulation circuit (2), the gate of the high voltage PMOS transistor PMOS1 is connected to the drain terminal of the high voltage PMOS transistor PMOS2, and the high voltage PMOS transistor PMOS1 drain terminal is connected to the gate of the high voltage PMOS transistor PMOS2.
  • the source end of the high voltage PMOS transistor PMOS3, and at the same time, under the bias of the second current mirror circuit image in the current mirror circuit, the output terminal of the second current mirror circuit transistor Q3 is connected to the drain terminal of the high voltage PMOS transistor PMOS1,
  • the gate of the high voltage PMOS transistor PMOS2 and the source terminal of the high voltage PMOS transistor PMOS3 serve as the bias current of the level shifting circuit.
  • the gate of the high voltage PMOS transistor PMOS2 is connected to the drain terminal of the high voltage PMOS transistor PMOS1, and the drain of the high voltage PMOS transistor PMOS2.
  • the second Current mirror circuit transistor Q4 The collector output terminal is connected to the gate of the high voltage PMOS transistor PMOS1, the source terminal of the high voltage PMOS transistor PMOS4, and the gate of the high voltage PMOS transistor PMOS5, and provides a bias current for the level shift circuit (3), the high voltage PMOS transistor PMOS3 and a gate connected to the common terminal of PMOS4 V b, high voltage PMOS transistor drain PMOS3 terminated at the drain end of the high-voltage NMOS transistor M3, high-voltage PMOS drain pipe PMOS4 terminated at the drain end of the high-voltage NMOS transistor M4, the high-voltage NMOS The gate of the tube M3 is connected to the output end of the inverter INV1, the source end of the high voltage NMOS transistor M3 is connected to
  • the gate of the high voltage NMOS transistor M4 is connected to the input end of the inverter INV1, that is, to the first logic switch signal S1, the source terminal of the high voltage NMOS transistor M4 is connected to the common terminal GND, and the gate of the high voltage PMOS transistor PMOS5 is connected.
  • the PMOS2 drain terminal of the high voltage PMOS transistor, the PMOS1 gate and the PMOS4 source terminal, the source terminal of the high voltage PMOS transistor PMOS5 is connected to the output V CLAMP of the high voltage premodulation circuit, and the drain terminal of the high voltage PMOS transistor PMOS5 is connected to the drain terminal of the high voltage NMOS transistor M5.
  • the second logic switch generated by the gate of the high NMOS transistor M5 is connected to the dead time control circuit S2, the source end high-voltage NMOS transistor M5 common ground terminal of the GND, drain terminals of the high voltage PMOS transistor and a high voltage NMOS transistor PMOS5 NOMS5 and connected together, the level shift circuit generates an output signal V S, the control high current output Level turn-on and turn-off.
  • the dead time control circuit uses a pulse width modulation signal in the switching power supply to generate a first logic switching signal S1 and a second logic switching signal S2 that do not overlap in reverse, when the pulse width modulation signal is converted from a low level to a high level.
  • the first logic switch signal S1 first changes from a high level to a low level, and then through the delay of the gate circuit and the capacitor, the second logic switch signal S2 changes from a low level to a high level; when the pulse width modulation When the signal is switched from a high level to a low level, the second logic switch signal S2 first changes from a high level to a low level, and then through the gate circuit and the capacitor delay, the first logic switch signal S1 changes from a low level. High level.
  • the high current output stage includes a Darlington composite structure and a combined pull-down high voltage NMOS transistor.
  • the Darlington composite structure has a large current sinking capability, and the combined pull-down high voltage NMOS transistor has a large source current capability, the Darlington.
  • the composite structure is composed of transistors Q1, Q2, diodes D1, D2, the collectors of Q1 and Q2 are connected to the common power supply VDD, the base of the transistor Q2 is connected to the N terminal of the diode D2, and one end of the resistor R5 is connected to the level shift circuit.
  • the emitter of the transistor Q2 is connected to the P terminal of the diode D2, the N terminal of the diode D1, the other end of the resistor R5, the end of the resistor R6, and the base of the transistor Q1.
  • the emitter of the transistor Q1 is connected to the resistor.
  • the other end of R6 and the P terminal of diode D1 are connected to the output terminal GATE_DRIVER of the high current output stage.
  • the combined pull-down high voltage NMOS transistor is composed of high voltage NMOS transistors M1, M2, M5 and resistors R5 and R6.
  • the drain end of the NMOS transistor M1 is connected to the emitter of the transistor Q1 and the end of the resistor R6, and is connected to the output terminal GATE_DRIVER of the high current output stage.
  • the drain of the high voltage NMOS transistor M2 is connected to the base of the transistor Q1 and the emission of the transistor Q2.
  • the gates of M2 and M5 are connected in parallel, connected to the second logic switch signal S2 generated by the dead time control circuit, and the source terminals of the high voltage NMOS transistors M1, M2, and M5 are connected to the common ground GND.
  • the present invention utilizes the high voltage isolation of the LDMOS transistor and the breakdown voltage regulation characteristic of the Zener diode to convert the higher input power supply voltage into a fixed level required for outputting the drive switching signal, which not only improves the reliability of the driving circuit. Sexual and well protected peripheral power devices.
  • the present invention utilizes a level shift circuit to convert a pulse width modulated signal generated from a digital logic drive circuit into an output drive switch signal having a fixed level, and simultaneously adds a dead time control circuit to prevent during level shifting. There is an instantaneous high current phenomenon of the power supply to the ground.
  • the present invention employs a classical Darlington output stage structure to improve the source current and sink current of the output drive circuit.
  • the present invention is directed to the requirements of the total power harmonic distortion (THD) of the active power factor correction circuit, and particularly the THD optimization mechanism is added to the sub-module circuit to reduce the THD.
  • THD total power harmonic distortion
  • FIG. 1 is a structural block diagram of a driving circuit applied to a power factor corrector according to the present invention
  • FIG. 2 is a schematic diagram of a specific circuit of the present invention.
  • FIG. 3 is a schematic diagram of a specific circuit of the level shift circuit 3 of the present invention.
  • FIG. 4 is a schematic diagram of a specific circuit of the dead time control circuit 4 of the present invention.
  • Fig. 5 is a timing chart of output signals generated by the dead time control circuit 4 of the present invention.
  • THD Total Harmonic Distortion, total harmonic distortion
  • MOS metal oxide semiconductor, metal oxide semiconductor
  • LDMOS Later double-diffused metal oxide Semiconductor, lateral double-diffused metal oxide semiconductor
  • NMOS N-channel metal oxide semiconductor FET, N-channel metal oxide semiconductor field effect transistor.
  • PMOS P-channel metal oxide semiconductor FET, P-channel metal oxide semiconductor field effect transistor.
  • a high voltage and high current driving circuit applied to a power factor corrector of the present invention includes: a current mirror circuit 1, a high voltage premodulation circuit 2, a level shift circuit 3, a dead time control circuit 4, and a large current output stage. 5.
  • each unit circuit of the present invention is as follows:
  • the circuit comprises transistors Q3, Q4, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14 and resistors R1, R2, R3, R4, R7; transistors Q13, Q14 form a first current mirror circuit; Q3, Q4, Q6, Q7, Q8, Q9, Q10, Q11, Q12 and resistors R1, R2, R3, R4, and R7 form a two-current mirror circuit.
  • the input end of the first current mirror circuit Q14 is connected to the output terminal Ibias of the external reference current source, wherein I3 is the output current of Q13 in the first current mirror circuit, and provides a bias for the third current mirror circuit in the high voltage premodulation circuit.
  • the second current mirror circuit is the most important part of the THD optimization mechanism in the present invention.
  • I4 is the output current of Q7 in the second current mirror circuit, and provides charging current for the clamp circuit.
  • Istart is the first current mirror circuit Q8.
  • the output current provides a mirror current for the other mirror circuits in the second current mirror circuit.
  • the VDD voltage required for the normal operation of the circuit is generally high. Therefore, if the VDD reaches the required voltage in an instant and the circuit is turned on, the overshoot of the output will occur, and the THD and EMI problems are very serious. Even the external power switch tube is burned; in the present invention, the THD optimization mechanism is added, and when the electric VDD is lower than the normal circuit, the first current mirror circuit provides the starting current IS:
  • the current is generated when VDD>VBE_Q12, and is mirrored out by the mirror circuit; the current IS is first mirrored to the output current Istart of Q8, I4 will also mirror the current, and charge the clamp diodes D4 and D5, and Q5 will gradually turn on. Therefore, the output voltage VCLAMP of the high voltage pre-modulation circuit will follow the input voltage change. When the VDD reaches the required voltage to open the circuit, VCLAMP will not instantaneously jump, and the output will not undergo overshoot change, which greatly optimizes THD. The problem of EMI is reduced; at the same time, I1 and I1 are the output currents of Q3 and Q4 in the second current mirror circuit, respectively, and provide a bias current for the level shift circuit.
  • the circuit includes an LDMOS transistor LDMOS1 (hereinafter referred to as a high voltage transistor LDMOS1) and an LDMOS2 (hereinafter referred to as a high voltage transistor LDMOS2); a Zener diode D4, D5, D6; and a transistor Q5.
  • LDMOS1 and LDMOS2 form a third current mirror circuit, wherein the high voltage tube LDMOS1 is used as the first high voltage isolation tube of the high voltage pre-modulation circuit, and the high voltage tube LDMOS2 provides a suitable bias voltage for the gate of the high voltage tube LDMOS1.
  • the voltage diode D6 acts as a gate clamp protection diode of the third current mirror circuit, ensuring that the gate-source voltage of the high-voltage transistors LDMOS1 and LDMOS2 is within the breakdown voltage range thereof, and the series connection of the Zener diodes D4 and D5 forms the core of the high-voltage pre-modulation circuit.
  • the unit when the input power voltage VDD is relatively high, and reaches the breakdown voltage of the Zener diodes D4 and D5, at this time, the second high voltage isolation tube Q5 is turned on, and the output voltage VCLAMP of the high voltage premodulation circuit is approximately doubled. Zener diode breakdown voltage value.
  • the level shift circuit 4 includes high voltage MOS transistors PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, NMOS5, high voltage NMOS transistors M3, M4, and an inverter INV1.
  • I1 and I2 are the output currents of Q3 and Q4 in the second current mirror circuit, respectively, and provide a current path for the level shift circuit.
  • the gates of the high voltage MOS transistors PMOS3 and PMOS4 are connected to the collector Vb of the transistor Q9.
  • the first logic switching signal S1 first changes from a high level to a low level, the high voltage NMOS transistor M3 is turned on, the NMOS transistor M4 is turned off, Vb and Under the action of input bias current I1, the PMOS3 transistor of the high voltage transistor is turned on, and the gate voltage of PMOS2 is VA ⁇ Vb+VGS3.
  • the pole voltage VB ⁇ Vb+VGS4 at this time, PMOS1 and PMOS5 are turned on, and the gate of the high voltage transistor PMOS2 Voltage VA is approximately the input power voltage VCLAMP is, the high-pressure pipe PMOS2 turned off, the high level output VS; dead time after addition of the control circuit, can be prevented during the power level conversion occurring phenomenon instantaneous large current to ground.
  • the dead time control circuit 4 uses the pulse width modulation signal Driver in the switching power supply to generate the first logic switching signal S1 and the second logic switching signal S2 that do not overlap in reverse, when the pulse width is When the modulation signal is converted from a low level to a high level, the first logic switching signal S1 first changes from a high level to a low level, and then the delay of the gate circuit and the capacitor, and the second logic switching signal S2 is low.
  • the pulse width modulation signal Driver is switched from a high level to a low level
  • the second logic switching signal S2 first changes from a high level to a low level, and then passes through the gate circuit and the capacitor delay, A logic switching signal S1 changes from a low level to a high level.
  • the high current output stage 5 includes a Darlington composite structure and a composite pull-down high voltage NMOS transistor.
  • the Darlington composite structure has a large current sinking capability, and the composite pull-down high voltage NMOS transistor has a large The source current capability, the Darlington composite structure is composed of transistors Q1, Q2, diodes D1, D2, and the composite pull-down high voltage NMOS transistor is composed of high voltage NMOS transistors M1, M2, M5 and resistors R5, R6.
  • the first logic switch signal S1 of the dead time control circuit is at a low level
  • the second logic switch signal S2 is at a high level
  • the output signal VS of the level shift circuit is low.
  • the output GATE_DRIVER of the large current output stage is pulled low; when the input pulse width modulation signal Driver is low, the first logic switch of the dead time control circuit
  • the signal S1 is at a high level
  • the second logic switch signal S2 is at a low level
  • the composite pull-down NMOS transistors M1, M2, and M5 are turned off, and the output VS of the level shift circuit is at a high level, in the Darlington composite tube Q1 and High current under the action of Q2
  • the output of the output stage GATE_DRIVER is quickly charged to a high level;
  • the resistors R5 and R6 in the high current output stage circuit are also an important part of the THD optimization mechanism of the present invention, and its main function is to limit the current level of the output stage and prevent the output stage from generating an instant.
  • the output drive signal GATE_DRIVER is connected to the peripheral power device through one pin of the chip, parasitic inductance is generated, and the parasitic inductance and the gate parasitic capacitance of the power device form a LC resonant circuit, after adding the appropriate size resistor in the output stage circuit, during the high-low level conversion of the output drive signal, it can effectively suppress the oscillation of the output drive signal and reduce the EMI problem; the output drive signal GATE_DRIVER is high level.
  • the diodes D1 and D2 are used to provide a fast discharge path to the base regions of the Darlington composite tubes Q1 and Q2, speeding up the shutdown of the Darlington composite tubes Q1 and Q2.
  • the invention utilizes the high voltage isolation function of the LDMOS transistor and the breakdown voltage regulation characteristic of the Zener diode to convert the higher input power supply voltage into a fixed level required for outputting the driving switch signal, which can not only improve the reliability and safety of the driving circuit.
  • sexual and well protected peripheral power devices utilizes a level shifting circuit to convert a pulse width modulated signal generated from a digital logic driving circuit into an output driving switching signal having a fixed level, and simultaneously add a dead time control circuit to prevent existence during level shifting.
  • the invention is directed to the requirement of total harmonic distortion (THD) of the active power factor correction circuit, and particularly adds a THD optimization mechanism and a smaller THD in the sub-module circuit.
  • THD total harmonic distortion

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Abstract

一种应用于功率因数校正器中的高压大电流驱动电路，包括电流镜像电路（1）、电平移位电路（3）、高压预调制电路（2）、死区时间控制电路（4）和大电流输出级（5）。大电流输出级采用了达林顿输出级结构，以提高驱动电路的最高工作频率。驱动电路利用稳压二极管的击穿稳压特性，保证驱动电路工作在一个安全的电压范围内。在电平移位电路中加入死区时间控制，不仅可以防止在电平转换期间存在的电源到地的瞬间大电流现象，而且可以减少驱动电路的静态功耗。

Description

一种应用于功率因数校正器中的高压大电流驱动电路
【技术领域】
本发明属于电路技术领域，涉及模拟集成电路，尤其是一种应用于功率因数校正器中的高压大电流驱动电路，可用于有源功率因数校正控制器中的输出级驱动。
【背景技术】
随着电力电子技术的迅速发展，开关电源因为具有高的电源转换效率而被大量使用，而在开关调整器电路中，半导体开关器件已是不可或缺的基本组件，同时，开关电源工作频率的不断提高促使电子元件工业发生了广泛的变革，对半导体开关器件的研究也显得有为重要，特别是功率型MOSFET和IGBT，由于功率型器件的特殊工艺和构造，有必要为功率型器件专门设计驱动电路。
传统的功率MOSFET驱动电路中，由于在其驱动级存在同时导通的时间段，需要消耗额外的功耗；同时，在较高电源电压的输出级驱动电路中，缺少必要的保护电路，不能保证驱动电路的可靠性工作；由于其有限的源电流和灌电流能力，不能够应用在一些特殊的场合。本发明能有效地解决较高电压驱动电路的保护问题，同时改善传统驱动电路有限源电流和灌电流的缺陷，降低驱动电路的静态功耗，减小总谐波失真，保证驱动电路的可靠性和安全性。
【发明内容】
本发明的目的在于克服上述现有技术的缺点，提供一种应用于功率因数校正器中的高压大电流驱动电路。
本发明的目的是通过以下技术方案来解决的：
这种应用于功率因数校正器中的高压大电流驱动电路，包括电流镜像电路、高压预调制电路、电平移位电路、死区时间控制电路和大电流输出级。所述电流镜像电路利用电阻和三极管组成的电流源电路和电流沉电路，将启动电流Istart和基准电流源产生的输入信号Ibias转换为高压预调制电路的输入信号，将启动电流Istart转换为电平移位电路的输入信号；所述高压预调制电路在电流镜像电路偏置作用下，利用高压LDMOS管的隔离作用以及稳压二极管的击穿稳压特性，将一个高的输入电源电压VDD转换为相对低的电压，以保证驱动电路工作在一个安全的电压范围内，同时产生电平移位电路的输入电压VCLAMP；所述电平移位电路在高压预调制电路的输出作用下，利用电流镜像电路的偏置作用，利用死区时间控制电路产生的第一逻辑开关信号S1和第二逻辑开关信号S2，控制高压管PMOS和高压管NOMS的导通与关断，从而产生电平移位电路的输出信号VS，为大电流输出级电路提供逻辑开关信号；所述死区时间控制电路在数字逻辑驱动信号的作用下，利用逻辑门电路和电容的延迟作用，产生反相不交迭的第一逻辑开关信号S1和第二逻辑开关信号S2，控制电平移位电路和大电流输出级的工作状态；所述大电流输出级，在高压三极管所组成的达林顿复合管作用下，利用高压管NMOS和电平移位电路产生的逻辑开关信号VS，以及死区时间控制电路产生的第二逻辑开关信号S2，产生具有较大源电流和灌电流能力的输出驱动信号GATE_DRIVER，驱动外围功率器件的导通与关断。
进一步，上述电流镜像电路包括三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、Q14和电阻R1、R2、R3、R4、R7；所述三极管Q13和三极管Q14组成第一电流镜像电路；其中三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12和电阻R1、R2、R3、R4、R7组成第二电流镜像电路；第一电流镜像电路的输入端连接到外部基准电流源的输出端Ibias上，第一电流镜像电路用于电流正常工作时为高压预调制电路提供偏置电流；第二电流镜像电路为高压预调制电路和电平移位电路提供偏置电流。
上述的高压预调制电路包括LDMOS管LDMOS1、LDMOS管LDMOS2、稳压二极管D4、D5、D6，三极管Q5；所述LDMOS管LDMOS1和LDMOS管LDMOS2组成第三电流镜像电路，其中，LDMOS管LDMOS1作为高压预调制电路的第一高压隔离管，LDMOS管LDMOS2作为LDMOS管LDMOS1的栅极偏置管，稳压二极管D6作为第三电流镜像电路的栅极箝位保护，稳压二极管D4、D5的串联组成第一高压预调制电路，三极管Q5作为高压预调制电路的第二高压隔离管。
上述高压预调制电路中，第三电流镜像电路中LDMOS管LDMOS2的栅极和漏极连接在一起，同时接在第一电流镜像电路中三极管Q13的集电极输出端，LDMOS管LDMOS1和LDMOS管LDMOS2的源极连接到输入电源VDD上，箝位二极管D6连接在第三电流镜像电路LDMOS管LDMOS1和LDMOS管LDMOS2的栅极和源极之间，LDMOS管LDMOS1的漏端连接在箝位二极管D4、D5串联的N端，同时连接三极管Q5的基极、以及第二电流镜像电路中三极管Q7的集电极输出端，在三极管Q5的发射极产生高压预调制信号VCLAMP。
上述电平移位电路包括高压PMOS管PMOS1、PMOS2、PMOS3、PMOS4、PMOS5，高压NMOS管M3、M4、M5以及反相器INV1；所述的高压PMOS管PMOS1、PMOS2、PMOS5的源端接公共电源VCLAMP，即接在高压预调制电路（2）的输出端，所述高压PMOS管PMOS1的栅极接高压PMOS管PMOS2的漏端，高压PMOS管PMOS1漏端接高压PMOS管PMOS2的栅极和高压PMOS管PMOS3的源端，同时，在电流镜像电路中第二电流镜像电路像的偏置作用下，将第二电流镜像电路三极管Q3的输出端集电极接在高压PMOS管PMOS1的漏端、高压PMOS管PMOS2的栅极、高压PMOS管PMOS3的源端，作为电平移位电路的偏置电流，所述高压PMOS管PMOS2的栅极接高压PMOS管PMOS1的漏端，高压PMOS管PMOS2的漏端接高压PMOS管PMOS1的栅极和高压PMOS管PMOS4的源端、高压PMOS管PMOS5的栅极，同时，在电流镜像电路（1）中第二电流镜像电路的偏置作用下，将第二电流镜像电路三极管Q4的集电极输出端连接在高压PMOS管PMOS1的栅极、高压PMOS管PMOS4的源端、高压PMOS管PMOS5的栅极，为电平移位电路（3）提供偏置电流，所述高压PMOS管PMOS3和PMOS4的栅极接在公共端Vb，高压PMOS管PMOS3的漏端接在高压NMOS管M3的漏端，高压PMOS管PMOS4的漏端接在高压NMOS管M4的漏端，所述高压NMOS管M3的栅极接在反相器INV1的输出端，高压NMOS管M3的源端接公共端GND，所述反相器INV1的输入端接死区时间控制电路产生的第一逻辑开关信号S1，所述高压NMOS管M4的栅极接反相器INV1的输入端，即接第一逻辑开关信号S1，高压NMOS管M4的源端接公共端GND，所述高压PMOS管PMOS5的栅极接高压PMOS管PMOS2漏端、PMOS1栅极以及PMOS4源端，高压PMOS管PMOS5的源端接高压预调制电路的输出VCLAMP，高压PMOS管PMOS5的漏端接高压NMOS管M5的漏端，所述高NMOS管M5的栅极接死区时间控制电路产生的第二逻辑开关信号S2，高压NMOS管M5的源端接公共地端GND，高压PMOS管PMOS5的漏端和高压NMOS管NOMS5的漏端并接在一起，产生电平移位电路的输出信号VS，控制大电流输出级的导通与关断。
上述死区时间控制电路是利用开关电源中脉宽调制信号产生反相不交迭的第一逻辑开关信号S1和第二逻辑开关信号S2，当脉宽调制信号是由低电平转换为高电平时，则第一逻辑开关信号S1先由高电平变成低电平，接着经过门电路和电容的延迟，第二逻辑开关信号S2才由低电平变为高电平；当脉宽调制信号是由高电平转换低电平时，则第二逻辑开关信号S2先由高电平变成低电平，接着经过门电路和电容延迟，第一逻辑开关信号S1才由低电平变为高电平。
上述大电流输出级包括一个达林顿复合结构和一个组合下拉高压NMOS管，达林顿复合结构具有大的灌电流能力，组合下拉高压NMOS管具有大的源电流能力，所述的达林顿复合结构是由三极管Q1、Q2、二极管D1、D2组成，Q1和Q2的集电极接公共电源VDD，三极管Q2的基极接二极管D2的N端、电阻R5的一端，共同接在电平移位电路的输出端VS上，三极管Q2的发射极接二极管D2的P端、二极管D1的N端、电阻R5的另一端、电阻R6的一端以及三极管Q1的基极，所述三极管Q1的发射极接电阻R6的另一端、二极管D1的P端，共同接在大电流输出级的输出端GATE_DRIVER上，所述的组合下拉高压NMOS管是由高压NMOS管M1、M2、M5以及电阻R5、R6组成，高压NMOS管M1的漏端接三极管Q1的发射极、电阻R6的一端，共同接在大电流输出级的输出端GATE_DRIVER上，高压NMOS管M2漏端接三极管Q1的基极、三极管Q2的发射极，二极管D1的N端、二极管D2的P端，高压NMOS管M5的漏端接三极管Q2的基极、电阻R5的一端，共同接在电平移位电路的输出端VS上，高压NMOS管M1、M2、M5的栅极并接在一起，连接在死区时间控制电路产生的第二逻辑开关信号S2，高压NMOS管M1、M2、M5的源端接公共地端GND。
本发明具有以下有益效果：
（1）本发明利用LDMOS管的高压隔离作用和稳压二极管的击穿稳压特性，将较高的输入电源电压转换为输出驱动开关信号所需要的固定电平，不仅可以提高驱动电路的可靠性，而且可以很好地保护外围功率器件。
（2）本发明利用电平移位电路，将来自于数字逻辑驱动电路产生的脉宽调制信号转换为具有固定电平的输出驱动开关信号，同时加入死区时间控制电路，防止在电平转换期间存在的电源到地的瞬间大电流现象。
（3）本发明采用经典的达林顿输出级结构，以提高输出驱动电路源电流和灌电流的能力。
（4）本发明针对于有源功率因数校正电路对于总谐波失真（THD）的要求，特别在子模块电路中加入了THD优化机制，减小THD。
【附图说明】
图1为本发明应用于功率因数校正器中的驱动电路的结构框图；
图2为本发明的具体电路原理图；
图3为本发明中电平移位电路3的具体电路原理图；
图4为本发明中死区时间控制电路4的具体电路原理图；
图5为本发明中死区时间控制电路4产生的输出信号时序图。
【具体实施方式】
下面将结合本发明具体实施例中的附图，对本发明实施例中的技术方案进行更为清楚完整的描述和解释，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通的技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
对发明所涉及的专业术语进行说明：
THD：Total Harmonic Distortion，总谐波失真
EMI：Electro magnetic interference，电磁干扰；
MOS：metal oxide semiconductor，金属氧化物半导体；
LDMOS：Later double-diffused metal oxide semiconductor，横向双扩散金属氧化物半导体；
NMOS：N-channel metal oxide semiconductor FET, N沟道金属氧化物半导体场效应晶体管。
PMOS：P-channel metal oxide semiconductor FET, P沟道金属氧化物半导体场效应晶体管。
为使本发明的目的、技术方案和优点表达的更加清楚明白，下面结合附图及具体实施例对本发明再做进一步详细地说明。
参照图1，本发明的应用于功率因数校正器中的高压大电流驱动电路包括：电流镜像电路1、高压预调制电路2、电平移位电路3、死区时间控制电路4和大电流输出级5。
参照图2，本发明各单元电路的结构和工作原理如下：
电流镜像电路1：
该电路包括三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、Q14和电阻R1、R2、R3、R4、R7；三极管Q13、Q14组成第一电流镜像电路；其中三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12和电阻R1、R2、R3、R4、R7组成二电流镜像电路。第一电流镜像电路Q14的输入端连接到外部基准电流源的输出端Ibias上，其中，I3为第一电流镜像电路中Q13的输出电流，为高压预调制电路中的第三电流镜像电路提供偏置电流；第二电流镜像电路是本发明中THD优化机制最为重要的部分，I4为第二电流镜像电路中Q7的输出电流，为箝位电路提供充电电流，Istart为第一电流镜像电路中Q8的输出电流，为第二电流镜像电路中其它镜像电路提供镜像电流。在有源功率因数校正控制器中，电路正常工作所需VDD电压一般比较高，因此如果瞬间VDD达到所需电压打开电路时，会造成输出端的过冲现象，此时THD和EMI问题就非常严重，甚至会烧毁外部功率开关管；在本发明中，加入了THD优化机制，当电VDD比较低电路未正常工作时，第一电流镜像电路提供启动电流IS：
IS=(VDD–VBE_Q12)/R7 （1）
该电流在VDD>VBE_Q12时产生，并且通过镜像电路镜像出去；电流IS首先镜像至Q8的输出电流Istart，I4也会镜像该电流，并为箝位二极管D4、D5充电，Q5会逐渐导通，因此高压预调制电路输出电压VCLAMP会跟随输入电压变化，当瞬间VDD达到所需电压打开电路时，VCLAMP不会发生瞬间跳变，输出端也就不会发生过冲变化，极大优化THD，并减少EMI的问题；同时I1和I1分别为第二电流镜像电路中Q3和Q4的输出电流，为电平移位电路提供偏置电流。
高压预调制电路2：
该电路包括LDMOS管LDMOS1（以下称为高压管LDMOS1）和LDMOS2（以下称为高压管LDMOS2）；稳压二极管D4、D5、D6；三极管Q5。该高压管LDMOS1和高压管LDMOS2组成第三电流镜像电路，其中，高压管LDMOS1作为高压预调制电路的第一高压隔离管，高压管LDMOS2为高压管LDMOS1的栅极提供合适的偏置电压，稳压二极管D6作为第三电流镜像电路的栅极箝位保护二极管，保证高压管LDMOS1和LDMOS2的栅源电压在其击穿电压范围内，稳压二极管D4、D5的串联形成高压预调制电路的核心单元，当输入电源电压VDD比较高时，且达到了稳压二极管D4和D5的击穿电压，此时第二高压隔离管Q5导通，高压预调制电路的输出电压VCLAMP大约稳定在二倍的稳压二极管击穿电压值。
电平移位电路4：
参照图3，所述电平移位电路4包括高压MOS管PMOS1、PMOS2、PMOS3、PMOS4、PMOS5、NMOS5，高压NMOS管M3、M4以及反相器INV1。I1和I2分别为第二电流镜像电路中Q3和Q4的输出电流，为电平移位电路提供电流通路，高压MOS管PMOS3和PMOS4的栅极接在三极管Q9的集电极Vb上。当脉宽调制信号Driver是由低电平转换为高电平时，则第一逻辑开关信号S1先由高电平变为低电平，高压NMOS管M3导通，NMOS管M4关断，Vb和输入偏置电流I1的作用下，高压管PMOS3管导通，PMOS2的栅极电压VA≈Vb＋VGS3，此时PMOS2导通，高压管PMOS5的栅极电压VB约为输入电源电压VCLAMP，高压管PMOS1和PMOS5关断，经过门电路和电容的延迟以后，第二逻辑开关信号S2才由低电平变为高电平，高压NMOS管M5才导通，VS输出低电平；当脉宽调制信号是由高电平转换低电平时，则第二逻辑开关信号S2先由高电平变成低电平，高压NMOS管M5马上被关断，接着经过门电路和电容的延迟，第一逻辑开关信号S1才由低电平变为高电平，高压NMOS管M3关断，NMOS管M4导通，在电压Vb和输入偏置电流I2的作用下，高压管PMOS4管导通，PMOS1和PMOS5的栅极电压VB≈Vb＋VGS4，此时PMOS1和PMOS5导通，高压管PMOS2的栅极电压VA约为输入电源电压VCLAMP，高压管PMOS2关断，VS输出高电平；加入死区时间控制电路以后，可以防止在电平转换期间存在的电源到地的瞬间大电流现象。
死区时间控制电路4
参照图4、图5，所述的死区时间控制电路4是利用开关电源中脉宽调制信号Driver产生反相不交迭的第一逻辑开关信号S1和第二逻辑开关信号S2，当脉宽调制信号是由低电平转换为高电平时，则第一逻辑开关信号S1先由高电平变成低电平，接着经过门电路和电容的延迟，第二逻辑开关信号S2才由低电平变为高电平；当脉宽调制信号Driver是由高电平转换低电平时，则第二逻辑开关信号S2先由高电平变成低电平，接着经过门电路和电容延迟，第一逻辑开关信号S1才由低电平变为高电平。
大电流输出级5：
参照图2、图4和图5，大电流输出级5包括一个达林顿复合结构和一个复合下拉高压NMOS管，达林顿复合结构具有大的灌电流能力，复合下拉高压NMOS管具有大的源电流能力，所述的达林顿复合结构是由三极管Q1、Q2、二极管D1、D2组成，所述的复合下拉高压NMOS管是由高压NMOS管M1、M2、M5以及电阻R5、R6组成，当输入脉宽调制信号Driver为高电平时，死区时间控制电路的第一逻辑开关信号S1为低电平，第二逻辑开关信号S2为高电平，电平移位电路的输出信号VS为低电平，在复合下拉NMOS管M1、M2和M5的作用下，大电流输出级的输出GATE_DRIVER被拉低；当输入脉宽调制信号Driver为低电平时，死区时间控制电路的第一逻辑开关信号S1为高电平，第二逻辑开关信号S2为低电平，复合下拉NMOS管M1、M2和M5关断，电平移位电路的输出VS为高电平，在达林顿复合管Q1和Q2的作用下，大电流输出级的输出GATE_DRIVER被快速充电至高电平；大电流输出级电路中电阻R5和R6也是本发明中THD优化机制的重要部分，其主要作用是为了限制输出级的电流大小，防止输出级产生瞬间过冲，优化THD；同时由于输出驱动信号GATE_DRIVER是通过芯片的一个管脚与外围功率型器件连接的，因此会产生寄生的电感，该寄生的电感与功率型器件的栅极寄生电容组成了一个LC谐振电路，而在输出级电路中加入大小合适的电阻以后，在输出驱动信号高低电平转化期间，能够有效地抑制输出驱动信号的振荡，减少EMI问题；在输出驱动信号GATE_DRIVER由高电平转换为低电平时，所述的二极管D1和D2是为了给达林顿复合管Q1和Q2的基区提供快速放电通路，加快达林顿复合管Q1和Q2的关断。
本发明利用LDMOS管的高压隔离作用和稳压二极管的击穿稳压特性，将较高的输入电源电压转换为输出驱动开关信号所需要的固定电平，不仅可以提高驱动电路的可靠性和安全性，而且可以很好地保护外围功率器件。并且本发明利用电平移位电路，将来自于数字逻辑驱动电路产生的脉宽调制信号转换为具有固定电平的输出驱动开关信号，同时加入死区时间控制电路，防止在电平转换期间存在的电源到地的瞬间大电流现象。其还采用经典的达林顿输出级结构，以提高输出驱动电路源电流和灌电流的能力。
本发明针对于有源功率因数校正电路对于总谐波失真（THD）的要求，特别在子模块电路中加入了THD优化机制，较小THD。
以上所述仅为本发明的较佳实例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的的任何修改，等同替换，改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种应用于功率因数校正器中的高压大电流驱动电路，包括电流镜像电路（1）、高压预调制电路（2）、电平移位电路（3）、死区时间控制电路（4）和大电流输出级（5），其特征在于：
    所述电流镜像电路（1）利用电阻和三极管组成的电流源电路和电流沉电路，将启动电流Istart和基准电流源产生的输入信号Ibias转换为高压预调制电路的输入信号，将启动电流Istar t转换为电平移位电路的输入信号；
    所述高压预调制电路（2）在电流镜像电路（1）偏置作用下，利用高压LDMOS管的隔离作用以及稳压二极管的击穿稳压特性，将一个高的输入电源电压VDD转换为相对低的电压，以保证驱动电路工作在一个安全的电压范围内，同时产生电平移位电路的输入电压VCLAMP；
    所述电平移位电路（3）在高压预调制电路（2）的输出作用下，利用电流镜像电路（1）的偏置作用，利用死区时间控制电路产生的第一逻辑开关信号S1和第二逻辑开关信号S2，控制高压管PMOS和高压管NOMS的导通与关断，从而产生电平移位电路的输出信号VS，为大电流输出级电路提供逻辑开关信号；
    所述死区时间控制电路（4）在数字逻辑驱动信号的作用下，利用逻辑门电路和电容的延迟作用，产生反相不交迭的第一逻辑开关信号S1和第二逻辑开关信号S2，控制电平移位电路和大电流输出级的工作状态；
    所述大电流输出级（3），在高压三极管所组成的达林顿复合管作用下，利用高压管NMOS和电平移位电路产生的逻辑开关信号VS，以及死区时间控制电路产生的第二逻辑开关信号S2，产生具有较大源电流和灌电流能力的输出驱动信号GATE_DRIVER，驱动外围功率器件的导通与关断。
  2. 根据权利要求1所述的高压大电流驱动电路，其特征在于：所述电流镜像电路（1）包括三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、Q14和电阻R1、R2、R3、R4、R7；所述三极管Q13和三极管Q14组成第一电流镜像电路；其中三极管Q3、Q4、Q6、Q7、Q8、Q9、Q10、Q11、Q12和电阻R1、R2、R3、R4、R7组成第二电流镜像电路；第一电流镜像电路的输入端连接到外部基准电流源的输出端Ibias上，第一电流镜像电路用于电流正常工作时为高压预调制电路提供偏置电流；第二电流镜像电路为高压预调制电路和电平移位电路提供偏置电流。
  3. 根据权利要求1所述的高压大电流驱动电路，其特征在于：所述的高压预调制电路（2）包括LDMOS管LDMOS1、LDMOS管LDMOS2、稳压二极管D4、D5、D6，三极管Q5；所述LDMOS管LDMOS1和LDMOS管LDMOS2组成第三电流镜像电路，其中，LDMOS管LDMOS1作为高压预调制电路的第一高压隔离管，LDMOS管LDMOS2作为LDMOS管LDMOS1的栅极偏置管，稳压二极管D6作为第三电流镜像电路的栅极箝位保护，稳压二极管D4、D5的串联组成第一高压预调制电路，三极管Q5作为高压预调制电路的第二高压隔离管。
  4. 根据权利要求3所述的高压大电流驱动电路，其特征在于：所述高压预调制电路（2）中，第三电流镜像电路中LDMOS管LDMOS2的栅极和漏极连接在一起，同时接在第一电流镜像电路中三极管Q13的集电极输出端，LDMOS管LDMOS1和LDMOS管LDMOS2的源极连接到输入电源VDD上，箝位二极管D6连接在第三电流镜像电路LDMOS管LDMOS1和LDMOS管LDMOS2的栅极和源极之间，LDMOS管LDMOS1的漏端连接在箝位二极管D4、D5串联的N端，同时连接三极管Q5的基极、以及第二电流镜像电路中三极管Q7的集电极输出端，在三极管Q5的发射极产生高压预调制信号VCLAMP。
  5. 根据权利要求1所述的高压大电流驱动电路，其特征在于：所述电平移位电路（3）包括高压PMOS管PMOS1、PMOS2、PMOS3、PMOS4、PMOS5，高压NMOS管M3、M4、M5以及反相器INV1；所述的高压PMOS管PMOS1、PMOS2、PMOS5的源端接公共电源VCLAMP，即接在高压预调制电路（2）的输出端，所述高压PMOS管PMOS1的栅极接高压PMOS管PMOS2的漏端，高压PMOS管PMOS1漏端接高压PMOS管PMOS2的栅极和高压PMOS管PMOS3的源端，同时，在电流镜像电路中第二电流镜像电路像的偏置作用下，将第二电流镜像电路三极管Q3的输出端集电极接在高压PMOS管PMOS1的漏端、高压PMOS管PMOS2的栅极、高压PMOS管PMOS3的源端，作为电平移位电路的偏置电流，所述高压PMOS管PMOS2的栅极接高压PMOS管PMOS1的漏端，高压PMOS管PMOS2的漏端接高压PMOS管PMOS1的栅极和高压PMOS管PMOS4的源端、高压PMOS管PMOS5的栅极，同时，在电流镜像电路（1）中第二电流镜像电路的偏置作用下，将第二电流镜像电路三极管Q4的集电极输出端连接在高压PMOS管PMOS1的栅极、高压PMOS管PMOS4的源端、高压PMOS管PMOS5的栅极，为电平移位电路（3）提供偏置电流，所述高压PMOS管PMOS3和PMOS4的栅极接在公共端Vb，高压PMOS管PMOS3的漏端接在高压NMOS管M3的漏端，高压PMOS管PMOS4的漏端接在高压NMOS管M4的漏端，所述高压NMOS管M3的栅极接在反相器INV1的输出端，高压NMOS管M3的源端接公共端GND，所述反相器INV1的输入端接死区时间控制电路产生的第一逻辑开关信号S1，所述高压NMOS管M4的栅极接反相器INV1的输入端，即接第一逻辑开关信号S1，高压NMOS管M4的源端接公共端GND，所述高压PMOS管PMOS5的栅极接高压PMOS管PMOS2漏端、PMOS1栅极以及PMOS4源端，高压PMOS管PMOS5的源端接高压预调制电路（2）的输出VCLAMP，高压PMOS管PMOS5的漏端接高压NMOS管M5的漏端，所述高NMOS管M5的栅极接死区时间控制电路产生的第二逻辑开关信号S2，高压NMOS管M5的源端接公共地端GND，高压PMOS管PMOS5的漏端和高压NMOS管NOMS5的漏端并接在一起，产生电平移位电路（3）的输出信号VS，控制大电流输出级（5）的导通与关断。
  6. 根据权利要求1所述的高压大电流驱动电路，其特征在于：所述死区时间控制电路（4）是利用开关电源中脉宽调制信号产生反相不交迭的第一逻辑开关信号S1和第二逻辑开关信号S2，当脉宽调制信号是由低电平转换为高电平时，则第一逻辑开关信号S1先由高电平变成低电平，接着经过门电路和电容的延迟，第二逻辑开关信号S2才由低电平变为高电平；当脉宽调制信号是由高电平转换低电平时，则第二逻辑开关信号S2先由高电平变成低电平，接着经过门电路和电容延迟，第一逻辑开关信号S1才由低电平变为高电平。
  7. 根据权利要求1所述的高压大电流驱动电路，其特征在于：所述大电流输出级（5）包括一个达林顿复合结构和一个组合下拉高压NMOS管，达林顿复合结构具有大的灌电流能力，组合下拉高压NMOS管具有大的源电流能力，所述的达林顿复合结构是由三极管Q1、Q2、二极管D1、D2组成，Q1和Q2的集电极接公共电源VDD，三极管Q2的基极接二极管D2的N端、电阻R5的一端，共同接在电平移位电路的输出端VS上，三极管Q2的发射极接二极管D2的P端、二极管D1的N端、电阻R5的另一端、电阻R6的一端以及三极管Q1的基极，所述三极管Q1的发射极接电阻R6的另一端、二极管D1的P端，共同接在大电流输出级的输出端GATE_DRIVER上，所述的组合下拉高压NMOS管是由高压NMOS管M1、M2、M5以及电阻R5、R6组成，高压NMOS管M1的漏端接三极管Q1的发射极、电阻R6的一端，共同接在大电流输出级的输出端GATE_DRIVER上，高压NMOS管M2漏端接三极管Q1的基极、三极管Q2的发射极，二极管D1的N端、二极管D2的P端，高压NMOS管M5的漏端接三极管Q2的基极、电阻R5的一端，共同接在电平移位电路的输出端VS上，高压NMOS管M1、M2、M5的栅极并接在一起，连接在死区时间控制电路产生的第二逻辑开关信号S2，高压NMOS管M1、M2、M5的源端接公共地端GND。
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