WO2024021695A1 - 一种电源管理芯片 - Google Patents

一种电源管理芯片 Download PDF

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Publication number
WO2024021695A1
WO2024021695A1 PCT/CN2023/089245 CN2023089245W WO2024021695A1 WO 2024021695 A1 WO2024021695 A1 WO 2024021695A1 CN 2023089245 W CN2023089245 W CN 2023089245W WO 2024021695 A1 WO2024021695 A1 WO 2024021695A1
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WIPO (PCT)
Prior art keywords
transistor
signal
switch
circuit
power management
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PCT/CN2023/089245
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English (en)
French (fr)
Inventor
易新敏
马玲莉
Original Assignee
圣邦微电子（北京）股份有限公司
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Publication of WO2024021695A1 publication Critical patent/WO2024021695A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits

Definitions

  • the present invention relates to the technical field of power management, and more specifically to a power management chip.
  • serial data (SDA) and serial clock (SCL) pins are usually used to exchange information between the external host (Host) and internal registers, allowing users to flexibly configure the charger. Discharge parameters and read the status of the power supply.
  • FIG. 1 shows a circuit schematic diagram of an existing I2C interface circuit 100 for a power management chip.
  • the I2C interface circuit 100 includes a flip-flop module 110 powered by an I/O voltage and an output buffer 120 powered by an internal voltage.
  • the flip-flop module 110 includes an input terminal 111, which is used to receive a logic input signal SCL_in and couple the logic input signal SCL_in to the gates of the transistors M1 to M4.
  • the transistors M1 to M4 are sequentially connected to the supply voltage VDIO and the ground voltage Vss. time, where the supply voltage VDIO is the internal I/O voltage designed specifically for the interface circuit, and the ground voltage Vss is the noise ground inside the chip.
  • the input terminal of the inverter 112 and the drains of the transistors M2 and M3 are connected to the node p1, the output terminal is connected to the gate of the transistor M7 in the output buffer 120, and the output terminal of the inverter 113 is connected to the node p1.
  • the input terminal is connected to the output terminal of the inverter 112 , and the output terminal is connected to the gate of the transistor M8 in the output buffer 120 .
  • the source of transistor M5 is connected to the drain of transistor M1 and the source of transistor M2, and the drain is connected to ground voltage Vss.
  • the source of transistor M6 is connected to the source of transistor M3 and the drain of transistor M4, and the drain is connected to the power supply.
  • the voltage VDIO is connected, and the gates of the transistors M5 and M6 and the output terminal of the inverter 113 are connected to the node p2.
  • the output buffer 120 also includes transistors M9 and M10.
  • the sources of the transistors M9 and M10 are connected to the power supply voltage VDD.
  • the gate of the transistor M9 is connected to the drain of the transistor M10.
  • the gate of the transistor M10 is connected to the drain of the transistor M9.
  • the drains of the transistors M9 and M10 are also connected to the drains of the transistors M7 and M8 respectively.
  • the sources of the transistors M7 and M8 are connected to the ground voltage Vss.
  • the drain of the transistor M8 is also connected to the logic output signal SCL_out.
  • resistor R1 and the transistor M0 in Figure 1 are chip peripheral circuits.
  • the resistor R1 and the transistor M0 are connected in turn between the voltage VREF_out and the ground voltage Vss_out, where the voltage VREF_out and the ground voltage Vss_out are the power supply and ground of the peripheral circuit respectively.
  • the host's control signal Host Control controls its on and off by controlling the gate voltage of transistor M0.
  • the logic input signal SCL_in is equal to Vss_out+Vds(M0), which is approximately equal to the ground voltage Vss_out; when the transistor M0 is turned off, the logic input signal SCL_in is equal to the voltage VREF_out-VR1, which is approximately equal to the voltage VREF_out.
  • the transistors M1, M2, and M6 are turned on, and the transistors M3 to M5 are turned off.
  • the voltages of the nodes p1 and p2 are approximately equal to the supply voltage VDIO.
  • the transistor M8 is turned on, and the logic output signal SCL_out is turned on. Pull down to ground voltage Vss.
  • the circuit can also generate a transition of the logic output signal SCL_out from high level to low level, realizing the level conversion between the logic signal of the external power rail (i.e. Host Control) and the logic signal of the internal power rail. .
  • Figure 2 shows the working waveform diagram of the existing I2C interface circuit 100.
  • Figure 2 shows the logic input signal SCL_in and the logic output signal SCL_out respectively.
  • the level changes, and the shaded area in Figure 2 represents the effective input voltage range under ideal conditions, and the shaded area represents the effective input voltage range under actual conditions.
  • the internal I2C interface circuit can Normally the logic input signal SCL_in is recognized and a flip occurs at the output (as shown by the dotted line of the SCL_out signal).
  • the ground voltage of the internal I2C interface circuit becomes low due to the switching noise of the power tube of the switching power supply converter, the effective voltage range becomes lower, as shown in the shaded area in Figure 2.
  • the logic input signal SCL_in The high and low levels may fall outside the voltage range limited by the shaded area, causing the internal I2C interface circuit to be unable to properly recognize the level change of the logic input signal SCL_in and cause a drain flip, as shown by the solid line of SCL_out in Figure 2. , thus causing interference to I2C communication.
  • the object of the present invention is to provide a power management chip that can adjust the power supply voltage of the I2C interface circuit and balance the efficiency problem of the DC/DC converter while improving the communication stability of the I2C interface.
  • a power management chip including: an I2C interface circuit connected to the logic pins of the chip for communicating with an external main controller to transfer adjustment parameters set by the main controller. ; And a drive circuit for converting the switch signal into a drive signal and applying it to the control end of the power switch in the power management chip, and adjusting the power of the power management chip by controlling the turn-on and turn-off of the power switch. Power is transferred from the input end to the output end to provide a stable output voltage, and the switching signal is obtained based on the adjustment parameter, wherein the driving rate of the driving circuit and/or the supply voltage of the I2C interface circuit can be adjusted.
  • the drive circuit includes: a buffer, the input end of which is used to receive the switch signal; a first totem pole circuit and a second totem pole circuit connected in parallel, the first totem pole circuit and the second totem pole circuit.
  • the totem pole circuit is used to charge and discharge the control terminal of the power switch based on the output of the buffer; and a drive control module is used to receive the first adjustment signal and control the second adjustment signal based on the first adjustment signal.
  • the signal path between the totem pole circuit and the buffer adjusts the driving rate of the driving circuit by controlling the opening and closing of the second totem pole circuit.
  • the I2C interface circuit includes: a power supply voltage generation module, used to provide a power supply voltage to the trigger module, the power supply voltage generation module is also used to receive a second adjustment signal, and adjust according to the second adjustment signal. the voltage value of the supply voltage; the flip-flop module for receiving a logic input signal from a logic pin of the chip, for comparing the logic input signal with a threshold voltage to generate a first signal; and an output buffer A processor configured to shape the first signal to obtain a logical output signal.
  • a power supply voltage generation module used to provide a power supply voltage to the trigger module, the power supply voltage generation module is also used to receive a second adjustment signal, and adjust according to the second adjustment signal. the voltage value of the supply voltage
  • the flip-flop module for receiving a logic input signal from a logic pin of the chip, for comparing the logic input signal with a threshold voltage to generate a first signal
  • an output buffer A processor configured to shape the first signal to obtain a logical output signal.
  • the second totem pole circuit includes: a first transistor and a second transistor connected between the first voltage and the second voltage, the control terminals of the first transistor and the second transistor are connected to the The output of the drive control module is connected, and the intermediate node of the first transistor and the second transistor is connected to the control terminal of the power switch.
  • the drive control module includes: a first switch connected between the output of the buffer and the control terminal of the first transistor; and a second switch connected between the output of the buffer and the control terminal of the first transistor. between the control terminals of the second transistor, wherein the first adjustment signal controls the buffer and the second totem pole by controlling the on and off of the first switch and the second switch. Signal paths between circuits.
  • the drive control module further includes: a third transistor, the first end of which is connected to the first voltage, the second end is connected to the control end of the first transistor, and the control end is connected to the first adjustment signal connection; and a fourth transistor, the first end of which is connected to the control end of the second transistor, the second end is connected to the second voltage, and the control end is connected to the inverse signal of the first adjustment signal.
  • the first switch and the second switch are turned on, the third transistor and the fourth transistor are turned off, and the first transistor and the second transistor is turned on non-overlappingly according to the output of the buffer.
  • the first adjustment signal is low level, the first switch and the second switch are turned off, and the third transistor and the fourth transistor are turned on, and the first transistor and the second transistor are turned off.
  • the first transistor and the third transistor are P-channel transistors
  • the second transistor and the fourth transistor are N-channel transistors.
  • the supply voltage generating module includes: a first current source, a fifth transistor, a sixth transistor and a first resistor connected in sequence between the power supply voltage and the ground voltage, the fifth transistor and the sixth
  • the transistors are respectively connected to form MOS diodes; a seventh transistor and a second current source are connected in sequence between the power supply voltage and the ground voltage, and the control end of the seventh transistor is connected to the second end of the first current source, The second end of the seventh transistor is used to output the supply voltage; an inverter, the input end of the inverter is used to receive the second adjustment signal; and an eighth transistor is connected in parallel with the sixth transistor. transistor, the control terminal of the eighth transistor is connected to the output terminal of the inverter.
  • the trigger module is a Schmitt trigger.
  • the ground voltage is a noise ground inside the chip.
  • the power management chip further includes: a power circuit, including at least one of the power switch and an inductance component.
  • the power switch is used to adjust the power transmission from the input end to the output end of the power management chip to provide stable Output voltage; a logic control circuit for receiving the adjustment parameter input by the I2C interface circuit and converting it into parameter information achievable by the switch controller; and the switch controller for controlling the parameter information according to the The corresponding switching signal is generated.
  • the adjustment signal for the driving rate of the driving circuit and/or the supply voltage of the I2C interface circuit may come from a trimming signal outside the chip or from the logic control circuit.
  • the power management chip provided by the present invention includes an I2C interface circuit, and can provide a first adjustment signal and/or a second adjustment signal when interference occurs in the communication of the I2C interface circuit to adjust the driving rate of the driving circuit and/or adjust the I2C interface circuit. Therefore, when interference occurs in the I2C communication of the chip, the driving speed of the converter can be reduced, and the power supply voltage of the I2C interface circuit can even be increased to achieve the purpose of improving communication accuracy.
  • the power management chip of the present invention can also optimize and balance corresponding functions according to actual applications, thereby improving communication efficiency. signal accuracy while balancing the efficiency of the converter.
  • Figure 1 shows a circuit schematic diagram of an existing I2C interface circuit 100 for a power management chip
  • Figure 2 shows the working waveform diagram of the existing I2C interface circuit
  • Figure 3 shows a structural block diagram of a control system of a power management chip according to an embodiment of the present invention
  • Figure 4 shows a structural block diagram of a power management chip according to an embodiment of the present invention
  • Figure 5 shows a circuit schematic diagram of a driving circuit in a power management chip according to an embodiment of the present invention
  • FIG. 6 shows a circuit schematic diagram of an I2C interface circuit in a power management chip according to an embodiment of the present invention.
  • circuitry may include a single or multiple combinations of hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions executed by programmable circuits.
  • an element or circuit When an element or circuit is said to be “connected” to another element, or an element/circuit is said to be “connected between” two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements can be Be physical, logical, or a combination thereof.
  • an element is said to be "directly coupled” or “directly connected to” another element, it means that the two elements are not There are intermediate elements.
  • FIG. 3 shows a structural block diagram of a control system of a power management chip according to an embodiment of the present invention.
  • the control system includes a power management chip 200 and a main controller 300.
  • the power management chip 200 is used to provide power to each functional module of the terminal.
  • the main controller 300 is used to detect the power supply voltage and actual power consumption of each functional module, and transmit the adjustment parameters corresponding to the requirements to the power management chip 200.
  • the power management chip 200 is also used to output the power supply voltage to each functional module according to the adjustment parameters.
  • communication modules are provided in both the main controller 300 and the power management chip 200 to ensure that the main controller 300 can correctly transmit the adjustment parameters to the power management chip 200 .
  • the communication module of the main controller 300 and the communication module inside the power management chip 200 are both I2C communication modules, ensuring the stability of information transmission.
  • the main controller 300 and the power management chip 200 are connected through an I2C bus (I2C BUS), and the serial data (SDA) line and serial clock (SCL) line in the I2C bus are used to implement the external host.
  • I2C BUS I2C bus
  • SDA serial data
  • SCL serial clock
  • FIG. 4 shows a structural block diagram of a power management chip according to an embodiment of the present invention.
  • the power management chip of the present invention is also called a programmable power management chip (or is called an output voltage programmable power supply chip, referred to as a chip) and includes: Power circuit 201, I2C interface circuit 202, logic control circuit 204, switch controller 205 and drive circuit 206.
  • the power circuit 201 includes one or more switching elements and filter elements (eg, inductors and/or capacitors, etc.) configured to adjust switches in response to the switch drive signal.
  • the power transmission from the input end of the converter to the output end converts the input voltage Vin into a stable and continuous output voltage Vout.
  • the power circuit 201 can be divided into a buck converter, a boost converter, a flyback converter and a buck-boost converter.
  • Buck-boost converter a buck-boost converter.
  • the power circuit 201 is implemented through a buck topology, including a power switch Mx and a peripheral inductor element Lx and a rectifier diode D1.
  • the first terminal of the power switch Mx is connected to the input voltage Vin, and the second terminal is connected to the anode of the rectifier diode D1.
  • the cathode of the rectifier diode D1 is grounded, the common terminal of the power switch Mx and the rectifier diode D1 forms a switch node SW, the first terminal of the inductor element Lx is connected to the switch node, and the second terminal of the inductor element Lx is connected to the output voltage Vout.
  • the power switch Mx can be any controllable semiconductor switching device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc.
  • MOSFET metal oxide semiconductor field effect transistor
  • IGBT insulated gate bipolar transistor
  • any other type of suitable switching element may be used without departing from the principles of the present invention.
  • this embodiment is explained using a non-synchronous buck converter, the present invention is not limited to this. The present invention is also applicable to a synchronous buck converter. Those skilled in the art can also use synchronous rectification switching elements instead of the above-mentioned ones. Rectifier diode D1 in the embodiment.
  • the I2C interface circuit 202 is connected to the serial clock (SCL) pin and the serial data (SDA) pin of the chip, and is mainly responsible for communicating with the I2C controller of the main controller and transmitting the adjustment parameters set by the main controller.
  • SCL serial clock
  • SDA serial data
  • the logic control circuit 204 receives the adjustment parameters input from the I2C interface circuit 202 and converts them into parameter information that can be implemented by the switch controller 205 .
  • This module can be controlled and enabled by an external host.
  • the logic control circuit 204 can use a DAC to convert the input adjustment parameter into a level signal or into a pulse signal with an adjustable duty cycle, thereby controlling the switch controller 205 .
  • the logic control circuit 204 of the present invention is not limited to the above method.
  • the switch controller 205 is the main control part of the power management chip. It controls the on and off of the power branch through the power switch Mx, thereby outputting different voltage values. Specifically, the switch controller 205 is connected to the feedback signal FB of the chip, and is used to obtain the divided voltage signal of the output voltage Vout according to the feedback signal, and adjust the switching of the power switch Mx according to the divided voltage signal to stabilize the output voltage Vout. In some embodiments, the divided voltage value of the output voltage Vout is obtained through a voltage dividing network formed by external resistors R1 and R2. In addition, the switch controller in the present invention may include a pulse width modulation (PWM), pulse frequency modulation (PFM) or width modulation frequency modulation (PWM-PFM) controller.
  • PWM pulse width modulation
  • PFM pulse frequency modulation
  • PWM-PFM width modulation frequency modulation
  • the driving circuit 206 is used to generate a driving signal of the power switch Mx according to the switching signal output by the switch controller 205 and apply it to the gate of the power switch Mx to control the turn-on and turn-off of the power switch Mx.
  • the power management chip 200 of the embodiment of the present invention also includes a method for switching the driving circuit 206 based on the first adjustment signal CTR1
  • the driving speed or the power supply voltage of the I2C interface circuit is adjusted based on the second adjustment signal CTR2 to improve the communication stability of the I2C interface circuit and balance the efficiency issue of the DC/DC converter.
  • the first adjustment signal CTR1 and the second adjustment signal CTR2 can be obtained by trimming outside the chip.
  • the logic control circuit 204 can also be used to generate the first adjustment signal CTR1 and/or the second adjustment signal CTR2 when interference occurs in the communication of the I2C interface circuit 201.
  • the first adjustment signal CTR1 is used to adjust the driving circuit.
  • the second adjustment signal CTR2 is used to adjust the power supply voltage of the I2C interface circuit 201, so that when interference occurs in the I2C communication, the driving speed of the converter can be reduced, or even the power supply voltage of the I2C interface circuit 201 can be increased to achieve improvement. Communication accuracy purposes.
  • the logic control circuit 204 can also adjust the driving speed of the driving circuit 206 to adapt to the communication accuracy of the I2C interface. Therefore, the power management chip 200 of the embodiment of the present invention can be adapted to the actual application. , optimize and balance the corresponding functions.
  • FIG. 5 shows a circuit schematic diagram of a driving circuit in a power management chip according to an embodiment of the present invention.
  • the driving circuit 206 of this embodiment uses several totem pole circuits to drive the power switch Mx.
  • the driving circuit 206 includes a buffer 261 implemented by a plurality of cascaded totem pole circuits, a first totem pole circuit 262 and a second totem pole circuit 263 .
  • the input terminal of the buffer 261 is connected with the switching signal DRV from the switch controller 205 in FIG. 4, and the output signal is applied to the input terminals of the first totem pole circuit 262 and the second totem pole circuit 263.
  • a totem pole circuit 262 and a second totem pole circuit 263 are connected in parallel between the voltage VSW+ ⁇ V and the switching node VSW, and their output terminals are connected to the gate of the power switch Mx for charging and discharging the gate of the power switch Mx. , to turn on or off the power switch Mx.
  • the first totem pole circuit 262 includes transistors M11 and M12
  • the second totem pole circuit 263 includes transistors M13 and M14.
  • the transistors M11 and M13 are, for example, P-channel transistors
  • the transistors M12 and M14 are, for example, N-channel transistors.
  • the transistors M11 and M12 The gate of the transistor M11 is connected to the output of the buffer 261, the source of the transistor M11 is connected to the voltage VSW+ ⁇ V, the drain is connected to the drain of the transistor M12 and the gate of the power switch Mx, and the source of the transistor M12 is connected to the switching node VSW. .
  • the source of the transistor M13 is connected to the voltage VSW+ ⁇ V, and the drain is connected to the drain of the transistor M14 and the gate of the power switch Mx.
  • the transistors M11 and M12 are complementary to each other, and the transistors M13 and M14 are complementary to each other.
  • the transistors M11 and M13 are used to charge the gate of the power switch Mx when it is turned on to turn on the power switch Mx.
  • the transistors M12 and M14 are used to turn on the power switch Mx. When it is on, it discharges to the gate of the power switch Mx to turn off the power switch Mx.
  • the rectifier diode D1 freewheels the inductor Lx, and the internal ground voltage of the chip will be pulled down. At this time, noise will be generated on the ground of the chip's I2C interface circuit that is difficult to eliminate.
  • the driving circuit 206 of this embodiment also includes a driving control module 264.
  • the drive control module 264 is used to control the signal path between the second totem pole circuit 263 and the buffer 261 based on the first adjustment signal CTR1 to control the switch of the second totem pole circuit 263 to thereby adjust the driving rate of the power switch Mx. Purpose.
  • the first adjustment signal CTR1 can be enabled to be a logic high level or a low level.
  • the second totem pole circuit 263 is turned on.
  • the first totem pole circuit 262 and the second totem pole circuit 263 drive the power switch Mx together.
  • the switching rate of the power switch Mx It is faster and the noise in the I2C interface circuit is larger.
  • the first adjustment signal CTR1 is low level, the second totem pole circuit 263 is closed. At this time, only the first totem pole circuit 262 is used to drive the power switch Mx. Since the time constant from the front-stage buffer to the power switch Mx is relatively long at this time, Small, so the switching rate of the power switch Mx is slower and the noise in the I2C interface circuit is also smaller.
  • the drive control module 264 of this embodiment includes an inverter INV1, a switch 301, a switch 302, and transistors M15 and M16.
  • the input terminal of the inverter INV1 is used to receive the first adjustment signal CTR1, and the output terminal is used to output the inverted signal of the first adjustment signal.
  • the input terminal of the switch 301 is connected to the output of the buffer 261, and the output terminal is connected to the gate of the transistor M13.
  • the turn-on and turn-off of the switch 301 is controlled by the first adjustment signal CTR1, and when the switch 301 is turned on, the signal communication between the buffer 261 and the gate of the transistor M13 is turned on. path, the switch 301 disconnects the signal path between the buffer 261 and the gate of the transistor M13 when turned off.
  • the switch 301 is realized, for example, by a parallel connection of an N-channel transistor M17 and a P-channel transistor M18.
  • the first terminals of the transistors M17 and M18 are connected to each other as the input terminal of the switch 301 and the output of the buffer 261.
  • the second terminals of the transistors M17 and M18 are connected to each other.
  • the output terminal of the switch 301 is connected to the gate of the transistor M13, the gate of the transistor M17 is connected to the first adjustment signal CTR1, and the gate of the transistor M18 is connected to the inverted signal of the first adjustment signal CTR1.
  • the transistor M15 is a P-channel transistor, its gate is connected to the first adjustment signal CTR1, its source is connected to the voltage VSW+ ⁇ V, and its drain is connected to the gate of the transistor M13.
  • the input terminal of the switch 302 is connected to the output of the buffer 261 , and the output terminal is connected to the gate of the transistor M14 .
  • the on and off of the switch 302 is controlled by the first adjustment signal CTR1, and when the switch 302 is on, it connects the signal path between the buffer 261 and the gate of the transistor M14, and when it is off, it disconnects the buffer. 261 and the gate of transistor M14.
  • the switch 302 is realized, for example, by a parallel connection of an N-channel transistor M19 and a P-channel transistor M20.
  • the first terminals of the transistors M19 and M20 are connected to each other as the input terminal of the switch 302 and the output of the buffer 261.
  • the second terminals of the transistors M19 and M20 are connected to each other.
  • the output terminal of the switch 302 is connected to the gate of the transistor M14, the gate of the transistor M19 is connected to the first adjustment signal CTR1, and the gate of the transistor M20 is connected to the inverted signal of the first adjustment signal CTR1.
  • the transistor M16 is an N-channel transistor, its gate is connected to the inverted signal of the first adjustment signal CTR1, its source is connected to the voltage VSW, and its drain is connected to the gate of the transistor M14.
  • the switches 301 and 302 are turned off, the signal path between the buffer 261 and the gates of the transistors M13 and M14 is disconnected, and at the same time, the transistors M15 and M16 are turned on, respectively.
  • the gate of transistor M14 is pulled up to voltage VSW+ ⁇ V, and the gate of transistor M14 is pulled down to voltage VSW, thereby turning off transistors M13 and M14.
  • the switches 301 and 302 are turned on, the transistors M15 and M16 are turned off, and the transistors M13 and M14 are respectively turned on in a complementary manner according to the output of the buffer 261 and participate in the driving process of the power switch Mx. .
  • the power management chip of this embodiment can reduce the power switch
  • the switching rate is used to reduce the noise generated in the I2C interface circuit, but the reduction in the driving rate will cause the power switch to consume energy during the turn-on and turn-off processes and then lose the conversion efficiency of the power supply.
  • FIG. 6 shows a circuit schematic diagram of an I2C interface circuit in a power management chip according to an embodiment of the present invention.
  • the I2C interface circuit 202 of this embodiment includes a supply voltage generation module 221 , a flip-flop module 222 and an output buffer 223 .
  • the supply voltage generating module 221 is used to generate the supply voltage VDIO of the flip-flop module 222 according to the supply voltage VDD, and the output buffer 223 is directly powered by the supply voltage VDD.
  • the supply voltage generating module 221 includes current sources I1 and I2, an inverter INV2, a resistor R12, and transistors M21 to M24.
  • the transistors M21 to M24 are N-channel transistors.
  • the first end of the current source I1 is connected to the power supply voltage VDD, and the second end is connected to the gate and drain of the transistor M21.
  • the source of the transistor M21 is connected to the drain of the transistor M22.
  • the source of the transistor M22 is connected to the gate, the source of the transistor M22 is connected to the first end of the resistor R12, and the second end of the resistor R12 is connected to the ground voltage Vss.
  • the input terminal of the inverter INV2 is connected to the second adjustment signal CTR2, the output terminal is connected to the gate of the transistor M23, the drain of the transistor M23 is connected to the drain of the transistor M22, and the source of the transistor M23 is connected to the source of the transistor M22.
  • the drain of the transistor M24 is connected to the power supply voltage VDD, the gate is connected to the common node between the current source I1 and the transistor M21, the source is used to output the power supply voltage VDIO, and the current source I2 is connected to the source of the transistor M24 and the ground voltage Vss. between.
  • the transistor M23 When the second adjustment signal CTR2 is low level, the transistor M23 is turned on, thereby short-circuiting the transistor M22.
  • VDIO I1 ⁇ R12+Vth_M21-Vth_M24, where Vth_M21 and Vth_M24 are the conduction thresholds of the transistors M21 and M24 respectively, it can be
  • the first voltage value of the supply voltage VDIO is calculated, for example, 1.2V.
  • the second voltage of the supply voltage VDIO can be calculated value, for example 1.8V.
  • increasing the voltage value of the supply voltage can make the conversion range of the logic input signal of the trigger module 222 wider. Even if the voltage difference between the internal ground and the external ground of the chip is relatively large, the trigger module can still ensure 222 makes it easier to identify the flipping of the SDA and SCL signals.
  • the flip-flop module 222 is implemented by a Schmitt trigger, for example, and includes an input terminal 111, which is used to receive the logic input signal SCL_in, and couple the logic input signal SCL_in to the gates of the transistors M1 ⁇ M4, and the transistors M1 ⁇ M4.
  • M4 is connected in turn between the power supply voltage VDIO and the ground voltage Vss.
  • the power supply voltage VDIO is the internal I/O voltage specially designed for the interface circuit, and the ground voltage Vss is the noise ground inside the chip.
  • the input terminal of the inverter 112 and the drains of the transistors M2 and M3 are connected to the node p1, the output terminal is connected to the gate of the transistor M7 in the output buffer 223, and the input terminal of the inverter 113 is connected to the output of the inverter 112.
  • the output terminal is connected to the gate of the transistor M8 in the output buffer 223 .
  • the output buffer 223 is used to shape the output signals of the inverters 112 and 113 to obtain the logic output signal SCL_out.
  • the source of transistor M5 is connected to the drain of transistor M1 and the source of transistor M2, and the drain is connected to ground voltage Vss.
  • the source of transistor M6 is connected to the source of transistor M3 and the drain of transistor M4, and the drain is connected to the power supply.
  • the voltage VDIO is connected, and the gates of the transistors M5 and M6 and the output terminal of the inverter 113 are connected to the node p2.
  • the output buffer 223 also includes transistors M9 and M10.
  • the sources of the transistors M9 and M10 are connected to the power supply voltage VDD.
  • the gate of the transistor M9 is connected to the drain of the transistor M10.
  • the gate of the transistor M10 is connected to the drain of the transistor M9.
  • the drains of the transistors M9 and M10 are also connected to the drains of the transistors M7 and M8 respectively.
  • the sources of the transistors M7 and M8 are connected to the ground voltage Vss.
  • the drain of the transistor M8 is also connected to the output terminal of the logic output signal SCL_out.
  • the transistors M1, M2, M5, M9 and M10 are P-channel transistors
  • the transistors M3, M4, M6, M7 and M8 are N-channel transistors.
  • the circuit can also generate a logic output signal SCL_out
  • the transition from high level to low level realizes the level conversion between the logic signal of the external power rail (ie Host Control) and the logic signal of the internal power rail.
  • the power management chip provided by the present invention includes an I2C interface circuit, and can provide the first adjustment signal and/or the second adjustment signal when interference occurs in the communication of the I2C interface circuit to adjust the driving rate and/or the driving circuit. Or adjust the power supply voltage of the I2C interface circuit, so that when interference occurs in the chip's I2C communication, the driving speed of the converter can be reduced, or even the power supply voltage of the I2C interface circuit can be increased to achieve the purpose of improving communication accuracy.
  • the power management chip of the present invention can also optimize and balance corresponding functions according to actual applications, thereby improving communication accuracy while balancing the efficiency of the converter.
  • the device is described as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, those of ordinary skill in the art will understand that according to the present invention, complementary Devices are also available.
  • the conductivity type refers to the mechanism by which electricity is generated, such as conduction through holes or electrons. Therefore, the conductivity type does not relate to the doping concentration but to the doping type, such as P-type or N-type.

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Abstract

本申请公开了一种电源管理芯片，包括：I2C接口电路，与芯片的逻辑引脚连接，用于与外部的主控制器进行通信，以传递主控制器设置的调整参数；以及驱动电路，用于将开关信号转换成驱动信号并施加到电源管理芯片中的功率开关的控制端，通过控制功率开关的导通和关断来调节电源管理芯片的输入端至输出端的电能传输，以提供稳定的输出电压，开关信号基于调整参数获得，其中，驱动电路的驱动速率和/或I2C接口电路的供电电压可以被调节，从而可以在I2C接口的通讯出现干扰时通过调节驱动电路的驱动速率和/或I2C接口电路的供电电压来提高芯片的通讯准确率。

Description

一种电源管理芯片
本申请要求了申请日为2022年07月25日、申请号为2022108769416、名称为“一种电源管理芯片”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本发明涉及电源管理技术领域，更具体地涉及一种电源管理芯片。
背景技术
随着5G、物联网的飞速发展，各类电子设备不断升级，需求也日益增加。这类电子设备一般不使用电网或者电池直接供电，而是将外部的高压通过开关电源变换器等稳压电源转换成精确、稳定的电源电压来供电。因此，电源管理芯片(Power Management Integrated Circuits)对这些电子设备非常重要。
在需要I2C通讯的电源管理芯片中，通常使用串行数据(SDA)和串行时钟(SCL)引脚实现外部主机(Host)与内部寄存器之间的信息交换，从而可以让用户灵活地配置充放电参数和读取电源所处的状态。
图1示出了现有的一种用于电源管理芯片的I2C接口电路100的电路示意图。如图1所示，I2C接口电路100包括由I/O电压供电的触发器模块110和由内部电压供电的输出缓冲器120。
触发器模块110包括输入端111，它用于接收逻辑输入信号SCL_in，并将该逻辑输入信号SCL_in耦合到晶体管M1～M4的栅极，晶体管M1～M4依次连接于供电电压VDIO和地电压Vss之间，其中供电电压VDIO为内部专为接口电路设计的I/O电压，地电压Vss为芯片内部的噪声地。反相器112的输入端与晶体管M2和M3的漏极连接于节点p1，输出端与输出缓冲器120中的晶体管M7的栅极连接，反相器113的输 入端与反相器112的输出端连接，输出端与输出缓冲器120中的晶体管M8的栅极连接。晶体管M5的源极与晶体管M1的漏极以及晶体管M2的源极连接，漏极与地电压Vss连接，晶体管M6的源极与晶体管M3的源极以及晶体管M4的漏极连接，漏极与供电电压VDIO连接，晶体管M5和M6的栅极与反相器113的输出端连接于节点p2。
输出缓冲器120还包括晶体管M9和M10，晶体管M9和M10的源极与电源电压VDD连接，晶体管M9的栅极与晶体管M10的漏极连接，晶体管M10的栅极与晶体管M9的漏极连接，晶体管M9和M10的漏极还分别与晶体管M7和M8的漏极连接，晶体管M7和M8的源极与地电压Vss连接，晶体管M8的漏极还与逻辑输出信号SCL_out连接。
此外，图1中的电阻R1和晶体管M0为芯片外围电路，电阻R1和晶体管M0依次连接于电压VREF_out和地电压Vss_out之间，其中电压VREF_out和地电压Vss_out分别为外围电路的供电电源和地。
在芯片内外部电路的地和电源没有压差的情况下，主机的控制信号Host Control通过控制晶体管M0的栅极电压来控制它的导通和关断。当晶体管M0导通时，逻辑输入信号SCL_in等于Vss_out+Vds(M0)，约等于地电压Vss_out；当晶体管M0关断时，逻辑输入信号SCL_in等于电压VREF_out－VR1，约等于电压VREF_out。
当逻辑输入信号SCL_in为低电平时，晶体管M1、M2、M6导通，晶体管M3～M5关断，节点p1和p2的电压约等于供电电压VDIO，继而晶体管M8被导通，将逻辑输出信号SCL_out拉低到地电压Vss。当逻辑输入信号SCL_in由低电平跳变为高电平时，当逻辑输入信号SCL_in的电压大于晶体管M4的导通阈值时，先把晶体管M4导通，接着把晶体管M3导通，随后晶体管M1和M2被关断，节点p1和p2被拉低到Vss，晶体管M8关断，逻辑输出信号SCL_out被拉高到电源VDD，最终实现逻辑输出信号SCL_out从低电平到高电平的跳变。同理，该电路还能够产生逻辑输出信号SCL_out从高电平到低电平的跳变，实现了外部电源轨的逻辑信号(即Host Control)与内部电源轨的逻辑信号之间的电平转换。
但是，在实际的应用中芯片的内外部电路的地和电源会因为噪声或者连接方式而存在一定的压差。当芯片内外部电路的电源轨存在压差时，可能会导致内部电路和I2C通讯的信号误触发或者漏触发的现象发生。
以内部地电压低于外部地电压的情况为例，如图2示出了现有的I2C接口电路100的工作波形图，在图2中分别示出了逻辑输入信号SCL_in和逻辑输出信号SCL_out的电平变化，且图2中的斜线区域表示理想情况下的有效输入电压范围，阴影区域表示实际情况下的有效输入电压范围。在理想情况下，当逻辑输入信号SCL_in的低电平落入Vss～VDD_lmax，高电平落入Vin_hmin～VDIO(如图2中的斜线区域所示)时，此时内部的I2C接口电路能够正常识别逻辑输入信号SCL_in而在输出发生翻转(如SCL_out信号的虚线所示的)。而当内部的I2C接口电路的地电压由于开关电源变换器的功率管开关噪声而变低时，有效电压范围随之变低，如图2中的阴影区域所示，此时逻辑输入信号SCL_in的高低电平可能会落入到阴影区域限定的电压范围之外，导致内部的I2C接口电路无法正常识别逻辑输入信号SCL_in的电平变化而出现漏翻转，如图2中的SCL_out的实线所示，从而对I2C通讯造成干扰。
发明内容
有鉴于此，本发明的目的在于提供一种电源管理芯片，可调整I2C接口电路的供电电压，在提高I2C接口的通讯稳定性的同时平衡了DC/DC变换器的效率问题。
根据本发明实施例，提供了一种电源管理芯片，包括：I2C接口电路，与芯片的逻辑引脚连接，用于与外部的主控制器进行通信，以传递所述主控制器设置的调整参数；以及驱动电路，用于将开关信号转换成驱动信号并施加到所述电源管理芯片中的功率开关的控制端，通过控制所述功率开关的导通和关断来调节所述电源管理芯片的输入端至输出端的电能传输，以提供稳定的输出电压，所述开关信号基于所述调整参数获得，其中，所述驱动电路的驱动速率和/或所述I2C接口电路的供电电压可以被调节。
可选的，所述驱动电路包括：缓冲器，其输入端用于接收所述开关信号；并联的第一图腾柱电路和第二图腾柱电路，所述第一图腾柱电路和所述第二图腾柱电路用于基于所述缓冲器的输出对所述功率开关的控制端进行充放电；以及驱动控制模块，用于接收第一调整信号，并基于所述第一调整信号控制所述第二图腾柱电路与所述缓冲器之间的信号通路，通过控制所述第二图腾柱电路的开启和关闭来调节所述驱动电路的驱动速率。
可选的，所述I2C接口电路包括：供电电压产生模块，用于向触发器模块提供供电电压，所述供电电压产生模块还用于接收第二调整信号，并根据所述第二调整信号调节所述供电电压的电压值；所述触发器模块，用于从芯片的逻辑引脚接收逻辑输入信号，用于将所述逻辑输入信号与阈值电压进行比较，以生成第一信号；以及输出缓冲器，用于对所述第一信号整形以得到逻辑输出信号。
可选的，所述第二图腾柱电路包括：连接于第一电压和第二电压之间的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的控制端与所述驱动控制模块的输出连接，所述第一晶体管和所述第二晶体管的中间节点与所述功率开关的控制端连接。
可选的，所述驱动控制模块包括：第一开关，连接于所述缓冲器的输出与所述第一晶体管的控制端之间；以及第二开关，连接于所述缓冲器的输出与所述第二晶体管的控制端之间，其中，所述第一调整信号通过控制所述第一开关和所述第二开关的导通和关断来控制所述缓冲器与所述第二图腾柱电路之间的信号通路。
可选的，所述驱动控制模块还包括：第三晶体管，其第一端与所述第一电压连接，第二端与所述第一晶体管的控制端连接，控制端与所述第一调整信号连接；以及第四晶体管，其第一端与所述第二晶体管的控制端连接，第二端与所述第二电压连接，控制端与所述第一调整信号的反相信号连接。
可选的，当所述第一调整信号为高电平时，所述第一开关和所述第二开关导通，所述第三晶体管和所述第四晶体管关断，所述第一晶体管 和所述第二晶体管根据所述缓冲器的输出非交叠导通，当所述第一调整信号为低电平时，所述第一开关和所述第二开关关断，所述第三晶体管和所述第四晶体管导通，将所述第一晶体管和所述第二晶体管关断。
可选的，所述第一晶体管和所述第三晶体管为P沟道晶体管，所述第二晶体管和所述第四晶体管为N沟道晶体管。
可选的，所述供电电压产生模块包括：依次连接于电源电压和地电压之间的第一电流源、第五晶体管、第六晶体管和第一电阻，所述第五晶体管和所述第六晶体管分别连接成MOS二极管；依次连接于所述电源电压和地电压之间的第七晶体管和第二电流源，所述第七晶体管的控制端与所述第一电流源的第二端连接，所述第七晶体管的第二端用于输出所述供电电压；反相器，所述反相器的输入端用于接收所述第二调整信号；以及与所述第六晶体管并联的第八晶体管，所述第八晶体管的控制端与所述反相器的输出端连接。
可选的，所述触发器模块为施密特触发器。
可选的，所述地电压为所述芯片内部的噪声地。
可选的，所述电源管理芯片还包括：功率电路，包括至少一个所述功率开关以及电感元件，所述功率开关用来调节所述电源管理芯片输入端至输出端的电能传输，以提供稳定的输出电压；逻辑控制电路，用于接收所述I2C接口电路输入的所述调整参数，并将其转换为开关控制器可实现的参数信息；以及所述开关控制器，用于根据所述参数信息产生相应的所述开关信号。
可选的，所述驱动电路的驱动速率和/或所述I2C接口电路的供电电压的调整信号可以来自芯片外部的修调信号或者来自所述逻辑控制电路。
本发明提供的电源管理芯片包括I2C接口电路，并且可以在I2C接口电路的通讯出现干扰时提供第一调整信号和/或第二调整信号，以调节驱动电路的驱动速率和/或调节I2C接口电路的供电电压，从而可以在芯片的I2C通讯出现干扰时，降低变换器的驱动速度，甚至提高I2C接口电路的供电电压，达到提高通讯准确率的目的。此外，本发明的电源管理芯片还可以根据实际应用对相应功能进行优化和平衡，从而在提高通 讯准确率的同时平衡变换器的效率。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚。
图1示出了现有的一种用于电源管理芯片的I2C接口电路100的电路示意图；
图2示出了现有的I2C接口电路的工作波形图；
图3示出了根据本发明实施例的电源管理芯片的控制系统的一种结构框图；
图4示出了根据本发明实施例的电源管理芯片的结构框图；
图5示出了根据本发明实施例的电源管理芯片中的驱动电路的电路示意图；
图6示出了根据本发明实施例的电源管理芯片中的I2C接口电路的电路示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本发明的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
应当理解，在以下的描述中，“电路”可包括单个或多个组合的硬件电路、可编程电路、状态机电路和/或能存储由可编程电路执行的指令的元件。当称元件或电路“连接到”另一元件或称元件/电路“连接在”两个节点之间时，它可以直接耦合或连接到另一元件或者可以存在中间元件，元件之间的连接可以是物理上的、逻辑上的、或者其结合。相反，当称元件“直接耦合到”或“直接连接到”另一元件时，意味着两者不 存在中间元件。
图3示出了根据本发明实施例的电源管理芯片的控制系统的一种结构框图。如图3所示，该控制系统包括电源管理芯片200和主控制器300。电源管理芯片200用于向终端的各个功能模块进行供电，主控制器300用于对各个功能模块的供电电压和实际功耗进行检测，并将与要求对应的调整参数传输给电源管理芯片200，电源管理芯片200还用于按照调整参数输出供电电压给各个功能模块。
在优选的实施例中，主控制器300和电源管理芯片200中均设置了通信模块，保证了主控制器300可以正确的将调整参数传输给电源管理芯片200。进一步的，主控制器300的通信模块和电源管理芯片200内部的通信模块均为I2C通信模块，保证了信息传输的稳定性。在优选的实施例中，主控制器300与电源管理芯片200之间通过I2C总线(I2C BUS)连接，使用I2C总线中的串行数据(SDA)线和串行时钟(SCL)线实现外部主机(Host)与芯片内部的寄存器之间的信息交换，从而可以让用户灵活地配置充放电参数和读取电源的状态所处的状态。
图4示出了根据本发明实施例的电源管理芯片的结构框图，本发明的电源管理芯片又被称为可编程的电源管理芯片(或称为输出电压可编程电源芯片，简称芯片)包括：功率电路201、I2C接口电路202、逻辑控制电路204、开关控制器205和驱动电路206。
其中，功率电路201包括一个或多个开关元件和滤波器元件(例如，电感和/或电容等)，所述一个或多个开关元件和滤波器元件被配置为响应于开关驱动信号来调节开关变换器输入端至输出端的电能传输，以将输入电压Vin转换成稳定连续的输出电压Vout。
在一些实施例中，按照功率电路201的拓扑分类，可以将其划分为降压型(buck)变换器、升压型(boost)变换器、反激型(flyback)变换器和降压-升压型(buck-boost)变换器。
在本实施例中，功率电路201通过降压拓扑结构实现，包括功率开关Mx以及外围的电感元件Lx和整流二极管D1。其中，功率开关Mx的第一端与输入电压Vin连接，第二端与整流二极管D1的阳极连接， 整流二极管D1的阴极接地，功率开关Mx和整流二极管D1的公共端形成一开关节点SW，电感元件Lx的第一端与该开关节点连接，第二端与输出电压Vout连接。其中，功率开关Mx可以是任何可控半导体开关器件，例如金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)等。
应当指出，尽管在本实施例中将MOSFET用于开关元件，在不偏离本发明原理的前提下，可以使用任何其他类型的合适开关元件。此外，本实施例虽然以非同步降压变换器进行说明，但是，本发明不以此为限制，本发明同样适用于同步降压变换器，本领域技术人员也可以采用同步整流开关元件代替上述实施例中的整流二极管D1。
I2C接口电路202与芯片的串行时钟(SCL)引脚和串行数据(SDA)引脚连接，主要负责与主控制器的I2C控制器进行通信，传递主控制器设置的调整参数。
逻辑控制电路204接收从I2C接口电路202输入来的调整参数，将其转换为开关控制器205可实现的参数信息。该模块可被外部主机控制使能。其中，逻辑控制电路204可以使用DAC将输入的调整参数转换为电平信号，或者转换为占空比可调的脉冲信号，从而控制开关控制器205。当然，本发明的逻辑控制电路204不局限于上述的方式。
开关控制器205是电源管理芯片的主要控制部分，通过功率开关Mx实现控制电源支路的通断，从而实现输出不同的电压值。具体的，开关控制器205与芯片的反馈信号FB连接，用于根据反馈信号得到输出电压Vout的分压信号，并根据该分压信号调整功率开关Mx的开关，来稳定输出电压Vout。在一些实施例中，通过外部的电阻R1和R2构成的分压网络获得输出电压Vout的分压值。此外，本发明中的开关控制器可以包括脉冲宽度调制(PWM)、脉冲频率调制(PFM)或者调宽调频(PWM-PFM)等控制器。
驱动电路206用于根据开关控制器205输出的开关信号产生功率开关Mx的驱动信号并施加到功率开关Mx的栅极，以控制功率开关Mx的导通和关断。
为了解决现有技术中因功率开关Mx的开关噪声而造成的I2C接口电路的误触发或漏触发问题，本发明实施例的电源管理芯片200还包括基于第一调整信号CTR1来切换驱动电路206的驱动速度或者基于第二调整信号CTR2来调整I2C接口电路的供电电压，以提高I2C接口电路的通讯稳定性，同时平衡了DC/DC变换器的效率问题。
在一种实施例中，第一调整信号CTR1和第二调整信号CTR2可以通过芯片外部的trim(修调)方式得到。在另外一种实施例中，也可以通过逻辑控制电路204在I2C接口电路201的通讯出现干扰时生成第一调整信号CTR1和/或第二调整信号CTR2，第一调整信号CTR1用于调节驱动电路206的驱动速度，第二调整信号CTR2用于调节I2C接口电路201的供电电压，从而可以在I2C通讯出现干扰时，降低变换器的驱动速度，甚至提高I2C接口电路201的供电电压，以达到提高通讯准确率的目的。当I2C接口电路201的供电电压无法调整时，逻辑控制电路204还可以通过调整驱动电路206的驱动速度来适应I2C接口的通讯准确率，因此，本发明实施例的电源管理芯片200能够根据实际应用，对相应功能进行优化和平衡。
图5示出了根据本发明实施例的电源管理芯片中的驱动电路的电路示意图。本实施例的驱动电路206采用若干个图腾柱电路来驱动功率开关Mx。如图5所示，驱动电路206包括由多个级联的图腾柱电路实现的缓冲器261、第一图腾柱电路262和第二图腾柱电路263。
其中，所述缓冲器261的输入端与来自图4中的开关控制器205的开关信号DRV连接，并将输出信号施加到第一图腾柱电路262和第二图腾柱电路263的输入端，第一图腾柱电路262和第二图腾柱电路263并联连接在电压VSW+ΔV与开关节点VSW之间，其输出端与功率开关Mx的栅极连接，用于对功率开关Mx的栅极进行充放电，以导通或关断所述功率开关Mx。
具体的，第一图腾柱电路262包括晶体管M11和M12，第二图腾柱电路263包括晶体管M13和M14，晶体管M11和M13例如为P沟道晶体管，晶体管M12和M14例如为N沟道晶体管，晶体管M11和M12 的栅极与缓冲器261的输出连接，晶体管M11的源极与电压VSW+ΔV连接，漏极与晶体管M12的漏极以及功率开关Mx的栅极连接，晶体管M12的源极与开关节点VSW连接。晶体管M13的源极与电压VSW+ΔV连接，漏极与晶体管M14的漏极以及功率开关Mx的栅极连接。晶体管M11和M12互补导通，晶体管M13和M14互补导通，且晶体管M11和M13用于在导通时向功率开关Mx的栅极充电以导通功率开关Mx，晶体管M12和M14用于在导通时向功率开关Mx的栅极放电以关断功率开关Mx。在功率开关Mx的关断过程中，整流二极管D1为电感Lx续流，芯片内部地电压会被拉低，此时会对芯片的I2C接口电路的地产生不容易被消除的噪声。
为了解决这一问题，本实施例的驱动电路206还包括驱动控制模块264。驱动控制模块264用于基于第一调整信号CTR1控制第二图腾柱电路263与缓冲器261之间的信号通路，以控制第二图腾柱电路263的开关，继而达到调节功率开关Mx的驱动速率的目的。
其中，第一调整信号CTR1可被使能为逻辑高电平或低电平。当第一调整信号CTR1为高电平时，第二图腾柱电路263开启，此时通过第一图腾柱电路262和第二图腾柱电路263一起来驱动功率开关Mx，此时功率开关Mx的开关速率较快，I2C接口电路中的噪声也较大。当第一调整信号CTR1为低电平时，第二图腾柱电路263关闭，此时仅通过第一图腾柱电路262来驱动功率开关Mx，由于此时经过前级buffer到功率开关Mx的时间常数较小，因此功率开关Mx的开关速率较慢，I2C接口电路中的噪声也较小。
具体的，本实施例的驱动控制模块264包括反相器INV1、开关301、开关302以及晶体管M15和M16。
其中，反相器INV1的输入端用于接收所述第一调整信号CTR1，输出端用于输出第一调整信号的反相信号。
开关301的输入端与所述缓冲器261的输出连接，输出端与所述晶体管M13的栅极连接。开关301的导通和关断受控于第一调整信号CTR1，且开关301在导通时接通缓冲器261与晶体管M13的栅极之间的信号通 路，开关301在关断时断开缓冲器261与晶体管M13的栅极之间的信号通路。开关301例如通过N沟道晶体管M17和P沟道晶体管M18并联实现，晶体管M17和M18的第一端相互连接作为开关301的输入端与缓冲器261的输出连接，晶体管M17和M18的第二端相互连接作为开关301的输出端与晶体管M13的栅极连接，晶体管M17的栅极与第一调整信号CTR1连接，晶体管M18的栅极与第一调整信号CTR1的反相信号连接。
晶体管M15为P沟道晶体管，其栅极与第一调整信号CTR1连接，源极与电压VSW+ΔV连接，漏极与晶体管M13的栅极连接。
开关302的输入端与所述缓冲器261的输出连接，输出端与所述晶体管M14的栅极连接。开关302的导通和关断受控于第一调整信号CTR1，且开关302在导通时接通缓冲器261与晶体管M14的栅极之间的信号通路，开关302在关断时断开缓冲器261与晶体管M14的栅极之间的信号通路。开关302例如通过N沟道晶体管M19和P沟道晶体管M20并联实现，晶体管M19和M20的第一端相互连接作为开关302的输入端与缓冲器261的输出连接，晶体管M19和M20的第二端相互连接作为开关302的输出端与晶体管M14的栅极连接，晶体管M19的栅极与第一调整信号CTR1连接，晶体管M20的栅极与第一调整信号CTR1的反相信号连接。
晶体管M16为N沟道晶体管，其栅极与第一调整信号CTR1的反相信号连接，源极与电压VSW连接，漏极与晶体管M14的栅极连接。
当第一调整信号CTR1为低电平时，开关301和302关断，缓冲器261与晶体管M13和M14的栅极之间的信号通路被断开，同时晶体管M15和M16导通，分别将晶体管M13的栅极上拉至电压VSW+ΔV，以及将晶体管M14的栅极下拉至电压VSW，从而将晶体管M13和M14关断。当第一调整信号CTR1为高电平时，开关301和302导通，晶体管M15和M16关断，晶体管M13和M14分别根据缓冲器261的输出互补导通，参与到对功率开关Mx的驱动过程中。
由上面的描述可知，本实施例的电源管理芯片可通过降低功率开关 的开关速率来减小I2C接口电路中产生的噪声，但是驱动速率的降低会导致功率开关在导通和关断过程中产生能量消耗继而损失电源的转换效率。
图6示出了根据本发明实施例的电源管理芯片中的I2C接口电路的电路示意图。如图6所示，本实施例的I2C接口电路202包括供电电压产生模块221、触发器模块222和输出缓冲器223。其中，供电电压产生模块221用于根据电源电压VDD产生触发器模块222的供电电压VDIO，输出缓冲器223由电源电压VDD直接供电。
供电电压产生模块221包括电流源I1和I2、反相器INV2、电阻R12以及晶体管M21至M24。其中，晶体管M21至M24为N沟道晶体管，电流源I1的第一端与电源电压VDD连接，第二端与晶体管M21的栅极和漏极连接，晶体管M21的源极与晶体管M22的漏极和栅极连接，晶体管M22的源极与电阻R12的第一端，电阻R12的第二端与地电压Vss连接。反相器INV2的输入端与第二调整信号CTR2连接，输出端与晶体管M23的栅极连接，晶体管M23的漏极与晶体管M22的漏极连接，晶体管M23的源极与晶体管M22的源极连接。晶体管M24的漏极与电源电压VDD连接，栅极与电流源I1和晶体管M21之间的公共节点连接，源极用于输出供电电压VDIO，电流源I2连接于晶体管M24的源极和地电压Vss之间。
当第二调整信号CTR2为低电平时，晶体管M23导通，从而将晶体管M22短路，根据公式VDIO＝I1×R12+Vth_M21-Vth_M24，其中Vth_M21和Vth_M24分别为晶体管M21和M24的导通阈值，可以计算得到供电电压VDIO的第一电压值，例如1.2V。当第二调整信号CTR2为高电平时，晶体管M23关断，根据公式VDIO＝I1×R12+Vth_M21+Vth_M22-Vth_M24，其中Vth_M22为晶体管M22的导通阈值，可以计算得到供电电压VDIO的第二电压值，例如1.8V。根据I2C通讯协议可知，增大供电电压的电压值可以使得触发器模块222的逻辑输入信号的变换范围更宽，即使芯片内部地和外部地之间的压差比较大，也能保证触发器模块222更加容易识别到SDA和SCL信号的翻转。
进一步的，触发器模块222例如通过施密特触发器实现，包括输入端111，它用于接收逻辑输入信号SCL_in，并将该逻辑输入信号SCL_in耦合到晶体管M1～M4的栅极，晶体管M1～M4依次连接于供电电压VDIO和地电压Vss之间，其中供电电压VDIO为内部专为接口电路设计的I/O电压，地电压Vss为芯片内部的噪声地。反相器112的输入端与晶体管M2和M3的漏极连接于节点p1，输出端与输出缓冲器223中的晶体管M7的栅极连接，反相器113的输入端与反相器112的输出端连接，输出端与输出缓冲器223中的晶体管M8的栅极连接。输出缓冲器223用于对反相器112和113的输出信号进行整形以得到逻辑输出信号SCL_out。晶体管M5的源极与晶体管M1的漏极以及晶体管M2的源极连接，漏极与地电压Vss连接，晶体管M6的源极与晶体管M3的源极以及晶体管M4的漏极连接，漏极与供电电压VDIO连接，晶体管M5和M6的栅极与反相器113的输出端连接于节点p2。
输出缓冲器223还包括晶体管M9和M10，晶体管M9和M10的源极与电源电压VDD连接，晶体管M9的栅极与晶体管M10的漏极连接，晶体管M10的栅极与晶体管M9的漏极连接，晶体管M9和M10的漏极还分别与晶体管M7和M8的漏极连接，晶体管M7和M8的源极与地电压Vss连接，晶体管M8的漏极还与逻辑输出信号SCL_out的输出端连接。
其中，晶体管M1、M2、M5、M9和M10为P沟道晶体管，晶体管M3、M4、M6、M7和M8为N沟道晶体管，当逻辑输入信号SCL_in为低电平时，晶体管M1、M2、M6导通，晶体管M3～M5关断，节点p1和p2的电压约等于供电电压VDIO，继而晶体管M8被导通，将逻辑输出信号SCL_out拉低到地电压Vss。当逻辑输入信号SCL_in由低电平跳变为高电平时，当逻辑输入信号SCL_in的电压大于晶体管M4的导通阈值时，先把晶体管M4导通，接着把晶体管M3导通，随后晶体管M1和M2被关断，节点p1和p2被拉低到Vss，晶体管M8关断，逻辑输出信号SCL_out被拉高到电源VDD，最终实现逻辑输出信号SCL_out从低电平到高电平的跳变。同理，该电路还能够产生逻辑输出信号SCL_out 从高电平到低电平的跳变，实现了外部电源轨的逻辑信号(即Host Control)与内部电源轨的逻辑信号之间的电平转换。
综上所述，本发明提供的电源管理芯片包括I2C接口电路，并且可以在I2C接口电路的通讯出现干扰时提供第一调整信号和/或第二调整信号，以调节驱动电路的驱动速率和/或调节I2C接口电路的供电电压，从而可以在芯片的I2C通讯出现干扰时，降低变换器的驱动速度，甚至提高I2C接口电路的供电电压，达到提高通讯准确率的目的。此外，本发明的电源管理芯片还可以根据实际应用对相应功能进行优化和平衡，从而在提高通讯准确率的同时平衡变换器的效率。
应当说明，尽管在本文中，将器件说明为某种N沟道或P沟道器件、或者某种N型或者P型掺杂区域，然而本领域的普通技术人员可以理解，根据本发明，互补器件也是可以实现的。本领域的普通技术人员可以理解，导电类型是指导电发生的机制，例如通过空穴或者电子导电，因此导电类型不涉及掺杂浓度而涉及掺杂类型，例如P型或者N型。本领域普通技术人员可以理解，本文中使用的与电路运行相关的词语“期间”、“当”和“当……时”不是表示在启动动作开始时立即发生的动作的严格术语，而是在其与启动动作所发起的反应动作(reaction)之间可能存在一些小的但是合理的一个或多个延迟，例如各种传输延迟等。本文中使用词语“大约”或者“基本上”意指要素值(element)具有预期接近所声明的值或位置的参数。然而，如本领域所周知的，总是存在微小的偏差使得该值或位置难以严格为所声明的值。本领域已恰当的确定了，至少百分之十(10％)(对于半导体掺杂浓度，至少百分之二十(20％))的偏差是偏离所描述的准确的理想目标的合理偏差。当结合信号状态使用时，信号的实际电压值或逻辑状态(例如“1”或“0”)取决于使用正逻辑还是负逻辑。
此外，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他 性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (13)

  1. 一种电源管理芯片，包括：
    I2C接口电路，与芯片的逻辑引脚连接，用于与外部的主控制器进行通信，以传递所述主控制器设置的调整参数；以及
    驱动电路，用于将开关信号转换成驱动信号并施加到所述电源管理芯片中的功率开关的控制端，通过控制所述功率开关的导通和关断来调节所述电源管理芯片的输入端至输出端的电能传输，以提供稳定的输出电压，所述开关信号基于所述调整参数获得，
    其中，所述驱动电路的驱动速率和/或所述I2C接口电路的供电电压可以被调节。
  2. 根据权利要求1所述的电源管理芯片，其中，所述驱动电路包括：
    缓冲器，其输入端用于接收所述开关信号；
    并联的第一图腾柱电路和第二图腾柱电路，所述第一图腾柱电路和所述第二图腾柱电路用于基于所述缓冲器的输出对所述功率开关的控制端进行充放电；以及
    驱动控制模块，用于接收第一调整信号，并基于所述第一调整信号控制所述第二图腾柱电路与所述缓冲器之间的信号通路，通过控制所述第二图腾柱电路的开启和关闭来调节所述驱动电路的驱动速率。
  3. 根据权利要求1所述的电源管理芯片，其中，所述I2C接口电路包括：
    供电电压产生模块，用于向触发器模块提供供电电压，所述供电电压产生模块还用于接收第二调整信号，并根据所述第二调整信号调节所述供电电压的电压值；
    所述触发器模块，用于从芯片的逻辑引脚接收逻辑输入信号，用于将所述逻辑输入信号与阈值电压进行比较，以生成第一信号；以及
    输出缓冲器，用于对所述第一信号整形以得到逻辑输出信号。
  4. 根据权利要求2所述的电源管理芯片，其中，所述第二图腾柱电路包括：
    连接于第一电压和第二电压之间的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的控制端与所述驱动控制模块的输出连接，所述第一晶体管和所述第二晶体管的中间节点与所述功率开关的控制端连接。
  5. 根据权利要求4所述的电源管理芯片，其中，所述驱动控制模块包括：
    第一开关，连接于所述缓冲器的输出与所述第一晶体管的控制端之间；以及
    第二开关，连接于所述缓冲器的输出与所述第二晶体管的控制端之间，
    其中，所述第一调整信号通过控制所述第一开关和所述第二开关的导通和关断来控制所述缓冲器与所述第二图腾柱电路之间的信号通路。
  6. 根据权利要求5所述的电源管理芯片，其中，所述驱动控制模块还包括：
    第三晶体管，其第一端与所述第一电压连接，第二端与所述第一晶体管的控制端连接，控制端与所述第一调整信号连接；以及
    第四晶体管，其第一端与所述第二晶体管的控制端连接，第二端与所述第二电压连接，控制端与所述第一调整信号的反相信号连接。
  7. 根据权利要求6所述的电源管理芯片，其中，当所述第一调整信号为高电平时，所述第一开关和所述第二开关导通，所述第三晶体管和所述第四晶体管关断，所述第一晶体管和所述第二晶体管根据所述缓冲器的输出非交叠导通，
    当所述第一调整信号为低电平时，所述第一开关和所述第二开关关断，所述第三晶体管和所述第四晶体管导通，将所述第一晶体管和所述第二晶体管关断。
  8. 根据权利要求6所述的电源管理芯片，其中，所述第一晶体管和所述第三晶体管为P沟道晶体管，所述第二晶体管和所述第四晶体管为N沟道晶体管。
  9. 根据权利要求3所述的电源管理芯片，其中，所述供电电压产生 模块包括：
    依次连接于电源电压和地电压之间的第一电流源、第五晶体管、第六晶体管和第一电阻，所述第五晶体管和所述第六晶体管分别连接成MOS二极管；
    依次连接于所述电源电压和地电压之间的第七晶体管和第二电流源，所述第七晶体管的控制端与所述第一电流源的第二端连接，所述第七晶体管的第二端用于输出所述供电电压；
    反相器，所述反相器的输入端用于接收所述第二调整信号；以及
    与所述第六晶体管并联的第八晶体管，所述第八晶体管的控制端与所述反相器的输出端连接。
  10. 根据权利要求3所述的电源管理芯片，其中，所述触发器模块为施密特触发器。
  11. 根据权利要求9所述的电源管理芯片，其中，所述地电压为所述芯片内部的噪声地。
  12. 根据权利要求1所述的电源管理芯片，其中，还包括：
    功率电路，包括至少一个所述功率开关以及电感元件，所述功率开关用来调节所述电源管理芯片输入端至输出端的电能传输，以提供稳定的输出电压；
    逻辑控制电路，用于接收所述I2C接口电路输入的所述调整参数，并将其转换为开关控制器可实现的参数信息；以及
    所述开关控制器，用于根据所述参数信息产生相应的所述开关信号。
  13. 根据权利要求12所述的电源管理芯片，其中，所述驱动电路的驱动速率和/或所述I2C接口电路的供电电压的调整信号可以来自芯片外部的修调信号或者来自所述逻辑控制电路。
PCT/CN2023/089245 2022-07-25 2023-04-19 一种电源管理芯片 WO2024021695A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101355764A (zh) * 2008-09-12 2009-01-28 中兴通讯股份有限公司 移动终端中向多卡提供可变电源的装置及其方法
CN102118516A (zh) * 2011-01-13 2011-07-06 中兴通讯股份有限公司 电源管理芯片输出电压的控制方法和系统
CN102290978A (zh) * 2011-08-04 2011-12-21 无锡中星微电子有限公司 电源管理系统
JP2012151202A (ja) * 2011-01-18 2012-08-09 Renesas Electronics Corp 半導体集積回路装置
CN104167778A (zh) * 2014-07-24 2014-11-26 深圳天珑无线科技有限公司 一种供电电路
CN115296530A (zh) * 2022-07-25 2022-11-04 圣邦微电子（北京）股份有限公司 一种电源管理芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101355764A (zh) * 2008-09-12 2009-01-28 中兴通讯股份有限公司 移动终端中向多卡提供可变电源的装置及其方法
CN102118516A (zh) * 2011-01-13 2011-07-06 中兴通讯股份有限公司 电源管理芯片输出电压的控制方法和系统
JP2012151202A (ja) * 2011-01-18 2012-08-09 Renesas Electronics Corp 半導体集積回路装置
CN102290978A (zh) * 2011-08-04 2011-12-21 无锡中星微电子有限公司 电源管理系统
CN104167778A (zh) * 2014-07-24 2014-11-26 深圳天珑无线科技有限公司 一种供电电路
CN115296530A (zh) * 2022-07-25 2022-11-04 圣邦微电子（北京）股份有限公司 一种电源管理芯片

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