WO2014080874A1 - 複合基板の製造方法及び複合基板 - Google Patents
複合基板の製造方法及び複合基板 Download PDFInfo
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- WO2014080874A1 WO2014080874A1 PCT/JP2013/081091 JP2013081091W WO2014080874A1 WO 2014080874 A1 WO2014080874 A1 WO 2014080874A1 JP 2013081091 W JP2013081091 W JP 2013081091W WO 2014080874 A1 WO2014080874 A1 WO 2014080874A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Definitions
- the present invention relates to a method of manufacturing a composite substrate using a method of bonding a support substrate and a semiconductor substrate through an insulating film, and a composite substrate obtained by the manufacturing method.
- III-V group semiconductors such as GaN and wide gap semiconductors such as SiC are being studied for application to light-emitting elements, high-voltage devices, and RF devices depending on the physical properties of the materials themselves.
- the defect is a problem.
- it is more advantageous in terms of the number of defects to use a single crystal bulk material than to grow a thin film by heteroepi or the like.
- ions of hydrogen and rare gases are implanted as used in the manufacture of silicon on insulator (SOI) and silicon on sapphire (SOS).
- the silicon wafer After bonding the bonded silicon wafer (Si wafer) to the support substrate of the silicon wafer or sapphire wafer, the silicon wafer is embrittled in the ion implantation region by heat treatment and then ion-implanted by heat or mechanical means. According to the manufacturing method based on the ion implantation separation method in which the Si thin film is transferred to the support substrate after being peeled off in the region, cost reduction by reusing the transferred wafer can be expected.
- an amorphous material such as SiO 2 or amorphous Si is formed on the substrate surface, and the formed surface is subjected to chemical mechanical polishing (CMP) or the like. Smoothing to a level at which direct bonding is possible has been studied (O. Moutanabbir et al., Journal of Electronic Materials 39 (5), 482-488 (2010) (Non-Patent Document 1)).
- vapor deposition methods such as PECVD (plasma-enhanced chemical vapor deposition) and LPCVD (low pressure chemical vapor deposition) are generally used for the film formation of SiO 2 and amorphous Si. Since an expensive apparatus is used, there is a problem that costs are high.
- the surface roughness after film formation is large, it is necessary to perform a polishing process before bonding, and there is a problem that the number of processes increases.
- spin-on-glass As a method for forming a film without requiring cost, a method of providing a spin-on-glass (SOG) layer on a rough surface or a surface with unevenness is conceivable.
- spin-on-glass include BPSG (Boron Phosphorus Silicon Glass), water glass, and the like, but these contain impurities such as B, P, Na, etc., so SOI, SOS, or SiC It is difficult to use as a bonding layer for electronic devices using GaN or GaN.
- a film converted from polysilazane to SiO 2 has few impurities and has a good embedding property in a concavo-convex pattern.
- a polysilazane solution is applied and converted to SiO 2 by heat treatment (firing treatment).
- a film converted from polysilazane to SiO 2 has few impurities and has a good embedding property in a concavo-convex pattern.
- Patent Document 1 Japanese Patent Laid-Open No. 2005-45230
- Patent Document 2 organic Application of a TFT to a gate insulating layer
- the SiO 2 film is formed at a low temperature of about 450 ° C. at the maximum, and there is concern about the influence of components and functional groups other than SiO 2 contained in the film when used as a bonding layer for electronic devices. Is done.
- Patent Document 3 As an example of using a polysilazane baked film in bonding the substrate, SiO 2 turned into the polysilazane to a surface with a concavo-convex pattern was baked by slit coating, there is an example in which bonded to the Si wafer (Patent No. 4,728,030 discloses ( Patent Document 3)).
- the substrate when bonding is performed using a substrate having a height difference of 500 nm, the substrate is slit coated, converted to SiO 2 by heating at 350 ° C., smoothed by CMP, and then subjected to hydrogen ions.
- the wafer is bonded to the implanted Si substrate, and the Si thin film is transferred by peeling in the ion implantation region to form a desired wafer structure. That is, the polishing process for smoothing is an essential process.
- an amorphous material is formed by a CVD method as a means for providing a smooth bonding layer on a substrate surface having a large surface roughness.
- an expensive apparatus is required for film formation. Since it is necessary to perform polishing for smoothing, there is a problem that costs are high.
- a simple method other than the CVD method for example, using SOG for the bonding surface of the semiconductor device layer has hardly been studied. Most of the methods using polysilazane as SOG have been studied for the purpose of converting to SiO 2 at a low temperature. For example, application to a bonding surface to be a buried oxide film layer of SOI has hardly been studied.
- the present invention has been made in view of the above circumstances, and an object thereof is to provide a composite substrate manufacturing method and a composite substrate in which a composite substrate can be easily obtained by suppressing poor bonding due to surface roughness and defects of a support substrate. To do.
- the inventors of the present invention formed a coating film containing polysilazane and performed a baking treatment at a heating temperature of 600 ° C. or more and 1200 ° C. or less in an atmosphere containing oxygen, thereby forming silicon. It has been found that a SiO 2 insulating film (SOG) having a breakdown voltage comparable to that of a thermal oxide film can be obtained.
- SOG SiO 2 insulating film
- SiO 2 film using polysilazane is excellent in smoothing such step coverage property, by using the SiO 2 film was converted by the temperature, without polishing the surface, the thickness at the time of firing process It has been found that they can be bonded together as they are, have superior insulating properties by a simple method compared to the CVD method, and can be bonded without polishing.
- the SiN insulating film can be formed by setting the atmosphere of the baking treatment to an inert atmosphere containing nitrogen or under vacuum, and in this case, the thickness of the baking treatment can be reduced without polishing the insulating film. It was confirmed that pasting was possible. The present inventors have conducted intensive studies based on these findings and have come to achieve the present invention.
- the present invention provides the following composite substrate manufacturing method and composite substrate.
- a method for manufacturing a composite substrate in which a semiconductor substrate and a support substrate are bonded together, and then the semiconductor substrate is thinned to obtain a composite substrate having a semiconductor layer on the support substrate.
- a coating film containing polysilazane is formed on at least one of the surfaces to be bonded together, and a silicon-containing insulating film is formed by performing a baking treatment in which the coating film is heated to 600 ° C. or more and 1200 ° C. or less.
- [2] The method for producing a composite substrate according to [1], wherein the polysilazane is perhydropolysilazane.
- [3] The method for producing a composite substrate according to [1] or [2], wherein the baking treatment is performed in an atmosphere containing oxygen and / or water vapor.
- [4] The method for producing a composite substrate according to [1] or [2], wherein the baking treatment is performed under an inert atmosphere containing nitrogen or under reduced pressure.
- [5] The method for manufacturing a composite substrate according to any one of [1] to [4], wherein the semiconductor substrate and the support substrate are bonded together while the insulating film is kept in the thickness at the time of baking.
- Ions are implanted from the surface of the semiconductor substrate to form an ion implantation region, the silicon-containing insulating film is formed on a surface to which the support substrate is bonded, and the surface of the semiconductor substrate into which ions are implanted.
- a method of manufacturing a composite substrate [7] A composite substrate produced by the method for producing a composite substrate according to any one of [1] to [6].
- the present invention by forming a coating film containing polysilazane, it is possible to easily form an insulating film that has good insulating properties and can be bonded, and an electronic device in which an insulating film and a semiconductor layer are laminated on a support substrate A composite substrate suitable for the application can be manufactured. Further, even if the substrate has a rough surface, the insulating film can reduce the roughness of the surface, and the insulating film can be bonded to the insulating film without changing the thickness at the time of baking.
- FIG. 1 It is the schematic which shows an example of the manufacturing process in the manufacturing method of the composite substrate which concerns on this invention, (a) is sectional drawing of the semiconductor substrate ion-implanted, (b) is the support which formed the coating film containing perhydropolysilazane. Sectional view of substrate, (c) is a sectional view of a support substrate on which an insulating film is formed by baking treatment, (d) is a sectional view showing a state in which the semiconductor substrate and the supporting substrate are bonded together, (e) is an ion implantation region Sectional drawing which shows the state which peeled the semiconductor substrate, (f) is sectional drawing of a composite substrate.
- FIG. 4 is a graph showing the results of infrared absorption spectrum analysis of SiO 2 films on a support substrate in Examples 1 to 3 and Comparative Example 1. It is a front view which shows the position which performs the insulation tolerance evaluation on a wafer. It is a figure which shows the evaluation result of the insulation tolerance of Example 1. FIG. It is a figure which shows the evaluation result of the insulation tolerance of the comparative example 1. It is a figure which shows the evaluation result of the insulation tolerance of the comparative example 2.
- a method for manufacturing a composite substrate according to the present invention includes a step of implanting hydrogen ions (rare gas ions) into a semiconductor substrate (step 1), a step of forming an insulating film (step 2), a semiconductor substrate and / or
- the support substrate surface activation treatment process (process 3), the semiconductor substrate and support substrate bonding process (process 4), the peeling process process (process 5), and the damage layer removal process (process 6) are performed in this order. is there.
- Step 1 Hydrogen ion (rare gas ion) implantation step into the semiconductor substrate
- hydrogen ions or rare gas that is, helium, neon, argon, krypton, xenon, radon
- the present invention is not limited to this, and the semiconductor substrate may be silicon-germanium (SiGe), carbonized. It is preferable to use a material made of any material selected from the group consisting of silicon (SiC), aluminum nitride (AlN), germanium (Ge), gallium nitride (GaN), zinc oxide (ZnO), and gallium arsenide (GaAs). it can. Alternatively, a substrate having a single crystal semiconductor layer on a bonding surface, such as an SOI substrate, can be used.
- the single crystal silicon substrate (hereinafter also referred to as a silicon substrate) which is the semiconductor substrate 1 is not particularly limited, but is obtained by slicing a single crystal grown by the Czochralski (CZ) method, for example.
- CZ Czochralski
- those having a diameter of 100 to 300 mm, a conductivity type of P type or N type, and a resistivity of about 10 ⁇ ⁇ cm can be mentioned.
- the formation method of the ion implantation region 2 is not particularly limited, and for example, a predetermined dose of hydrogen ions or rare gas ions with an implantation energy capable of forming the ion implantation region 2 at a desired depth from the surface of the semiconductor substrate 1.
- the implantation energy can be 50 to 100 keV
- the implantation dose can be 2 ⁇ 10 16 to 5 ⁇ 10 17 / cm 2 .
- Hydrogen ions to be implanted are hydrogen ions (H + ) having a dose of 2 ⁇ 10 16 to 5 ⁇ 10 17 (atoms / cm 2 ), or 1 ⁇ 10 16 to 2.5 ⁇ 10 17 (atoms / cm 2).
- H 2 + hydrogen molecular ion 2
- the depth from the ion-implanted substrate surface to the ion-implanted region 2 corresponds to the desired thickness of the semiconductor layer (silicon thin film) provided on the support substrate 3.
- the thickness is preferably 300 to 500 nm, more preferably about 400 nm.
- the thickness of the ion implantation region 2 (that is, the ion distribution thickness) is such that it can be easily peeled off by mechanical impact or the like, and is preferably about 200 to 400 nm, more preferably about 300 nm.
- the silicon-containing insulating film 4 is formed on one or both of the surfaces on which the semiconductor substrate 1 and the support substrate 3 to be described later are bonded.
- the case where the insulating film 4 is formed on the bonding surface of the support substrate 3 will be described (FIGS. 1B and 1C).
- a coating film 4a containing polysilazane is formed on the support substrate 3 (FIG. 1B).
- the support substrate 3 single crystal substrates such as silicon, sapphire, SiC, GaAs, GaN, ZnO, amorphous substrates such as synthetic quartz and multicomponent glass, p-Si, SiC, Si 3 N 4 , Al 2 O 3
- a polycrystalline substrate such as AlN can be used.
- the coating composition used for forming the coating film 4a containing polysilazane contains polysilazane and a solvent.
- polysilazane perhydropolysilazane represented by the general formula — (SiH 2 NH) n ⁇ is preferable because there are few impurities remaining in the insulating film after conversion.
- Perhydropolysilazane is an inorganic polymer having — (SiH 2 NH) — as a basic unit, all of its side chains being hydrogen, and being soluble in an organic solvent.
- the solvent may be any solvent that does not react with perhydropolysilazane.
- Aromatic solvents such as hexane, aliphatic solvents, and ether solvents.
- the concentration of polysilazane in the solvent is preferably 1 to 30% by mass, more preferably 3 to 20% by mass. If the amount is less than 1% by mass, the film thickness after coating becomes thin and the effect of improving the surface roughness of the support substrate 3 may be insufficient. If the amount exceeds 30% by mass, the stability of the solution may decrease.
- the coating composition As a coating method of the coating composition, known methods such as spray coating, spin coating, dip coating, roll coating, screen printing, and slit coating can be used.
- the thickness to be applied is determined by the roughness of the surface of the substrate to be applied, the level of the step, and the thickness of the buried layer required as a semiconductor device, but the thickness as the insulating film 4 after firing is 10 nm to 10 ⁇ m. Is preferred. When it is not formed by one application, the application may be repeated. After coating, the solvent is removed, and the coating film 4a is dried at about 50 to 200 ° C. for 1 minute to 2 hours.
- the coating film 4a is baked by heating at 600 ° C. or more and 1200 ° C. or less, and the polysilazane of the coating film 4a is converted into SiO 2 or SiN to form the insulating film 4 (FIG. 1 (c)).
- a baking treatment is performed at a heating temperature of 600 ° C. or higher and 1200 ° C. or lower, preferably 800 ° C. or higher and 1000 ° C. or lower, in an atmosphere containing oxygen and / or water vapor.
- the heating temperature is less than 600 ° C., for example, when the treatment is performed at 450 ° C., the polysilazane skeleton is converted into a siloxane skeleton, but silanol groups remain, and the leakage current becomes higher as the insulation resistance than the thermal oxide film of silicon.
- the higher the heating temperature the more the surface roughness of the insulating film 4 tends to be improved. However, if it exceeds 1200 ° C., SiO 2 will be decomposed.
- a baking treatment is performed at a heating temperature of 600 ° C. or higher and 1200 ° C. or lower, preferably 800 ° C. or higher and 1000 ° C. or lower, under an inert atmosphere containing nitrogen or under reduced pressure. If the heating temperature is less than 600 ° C., the conversion to SiN does not proceed. In addition, the higher the heating temperature, the more the surface roughness of the insulating film 4 tends to be improved. However, when the heating temperature exceeds 1200 ° C., SiN is decomposed.
- Calcination treatment time is preferably 10 seconds to 12 hours, more preferably 1 minute to 1 hour. If the treatment time is shorter than 10 seconds, the conversion reaction from polysilazane may be insufficient, and if it is longer than 12 hours, the firing treatment cost may increase.
- the insulating film 4 can be formed on the surface to which the support substrate 3 is bonded (FIG. 1C).
- the thickness of the insulating film 4 is preferably 10 nm to 10 ⁇ m, more preferably 20 nm to 5 ⁇ m. If the thickness is less than 10 nm, the effect of improving the surface roughness of the support substrate 3 may be insufficient, and if it exceeds 10 ⁇ m, it may be unsuitable as a buried layer in a semiconductor device.
- This insulating film 4 has an insulation resistance comparable to that of a conventional silicon thermal oxide film.
- the surface of the insulating film 4 is smoothed to such an extent that it can be bonded without changing the thickness of the baking process without polishing the surface of the insulating film 4.
- the support substrate 3 is made of a GaN wafer, a SiC wafer, or a polycrystalline material, and the surface is rough to the extent that it is difficult to bond the next process as it is, by forming this insulating film 4, The surface roughness is improved, and the surface of the insulating film 4 is smoothed to the extent that it can be bonded without changing the surface of the insulating film 4 while maintaining the thickness during the baking treatment.
- the insulating film 4 with the thickness at the time of the baking treatment means that a treatment for changing the roughness of the surface such as polishing or etching is not performed, and a surface activation treatment described later is allowed.
- the surface roughness Rms of the insulating film 4 with the thickness at the time of the baking treatment is preferably 1.0 nm or less, and more preferably 0.8 nm or less.
- Rms (Root-mean-square) is the root mean square roughness obtained as the square root of the mean of the square value of the deviation from the arithmetic mean value of the cross-sectional profile at the reference length, according to JIS B0601: 2013.
- the root mean square roughness Rq to be defined (hereinafter the same).
- Step 3 Surface activation treatment step of semiconductor substrate and / or support substrate
- a surface activation process is performed on both or one of the ion-implanted surface of the semiconductor substrate 1 and the surface of the insulating film 4 on the support substrate 3.
- activation is achieved by exposing highly reactive dangling bonds (dangling bonds) to the substrate surface, or by adding OH groups to the dangling bonds. It is performed by processing or processing by ion beam irradiation.
- the surface is exposed to high-frequency plasma of about 100 W for about 5 to 10 seconds.
- Plasma treatment As the plasma gas, when processing the semiconductor substrate 1, the surface is oxidized with oxygen gas plasma, and when not oxidized, hydrogen gas, argon gas, or a mixed gas thereof or a mixture of hydrogen gas and helium gas is used. Gas etc. can be mentioned.
- hydrogen gas, argon gas, a mixed gas thereof, a mixed gas of hydrogen gas and helium gas, or the like is used.
- organic substances on the surface of the semiconductor substrate 1 are oxidized and removed, and OH groups on the surface are further increased and activated. Further, impurities on the surface of the support substrate 3 (insulating film 4) are removed and activated.
- the treatment by ion beam irradiation is a treatment in which the surface is sputtered by irradiating the semiconductor substrate 1 and / or the support substrate 3 (insulating film 4) with an ion beam using a gas used in plasma treatment. It is possible to expose the bond and increase the bonding force.
- heat is applied to the bonded substrate 5 to perform heat treatment (second heat treatment).
- second heat treatment heat treatment
- the bond between the semiconductor substrate 1 and the support substrate through the insulating film 4 is strengthened.
- a temperature at which the bonded substrate 5 is not damaged by the influence (thermal stress) of the difference in thermal expansion coefficient between the semiconductor substrate 1 and the support substrate 3 is selected.
- the heat treatment temperature is preferably 300 ° C. or lower, more preferably 150 to 250 ° C., and further preferably 150 to 200 ° C.
- the heat treatment time is, for example, 1 to 24 hours.
- Process 5 Peeling process
- thermal energy, mechanical energy, or optical energy is applied to the ion-implanted portion of the bonded substrate 5 so as to be separated along the ion-implanted region 2, and a part of the semiconductor substrate 1 is used as the semiconductor layer 6.
- the wafer 7 is transferred to the support substrate 3 side (FIG. 1E). That is, a semiconductor thin film bonded to the support substrate 3 through the insulating film 4 is peeled from the semiconductor substrate 1 to form a semiconductor layer (silicon layer) 6.
- the peeling is preferably performed by cleaving from one end to the other end of the bonded substrate 5 along the ion implantation region 2.
- heating is preferably performed at 200 ° C. or more, more preferably 250 to 350 ° C., and thermal energy is applied to the ion-implanted portion to generate minute bubble bodies in the ion-implanted portion. Since the method to be performed and the ion-implanted portion are embrittled by the heat treatment, a pressure that does not damage a wafer of, for example, 1 MPa or more and 5 MPa or less is appropriately selected in this embrittled portion, and a fluid such as gas or liquid is selected. A method of peeling by applying mechanical energy such as an impact force that blows a jet.
- the amorphous part is irradiated with light of a wavelength that is absorbed to absorb light energy.
- the ion-implanted damage layer is preferably removed by wet etching or dry etching.
- the wet etching such as KOH solution, NH 4 OH solution, NaOH solution, CsOH solution, ammonia water (28 mass%), hydrogen peroxide (30-35 wt%), SC-l solution consisting of water (balance) , EDP (ethylenediamine pyrocatechol) solution, TMAH (4-methyl ammonium hydroxide) solution, and hydrazine solution may be used.
- dry etching for example, reactive gas etching in which the semiconductor layer 6 on the support substrate 3 is exposed to etching in a fluorine-based gas or reactivity in which the fluorine-based gas is ionized and radicalized by plasma to etch the semiconductor layer 6 is etched.
- fluorine-based gas reactive gas etching in which the semiconductor layer 6 on the support substrate 3 is exposed to etching in a fluorine-based gas or reactivity in which the fluorine-based gas is ionized and radicalized by plasma to etch the semiconductor layer 6 is etched. Examples include ion etching.
- the region to be removed in this step is at least the entire ion-implanted damage layer of the semiconductor layer 6 related to crystal defects, and the thickness of the surface layer of the semiconductor layer 6 is preferably 120 nm or more, more preferably 150 nm or more. That's it.
- the thickness of the semiconductor layer 6 on the support substrate 3 is 100 to 400 nm.
- the surface of the semiconductor layer 6 on the support substrate 3 is mirror finished.
- the semiconductor layer 6 is subjected to chemical mechanical polishing (CMP polishing) and finished to a mirror surface.
- CMP polishing chemical mechanical polishing
- a conventionally known CMP polishing used for planarization of a silicon wafer or the like may be used.
- the CMP polishing may also serve as the removal of the ion implantation damage layer.
- a composite substrate 8 suitable for electronic device applications in which the insulating film 4 and the semiconductor layer 6 are laminated on the support substrate 3 can be manufactured (FIG. 1F).
- the method using the ion implantation separation method has been described.
- the method is not limited thereto, and examples thereof include grinding, lapping, polishing, and the like.
- the semiconductor substrate 1 may be thinned using a mechanical method, a chemical method such as etching, or a combination thereof.
- Example 1 A sample for evaluation was prepared and evaluated by the following procedure. First, a film converted from perhydropolysilazane to SiO 2 was formed on a support substrate of a Si wafer. Specifically, 2 mL of a solution containing 20% by mass of perhydropolysilazane in a solvent n-dibutyl ether (Sanwa Chemical's Tresmile, model number ANN120-20) is spin-coated on a 150 mm outer diameter Si wafer and heated at 150 ° C. for 3 minutes. The solvent was removed. Then, the resulting mixture was fired process heating 3 minutes at 600 ° C. in air, it was converted to the coating film to SiO 2 film.
- a solvent n-dibutyl ether Sanwa Chemical's Tresmile, model number ANN120-20
- the film thickness after the baking treatment was 200 nm.
- the change in film quality before and after the baking treatment was confirmed by an infrared absorption spectrum, and the surface roughness (Rms) of the SiO 2 film forming surface after the baking treatment was measured by an atomic force microscope (AFM).
- the dielectric breakdown voltage of the SiO 2 film at 10 points in the wafer surface was evaluated by an instantaneous dielectric breakdown method (Time Zero Dielectric Breakdown).
- the SiO 2 film formation surface of the support substrate and the ion implantation surface of the Si wafer into which hydrogen ions were implanted were bonded together, and a heat treatment for bonding was performed.
- hydrogen ions are implanted into the Si wafer at 57 keV and a dose amount of 6.0 ⁇ 10 16 atoms / cm 2 , and ion beam activation is performed on the ion implantation surface side and the SiO 2 film formation surface of the support substrate.
- the two were bonded together and further subjected to a heat treatment for bonding at 300 ° C. for 10 hours.
- the presence / absence of peeling and the occurrence of voids at the bonding interface after the heat treatment at 300 ° C. were observed and confirmed with an ultrasonic microscope.
- transfer of the Si single crystal thin film to the support substrate was performed by peeling the bonded substrate in the ion implantation region.
- the substrate onto which the Si single crystal thin film was transferred was subjected to a heat treatment at 1000 ° C. in an N 2 atmosphere, and the presence or absence of peeling from the bonding interface or the generation of voids was confirmed by observing with an ultrasonic microscope.
- Example 2 In Example 1, the firing temperature was changed to 800 ° C., and other than that, the transfer of the Si single crystal thin film to the support substrate was performed in the same manner as in Example 1. Moreover, the same evaluation as Example 1 was performed.
- Example 3 In Example 1, the firing temperature was changed to 1000 ° C., and otherwise, the transfer of the Si single crystal thin film to the support substrate was performed in the same manner as in Example 1. Moreover, the same evaluation as Example 1 was performed.
- Example 1 In Example 1, the firing temperature was changed to 450 ° C., and otherwise, the transfer of the Si single crystal thin film to the support substrate was performed in the same manner as in Example 1. Moreover, the same evaluation as Example 1 was performed.
- Example 2 a Si substrate having a SiO 2 film having a thickness of 200 nm formed by performing thermal oxidation at 1000 ° C. in an atmosphere containing oxygen is used for the support substrate. The single crystal thin film was transferred to the support substrate. Moreover, the same evaluation as Example 1 was performed.
- FIG. 2 shows the results of infrared absorption spectrum analysis of the SiO 2 films on the support substrate in Examples 1 to 3 and Comparative Example 1. Moreover, the infrared absorption spectrum about the perhydropolysilazane film
- FIG. 5 shows the evaluation results of Comparative Example 1 (SiO 2 film fired at 450 ° C.), and FIG. 6 shows the comparative example. This is an evaluation result of 2 (thermal oxide film).
- the numbers in FIGS. 4 to 6 correspond to the evaluation positions shown in FIG.
- the SiO 2 film condensed with silanol groups at a baking temperature of 600 ° C. in Example 1 shows the same IV characteristics as the thermal oxide film in Comparative Example 2 (FIG. 6). It is presumed that when the baking treatment is performed at 600 ° C. or higher, silanol groups in the film are condensed and the leakage current is reduced.
- FIG. 6 shows the evaluation results of Comparative Example 1 (SiO 2 film fired at 450 ° C.)
- FIG. 6 shows the comparative example. This is an evaluation result of 2 (thermal oxide film).
- the numbers in FIGS. 4 to 6 correspond to the evaluation positions shown in FIG.
- the dielectric breakdown electric field strength is the same as in Example 1 (FIG. 4) and Comparative Example 2 (FIG. 6).
- the leak current value is higher than the others.
- the bonded wafer was observed with an ultrasonic microscope, and the presence or absence of bubbles at the bonding interface was observed to determine whether bonding was possible. As a result, bonding was possible in all of Examples 1 to 3 and Comparative Example 1. Further, after the heat treatment for bonding heated at 300 ° C., the bonded substrate before peeling treatment was examined with an ultrasonic microscope for the presence of peeling or void generation at the bonding interface. As a result, in Comparative Example 1, that is, the SiO 2 film having a baking temperature of 450 ° C., significant voids were observed at the bonding interface. On the other hand, in Examples 1 to 3, no peeling or void was observed at the bonding interface.
- Comparative Example 1 it is considered that voids were generated because condensation of silanol groups in the SiO 2 film or moisture in the film became gas due to heat treatment for bonding and diffused to the bonding interface. Then, after transferring the Si film was peeled at the ion implanted region, was confirmed whether the generation of new peeling or voids at the bonding interface by the heat treatment up to 1000 ° C. resulting membrane was SiO 2 conversion at 600 ° C. or higher ( No changes were observed in Examples 1 to 3) and the thermal oxide film (Comparative Example 2).
- Example 4 A polysilazane was applied to a substrate with a rough surface, and it was confirmed whether it could be bonded to a Si wafer by converting to SiO 2 .
- a GaN wafer having a diameter of 2 inches was used as the substrate.
- the surface roughness Rms was confirmed by AFM, it was 2.14 nm, and bonding with an ion-implanted Si wafer having an outer diameter of 2 inches was not possible.
- 1 mL of a solution containing 5% by mass of perhydropolysilazane in n-dibutyl ether was spin-coated, and the solvent was removed by heating at 150 ° C. for 3 minutes.
- the film can be easily formed by spin coating or the like and can be bonded without polishing.
- the temperature at which the SiO 2 film is converted is set to a firing temperature at which no silanol groups remain, a bonding layer having good insulating properties can be obtained.
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Abstract
Description
〔1〕 半導体基板と支持基板とを貼り合わせた後、上記半導体基板を薄化して、支持基板上に半導体層を有する複合基板を得る複合基板の製造方法であって、上記半導体基板と支持基板の貼り合わせを行う面の少なくともいずれかに、ポリシラザンを含有する塗膜を形成し、該塗膜を600℃以上1200℃以下に加熱する焼成処理を行ってケイ素含有絶縁膜を形成し、その後に上記半導体基板と支持基板とを該絶縁膜を介して貼り合わせることを特徴とする複合基板の製造方法。
〔2〕 上記ポリシラザンがパーヒドロポリシラザンである〔1〕記載の複合基板の製造方法。
〔3〕 上記焼成処理が、酸素及び/又は水蒸気を含む雰囲気下で行われる〔1〕又は〔2〕記載の複合基板の製造方法。
〔4〕 上記焼成処理が、窒素を含む不活性雰囲気下又は減圧下で行われる〔1〕又は〔2〕記載の複合基板の製造方法。
〔5〕 上記絶縁膜を焼成処理時の厚さのままとして、上記半導体基板と支持基板の貼り合わせを行う〔1〕~〔4〕のいずれかに記載の複合基板の製造方法。
〔6〕 上記半導体基板の表面からイオンを注入してイオン注入領域を形成すると共に、上記支持基板の貼り合わせを行う面に上記ケイ素含有絶縁膜を形成し、上記半導体基板のイオン注入した表面と支持基板の表面とを該絶縁膜を介して貼り合わせた後、上記イオン注入領域で半導体基板を剥離させて支持基板上に半導体層を形成する〔1〕~〔5〕のいずれかに記載の複合基板の製造方法。
〔7〕 〔1〕~〔6〕のいずれかに記載の複合基板の製造方法により製造されてなる複合基板。
本発明に係る複合基板の製造方法は、図1に示すように、半導体基板への水素イオン(希ガスイオン)注入工程(工程1)、絶縁膜形成工程(工程2)、半導体基板及び/又は支持基板の表面活性化処理工程(工程3)、半導体基板と支持基板の貼り合わせ工程(工程4)、剥離処理工程(工程5)、ダメージ層除去工程(工程6)の順に処理を行うものである。
まず、半導体基板1の表面から水素イオン又は希ガス(即ち、ヘリウム、ネオン、アルゴン、クリプトン、キセノン、ラドン)イオンを注入し、基板中にイオン注入領域2を形成する(図1(a))。
次に、後述する半導体基板1と支持基板3との貼り合わせを行う面のいずれか又は両方にケイ素含有絶縁膜4を形成する。ここでは、支持基板3の貼り合わせ面に絶縁膜4を形成する場合について説明する(図1(b)、(c))。
支持基板3としては、シリコン、サファイア、SiC、GaAs、GaN、ZnO等の単結晶基板、合成石英や多成分ガラス等のアモルファス基板、またp-Si、SiC、Si3N4、Al2O3、AlN等の多結晶基板を用いることができる。
ポリシラザンとしては、一般式 -(SiH2NH)n- で表されるパーヒドロポリシラザンが、転化後の絶縁膜中に残存する不純物が少ないことから好ましい。なお、パーヒドロポリシラザンは、―(SiH2NH)-を基本ユニットとし、その側鎖すべてが水素であり有機溶剤に可溶な無機ポリマーである。
塗布する厚さは、塗布をする基板表面の粗さや段差の程度、半導体デバイスとして要求される埋め込み層の厚さによって決まるが、焼成後の絶縁膜4としての厚さが10nm~10μmとなる程度の厚さが好ましい。1回の塗布で形成されない場合は、塗布を繰り返し積層してもよい。
塗布後は溶媒を除去するため、50~200℃程度で1分~2時間乾燥され、塗膜4aとなる。
なお、Rms(Root-mean-square)とは、基準長さにおける断面プロファイルの算術平均値に対する偏差の2乗値の平均に対する平方根として得られる2乗平均平方根粗さであり、JIS B0601:2013に規定する二乗平均平方根粗さRqをいう(以下同じ)。
貼り合わせの前に、半導体基板1のイオン注入された表面と、支持基板3上の絶縁膜4表面との双方もしくは片方に表面活性化処理を施す。
次に、支持基板1のイオン注入された表面と支持基板3の絶縁膜4の表面とを貼り合わせる(図1(d))。このとき、150~200℃程度に加熱しながら貼り合わせるとよい。以下、この接合体を貼り合わせ基板5という。半導体基板1のイオン注入面と絶縁膜4の表面の少なくとも一方が活性化処理されていると、より強く接合できる。
次に、貼り合わせ基板5におけるイオン注入した部分に熱的エネルギー、機械的エネルギー又は光的エネルギーを付与して、イオン注入領域2に沿って剥離させ、半導体基板1の一部を半導体層6として支持基板3側に転写してウェハ7とする(図1(e))。即ち、支持基板3に絶縁膜4を介して結合した半導体の薄膜を半導体基板1から剥離させて半導体層(シリコン層)6とする。なお、剥離は、イオン注入領域2に沿って貼り合わせ基板5の一端から他端に向かうへき開によるものが好ましい。
次に、ウェハ7の支持基板3上の半導体層6表層において、上記イオン注入によりダメージを受けて結晶欠陥を生じている層を除去する。
なお、ここでは半導体基板1を薄化して半導体層6を得る方法として、イオン注入剥離法を用いたものを説明したが、これに限定されるものではなく、例えば研削、ラップ加工、研磨等の機械的手法やエッチング等の化学的手法、あるいはそれらの組み合わせた手法を用いて、半導体基板1を薄化してもよい。
評価用サンプルの作製及び評価を次の手順で行った。
まず、パーヒドロポリシラザンからSiO2に転化した膜をSiウェハの支持基板上に形成した。詳しくは、溶媒n-ジブチルエーテルにパーヒドロポリシラザンを20質量%含む溶液(サンワ化学製トレスマイル、型番ANN120-20)2mLを外径150mmのSiウェハ上にスピンコートし、150℃で3分間加熱して溶媒を除去した。その後、大気中600℃で3分間加熱する焼成処理を行い、塗膜をSiO2膜へ転化させた。焼成処理後の膜厚は200nmであった。このときの焼成処理前後の膜質の変化を赤外吸収スペクトルにより確認し、焼成処理後のSiO2膜形成面の表面粗さ(Rms)を原子間力顕微鏡(AFM)により測定した。更に、瞬時絶縁破壊法(Time Zero Dielectric Breakdown)により、ウェハ面内10点のSiO2膜の絶縁耐圧を評価した。
次に、上記支持基板のSiO2膜形成面と水素イオンをイオン注入したSiウェハのイオン注入面とを貼り合わせ、接合用の熱処理を行った。詳しくは、Siウェハに57keV、ドーズ量6.0×1016atoms/cm2で水素イオンを注入し、そのイオン注入面側、及び上記支持基板のSiO2膜形成面に対してイオンビーム活性化処理を行った後、両者を貼り合わせ、更に300℃で10時間の接合用の熱処理を行った。この300℃加熱の熱処理後の接合界面における剥がれの有無やボイド発生の有無を超音波顕微鏡で観察して確認した。
次に、上記貼り合わせ基板についてイオン注入領域で剥離することによってSi単結晶薄膜の支持基板への転写を行った。このSi単結晶薄膜が転写された基板について、N2雰囲気下で1000℃の加熱処理を行い、接合界面からの剥がれやボイド発生の有無を超音波顕微鏡で観察して確認した。
実施例1において、焼成温度を800℃に変更し、それ以外は実施例1と同様にして、Si単結晶薄膜の支持基板への転写を行った。また、実施例1と同様の評価を行った。
実施例1において、焼成温度を1000℃に変更し、それ以外は実施例1と同様にして、Si単結晶薄膜の支持基板への転写を行った。また、実施例1と同様の評価を行った。
実施例1において、焼成温度を450℃に変更し、それ以外は実施例1と同様にして、Si単結晶薄膜の支持基板への転写を行った。また、実施例1と同様の評価を行った。
実施例1において、支持基板を酸素を含む雰囲気下において1000℃加熱の熱酸化を行うことにより厚さ200nmのSiO2膜を形成したSiウェハとし、それ以外は実施例1と同様にして、Si単結晶薄膜の支持基板への転写を行った。また、実施例1と同様の評価を行った。
図2に、実施例1~3、比較例1における支持基板上のSiO2膜の赤外吸収スペクトル分析結果を示す。また、150℃乾燥後、焼成処理前のパーヒドロポリシラザン膜(塗布後)についての赤外吸収スペクトルも図2に示す。なお、赤外吸収スペクトルの測定は、フーリエ変換赤外分光分析装置(Spectrum One、パーキンエルマー社製)を用いて透過法で測定した。
図2に示すように、実施例1~3及び比較例1と塗布後とを比較すると、450℃以上の焼成処理によって、Si-H、N-H、Si-Nに起因する吸収ピークが消滅し、Si-Oに起因するピークが出現していることから、SiO2への転化がなされていることがわかる。ただし、比較例1(焼成温度450℃)においては、波数3000~3800cm-1においてOH基による吸収が見られることから、塗膜のSiO2化は進んでいるが、シラノール基が存在していることがわかる。焼成温度を600℃以上とするとシラノール基に起因するピークは見られなくなり、シラノールの縮合が進んでいるものと推測される。
実施例1、比較例1及び比較例2で作製したSiO2膜について、図3に示すように、ウェハ上の1~10で示す位置の10点で、TZDB(Time Zero Dielectric Breakdown)法により絶縁耐圧評価を行った。なお、TZDB法による測定は、ゲート面積を8mm2とし、1Vステップの電圧印加を行ってリーク電流を測定した。このとき、印加電圧をSiO2膜の膜厚で除したものを電界強度(MV/cm)とした。
その結果を図4~図6に示す。図4は、実施例1(600℃で焼成処理したSiO2膜)の評価結果、図5は、比較例1(450℃で焼成処理したSiO2膜)の評価結果、図6は、比較例2(熱酸化膜)の評価結果である。なお、図4~図6の図中の数字は図3に示す評価位置に対応するものである。
図4に示すように、実施例1の焼成温度600℃のシラノール基が縮合したSiO2膜では、比較例2の熱酸化膜(図6)と同様のI-V特性を示している。600℃以上で焼成処理することによって膜中のシラノール基が縮合し、リーク電流が小さくなるものと推測される。一方、図5に示すように、比較例1の450℃で焼成したシラノール基が残存するSiO2膜では、絶縁破壊電界強度は実施例1(図4)や比較例2(図6)と同程度であるが、リーク電流値が他のものより高くなっている。
このように、パーヒドロポリシラザンを含む塗膜を600℃以上で焼成処理することにより、膜中のシラノール基を縮合させ、SiO2膜の膜質を熱酸化膜と同程度にすることができる。
実施例1~3及び比較例1、2において、SiO2膜の表面粗さ測定結果、並びに支持基板とSiウェハとの貼り合わせ可否を調べた結果を表1に示す。
実施例1~3及び比較例1のパーヒドロポリシラザンから得たSiO2膜の表面粗さRmsは、比較例2に示す熱酸化膜の表面粗さRmsに比べて若干大きな値を示した。そこで、支持基板のSiO2膜の表面研磨をすることなく、Siウェハとの貼り合わせが可能か否かを調べるため、水素イオンを注入したSiウェハを用い、貼り合わせ可否を調べた。詳しくは、貼り合わせたウェハを超音波顕微鏡によって観察し、貼り合わせ界面の気泡の有無を観察することにより貼り合わせ可否を判断した。その結果、実施例1~3、比較例1の全てで貼り合わせが可能であった。
また、300℃加熱の接合用の熱処理後で、剥離処理前の貼り合わせ基板について、接合界面における剥がれやボイド発生の有無を超音波顕微鏡で調べた。その結果、比較例1、即ち焼成温度450℃のSiO2膜については、接合界面で著しいボイドの発生が見られた。一方、実施例1~3については接合界面に剥がれやボイドの発生は見られなかった。比較例1では、SiO2膜中のシラノール基の縮合あるいは膜中の水分が接合用の熱処理によってガスとなり、接合界面に拡散したためにボイドが生成したものと思われる。
次に、イオン注入領域で剥離させてSi膜を転写した後、1000℃まで熱処理して接合界面に新たに剥がれやボイドの発生が生じるか確認したところ、600℃以上でSiO2転化した膜(実施例1~3)及び熱酸化膜(比較例2)について変化は見られなかった。
表面の粗い基板にポリシラザンを塗布、SiO2転化することでSiウェハとの貼り合わせができるか確認を行った。基板として、直径2インチのGaNウェハを用いた。その表面粗さRmsをAFMで確認したところ、2.14nmであり、そのままで外径が2インチのイオン注入したSiウェハとの貼り合わせはできなかった。
GaNウェハ表面に、n-ジブチルエーテルにパーヒドロポリシラザンを5質量%含む溶液1mLをスピンコートし、150℃で3分間加熱して溶媒を除去した。その後、大気中600℃で3分間加熱する処理を行い、塗膜をSiO2膜へ転化させた。焼成処理後の膜厚は50nm、AFMで確認した表面粗さRmsは0.39nmであり、表面粗さが貼り合わせ可能なレベルにまで小さくなっていた。イオン注入したSiウェハとの貼り合わせ可否を調べたところ、界面のボイドは無く接合することができた。
GaN表面の粗さ改善をパーヒドロポリシラザンのスピンコートでなく、PECVD法でSiO2を成膜して調べた。SiO2膜の厚さは50nmとし、成膜後の表面粗さRmsをAFMで調べたところ1.38nmであり、ポリシラザンのSiO2転化膜に比べ大きかった。この表面粗さでSiウェハとの貼り合わせを試みたが、貼り合わせはできなかった。貼り合わせを可能とするためには、SiO2成膜後に研磨をするプロセスがさらに必要となることを確認した。
本実施例では、支持基板であるSi基板上の塗布及びイオン注入したSi基板との接合の例を示したが、表面粗さRmsがSiウェハに比べ1桁高いSiCやGaN単結晶ウェハに対しても、パーヒドロポリシラザンを塗布し、600℃以上の焼成処理によりSiO2絶縁膜に転化することで、表面の粗さを小さくし、剥がれやボイドの発生なしに接合することが可能である。この場合、CVD法で成膜する方法と異なり、スピンコートなど簡易的に成膜でき、研磨をすることなく接合することが可能である。また、SiO2膜に転化する温度をシラノール基が残存しない焼成温度とするので、絶縁特性が良好な接合層を得ることができる。
2 イオン注入領域
3 支持基板
4 絶縁膜(シリコン酸化膜)
4a 塗膜
5 貼り合わせ基板(接合体)
6 半導体層
7 ウェハ
8 複合基板
Claims (7)
- 半導体基板と支持基板とを貼り合わせた後、上記半導体基板を薄化して、支持基板上に半導体層を有する複合基板を得る複合基板の製造方法であって、上記半導体基板と支持基板の貼り合わせを行う面の少なくともいずれかに、ポリシラザンを含有する塗膜を形成し、該塗膜を600℃以上1200℃以下に加熱する焼成処理を行ってケイ素含有絶縁膜を形成し、その後に上記半導体基板と支持基板とを該絶縁膜を介して貼り合わせることを特徴とする複合基板の製造方法。
- 上記ポリシラザンがパーヒドロポリシラザンである請求項1記載の複合基板の製造方法。
- 上記焼成処理が、酸素及び/又は水蒸気を含む雰囲気下で行われる請求項1又は2記載の複合基板の製造方法。
- 上記焼成処理が、窒素を含む不活性雰囲気下又は減圧下で行われる請求項1又は2記載の複合基板の製造方法。
- 上記絶縁膜を焼成処理時の厚さのままとして、上記半導体基板と支持基板の貼り合わせを行う請求項1~4のいずれか1項記載の複合基板の製造方法。
- 上記半導体基板の表面からイオンを注入してイオン注入領域を形成すると共に、上記支持基板の貼り合わせを行う面に上記ケイ素含有絶縁膜を形成し、上記半導体基板のイオン注入した表面と支持基板の表面とを該絶縁膜を介して貼り合わせた後、上記イオン注入領域で半導体基板を剥離させて支持基板上に半導体層を形成する請求項1~5のいずれか1項記載の複合基板の製造方法。
- 請求項1~6のいずれか1項記載の複合基板の製造方法により製造されてなる複合基板。
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TWI627657B (zh) | 2018-06-21 |
US9613849B2 (en) | 2017-04-04 |
JPWO2014080874A1 (ja) | 2017-01-05 |
CN104798176A (zh) | 2015-07-22 |
EP2924715A1 (en) | 2015-09-30 |
TW201440116A (zh) | 2014-10-16 |
CN104798176B (zh) | 2018-01-02 |
JP6265130B2 (ja) | 2018-01-24 |
KR102120509B1 (ko) | 2020-06-08 |
EP2924715A4 (en) | 2016-07-27 |
SG11201504015SA (en) | 2015-06-29 |
KR20150087229A (ko) | 2015-07-29 |
US20150303097A1 (en) | 2015-10-22 |
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