TWI389250B - 矽石質膜之製法及附有由它製造的矽石質膜之基板 - Google Patents
矽石質膜之製法及附有由它製造的矽石質膜之基板 Download PDFInfo
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- TWI389250B TWI389250B TW096101534A TW96101534A TWI389250B TW I389250 B TWI389250 B TW I389250B TW 096101534 A TW096101534 A TW 096101534A TW 96101534 A TW96101534 A TW 96101534A TW I389250 B TWI389250 B TW I389250B
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- film
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- polyfluorene
- insulating film
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- 229910052707 ruthenium Inorganic materials 0.000 claims description 13
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 12
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Description
本發明係關於電子裝置用之矽石質膜之製法及由該方法形成的附有矽石質膜之基板。本發明亦關於半導體元件等電子裝置之製造,其使用聚矽氮類化合物於電子裝置形成用於絕緣的淺溝槽隔離構造之方法。
一般,如半導體裝置之電子裝置中,半導體元件例如電晶體、電阻器等係配置於基板上,這些須予電絕緣。因此,這些元件間須具用以分離元件之區域,稱為隔離區域。向來一般係於半導體基板表面選擇性形成絕緣膜作為此隔離區域。
而近年來在電子零件領域有高密度化及高積體化之進展。有如此的高密度化及高積體化之進展,則配合必要積體度之微細隔離構造難以形成,合乎該等需求之新穎隔離構造受到期待,溝槽隔離構造即其一。此構造乃於半導體基板表面形成微溝,於該溝內部填充絕緣物,製作形成在溝兩側之元件間的電分離構造。如此之用於元件分離之構造,因隔離區域可較習知方法窄,乃可有效達成最近之高積體度要求之元件分離構造。
用以形成如此之溝槽隔離構造之方法有CVD法、高密度電漿CVD法(參考例如專利文獻1)。然而以如此方法,則於最近要求之例如100nm以下之微細溝內埋設使用時,會於溝內有空孔形成。這些構造缺失造成基板物理強度、絕緣特性之損害。
而為改良溝槽之埋設性,有以氫氧化矽溶液塗敷後,形成之塗膜藉加熱處理轉化為二氧化矽之方法之探討(參考例如專利文獻1)。可是此方法在氫氧化矽轉化為二氧化矽之際體積會收縮,產生皸裂。
為抑制該等皸裂,有取代氫氧化矽改用聚矽氮類之方法的探討(參考例如專利文獻1及2)。這些方法係藉由使用轉化為二氧化矽之際體積收縮較小之聚矽氮類,以防體積收縮造成皸裂。塗敷含聚矽氮類之組成物埋設溝槽後於氧化氛圍作處理,形成高純度且緻密之二氧化矽形成溝槽隔離構造之方法,其優點係組成物之滲透性佳而不易產生空孔。然而,經本發明人之探討得知,如此之溝槽隔離構造中,聚矽氮類轉化為二氧化矽形成矽石質膜之際,塗膜表面部分及溝槽內部因反應條件之微妙差別,矽石質膜之膜質隨溝槽內部及外部或溝內深度而不同,有蝕刻率不均之問題。此問題因限於零件設計及程序設計,於作要求之低溫處理時更顯著,尤以於高長寬比之溝槽部有蝕刻率加大之現象出現。
專利文獻1 日本專利第3178412號公報(段落0005~0016)專利文獻2 日本專利特開平2001-308090號公報專利文獻3 日本專利特開2002-88156號公報
本發明鑑於如上問題,涉及使用聚矽氮類化合物形成矽石質膜於具凹凸之矽基板表面,以形成溝槽隔離構造,以均質矽石質膜覆蓋表面之際,形成之矽石質膜其膜質在任一部分皆均勻之矽石質膜之製法,及具備由該方法形成之矽石質膜之電子零件。
依本發明,矽石質膜之製法其特徵為包含於具凹凸之矽基板表面形成經二次離子質量分析測定之含氫量在9×102 0
atoms/cm3
以上之絕緣膜之絕緣膜形成步驟,以含聚矽氮類化合物之組成物塗於上述基板之塗敷步驟,及已塗敷之基板經加熱處理使聚矽氮類化合物轉化為二氧化矽之硬化步驟。
依本發明,附有矽石質膜之基板其特徵為具備經上述方法形成之矽石質膜。
依本發明之矽石質膜之製法,以較低溫之熱處理即可製造附有矽石質膜之基板,該矽石質膜之膜質無論基板凹凸、在溝內外,不論溝部深度一概均勻,進行蝕刻處理時可得均一的蝕刻率。如此之矽石質膜,於溝內部同時無空孔、皸裂,亦即用於半導體元件時無性能之劣化,且機械強度佳之特性。又因可在較低溫作熱處理,適用於最近被指稱有高溫處理而產生之問題,例如矽基板之氧化或結晶構造起變化而導致裝置特性有不良影響之電子裝置製程。
依本發明之矽石質膜製法,可於具凹凸之矽基板上形成無空孔,膜質均勻之被膜。因此,形成為電子裝置之電晶體部、電容器部之平坦化絕緣膜(金屬前絕緣膜),並於有溝之矽基板上形成矽石質膜將溝埋封,即可形成溝槽隔離構造。以下基於溝槽隔離構造之形成法說明本發明。
依本發明,矽石質膜之製法係依以下順序作處理,形成溝槽隔離構造:於具凹凸之矽基板表面上形成經二次離子質量分析(下稱SIMS分析)測定之含氫量在9×102 0
atoms/cm3
以上之絕緣膜之絕緣膜形成步驟,以含聚矽氮類化合物之組成物塗於上述基板之塗敷步驟,及經塗敷之基板以加熱處理使聚矽氮類化合物轉化為二氧化矽膜之硬化步驟。
本發明之方法係於絕緣膜形成步驟前,準備具有凹凸之矽基板。形成溝槽隔離構造時,則特別準備具有所欲溝槽圖案之矽基板。此溝之形成可採任意方法,例如專利文獻1或2所述者。具體方法如下。
首先,於矽基板表面以例如熱氧化法形成二氧化矽膜。此所形成之二氧化矽膜其厚度一般在5~30nm。
必要時,於形成之二氧化矽膜上,以例如減壓CVD法形成氮化矽膜。此氮化矽膜可用作嗣後蝕刻步驟之遮罩或後敘研磨步驟之停止層。有氮化矽膜之形成時其一般厚度在100~400nm。
以光阻塗於如此形成之二氧化矽膜或氮化矽膜上。必要時將光阻膜乾燥或硬化後,以所欲圖案曝光及顯像形成圖案。曝光可由光罩曝光、掃描曝光等任意方法為之。光阻亦可依解析度等任意選用。
以形成之光阻膜為遮罩依序蝕刻氮化矽膜及其下之二氧化矽膜。經此操作可於氮化矽膜及二氧化矽膜形成所欲圖案。
以形成圖案之氮化矽膜及二氧化矽膜為遮罩,作矽基板之乾式蝕刻形成隔離溝槽。
形成之隔離溝槽之寬度取決於光阻膜之曝光圖案。雖隨目標半導體元件而異,半導體元件之隔離溝槽寬度一般在0.02~10 μ m,0.05~5 μ m更佳,深度一般在200~1000nm,300~700nm更佳。本發明方法因較之習知溝槽隔離構造形成方法可均勻埋設至更狹窄,更深部分,適於更狹窄,更深之溝槽隔離構造之形成。
更於形成溝槽之基板表面形成絕緣膜。此絕緣膜連續覆蓋於包含溝內側之基板表面。本發明中,此絕緣膜經SIMS分析測定之含氫量在9×102 0
atoms/cm3
以上,1×102 1
atoms/cm3
以上更佳。含氫量低於該量則如後敘氫不於聚矽氮類塗膜移動,不得本發明效果。如此之高含氫率絕緣膜可由任意方法形成,電漿化學氣相沈積法較佳。由使用四乙氧矽烷(下稱TEOS)等有機矽烷化合物之電漿化學氣相沈積法形成之二氧化矽膜及由電漿化學氣相沈積法形成之氮化矽膜尤佳。由電漿化學氣相沈積法形成之絕緣膜因非化學計量而含過剩之氫,故含氫量不為零。而例如塗以含矽組成物等之水溶液,經加熱處理得之絕緣膜乃經高溫處理,絕緣膜含氫量極低,於本發明難得特定含氫量之絕緣膜。然而,本發明中絕緣膜若在上述範圍即可獲致本發明效果,其形成方法無特殊限制。而形成充分含氫之絕緣膜,於其上形成聚矽氮類塗膜,硬化前若氫釋出即不得本發明效果(詳如後敘)。例如,由使用TEOS之電漿化學氣相沈積法形成之二氧化矽膜於高溫退火則常有氫自絕緣膜釋出。因此,對於如此之絕緣膜,不宜在形成聚矽氮類塗膜前作加熱處理,而須作退火處理時,一般係以高於絕緣膜成膜溫度100℃之溫度為上限。
用以測定絕緣膜中含氫量之SIMS分析之測定條件如下。
測定裝置:Physical Electronics公司製6600一次離子種類:Cs+
一次加速電壓:5.0kV檢測區域:120 μ m×192 μ m
在無損於本發明效果之範圍內,此絕緣膜之厚度隨意,一般係形成為1~100 nm,2~20 nm更佳。
其次,在經上述絕緣膜形成步驟於絕緣膜形成溝之矽基板上,以含矽石質膜材料:聚矽氮類化合物之組成物形成塗膜。可用於本發明方法之聚矽氮類化合物無特殊限制,有上述專利文獻1或2所述者。可用之聚矽氮類化合物的調製法之範例如下。
攪拌下注入純度99%以上之二氯矽烷於調溫為-20~20℃之脫水吡啶。
繼之調溫為-20~20℃,攪拌下注入純度99%以上之氨。此反應液中生成聚矽氮類粗產物及副產物氯化氨。
過濾去除反應生成之氯化氨。
將濾液加熱至30~150℃去除殘餘之氨,同時調整聚矽氮類之分子量為重量平均分子量1500~15000。
將有機溶劑加熱至30~50℃,經50mmHg以下之減壓蒸餾去除殘餘吡啶。可用之有機溶劑乃(甲)芳香族化合物,例如苯、甲苯、二甲苯、乙苯、二乙苯、三甲苯、三乙苯及十氫萘,(乙)鏈狀飽和烴,例如正戊烷、異戊烷、正己烷、異己烷、正庚烷、異庚烷、正辛烷、異辛烷、正壬烷、異壬烷、正癸烷及異癸烷,(丙)環狀飽和烴,例如環己烷、乙環己烷、甲環己烷及對,(丁)環狀不飽和烴,例如環己烯及雙戊烯(檸檬烯;limonene),(戊)醚,例如二丙醚、二丁醚及甲氧苯,(己)酯,例如乙酸正丁酯、乙酸異丁酯、乙酸正戊酯及乙酸異戊酯,(庚)酮,例如甲基異丁酮。
上述減壓蒸餾可去除吡啶,而同時有機溶劑亦去除,將聚矽氮類濃度調整為一般之5~30重量%。
得到之聚矽氮類組成物以過濾精度0.1 μ m以下之濾器循環過濾,將粒徑0.2 μ m以上之粗大粒子減至50個/cc以下。
上述聚矽氮類組成物製法乃其例示,而不限於此。亦可取得固態聚矽氮類,於上述適當溶劑溶解或分散為一般之5~30重量%濃度使用。溶液濃度應依最終形成之聚矽氮類塗膜厚度適當調整。
所準備之聚矽氮類組成物可由任意方法塗於基板上。具體有旋塗、幕塗、沾塗等。其中旋塗因塗膜面均勻等而尤佳。
聚矽氮類組成物塗敷後,為兼顧溝槽埋設性及聚矽氮類塗膜表面之平坦性,所塗聚矽氮類塗膜之厚度一般為10~1,000nm,50~800nm更佳。
塗敷條件隨聚矽氮類組成物濃度、溶劑或塗敷法而異,以旋塗為例則如下。
最近為改善製造良率,多於大型基板形成元件,為在8吋以上之矽基板形成聚矽氮類塗膜,多段組合之旋塗即有用。
為於矽基板中心部或於基板全面平均形成塗膜,首先於含中心部之數處滴下一般係每1矽基板0.5~20cc之聚矽氮類組成物。
其次,為使滴下之聚矽氮類溶液廣布於矽基板全面,以較低速短時間例如50~500rpm,0.5~10秒旋轉(預旋轉)。
其次為使塗膜成所欲厚度,以較高速例如500~4500rpm旋轉0.5~800秒(主旋轉)。
又為減少矽基板之聚矽氮類塗膜隆起,並將聚矽氮類塗膜中之溶劑盡可能乾燥,以比上述主旋轉高500rpm以上之速度例如1000~5000rpm旋轉5~300秒(終旋轉)。
這些塗敷條件係依所用基板之大小、目標半導體元件之性能等適當調整。
塗敷聚矽氮類組成物後,必要時附加預烘烤步驟(詳如後敘)後,為使聚矽氮類塗膜轉化成矽石質膜並硬化,將基板全體加熱。一般係將基板全體送入硬化爐等加熱。
硬化係以用硬化爐、熱板,於含水蒸氣之惰性氣體或氧氛圍下進行為佳。水蒸氣於聚矽氮類之充分轉化為矽石質膜(亦即二氧化矽)具重要性,30%以上為佳,50%以上更佳,70%以上最佳。水蒸氣濃度80%以上則聚矽氮類之轉化為矽石質膜變容易,少有空孔等缺失產生,改善矽石質膜之特性而尤佳。氛圍氣體採用惰性氣體時,係用氮、氬或氦。
硬化時之溫度條件隨所用聚矽氮類化合物之種類、步驟之組合(詳如後敘)而異。然而溫度愈高則聚矽氮類化合物之轉化為矽石質膜傾向愈快,且溫度愈低則矽基板氧化或結晶構造變化對於零件特性之不良影響傾向較小。由此觀點,於本發明方法,加熱係於400~1,200℃,較佳者500~1,000℃一段為之。本發明中因有會釋出氫之絕緣膜存在,可藉較低溫之熱處理充分硬化,由對零件特性之影響的觀點,以於較低溫硬化為佳。此時,升溫至目標溫度之速度一般在1~100℃/分鐘,到達目標溫度後之硬化時間一般係1分鐘~10小時,15分鐘~3小時更佳。必要時可分段改變硬化溫度或硬化氛圍之組成。本發明中因有會釋出氫之絕緣膜存在,可藉較低溫之熱處理充分硬化,由對零件特性之影響的觀點,以於較低溫硬化為佳。
經此加熱,聚矽氮類化合物轉化為二氧化矽而成矽石質膜。本發明方法中,已知氫自含氫之絕緣膜移往聚矽氮類塗膜。推測因氫之移往聚矽氮類塗膜,聚矽氮類化合物轉化為二氧化矽之反應變得均勻。因此,使用含氫率為零或較低之絕緣膜即不得本發明效果。
本發明之溝槽隔離構造形成法須經上述(A)~(C)各步驟,必要時可組合其它步驟。這些可予組合之步驟如下。
(a)預烘烤步驟硬化步驟前,塗有聚矽氮類溶液之基板可施以預烘烤處理。此步驟之目的在完全去除聚矽氮類塗膜中含之溶劑,並作聚矽氮類塗膜之預硬化。使用聚矽氮類之本發明的溝槽隔離構造形成法,因藉預烘烤處理可提升矽石質膜之緻密度,組合預烘烤步驟即尤佳。
習知預烘烤步驟實質上係於一定溫度加熱,該等方法中硬化之際塗膜收縮,隔離溝部凹陷,於溝內部產生空孔。
本發明方法中,施以預烘烤處理時,以控制預烘烤步驟之溫度,使其隨時間上升一邊進行烘烤為佳。此時預烘烤溫度通常係50~400℃,100~300℃更佳。預烘烤步驟所需時間一般係10秒~30分鐘,30秒~10分鐘更佳。
為使預烘烤步驟中之溫度隨時間上升,有分段上升基板之氛圍溫度之方法,或單純提升溫度之方法。預烘烤步驟中之最高預烘烤溫度,基於自被膜去除溶劑,一般係設定為高於用在聚矽氮類溶液之溶劑的沸點。
分段上升預烘烤溫度之方法係例如溫度T1數分鐘,高於T1之溫度數分鐘,將基板保持於定溫度一定時間,再保持於較高溫度一定時間,一再重複。各段溫差一般在30~150℃,保持一定之時間一般係於各溫度10秒~3分鐘。以如此條件進行預烘烤,本發明效果可顯著呈現。
例如,以2段溫度預烘烤時,第一段之預烘烤溫度在第二段預烘烤溫度(最高預烘烤溫度)為A(℃)時係以(1/4)A~(3/4)A(℃)為佳。
例如溫度分3段作預烘烤時,第三段之預烘烤溫度(最高預烘烤溫度)為A(℃)時第一段預烘烤溫度係以(1/4)A~(5/8)A(℃)為佳,第二段預烘烤溫度以(5/8)A~(7/8)A(℃)為佳。
例如聚矽氮類溶液使用二甲苯等沸點150℃左右之溶劑,最高預烘烤溫度選在200℃時,(a)以2段溫度預烘烤時,第一段預烘烤溫度以50~150℃為佳,(b)以3段溫度預烘烤時,第一段預烘烤溫度以50~125℃,第二段預烘烤溫度以125~175℃為佳。
亦即,分段升溫法由整體預烘烤步驟觀之,乃分多段設定溫度為之,以穩定升溫至目標溫度。
單純升溫法係須使溫度較之先前上升0℃以上。此時對於其前任一時間點之溫差可為0但不可為負。易言之,預烘烤溫度對溫度繪圖時,溫度曲線之斜率須不為負。於此,基板之升溫速度一般在0~500℃/分鐘,10~300℃/分鐘較佳。升溫速度愈高步驟時間愈短,但基於溝構造內部溶劑之去除及聚矽氮類之充分聚合,以低速升溫為佳。
本發明中之「控制使預烘烤步驟中之溫度隨時間上升」不包括例如將低溫基板移往高溫條件下,使基板溫度急遽上升至與氛圍溫度同後,維持於該溫度預烘烤該基板者。此時基板溫度雖隨時間上升,其溫度上升不受控制,如此大多不得本發明之效果。
如此之預烘烤步驟中溫度控制之目的在防塗膜溫度急遽上升,以比通常之一段加熱預烘烤穩定之速度升溫。依本發明方法,例如溝內部空孔減少之理由雖非明確,但推測應係若基板急遽升溫則溶劑自隔離溝內部完全去除前表面過度硬化,溶劑蒸汽殘留在溝內部所致。本發明因於預烘烤步驟作溫度控制,該問題即獲解決。
本發明中組合有預烘烤步驟時,經預烘烤而達高溫之基板在溫度下降前,以附加較佳者50℃以上,預烘烤最高溫以下之溫度的基板硬化步驟為佳。溫度下降前附加基板硬化步驟,即可節省再次升溫之能量及時間。
(b)研磨步驟施以硬化後,以去除硬化二氧化矽膜之不必要部分為佳。因之,首先以研磨步驟研磨去除基板表面之聚矽氮類塗膜。此步驟即研磨步驟。此研磨步驟除在硬化處理後為之以外,組合有預烘烤步驟時亦可於預烘烤後隨即進行。
研磨係藉化學機械研磨(Chemical Mechanical Polishing,下稱CMP)為之。此CMP研磨可用一般研磨劑及研磨裝置施行。具體言之,研磨劑可用矽石、氧化鋁或氧化鈰等研磨材及必要時之其它添加劑之分散水溶液。研磨裝置可用一般市售CMP裝置。
(c)蝕刻步驟上述研磨步驟中,基板表面之來自聚矽氮類之矽石質膜幾已去除,為去除殘留之矽石質膜,以更作蝕刻處理為佳。蝕刻處理一般係用蝕刻液,蝕刻液者若可去除矽石質膜即無特殊限制,通常係用含氟化銨之氟酸水溶液。此水溶液之氟化銨濃度以5%以上為佳,30%以上更佳。
由習知方法形成之溝槽隔離構造,溝內外部之矽石質膜膜質不同。因此,這些研磨或蝕刻等基板處理之際,會有溝部發生凹陷,最終製品品質惡化。而依本發明方法之溝槽隔離構造因膜質均勻,可製造具所欲性能之製品。
依本發明,附有矽石質膜之基板係由上述溝槽隔離構造形成法為例所說明之矽石質膜製造法所製造。如此之附有矽石質膜之基板,因矽石質膜之膜質到處均勻,機械強度亦均勻,施以蝕刻、研磨等加工之際仍保有均勻性及平坦性,可得優良最終製品。
以下舉STI(淺溝槽隔離)構造之元件分離溝埋設技術之實施例參照第1圖說明本發明。
首先,準備構造如第1圖之評估用有溝樣本。此有溝樣本具有,於矽基板1上面沈積例如150nm之氮化矽(SiN)膜2後,利用微影技術及乾式蝕刻技術形成之溝(圖示5條溝)。此時5條溝之寬度全係例如80nm至400nm,深度全係例如450nm(矽基板部分之深度為300nm)。
然後於如此構造之有溝樣本上,以TEOS用作矽源,藉電漿化學析出(電漿TEOS)技術沈積20nm之二氧化矽膜3。
利用上述電漿TEOS技術形成二氧化矽膜3之際,成膜條件如下。亦即,TEOS/O2
氣體流量及源功率/偏壓功率條件為TEOS/O2
=55/110sccm,SRF/BRF=4400/2600W,基板溫度350℃。
由SIMS分析及TDS測定,確認上述電漿TEOS膜中含過剩之氫。具體言之,由SIMS分析確認膜中約含氫2×102 1
atoms/cm3
,由TDS分析知真空中350℃左右氫自膜釋出,確認此膜含氫。
其次調製聚矽氮類溶液。於內容積2升之四口燒瓶裝配氣體吹入管、機械攪拌機、杜瓦冷凝器。反應器內部以乾燥氮取代後,於四口燒瓶注入乾燥吡啶1500ml,以油浴保溫於20℃。其次加二氯矽烷100g生成白色固態加成物(SiH2
Cl2
.2C5
H5
N)。將反應混合物冰冷,攪拌下緩慢吹入氨70g。持續以乾燥氮吹入液相30分鐘,去除剩餘之氨。
得到之產物以瓷漏斗於乾燥氮氛圍下減壓過濾,得濾液1200ml。利用蒸發器餾除吡啶,得全氫聚矽氮類45g。
將此全氫聚矽氮類溶解於經分子篩充分乾燥之二丁醚,調製濃度20%之溶液。以過濾精度50nm之PTFE濾器過濾得聚矽氮類溶液。
以如此得之聚矽氮類溶液旋塗形成聚矽氮類塗膜4。旋塗條件係主旋轉2000rpm/30秒。
其次,形成之聚矽氮類塗膜4於含水蒸氣之氧化氛圍下作熱處理。具體言之係首先以400℃之H2
O氛圍(H2
O濃度50%,載氣為氧)加熱處理30分鐘後,以700℃之N2
氛圍加熱處理30分鐘。此熱處理係用光洋熱系統公司製之氧化爐VF-1000。
藉此形成構造如第1圖之樣本。
如同實施例1之樣本,取代第1圖之電漿TEOS膜改由電漿化學析出法(PE-CVD)沈積氮化矽膜20nm。
利用上述PE-CVD技術形成氮化矽膜3之際,成膜條件如下。亦即,SiH4
/NH3
氣體流量及源功率/偏壓功率條件為SiH4
/NH3
=55/110sccm,SRF/BRF=4400/2600W,基板溫度400℃。
經SIMS分析及TDS測定,確認上述電漿PE-CVD膜中含過剩之氫。具體言之由SIMS分析確認膜中約含氫1×102 1
atoms/cm3
,由TDS分析知真空中350℃左右有氫自膜釋出,確認含氫。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
如同實施例1之樣本,取代第1圖之電漿TEOS膜改由低壓CVD法沈積形成氮化矽膜(LP-CVD氮化矽膜)20nm。
利用上述LP-CVD技術形成氮化矽膜3(絕緣膜)之際,成膜條件如下。亦即,SiH4
/NH3
氣體流量為SiH4
/NH3
=55/110sccm,基板溫度700℃。
上述LP-CVD氮化矽膜係含氫量低之優質氮化矽膜,可由全膜之SIMS分析及TDS分析確認。亦即,由SIMS分析知膜中含氫約1×102 0
atoms/cm3
,TDS分析則真空中至700℃之條件下除吸附水分以外仍無特定氣體釋出,乃不含可釋出之氫。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
如同實施例1以電漿TEOS技術沈積20nm之二氧化矽膜3後,至此構造之樣本一度於氮氛圍中以700℃退火。上述退火後之電漿TEOS膜少量含氫,係由全膜之SIMS分析及TDS分析確認。亦即,由SIMS分析知膜中含氫約8×102 0
atoms/cm3
,TDS分析則真空中至700℃之條件下除吸附水分以外仍無特定氣體釋出,知不含可釋出之氫。
應係經退火處理,於電漿TEOS成膜時高含量之氫釋出。聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
之後測定上述4樣本之折射率,其值各如下。
實施例1 1.447實施例2 1.448比較例1 1.445比較例2 1.444
由此結果確認,所有樣本之聚矽氮類塗膜4已轉化為二氧化矽膜。
構造如同實施例1之樣本,取代第1圖之電漿TEOS膜改由以SiH4
及O2
為源之電漿化學析出法沈積二氧化矽膜20nm。
形成上述二氧化矽膜3之際,成膜條件如下。亦即,SiH4
/O2
氣體流量及源功率/偏壓功率條件為SiH4
/O2
=50/100sccm,SRF/BRF=4500/3000W,基板溫度250。C。
由SIMS分析及TDS測定,確認上述二氧化矽膜中含過剩之氫。具體言之由SIMS分析可確認膜中約含氫1.5×102 1
atoms/cm3
。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
構造如同實施例1之樣本,取代第1圖之電漿TEOS膜改由以SiH4
及O2
為源之電漿化學析出法沈積二氧化矽膜20 nm。
形成上述二氧化矽膜3之際,成膜條件如下。亦即,SiH4
/O2
氣體流量為SiH4
/O2
=50/100sccm,基板溫度700℃,壓力1Torr。
由SIMS分析及TDS測定,確認上述二氧化矽膜中含過剩之氫。具體言之由SIMS分析可確認膜中約含氫1.1×102 1
atoms/cm3
。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
構造如同實施例1之樣本,取代第1圖之電漿TEOS膜改由以TEOS及O2
為源之低壓化學析出法沈積二氧化矽膜20 nm。
形成上述二氧化矽膜3之際,成膜條件如下。亦即,TEOS/O2
氣體流量為TEOS/O2
=50/100sccm,基板溫度700℃,壓力1Torr。
由SIMS分析及TDS測定,確認上述二氧化矽膜中含過剩之氫。具體言之由SIMS分析可確認膜中約含氫1.2×102 1
atoms/cm3
。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
構造如同實施例1之樣本,取代實施例1之電漿TEOS膜改由以SiH4
及N2
O為源之快速熱蒸鍍法沈積二氧化矽膜20 nm。
形成上述二氧化矽膜3之際,成膜條件如下。亦即,SiH4
/N2
O氣體流量條件為SiH4
/N2
O=10/250sccm,基板溫度800℃。
由SIMS分析及TDS測定,確認上述二氧化矽膜中含過剩之氫。具體言之由SIMS分析可確認膜中約含氫1.2×102 1
atoms/cm3
。
聚矽氮類溶液之製膜及熱處理係以如同實施例1之條件施行。
首先,沿垂直於溝長方向切斷基板,切面之溝部分使用日立製作所製之S-4600型SEM以倍率100,000倍自垂直方向觀察,測定第2圖(蝕刻前)之含絕緣膜之有溝基板5至矽石質膜6表面之長度(a)。
其次,將沿垂直於溝長方向切斷之基板在20℃浸泡於含0.5重量%氟化氫及5重量%氟化銨之水溶液1分鐘,以純水充分洗淨並乾燥。然後,切面之溝部分使用上述SEM以倍率100,000倍首先自切面垂直方向觀察,測定第3圖(蝕刻後1)之長度(b),亦即含絕緣膜之有溝基板5至矽石質膜6表面之厚度。
繼之同樣切面之溝部分使用上述SEM以倍率200,000倍自切面垂直方向之仰角30度上方觀察溝最深部並攝影,由相片上之長度以三角法算出蝕刻長度(c)。參照第4圖(蝕刻後2)。
因溝最深部之蝕刻長度(c)隨溝寬(長寬比)而異,於4種寬度之溝(80、100、200及400nm)各作測定。
微細溝內部之蝕刻率(A)及溝外部之蝕刻率(B)各利用得到之(a)、(b)及(c)依以下方法計算求出。
(A)=(c)(B)=(a)-(b)
蝕刻後界面狀態係以溝內部:第4圖(蝕刻後2)之斜線部分之SEM相片評估是否平滑。因蝕刻之界面狀態隨溝寬(長寬比)而異,於4種寬度之溝(80、100、200及400nm)各作評估。
由以上方法測定之結果如表1。
實施例1、2及比較例1、2之樣本,聚矽氮類製膜、熱處理後更以SIMS分析確認深度方向之元素分佈,結果實施例1、2確認有氫自(含過剩氫之)絕緣膜3移往聚矽氮類塗膜4。(例如,實施例1之樣本自2×102 1
atoms/cm3
變為6×102 0
atoms/cm3
)。反之,確認有氮自聚矽氮類塗膜4移往(含過剩氫之)絕緣膜3(自1×101 8
atoms/cm3
變為1×102 0
atoms/cm3
)。
而比較例1及2中,氫、氮之任一皆不移動,蝕刻特性沿深度方向之分佈亦大,故聚矽氮類之熱處理時過剩氫自P-TEOS或PE-CVD氮化矽膜之釋出及移動,及/或氮自聚矽氮類往P-TEOS或PE-CVD氮化矽膜之釋出及移動,應於聚矽氮類塗膜4之轉化為均質氧化膜有效。
1...矽基板
2...氮化矽膜
3...絕緣膜
4...聚矽氮類塗膜
5...含絕緣膜之有溝基板
6...矽石質膜
第1圖依本發明製造之溝槽隔離構造切面圖。
第2圖實施例之溝槽隔離構造說明用切面圖(蝕刻前)。
第3圖實施例之溝槽隔離構造說明用切面圖(蝕刻後)。
第4圖實施例之溝槽隔離構造說明用切面圖(蝕刻後)。
1...矽基板
2...氮化矽膜
3...絕緣膜
4...聚矽氮類塗膜
Claims (7)
- 一種矽石質膜之製法,其特徵為包含於具凹凸之矽基板表面上形成絕緣膜之絕緣膜形成步驟,其中該絕緣膜係由電漿化學氣相沈積法形成之氮化矽膜且由二次離子質量分析測定之含氫量係9×1020 atoms/cm3 以上;以含聚矽氮類化合物之組成物塗於上述基板之塗敷步驟;及加熱處理經塗敷之基板使聚矽氮類化合物轉化為二氧化矽膜之硬化步驟。
- 如申請專利範圍第1項之矽石質膜之製法,其中絕緣膜係由使用四乙氧矽烷之電漿化學氣相沈積法形成之二氧化矽膜。
- 如申請專利範圍第1項之矽石質膜之製法,其中加熱處理係於水蒸氣濃度1%以上之惰性氣體或氧氛圍下施行。
- 如申請專利範圍第1項之矽石質膜之製法,其中加熱處理之加熱溫度係400℃以上1,200℃以下。
- 如申請專利範圍第1~4項中任一項之矽石質膜之製法,其中絕緣膜之厚度在1~100nm。
- 一種溝槽隔離構造之形成法,其特徵為具凹凸之矽基板係溝槽隔離構造形成用之有溝基板,由如申請專利範圍 第1~5項中任一項之方法將上述溝予以埋封。
- 一種附有矽石質膜之基板,其特徵為具備由如申請專利範圍第1項之方法形成之矽石質膜。
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