WO2014061820A1 - 固体撮像素子 - Google Patents
固体撮像素子 Download PDFInfo
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- WO2014061820A1 WO2014061820A1 PCT/JP2013/078483 JP2013078483W WO2014061820A1 WO 2014061820 A1 WO2014061820 A1 WO 2014061820A1 JP 2013078483 W JP2013078483 W JP 2013078483W WO 2014061820 A1 WO2014061820 A1 WO 2014061820A1
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- photoelectric conversion
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- transfer gate
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- gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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Definitions
- the present invention relates to a solid-state imaging device.
- solid state image sensors such as CMOS image sensors
- video cameras and digital cameras are used.
- pixels including a photoelectric conversion unit that generates charges according to the amount of incident light are usually provided in a matrix.
- a solid-state imaging device one having one photoelectric conversion unit per pixel or one having two or more photoelectric conversion units per pixel is known (see Patent Document 1).
- each photoelectric conversion unit is transferred to the corresponding FD (floating diffusion) region through the transfer gate.
- the electric charge is converted into a voltage corresponding to the capacity of the FD region, and this voltage signal is read out as a photoelectric conversion signal.
- the solid-state imaging device includes a first pixel in which a first photoelectric conversion unit and a second photoelectric conversion unit are arranged in a first direction, a third photoelectric conversion unit, and a fourth photoelectric conversion unit.
- a second pixel lined up in the second direction, a first transfer gate that transfers the signal charge generated by the first photoelectric conversion unit to the first charge voltage conversion unit, and a second photoelectric conversion unit.
- the at least one transfer gate includes a first charge-voltage converter, a second power Voltage converter, the third charge-voltage converter, and the fourth to align the voltage conversion efficiency by the charge-voltage converter, the gate width, at least one of the gate length or position different.
- the first direction and the second direction are orthogonal to each other.
- the first transfer gate and the second transfer gate are configured with substantially the same gate width or gate length, and the third transfer gate.
- the fourth transfer gate are configured with substantially the same gate width or gate length, the arrangement positions of the first transfer gate and the second transfer gate in the first pixel, and the second transfer gate and the second transfer gate The arrangement positions in the pixels are preferably substantially the same.
- the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit have substantially the same size.
- the first transfer gate and the second transfer gate are arranged on the long sides of the first photoelectric conversion unit and the second photoelectric conversion unit, respectively.
- the third photoelectric conversion unit and the fourth photoelectric conversion unit are arranged. It is preferable that a third transfer gate and a fourth transfer gate are respectively disposed on the short side of the photoelectric conversion unit.
- the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit have substantially the same size.
- the first transfer gate and the second transfer gate are arranged at diagonal corners of the first pixel, and the third transfer gate and the fourth transfer gate are arranged at diagonal corners of the second pixel. It is preferable.
- the arrangement positions of the first transfer gate and the second transfer gate in the first pixel, and the third transfer gate and the fourth transfer gate are provided in the first or second aspect.
- the arrangement position in the second pixel is different, the gate width or gate length of the transfer gate composed of the first transfer gate and the second transfer gate, and the transfer gate composed of the third transfer gate and the fourth transfer gate.
- the gate width or the gate length is the length of the side of the first photoelectric conversion unit and the second photoelectric conversion unit where the first transfer gate and the second transfer gate are arranged, and the third transfer gate and the fourth transfer gate are arranged. It is preferable that the length differs depending on the side lengths of the third photoelectric conversion unit and the fourth photoelectric conversion unit.
- the solid-state imaging device includes a first photoelectric conversion unit having a photoelectric conversion region divided in the horizontal direction, and a charge photoelectrically converted by the first photoelectric conversion unit from the first photoelectric conversion unit.
- the first pixel including a plurality of first transfer gates transferred to the first charge-voltage converter, the second photoelectric converter having a photoelectric conversion region divided in the vertical direction, and the second photoelectric converter are photoelectrically converted.
- a second pixel including a plurality of second transfer gates for transferring charges from the second photoelectric conversion unit to the second charge voltage conversion unit, and the arrangement position of the first transfer gate in the first pixel and the second transfer gate The arrangement position in the second pixel is substantially the same.
- the solid-state imaging device includes a first photoelectric conversion unit having a photoelectric conversion region divided in the horizontal direction and a charge photoelectrically converted by the first photoelectric conversion unit from the first photoelectric conversion unit.
- the first pixel including a plurality of first transfer gates transferred to the first charge-voltage converter, the second photoelectric converter having a photoelectric conversion region divided in the vertical direction, and the second photoelectric converter are photoelectrically converted.
- a second pixel including a plurality of second transfer gates for transferring charges from the second photoelectric conversion unit to the second charge voltage conversion unit, wherein the first transfer gate and the second transfer gate are the first charge voltage conversion unit.
- the gate width or the gate length is different so that the voltage conversion efficiencies of the second charge voltage conversion units are uniform.
- FIG. 2 is a circuit diagram illustrating pixels adjacent in the vertical direction in FIG. 1.
- 4A is a plan view illustrating the case of horizontal division
- FIG. 4B is a plan view illustrating the case of vertical division.
- FIG. 5A is a plan view illustrating the case of horizontal division according to Modification 1.
- FIG. 5B is a plan view illustrating the case of vertical division.
- FIG. 6A is a plan view illustrating the case of horizontal division according to the second embodiment
- FIG. 6B is a plan view illustrating the case of vertical division. It is a figure which compares the magnitude
- FIG. 1 is a block diagram illustrating a digital camera 1 equipped with a solid-state imaging device 3 according to the first embodiment of the invention.
- the digital camera 1 is equipped with a photographing lens 2 as an imaging optical system.
- the focusing lens and the diaphragm are driven and controlled by the lens control unit 2 a that receives an instruction from the microprocessor 9.
- the photographing lens 2 forms a subject image on the imaging surface of the solid-state imaging device 3.
- the solid-state imaging device 3 photoelectrically converts the subject image based on the drive signal from the imaging control unit 4 that has received an instruction from the microprocessor 9.
- the photoelectric conversion signal output from the solid-state imaging device 3 is processed through the signal processing unit 5 and the A / D conversion unit 6 and then temporarily stored in the memory 7.
- Connected to the bus 8 are a lens control unit 2a, an imaging control unit 4, a memory 7, a microprocessor 9, a focus calculation unit (detection processing unit) 10, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. .
- the microprocessor 9 receives an operation signal from an operation unit 9a such as a release button.
- the microprocessor 9 sends an instruction to each block based on the operation signal from the operation unit 9a, and controls the photographing operation of the digital camera 1.
- the focus calculation unit 10 detects a focus adjustment state (specifically, a defocus amount) by the imaging lens 2 by performing a phase difference detection calculation using an output signal from a pixel formed in the solid-state imaging device 3. To do. Since this phase difference detection calculation is the same as that disclosed in Japanese Patent Application Laid-Open No. 2007-317951, description thereof is omitted.
- the microprocessor 9 instructs the lens control unit 2a to drive the focusing lens according to the defocus amount.
- the image processing unit 13 performs predetermined image processing on the photoelectric conversion signal stored in the memory 7.
- the image compression unit 12 compresses the image data after image processing in a predetermined format.
- the recording unit 11 records the compressed image data on the recording medium 11a in a predetermined file format.
- the recording medium 11 a is configured by a memory card that is detachable from the recording unit 11.
- FIG. 2 is a diagram illustrating a schematic configuration of the solid-state imaging device 3.
- the solid-state imaging device 3 includes a plurality of pixels 20 arranged in a matrix and a peripheral circuit for outputting a signal from each pixel 20.
- the imaging area 31 is an area where the pixels 20 are arranged in a matrix. In the example of FIG. 2, a range of 16 pixels of 4 rows horizontally and 4 columns vertically is illustrated as the imaging region 31, but the actual number of pixels is much larger than that illustrated in FIG. 2.
- the solid-state imaging device 3 is provided with two photoelectric conversion units in each pixel 20.
- two photoelectric conversion units are provided for each pixel in the solid-state imaging device 3 in which the pixels are arranged in the horizontal and vertical directions
- two photoelectric conversion units are provided when the two photoelectric conversion units are arranged in the horizontal direction (referred to as horizontal division).
- horizontal division Exist in a vertical direction (referred to as vertical division).
- horizontally divided pixels are arranged over the entire imaging region 31.
- vertical division pixels are arranged in a predetermined area instead of horizontal division pixels.
- the horizontal division pixel and the vertical division pixel are not distinguished from each other and are denoted by a common reference numeral 20.
- Each pixel 20 performs photoelectric conversion according to the drive signal from the peripheral circuit, and outputs a photoelectric conversion signal.
- the peripheral circuits are connected to the vertical scanning circuit 21, the horizontal scanning circuit 22, drive signal lines 23 and 24 connected thereto, a vertical signal line 25 that receives a signal from the pixel 20, and a vertical signal line 25.
- a constant current source 26 a correlated double sampling circuit (CDS circuit) 27, a horizontal signal line 28 that receives a signal output from the CDS circuit 27, an output amplifier 29, and the like.
- CDS circuit correlated double sampling circuit
- the vertical scanning circuit 21 and the horizontal scanning circuit 22 output a predetermined drive signal in response to an instruction from the imaging control unit 4.
- Each pixel 20 is driven by a drive signal output from the vertical scanning circuit 21 and outputs a photoelectric conversion signal to the vertical signal line 25.
- the signal output from the pixel 20 is subjected to noise removal by the CDS circuit 27, and output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal from the horizontal scanning circuit 22.
- FIG. 3 is a circuit diagram illustrating the pixels 20n and 20 (n + 1) adjacent in the vertical direction in FIG.
- a pixel 20n has two photodiodes PDn1 and PDn2 as photoelectric conversion portions inside a microlens (not shown).
- the pixel 20 (n + 1) includes two photodiodes PDn (n + 1) 1 and PD (n + 1) 2 as photoelectric conversion units inside a microlens (not shown).
- the pixel 20 has a horizontal division and a vertical division, both of which are the same as shown in the circuit diagram.
- the photodiodes PDn1 and PDn2 each generate a charge corresponding to incident light.
- the signal charge generated by the photodiode PDn1 is transferred to the FD (floating diffusion) region located on the vertical signal line 25A side via the transfer gate Txn1.
- the FD region receives a signal charge and converts the signal charge into a voltage.
- a signal corresponding to the potential of the FD region is amplified by the amplification transistor AMP. Then, it is read out through the vertical signal line 25A as the signal of the “row” selected by the “row” selection transistor SEL.
- the reset transistor RST operates as a reset unit that resets the potential of the FD region.
- the signal charge generated by the photodiode PDn2 of the pixel 20n is transferred to the FD (floating diffusion) region located on the vertical signal line 25B side via the transfer gate Txn2.
- the FD region receives a signal charge and converts the signal charge into a voltage.
- a signal corresponding to the potential of the FD region is amplified by the amplification transistor AMP.
- a “row” signal selected by the “row” selection transistor SEL is read out via the vertical signal line 25B.
- the reset transistor RST operates as a reset unit that resets the potential of the FD region.
- the photodiodes PD (n + 1) 1 and PD (n + 1) 2 each generate a charge corresponding to incident light. Reading of a signal based on the generated electric charge is the same as in the case of the pixel 20n described above. Note that switching of the “row” selection transistor SEL is performed by a drive signal output from the vertical scanning circuit 21.
- FIG. 4 is a plan view illustrating pixels 20n and 20 (n + 1) adjacent in the vertical direction in the solid-state imaging device 3.
- FIG. 4A is a diagram illustrating the case of horizontal division
- FIG. 4B is a diagram illustrating the case of vertical division.
- the photodiodes PDn1 and PDn2 located on the left and right of the pixel 20n have substantially the same shape and size.
- the shape and size of the photodiodes PD (n + 1) 1 and PD (n + 1) 2 located on the left and right of the pixel 20 (n + 1) are substantially the same.
- the shape and size of the photodiodes PDn1 and PDn2 of the pixel 20n are substantially the same as the shape and size of the photodiodes PD (n + 1) 1 and PD (n + 1) 2 of the pixel 20 (n + 1). That is, the configuration of the horizontally divided pixels 20 is substantially the same as the other horizontally divided pixels 20.
- the photodiode PDn1 of the pixel 20n and the photodiode PD (n + 1) 1 of the pixel 20 (n + 1) include the FD region, the reset transistor RST, the “row” selection transistor SEL on the vertical signal line 25A side, and The amplification transistor AMP is shared.
- the photodiode PDn2 of the pixel 20n and the photodiode PD (n + 1) 2 of the pixel 20 (n + 1) include an FD region, a reset transistor RST, a “row” selection transistor SEL, and an amplification transistor AMP on the vertical signal line 25B side. Share As described above, the mounting efficiency of the solid-state imaging device 3 is increased by sharing a plurality of transistors between pixels adjacent in the vertical direction.
- the shapes and sizes of the photodiodes PDn1 and PDn2 located above and below the pixel 20n are substantially the same.
- the photodiodes PD (n + 1) 1 and PD (n + 1) 2 located above and below the pixel 20 (n + 1) have substantially the same shape and size.
- the shape and size of the photodiodes PDn1 and PDn2 of the pixel 20n are substantially the same as the shape and size of the photodiodes PD (n + 1) 1 and PD (n + 1) 2 of the pixel 20 (n + 1). That is, the configuration of the vertically divided pixels 20 is substantially the same as the other vertically divided pixels 20.
- the shape and size of the photodiodes PDn1, PDn2, PD (n + 1) 1, and PD (n + 1) 2 are substantially the same in the case of FIG. 4A and FIG. 4B. It is. That is, in the present embodiment, the shape and size of each pixel 20, that is, the shape and size of the two photodiodes that each pixel 20 has are substantially the same regardless of horizontal division or vertical division.
- the photodiode PDn1 of the pixel 20n and the photodiode PD (n + 1) 1 of the pixel 20 (n + 1) are arranged on the vertical signal line 25A side.
- the FD region, the reset transistor RST, the “row” selection transistor SEL, and the amplification transistor AMP are shared.
- the photodiode PDn2 of the pixel 20n and the photodiode PD (n + 1) 2 of the pixel 20 (n + 1) include an FD region, a reset transistor RST, a “row” selection transistor SEL, and an amplification transistor AMP on the vertical signal line 25B side. Share
- the feature of the first embodiment is that the arrangement positions of transfer gates arranged in the photodiodes in the same pixel are different, so that the horizontal division (FIG. 4 (a)) and the vertical division (FIG. 4). 4 (b)), the gate width and gate length size and shape of the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 as a whole are configured in common. It is.
- the common arrangement position means that the position coordinates of the transfer gate Tx as seen from the reference position of the pixel (for example, the pixel center that is the intersection of the diagonal lines of the square pixels) match in each pixel. That is, regardless of the horizontal division (FIG. 4A) and the vertical division (FIG.
- the corresponding transfer gates Tx have the same size, the same orientation, and the same position ( They are provided at predetermined positions on the upper right and lower left of the pixel 20.
- the positions of the transfer gates Tx are the same in each pixel 20, the conditions for transferring the charge Q from the two photodiodes PD to the FD region are equal in all the pixels 20.
- the parasitic capacitances existing in the transfer gate Tx are substantially equal, the capacitance on the FD region side (the total of the capacitors in the FD region and the parasitic capacitance existing in the transfer gate Tx) is substantially the same in all the pixels 20. It is done.
- the size of the two photodiodes in the pixel is substantially the same regardless of the horizontal division or the vertical division, so that the same amount of light is incident on the photodiode PD.
- the charge Q generated in each photodiode PD becomes substantially equal.
- Suppressing variation in photoelectric conversion signals from a plurality of photoelectric conversion units is equivalent to suppressing variation in charge-voltage conversion efficiency.
- the solid-state imaging device 3 includes a first pixel (horizontal division) in which a first photoelectric conversion unit PDn1 and a second photoelectric conversion unit PDn2 are arranged in the horizontal direction, a third photoelectric conversion unit PDn1, and a fourth photoelectric conversion unit PDn2.
- the third transfer gate Txn1 that transfers the signal charge generated by the three photoelectric conversion units PDn1 to the third charge voltage conversion unit (FD region) and the signal charges generated by the fourth photoelectric conversion unit PDn2 of the second pixel 4-charge voltage converter
- PDn1, second photoelectric conversion unit PDn2, third photoelectric conversion unit PDn1, and fourth photoelectric conversion unit PDn2 are arranged respectively. Thereby, regardless of the horizontal division (first pixel) and the vertical division (second pixel), variations in photoelectric conversion signals from the plurality of photoelectric conversion units are suppressed.
- the first transfer gate Txn1 and the second transfer gate Txn2 of the first pixel are configured with substantially the same gate width and gate length
- the second The third transfer gate Txn1 and the fourth transfer gate Txn2 of the pixel are configured with substantially the same gate width and gate length
- the arrangement positions of the first transfer gate Txn1 and the second transfer gate Txn2 in the first pixel horizontal division
- the arrangement positions of the third transfer gate Txn1 and the fourth transfer gate Txn2 in the second pixel are substantially the same.
- the fourth photoelectric conversion unit PDn2 of the pixel is configured to have substantially the same size, and in the first pixel, the first transfer gate Txn1 and the second transfer gate are arranged on the long sides of the first photoelectric conversion unit PDn1 and the second photoelectric conversion unit PDn2, respectively.
- Txn2 is arranged, and in the second pixel, the third transfer gate Txn1 and the fourth transfer gate Txn2 are arranged on the short sides of the third photoelectric conversion unit PDn1 and the fourth photoelectric conversion unit PDn2, respectively. Thereby, regardless of the horizontal division and the vertical division, variations in photoelectric conversion signals from the plurality of photoelectric conversion units can be suppressed.
- the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 of the first pixel are respectively rectangular photodiodes PDn1. , PDn2, PD (n + 1) 1, and PD (n + 1) 2 are provided on the long side.
- the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 of the second pixel are rectangular photodiodes PDn1 and PDn2, respectively.
- PD (n + 1) 1 and PD (n + 1) 2 are provided on the short side.
- the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 are respectively set.
- the photodiodes PDn1, PDn2, PD (n + 1) 1, and PD (n + 1) 2 may be provided at the corners.
- FIG. 5 is a plan view for explaining the pixels 20n and 20 (n + 1) in the first modification.
- FIG. 5A is a diagram illustrating the case of horizontal division (first pixel)
- FIG. 5B is a diagram illustrating the case of vertical division (second pixel).
- the arrangement positions of the transfer gates Tx and the angles of the transfer gates Tx with respect to the photodiode PD are different.
- Transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 are placed at the corners of the photodiodes PDn1, PDn2, PD (n + 1) 1, PD (n + 1) 2, and 45 degrees with respect to the photodiode PD.
- the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 are provided regardless of the horizontal division (first pixel) and the vertical division (second pixel).
- the photodiodes PDn1, PDn2, PD (n + 1) 1, and PD (n + 1) 2 are provided at a portion (corner) sandwiched between the long side and the short side at a common angle (45 degrees).
- the condition for transferring the charge Q from the two photodiodes PD to the FD region, and the capacitance on the FD region side is made substantially the same. That is, variations in photoelectric conversion signals from a plurality of photoelectric conversion units can be suppressed regardless of horizontal division or vertical division.
- FIG. 6 is a plan view for explaining the pixels 20n and 20 (n + 1) in the second embodiment.
- FIG. 6A is a diagram illustrating the case of horizontal division
- FIG. 6B is a diagram illustrating the case of vertical division.
- the arrangement of the transfer gates Txn1 *, Txn2 *, Tx (n + 1) 1 *, and Tx (n + 1) 2 * of FIG. Installation position and size are different.
- the content of FIG. 6B in the case of the vertical division is the same as FIG. 4B of the first embodiment.
- transfer gates Txn1 *, Txn2 *, Tx (n + 1) 1 *, and Tx (n + 1) 2 * are the lengths of the photodiodes PDn1, PDn2, PD (n + 1) 1, and PD (n + 1) 2, respectively. It is provided at the center of the side.
- transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) are the centers of the short sides of the photodiodes PDn1, PDn2, PD (n + 1) 1, and PD (n + 1) 2, respectively.
- the gate width or gate length of the transfer gates Txn1, Txn2, Tx (n + 1) 1, and Tx (n + 1) 2 is different between the horizontal division and the vertical division.
- FIG. 7 is a diagram for comparing the gate width or gate length of the transfer gate Tx between the horizontal division and the vertical division.
- the gate width W1 and gate length L1 of the transfer gate Tx * in the horizontal division are longer than the gate width W2 and gate length L2 of the transfer gate Tx in the vertical division, respectively.
- the shape of the transfer gate Tx * is adjusted to the size of the photodiode PD.
- the shape of the transfer gate Tx * is changed in the case of horizontal division than in the case of vertical division. Enlarge.
- the reason is as follows.
- the transfer gate is arranged in the approximate center of the long side of the photodiode PD, the charge Q existing near the transfer gate is smaller than in the case where the transfer gate is arranged in the approximate center of the short side of the photodiode PD. Many. For this reason, by ensuring a large transfer gate, it is possible to efficiently transfer at the time of charge transfer, so that it is possible to avoid the occurrence of transfer failure.
- the solid-state imaging device 3 includes a first pixel (horizontal division) in which a first photoelectric conversion unit PDn1 and a second photoelectric conversion unit PDn2 are arranged in the horizontal direction, a third photoelectric conversion unit PDn1, and a fourth photoelectric conversion unit PDn2.
- a fourth transfer gate Txn2 for transferring to the (FD region), and at least one of the first transfer gate Txn1 *, the second transfer gate Txn2 *, the third transfer gate Txn1, and the fourth transfer gate Txn2.
- the gate is converted by the first charge voltage converter (FD region), the second charge voltage converter (FD region), the third charge voltage converter (FD region), and the fourth charge voltage converter (FD region).
- the gate width or the gate length is changed to be arranged in the first photoelectric conversion unit PDn1, the second photoelectric conversion unit PDn2, the third photoelectric conversion unit PDn1, and the fourth photoelectric conversion unit PDn2, respectively. Yes. Thereby, regardless of the horizontal division (first pixel) and the vertical division (second pixel), variations in photoelectric conversion signals from the plurality of photoelectric conversion units are suppressed.
- the size of the gate is the length of the side of the first photoelectric conversion unit PDn1 and the second photoelectric conversion unit PDn2 of the first pixel in which the first transfer gate Txn1 * and the second transfer gate Txn2 * are arranged, and the third transfer gate.
- the lengths of the sides of the third photoelectric conversion unit PDn1 and the fourth photoelectric conversion unit PDn1 of the second pixel in which the Txn1 and the fourth transfer gate Txn2 are arranged Different depending on. Thereby, regardless of the horizontal division and the vertical division, variations in photoelectric conversion signals from the plurality of photoelectric conversion units can be suppressed.
- Modification 2 In the second embodiment, the example in which the shape of the transfer gate Tx in the horizontal division is larger than that in the vertical division has been described. However, the shape of the transfer gate Tx in the vertical division is larger than that in the horizontal division. By reducing the size, the variation in photoelectric conversion signals from a plurality of photoelectric conversion units may be suppressed in the horizontal division and the vertical division.
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Abstract
Description
本発明の第2の態様によると、第1の態様の固体撮像素子において、第1方向と第2方向とは、互いに直交していることが好ましい。
本発明の第3の態様によると、第1または2の態様の固体撮像素子において、第1転送ゲートと第2転送ゲートとが略同じゲート幅又はゲート長で構成されるとともに、第3転送ゲートと第4転送ゲートとが略同じゲート幅又はゲート長で構成され、かつ、第1転送ゲートと第2転送ゲートの第1画素における配置位置、および第3転送ゲートと第4転送ゲートの第2画素における配置位置は、略同じであることが好ましい。
本発明の第4の態様によると、第3の態様の固体撮像素子において、第1光電変換部、第2光電変換部、第3光電変換部、および第4光電変換部が略同じ大きさに構成され、第1画素において、第1光電変換部および第2光電変換部の長辺にそれぞれ第1転送ゲートおよび第2転送ゲートが配置され、第2画素において、第3光電変換部および第4光電変換部の短辺にそれぞれ第3転送ゲートおよび第4転送ゲートが配置されていることが好ましい。
本発明の第5の態様によると、第3の態様の固体撮像素子において、第1光電変換部、第2光電変換部、第3光電変換部、および第4光電変換部が略同じ大きさに構成され、第1転送ゲートおよび第2転送ゲートは、第1画素における対角の隅部に配置され、第3転送ゲートおよび第4転送ゲートは、第2画素における対角の隅部に配置されていることが好ましい。
本発明の第6の態様によると、第1または2の態様の固体撮像素子において、第1転送ゲートと第2転送ゲートの第1画素における配置位置、および第3転送ゲートと第4転送ゲートの第2画素における配置位置が異なっており、第1転送ゲートおよび第2転送ゲートで構成される転送ゲートのゲート幅又はゲート長と、第3転送ゲートおよび第4転送ゲートで構成される転送ゲートのゲート幅又はゲート長とが、第1転送ゲートおよび第2転送ゲートが配置される第1光電変換部および第2光電変換部の辺の長さと、第3転送ゲートおよび第4転送ゲートが配置される第3光電変換部および第4光電変換部の辺の長さと、に応じて異なることが好ましい。
本発明の第7の態様によると、固体撮像素子は、水平方向に分割された光電変換領域を有する第1光電変換部と第1光電変換部で光電変換された電荷を第1光電変換部から第1電荷電圧変換部へ転送する複数の第1転送ゲートとを含む第1画素と、垂直方向に分割された光電変換領域を有する第2光電変換部と第2光電変換部で光電変換された電荷を第2光電変換部から第2電荷電圧変換部へ転送する複数の第2転送ゲートとを含む第2画素とを備え、第1転送ゲートの第1画素における配置位置と第2転送ゲートの第2画素における配置位置とは、略同一である。
本発明の第8の態様によると、固体撮像素子は、水平方向に分割された光電変換領域を有する第1光電変換部と第1光電変換部で光電変換された電荷を第1光電変換部から第1電荷電圧変換部へ転送する複数の第1転送ゲートとを含む第1画素と、垂直方向に分割された光電変換領域を有する第2光電変換部と第2光電変換部で光電変換された電荷を第2光電変換部から第2電荷電圧変換部へ転送する複数の第2転送ゲートとを含む第2画素とを備え、第1転送ゲート及び第2転送ゲートは、第1電荷電圧変換部及び第2電荷電圧変換部の電圧変換効率を揃えるように、ゲート幅又はゲート長が異なる。
(第一の実施形態)
図1は、本発明の第一の実施の形態による固体撮像素子3を搭載するデジタルカメラ1を例示するブロック図である。デジタルカメラ1には、撮像光学系として撮影レンズ2が装着される。撮影レンズ2は、マイクロプロセッサ9から指示を受けたレンズ制御部2aによって、フォーカシングレンズや絞りが駆動制御される。撮影レンズ2は、固体撮像素子3の撮像面に被写体像を結像させる。
(1)固体撮像素子3は、第1光電変換部PDn1と第2光電変換部PDn2とが水平方向に並ぶ第1画素(水平分割)と、第3光電変換部PDn1と第4光電変換部PDn2とが垂直方向に並ぶ第2画素(垂直分割)と、を有する画素部と、第1画素の第1光電変換部PDn1により生成された信号電荷を第1電荷電圧変換部(FD領域)に転送する第1転送ゲートTxn1と、第1画素の第2光電変換部PDn2により生成された信号電荷を第2電荷電圧変換部(FD領域)に転送する第2転送ゲートTxn2と、第2画素の第3光電変換部PDn1により生成された信号電荷を第3電荷電圧変換部(FD領域)に転送する第3転送ゲートTxn1と、第2画素の第4光電変換部PDn2により生成された信号電荷を第4電荷電圧変換部(FD領域)に転送する第4転送ゲートTxn2と、を備え、第1転送ゲートTxn1、第2転送ゲートTxn2、第3転送ゲートTxn1、および第4転送ゲートTxn2は、第1電荷電圧変換部(FD領域)、第2電荷電圧変換部(FD領域)、第3電荷電圧変換部(FD領域)、および第4電荷電圧変換部(FD領域)による電圧変換効率を揃えるように、第1光電変換部PDn1、第2光電変換部PDn2、第3光電変換部PDn1、および第4光電変換部PDn2にそれぞれ配置されている。これにより、水平分割の場合(第1画素)と垂直分割の場合(第2画素)とにかかわらず、複数の光電変換部からの光電変換信号のばらつきが抑えられる。
第一の実施形態では、水平分割の場合(図4(a))において、第1画素の転送ゲートTxn1、Txn2、Tx(n+1)1、Tx(n+1)2が、それぞれ長方形状のフォトダイオードPDn1、PDn2、PD(n+1)1、PD(n+1)2の長辺側に設けられる。これに対し、垂直分割の場合(図4(b))においては、第2画素の転送ゲートTxn1、Txn2、Tx(n+1)1、Tx(n+1)2が、それぞれ長方形状のフォトダイオードPDn1、PDn2、PD(n+1)1、PD(n+1)2の短辺側に設けられる。
第一の実施形態では、水平分割の場合(第1画素)と垂直分割の場合(第2画素)とにかかわらず、各画素20において同じ位置(画素の右上と左下の所定位置)に、同じ大きさおよび形状の転送ゲートTxを設けるようにした。第二の実施形態では、水平分割の場合(第1画素)と垂直分割の場合(第2画素)とで、転送ゲートTxの位置を同じにしない代わりに、転送ゲートTxのゲート幅又はゲート長の大きさ、形状を異ならせることにより、水平分割の場合と垂直分割の場合との間で、2つのフォトダイオードPDからFD領域へ電荷Qを転送する条件、およびFD領域側の容量(FD領域のキャパシタと転送ゲートTxに存在する寄生容量などの合計)を揃える。
(1)固体撮像素子3は、第1光電変換部PDn1と第2光電変換部PDn2とが水平方向に並ぶ第1画素(水平分割)と、第3光電変換部PDn1と第4光電変換部PDn2とが垂直方向に並ぶ第2画素(垂直分割)と、を有する画素部と、第1画素の第1光電変換部PDn1により生成された信号電荷を第1電荷電圧変換部(FD領域)に転送する第1ゲート部Txn1*と、第1画素の第2光電変換部PDn2により生成された信号電荷を第2電荷電圧変換部(FD領域)に転送する第2転送ゲートTxn2*と、第2画素の第3光電変換部PDn1により生成された信号電荷を第3電荷電圧変換部(FD領域)に転送する第3転送ゲートTxn1と、第2画素の第4光電変換部PDn2により生成された信号電荷を第4電荷電圧変換部(FD領域)に転送する第4転送ゲートTxn2と、を備え、第1転送ゲートTxn1*、第2転送ゲートTxn2*、第3転送ゲートTxn1、および第4転送ゲートTxn2のうち、少なくとも1つの転送ゲートは、第1電荷電圧変換部(FD領域)、第2電荷電圧変換部(FD領域)、第3電荷電圧変換部(FD領域)、および第4電荷電圧変換部(FD領域)による電圧変換効率を揃えるように、ゲート幅又はゲート長の大きさを変えて第1光電変換部PDn1、第2光電変換部PDn2、第3光電変換部PDn1、および第4光電変換部PDn2にそれぞれ配置されている。これにより、水平分割の場合(第1画素)と垂直分割の場合(第2画素)とにかかわらず、複数の光電変換部からの光電変換信号のばらつきが抑えられる。
なお、第二の実施形態においては、水平分割の場合の転送ゲートTxの形状を垂直分割の場合より大きくする例を説明したが、垂直分割の場合の転送ゲートTxの形状を水平分割の場合より小さくすることによって、水平分割の場合と垂直分割の場合とで、複数の光電変換部からの光電変換信号のばらつきを抑えるように構成してもよい。
日本国特許出願2012年第232422号(2012年10月19日出願)
3…固体撮像素子
9…マイクロプロセッサ
20…画素
21…垂直走査回路
22…水平走査回路
25、25A、25B…垂直信号線
27…CDS回路
28…水平信号線
29…出力アンプ
AMP…増幅トランジスタ
FD…フローティング拡散領域
RST…リセットトランジスタ
SEL…行選択トランジスタ
Tx…転送ゲート
Claims (8)
- 第1光電変換部と第2光電変換部とが第1方向に並ぶ第1画素と、第3光電変換部と第4光電変換部とが第2方向に並ぶ第2画素と、を有する画素部と、
前記第1光電変換部により生成された信号電荷を第1電荷電圧変換部に転送する第1転送ゲートと、
前記第2光電変換部により生成された信号電荷を第2電荷電圧変換部に転送する第2転送ゲートと、
前記第3光電変換部により生成された信号電荷を第3電荷電圧変換部に転送する第3転送ゲートと、
前記第4光電変換部により生成された信号電荷を第4電荷電圧変換部に転送する第4転送ゲートと、を備え、
前記第1転送ゲート、前記第2転送ゲート、前記第3転送ゲート、および前記第4転送ゲートのうち、少なくとも1つの転送ゲートは、前記第1電荷電圧変換部、前記第2電荷電圧変換部、前記第3電荷電圧変換部、および前記第4電荷電圧変換部による電圧変換効率を揃えるように、ゲート幅、ゲート長または配置位置の少なくとも1つが異なる固体撮像素子。 - 請求項1に記載の固体撮像素子において、
前記第1方向と前記第2方向とは、互いに直交している固体撮像素子。 - 請求項1または2に記載の固体撮像素子において、
前記第1転送ゲートと前記第2転送ゲートとが略同じゲート幅又はゲート長で構成されるとともに、前記第3転送ゲートと前記第4転送ゲートとが略同じゲート幅又はゲート長で構成され、かつ、前記第1転送ゲートと前記第2転送ゲートの前記第1画素における配置位置、および前記第3転送ゲートと前記第4転送ゲートの前記第2画素における配置位置は、略同じである固体撮像素子。 - 請求項3に記載の固体撮像素子において、
前記第1光電変換部、前記第2光電変換部、前記第3光電変換部、および前記第4光電変換部が略同じ大きさに構成され、
前記第1画素において、前記第1光電変換部および前記第2光電変換部の長辺にそれぞれ前記第1転送ゲートおよび前記第2転送ゲートが配置され、前記第2画素において、前記第3光電変換部および前記第4光電変換部の短辺にそれぞれ前記第3転送ゲートおよび前記第4転送ゲートが配置されている固体撮像素子。 - 請求項3に記載の固体撮像素子において、
前記第1光電変換部、前記第2光電変換部、前記第3光電変換部、および前記第4光電変換部が略同じ大きさに構成され、
前記第1転送ゲートおよび前記第2転送ゲートは、前記第1画素における対角の隅部に配置され、前記第3転送ゲートおよび前記第4転送ゲートは、前記第2画素における対角の隅部に配置されている固体撮像素子。 - 請求項1または2に記載の固体撮像素子において、
前記第1転送ゲートと前記第2転送ゲートの前記第1画素における配置位置、および前記第3転送ゲートと前記第4転送ゲートの前記第2画素における配置位置が異なっており、
前記第1転送ゲートおよび前記第2転送ゲートで構成される転送ゲートのゲート幅又はゲート長と、前記第3転送ゲートおよび前記第4転送ゲートで構成される転送ゲートのゲート幅又はゲート長とが、前記第1転送ゲートおよび前記第2転送ゲートが配置される前記第1光電変換部および前記第2光電変換部の辺の長さと、前記第3転送ゲートおよび前記第4転送ゲートが配置される前記第3光電変換部および前記第4光電変換部の辺の長さと、に応じて異なる固体撮像素子。 - 水平方向に分割された光電変換領域を有する第1光電変換部と前記第1光電変換部で光電変換された電荷を前記第1光電変換部から第1電荷電圧変換部へ転送する複数の第1転送ゲートとを含む第1画素と、
垂直方向に分割された光電変換領域を有する第2光電変換部と前記第2光電変換部で光電変換された電荷を前記第2光電変換部から第2電荷電圧変換部へ転送する複数の第2転送ゲートとを含む第2画素と、を備え、
前記第1転送ゲートの前記第1画素における配置位置と前記第2転送ゲートの前記第2画素における配置位置とは、略同一である固体撮像素子。 - 水平方向に分割された光電変換領域を有する第1光電変換部と前記第1光電変換部で光電変換された電荷を前記第1光電変換部から第1電荷電圧変換部へ転送する複数の第1転送ゲートとを含む第1画素と、
垂直方向に分割された光電変換領域を有する第2光電変換部と前記第2光電変換部で光電変換された電荷を前記第2光電変換部から第2電荷電圧変換部へ転送する複数の第2転送ゲートとを含む第2画素と、を備え、
前記第1転送ゲート及び前記第2転送ゲートは、前記第1電荷電圧変換部及び前記第2電荷電圧変換部の電圧変換効率を揃えるように、ゲート幅又はゲート長が異なる固体撮像素子。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/436,133 US9620558B2 (en) | 2012-10-19 | 2013-10-21 | Solid-state image sensor |
CN201380066713.1A CN104871315B (zh) | 2012-10-19 | 2013-10-21 | 固态摄像元件 |
EP13846627.1A EP2911203B1 (en) | 2012-10-19 | 2013-10-21 | Solid-state image pickup element |
KR1020157013034A KR102125673B1 (ko) | 2012-10-19 | 2013-10-21 | 고체 촬상 소자 |
JP2014542210A JP6135677B2 (ja) | 2012-10-19 | 2013-10-21 | 撮像素子および撮像装置 |
IN4192DEN2015 IN2015DN04192A (ja) | 2012-10-19 | 2015-05-15 | |
US15/447,756 US10038020B2 (en) | 2012-10-19 | 2017-03-02 | Solid-state image sensor |
US16/025,151 US10580810B2 (en) | 2012-10-19 | 2018-07-02 | Solid-state image sensor |
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KR102437162B1 (ko) * | 2015-10-12 | 2022-08-29 | 삼성전자주식회사 | 이미지 센서 |
JP6889571B2 (ja) | 2017-02-24 | 2021-06-18 | キヤノン株式会社 | 撮像装置および撮像システム |
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US10580810B2 (en) | 2020-03-03 |
IN2015DN04192A (ja) | 2015-10-16 |
JP2017135422A (ja) | 2017-08-03 |
CN104871315A (zh) | 2015-08-26 |
US9620558B2 (en) | 2017-04-11 |
JPWO2014061820A1 (ja) | 2016-09-05 |
KR20150070376A (ko) | 2015-06-24 |
US20170179175A1 (en) | 2017-06-22 |
CN108551559B (zh) | 2021-06-22 |
CN108551558B (zh) | 2021-03-09 |
US10038020B2 (en) | 2018-07-31 |
EP2911203A4 (en) | 2016-09-14 |
KR102125673B1 (ko) | 2020-06-23 |
CN108551558A (zh) | 2018-09-18 |
EP2911203A1 (en) | 2015-08-26 |
JP6135677B2 (ja) | 2017-05-31 |
JP6421836B2 (ja) | 2018-11-14 |
CN108551559A (zh) | 2018-09-18 |
US20160111469A1 (en) | 2016-04-21 |
EP2911203B1 (en) | 2020-07-08 |
JP2018207121A (ja) | 2018-12-27 |
CN104871315B (zh) | 2018-07-13 |
JP7012619B2 (ja) | 2022-01-28 |
US20180308885A1 (en) | 2018-10-25 |
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