WO2014061724A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2014061724A1 WO2014061724A1 PCT/JP2013/078145 JP2013078145W WO2014061724A1 WO 2014061724 A1 WO2014061724 A1 WO 2014061724A1 JP 2013078145 W JP2013078145 W JP 2013078145W WO 2014061724 A1 WO2014061724 A1 WO 2014061724A1
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- groove
- electric field
- region
- field relaxation
- semiconductor device
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Definitions
- the present invention relates to a semiconductor device for rectification having a groove structure and a manufacturing method thereof.
- Various semiconductor devices have been proposed to improve the characteristics of rectifying semiconductor devices. For example, a method has been proposed in which ions are implanted into the entire bottom of a trench (trench) of a semiconductor device to reduce the electric field at the corner of the trench bottom (see Patent Document 1, for example). By disposing a region for electric field relaxation (hereinafter referred to as “electric field relaxation region”) at the bottom of the groove, the breakdown voltage of the semiconductor device can be improved.
- electric field relaxation region a region for electric field relaxation
- the electric field relaxation region is arranged at the bottom of the groove, the region through which the current of the semiconductor device flows is limited. This is because current does not flow in the electric field relaxation region whose resistance is increased by ion implantation, and the current is reduced by the amount that current does not flow through the bottom of the groove. As a result, there arises a problem that the forward current of the semiconductor device is reduced.
- an object of the present invention is to provide a semiconductor device in which an electric field relaxation region is formed at the bottom of a groove in order to improve breakdown voltage, and a method for manufacturing the semiconductor device in which a decrease in forward current is suppressed.
- a semiconductor device is disposed on a first main surface of a semiconductor substrate, and is disposed around a first conductivity type drift region having a groove formed on a surface thereof and a corner of a groove bottom.
- a second conductivity type electric field relaxation region, an anode electrode embedded in the groove, and a cathode electrode disposed on the second main surface of the semiconductor substrate.
- FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view for explaining the operation of the semiconductor device shown in FIG. 1 in the off state.
- FIG. 3 is a schematic cross-sectional view for explaining the operation of the semiconductor device shown in FIG. 1 in the on state.
- FIG. 4 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the first embodiment.
- FIG. 5 is a cross-sectional view for explaining a manufacturing process performed after FIG. 4 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 6 is a cross-sectional view for explaining a manufacturing process performed after FIG. 5 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view for explaining a manufacturing step performed after FIG. 6 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 8 is a cross-sectional view for explaining a manufacturing step performed after FIG. 7 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 9 is a cross-sectional view for explaining a manufacturing step performed after FIG. 8 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 10 is a cross-sectional view for explaining a manufacturing step performed after FIG. 9 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 11 is a cross-sectional view for explaining a manufacturing step performed after FIG. 10 in the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 12 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the modification of the first embodiment.
- FIG. 13 is a cross-sectional view for explaining a manufacturing process performed after FIG. 12 in the method for manufacturing the semiconductor device according to the variation of the first embodiment.
- FIG. 14 is a cross-sectional view for explaining a manufacturing process performed after FIG. 13 in the method for manufacturing a semiconductor device according to the modification of the first embodiment.
- FIG. 15 is a cross-sectional view for explaining a manufacturing step performed after FIG. 14 in the method for manufacturing a semiconductor device according to the modification of the first embodiment.
- FIG. 16 is a cross-sectional view for explaining a manufacturing process performed after FIG. 15 in the method for manufacturing the semiconductor device according to the modification of the first embodiment.
- FIG. 17 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the second embodiment.
- 18 is a cross-sectional view for explaining a manufacturing step performed after FIG. 17 in the method for manufacturing a semiconductor device according to the second embodiment.
- FIG. 19 is a cross-sectional view for explaining a manufacturing step performed after FIG. 18 in the method for manufacturing a semiconductor device according to the second embodiment.
- FIG. 20 is a cross-sectional view for explaining a manufacturing step performed after FIG. 19 in the method for manufacturing a semiconductor device according to the second embodiment.
- FIG. 21 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the modification of the second embodiment.
- FIG. 22 is a cross-sectional view for explaining a manufacturing step performed after FIG. 21 in the method for manufacturing a semiconductor device according to the modification of the second embodiment.
- FIG. 23 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the third embodiment.
- FIG. 24 is a cross-sectional view for explaining a manufacturing step performed after FIG. 23 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 25 is a cross-sectional view for explaining a manufacturing step performed after FIG. 24 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 26 is a cross-sectional view for explaining a manufacturing step performed after FIG. 25 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 27 is a cross-sectional view for explaining a manufacturing step performed after FIG. 26 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 28 is a cross-sectional view for explaining a manufacturing step performed after FIG. 27 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 29 is a cross-sectional view for explaining a manufacturing step performed after FIG. 28 in the method for manufacturing a semiconductor device according to the third embodiment.
- FIG. 30 is a cross-sectional view showing a manufacturing process for explaining the method of manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 31 is a cross-sectional view for explaining a manufacturing step performed after FIG. 30 in the method for manufacturing a semiconductor device according to the fourth embodiment.
- FIG. 32 is a cross-sectional view for explaining a manufacturing step performed after FIG. 31 in the method for manufacturing a semiconductor device according to the fourth embodiment.
- FIG. 33 is a cross-sectional view for explaining a manufacturing step performed after FIG. 32 in the method for manufacturing a semiconductor device according to the fourth embodiment.
- FIG. 34 is a cross-sectional view for explaining a manufacturing step performed after FIG. 33 in the method for manufacturing a semiconductor device according to the fourth embodiment.
- FIG. 35 is a schematic cross-sectional view for explaining an operation in the off state of the semiconductor device according to the fourth embodiment.
- FIG. 36 is a schematic cross-sectional view for explaining an operation in an on state of the semiconductor device according to the fourth embodiment.
- the semiconductor device 100 As shown in FIG. 1, the semiconductor device 100 according to the first embodiment of the present invention includes a semiconductor substrate 1, a first conductivity type drift region 2, and a second conductivity type electric field relaxation region 4.
- the drift region 2 has a groove in a part of its upper portion, and is disposed on the first main surface 11 of the semiconductor substrate 1.
- the electric field relaxation region 4 is disposed only around the corner except for the central portion at the bottom of the groove formed in the drift region 2.
- the electric field relaxation region 4 is disposed around the side surface of the groove, but is not disposed around the region other than the corner portion at the bottom of the groove.
- the first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type.
- the semiconductor substrate 1 is a high-concentration N-type silicon carbide (SiC) substrate, and the drift region 2 is a low-concentration N-type SiC layer.
- the groove formed in the drift region 2 has an opening formed on the surface of the drift region 2 and extends toward the semiconductor substrate 1.
- the bottom of the groove is located inside the drift region 2, and the groove does not reach the semiconductor substrate 1.
- the anode electrode 9 is formed so as to fill the groove, and the anode electrode 9 is also disposed on the upper surface of the drift region 2.
- the cathode electrode 10 is disposed on the second main surface 12 of the semiconductor substrate 1 facing the first main surface 11.
- the depletion layer extends from the second conductivity type electric field relaxation region 4 as shown in FIG. 202 spreads and the electric field at the groove end is relaxed. Further, since the depletion layer 202 extending from the electric field relaxation region 4 also extends to the groove bottom, the electric field of the entire bottom can be relaxed. As shown in FIG. 2, the depletion layer 201 extends from the upper surface of the anode electrode 9 to the drift region 2.
- drift region 2 made of N ⁇ type silicon carbide is formed on the first main surface 11 of the semiconductor substrate 1 made of N + type silicon carbide by epitaxial growth or the like.
- the electric field relaxation region 4 is formed in the drift region 2. Specifically, as shown in FIG. 5, an oxide film is formed on the upper surface of the drift region 2, and this oxide film is patterned to selectively remove the oxide film above the portion where the electric field relaxation region 4 is formed.
- the etched etching mask 3 is formed. Then, using the etching mask 3 as a mask, ion implantation of P-type impurities is performed in the drift region 2 as shown by arrows in FIG.
- the electric field relaxation region 4 is formed so as to surround a part of the drift region 2 when viewed from a direction parallel to the normal line of the first main surface 11 of the semiconductor substrate 1. For example, the shape seen from above the drift region 2 surrounded by the electric field relaxation region 4 is rectangular.
- Aluminum (Al), boron (B), or the like is used as the P-type impurity in the electric field relaxation region 4.
- the substrate temperature is set to about 600 ° C., and ions are implanted while the drift region 2 is heated, thereby suppressing the occurrence of crystal defects in the region into which the impurity ions are implanted. Can do.
- a general photolithography technique can be used for patterning the oxide film. That is, using the photoresist film patterned on the oxide film as a mask, the oxide film on the drift region 2 is etched. As an etching method, wet etching using hydrofluoric acid, dry etching such as reactive ion etching, or the like can be employed. After patterning the oxide film, the photoresist film is removed using oxygen plasma or sulfuric acid.
- a photoresist film patterned so as to expose the etching mask 3 above the region where the groove is to be formed is formed on the etching mask 3. Specifically, the region surrounded by the electric field relaxation region 4 in the drift region 2 and the etching mask 3 on the electric field relaxation region 4 are exposed. Then, as shown in FIG. 6, the etching mask 3 is removed by etching using the photoresist film 51 as an etching mask, and the upper surfaces of the drift region 2 and the electric field relaxation region 4 in the region where the groove is formed are exposed. That is, an opening that exposes the surface of the drift region 2 surrounded by the electric field relaxation region 4 and the surface of the electric field relaxation region 4 is formed in the etching mask 3.
- an oxide film 6 for forming side wales on the side surface of the groove is formed on the etching mask 3, the drift region 2, and the etching mask 3. Then, by dry etching the oxide film 6, as shown in FIG. 8, a part of the oxide film 6 remains around the opening of the etching mask 3 where the region where the groove is formed is exposed, and the sidewall 7 is formed. It is formed. At this time, the sidewall 7 is formed so that the end (inner periphery) is positioned on the electric field relaxation region 4 along the opening of the etching mask 3. That is, the end of the opening of the mask that forms the groove is positioned on the electric field relaxation region 4.
- a groove 8 is formed in a part of the upper portion of the drift region 2 by etching using the etching mask 3 and the sidewall 7 as a mask, as shown in FIG. Specifically, the drift region 2 surrounded by the electric field relaxation region 4 and the inner portion of the electric field relaxation region 4 are removed by etching, and the side surface is surrounded by the electric field relaxation region 4 at a part of the upper portion of the drift region 2.
- the groove 8 is formed.
- the part exposed to the side surface of the groove 8 of the electric field relaxation region 4 is etched.
- the groove 8 is formed so that the bottom of the groove 8 does not become lower than the bottom surface of the electric field relaxation region 4.
- the anode 8 is formed on the drift region 2 by filling the entire groove 8. Further, as shown in FIG. 11, the cathode electrode 10 is formed on the second main surface 12 of the semiconductor substrate 1. Thus, the semiconductor device 100 shown in FIG. 1 is completed.
- ion implantation is performed only on a portion along the side wall of the groove 8.
- the electric field concentrated at the corner of the bottom of the groove 8 is relaxed by the electric field relaxation region 4 formed by this ion implantation. Thereby, generation
- the electric field relaxation region 4 is not formed at the bottom of the groove 8 except for the corner. For this reason, in the ON state, a current flows from the anode electrode 9 to the cathode electrode 10 through a region other than the corner portion at the bottom of the groove 8, that is, a central portion between the corner portions. As a result, it is possible to suppress a decrease in forward current of the semiconductor device 100 while improving the reverse breakdown voltage by forming the electric field relaxation region 4.
- the electric field relaxation region 4 is disposed so as to cover the side surface of the groove 8, the second conductivity type (N type) ⁇ the first conductivity type (P type) ⁇ the second conductivity type (N type) at the bottom of the groove 8.
- the semiconductor regions are arranged in this order. That is, the bottom of the groove 8 has a junction barrier diode (Junction Barrier Diode) structure, and therefore, the entire bottom of the groove 8 can have an electric field relaxation effect.
- the groove 8 surrounded by the electric field relaxation region 4 is formed by self-alignment. For this reason, misalignment between the corner of the bottom of the groove 8 and the electric field relaxation region 4 that occurs during formation using a mask does not occur.
- the sidewall 7 is formed so that the end portion (inner periphery) is located in the surface of the electric field relaxation region 4. Therefore, the electric field relaxation region 4 can be left on the wall surface of the groove 8 by etching using the etching mask 3 and the sidewall 7 as a mask. That is, the electric field relaxation region 4 is reliably exposed on the side surface of the groove 8.
- a groove from which the side surface electric field relaxation region 4 is removed by sacrificial oxidation and etching is formed. That is, the electric field relaxation region 4 is formed only at the corner of the bottom of the groove 8.
- the side surface is surrounded by the electric field relaxation region 4 in a part of the upper portion of the drift region 2 formed on the semiconductor substrate 1.
- the groove 8 is formed.
- a sacrificial oxide film 15 is formed on the inner surface of the groove 8. At this time, the portion of the electric field relaxation region 4 exposed on the side surface of the groove 8 is oxidized.
- the inside of the trench 8 is thermally oxidized at 900 ° C. to 1300 ° C.
- the oxidation rate on the side surface is higher than the oxidation rate on the bottom surface of the groove 8. Therefore, the sacrificial oxide film 15 can be formed on the side surface of the groove 8 by leaving the electric field relaxation region 4 that is not oxidized at the corner of the bottom of the groove 8 by thermal oxidation.
- the sacrificial oxide film 15 is removed by etching.
- the sacrificial oxide film 15 on the side surface of the groove 8 is removed by etching using hydrofluoric acid.
- the groove 8 is formed such that the side surface of the groove 8 has a taper with respect to the bottom surface, as shown in FIG. And the electric field relaxation area
- the semiconductor device 100 is completed.
- the groove may be formed by etching so that the side surface of the groove 8 has a taper with respect to the bottom surface.
- the shape shown in FIG. 15 is obtained by etching away a part of the upper portion of the drift region 2 under the condition that the side surface of the groove 8 is formed in a tapered shape.
- the anode electrode 9 is formed so as to cover the groove 8, and the cathode electrode 10 is formed on the second main surface 12 of the semiconductor substrate 1.
- the groove 8 is formed in a tapered shape, and the electric field relaxation region 4 is disposed only at the corner of the bottom of the groove 8.
- a drift region 2 having a low impurity concentration is formed on a semiconductor substrate 1 having a high impurity concentration.
- an etching mask 3 is formed in which the upper surface of the drift region 2 in the region where the groove 8 is to be formed is exposed.
- a groove 8 is formed in the drift region 2 under the condition that a small groove called a micro-trench can be formed by etching.
- oxygen (O 2 ) gas or sulfur hexafluoride (SF 6 ) gas is used as an etching gas.
- the etching conditions are an antenna output of 300 to 500 W and a bias output of 50 to 100 W.
- the micro-trench 81 exists at the bottom corner as shown in FIG. A groove 8 is formed. At this time, the groove 8 is formed so that the side surface has a taper with respect to the bottom surface. Note that the micro-trench is a recess (or sag) formed by etching formed at the boundary between the side surface and the bottom surface of the groove 8 (trench).
- FIG. 19 shows a state where the lateral etching is completed.
- the central portion of the bottom of the groove 8 is also etched away, leaving only the electric field relaxation region 4 around the region where the microtrenches 81 are formed. That is, it is possible to obtain a state in which the electric field relaxation region 4 is disposed only at the corners of the bottom of the groove 8.
- the anode electrode 9 is formed so as to fill the groove 8 and the cathode electrode 10 is formed on the second main surface of the semiconductor substrate 1, whereby the semiconductor device 100 is completed.
- the electric field relaxation region 4 is formed only at the corner of the bottom of the groove 8. As a result, it is possible to suppress a decrease in the forward current of the semiconductor device 100 while improving the reverse breakdown voltage.
- the electric field relaxation region 4 is formed by ion implantation. Then, the electric field relaxation region 4 is left only at the bottom corner by etching inside the groove 8.
- the ion implantation energy for forming the electric field relaxation region 4 can be smaller than that in the case of ion implantation from the surface of the drift region 2. Further, the process can be shortened as compared with the first embodiment.
- ions may be implanted from an oblique direction with respect to the surface of the drift region 2. The method will be described below with reference to FIGS.
- the groove 8 is formed in a part of the upper portion of the drift region 2 by dry etching.
- impurity ions are implanted into the groove 8 from a direction oblique to the surface of the drift region 2.
- the electric field relaxation region 4 is formed on the side surface of the groove 8.
- the angle of ion implantation with respect to the surface of the drift region 2 is set so that impurity ions are implanted into the corners of the bottom of the trench 8 and impurity ions are not implanted into the bottom other than the corners.
- the electric field relaxation region 4 formed on the side surface of the trench 8 is removed by etching using, for example, the method of repeating the sacrificial oxidation and the removal of the sacrificial oxide film described with reference to FIGS.
- etching using, for example, the method of repeating the sacrificial oxidation and the removal of the sacrificial oxide film described with reference to FIGS.
- FIG. 22 a state is obtained in which the electric field relaxation region 4 is disposed only at the corner of the bottom of the groove 8.
- the anode electrode 9 and the cathode electrode 10 are formed, whereby the semiconductor device 100 is completed.
- the manufacturing method described above after the grooves 8 are formed, ion implantation is performed in an oblique direction with respect to the side surfaces of the grooves 8 to remove the bottoms of the grooves 8 other than the corners.
- Electric field relaxation region 4 is formed in a region exposed inside. For this reason, the electric field relaxation area
- drift region 2 having a low impurity concentration is formed on a semiconductor substrate 1 having a high impurity concentration, and an anode electrode layer 90 is further formed on the drift region 2.
- a trench 8 that penetrates the anode electrode layer 90 and reaches the inside of the drift region 2 is formed by dry etching using an etching mask (not shown).
- a sidewall formation film 21 for forming a sidewall to be described later is formed on the inner surface of the trench 8 and the upper surface of the drift region 2.
- a sidewall formation film 21 for the sidewall formation film 21 an oxide film such as a silicon oxide (SiO 2 ) film is employed.
- the sidewall formation film 21 is etched by dry etching to form sidewalls 22 on the side surfaces of the grooves 8 as shown in FIG. At this time, the central portion of the bottom of the groove 8 is exposed.
- the anode electrode 9 is formed so as to fill the sidewalls 22 with the grooves 8 whose side surfaces are covered.
- the upper portion of the anode electrode 9 is etched back until the upper surface of the sidewall 22 is exposed.
- the sidewall 22 is removed by etching.
- a gap is formed between the side surface of the groove 8 and the anode electrode 9 as shown in FIG.
- impurity ions that have passed through the side surface of the anode electrode 9 are formed at the corners at the bottom of the groove 8. Injected into.
- a mask material (not shown) is disposed in a region where the groove 8 of the anode electrode layer 90 is not formed, and impurity ions are implanted into a region where the mask material is not disposed.
- the electric field relaxation region 4 is formed only at the corner of the bottom of the groove 8.
- the anode electrode 9 is doped with impurity ions.
- the semiconductor device 100 is completed.
- the anode of the semiconductor device 100 is configured by the anode electrode layer 90 and the anode electrode 9.
- a polysilicon film is grown to form the anode electrodes 9 in the grooves 8. Then, only the portion buried in the trench 8 of the polysilicon film is left by the etch back. Thereby, the side wall 22 formed on the side surface of the groove 8 can be removed. By removing the side wall 22, the corner of the bottom of the groove 8 is exposed, and impurity ions are selectively implanted around the corner.
- the conductive polysilicon electrode as the anode electrode 9 and the electric field relaxation region 4 can be formed with a small number of steps.
- the method for manufacturing the semiconductor device 100 according to the fourth embodiment of the present invention is a method for manufacturing a heterojunction diode (HJD) made of SiC.
- HJD heterojunction diode
- a P-type polysilicon film that forms a relatively high energy barrier with the SiC interface is embedded in the trench to form a relatively low energy barrier with the SiC interface.
- An N type polysilicon film to be formed is formed on the upper surface of the drift region 2 excluding the region where the groove is formed.
- a groove is formed in a part of the upper portion of the drift region 2 by dry etching.
- the structure shown in FIG. 30 is obtained by using the method of repeating the sacrificial oxidation and the removal of the sacrificial oxide film described with reference to FIGS. 13 to 15 or the method of forming the groove 8 in a tapered shape. That is, the electric field relaxation region 4 is formed at the corner of the bottom of the groove 8.
- a polysilicon film 19 to be the anode electrode 9 is grown on the drift region 2 so as to fill the groove 8.
- ion implantation is performed on the polysilicon film 19 as shown in FIG. 32 using the photoresist film 52 opened above the groove 8 by patterning as a mask.
- the polysilicon film 19 is doped with a P-type (second conductivity type) impurity serving as an acceptor in the anode electrode 9 to form a second conductivity type impurity implantation region 192.
- ions are implanted into the polysilicon film 19 as shown in FIG. Specifically, an N-type (first conductivity type) impurity serving as a donor in the anode electrode 9 is doped into the polysilicon film 19 to form a first conductivity type impurity implantation region 191.
- annealing for activating impurities in the first conductivity type impurity implantation region 191 and the second conductivity type impurity implantation region 192 is performed, and as shown in FIG. 34, the first conductivity type anode electrode region 91 and the second conductivity type An anode electrode region 92 is formed. That is, the second conductivity type impurity is doped in the region embedded in the groove 8 of the anode electrode 9 to form the second conductivity type anode electrode region 92. Then, the first conductivity type impurity electrode 91 is formed by doping the anode electrode 9 formed on the drift region 2 in the remaining region of the region where the groove 8 is formed with the first conductivity type impurity.
- the semiconductor device 100 is completed.
- the depletion layer 211 spreads from the second conductivity type anode electrode region 92 to the first conductivity type anode electrode region 91 having a low barrier as shown in FIG. And the electric field is relaxed.
- the depletion layer 212 spreads from the second conduction type electric field relaxation region 4 at the groove end to cover the groove end, so that the electric field at the groove end where the electric field concentrates is relaxed.
- Lower first conductivity type anode electrode regions 91 are respectively disposed.
- the electric field relaxation region 4 is not formed in the entire groove bottom, it is possible to provide a semiconductor device in which a decrease in forward current is suppressed and a method for manufacturing the same.
- the semiconductor device and the semiconductor device manufacturing method according to the embodiment can be used in the electronic equipment industry including a manufacturing industry that manufactures a semiconductor device for rectification in which a groove is formed.
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Abstract
Description
本発明の第1の実施形態に係る半導体装置100は、図1に示すように、半導体基体1と、第1導電型のドリフト領域2と、第2導電型の電界緩和領域4とを備える。ドリフト領域2は、その上部の一部に溝を有し、半導体基体1の第1の主面11上に配置されている。電界緩和領域4は、ドリフト領域2に形成された溝の底部において中央部を除いた角部の周囲のみに配置されている。電界緩和領域4は、溝の側面の周囲に配置されているが、溝の底部においては角部以外の領域の周囲には配置されていない。
本発明の第2の実施形態に係る半導体装置100の製造方法を、図17~図20を参照して説明する。
本発明の第3の実施形態に係る半導体装置100の製造方法を、図23~図29を参照して説明する。
本発明の第4の実施形態に係る半導体装置100の製造方法を、図30~図34を参照して説明する。第4の実施形態に係る半導体装置100の製造方法は、SiCからなるヘテロジャンクションダイオード(HJD)の製造方法である。以下に説明するように、SiC界面との間で相対的に高いエネルギー障壁を形成するP型のポリシリコン膜が溝の内部に埋め込まれ、SiC界面との間で相対的に低いエネルギー障壁を形成するN型のポリシリコン膜が溝の形成された領域を除いたドリフト領域2の上面に形成される。
2 ドリフト領域
4 電界緩和領域
6 酸化膜
7 サイドウォール
8 溝
9 アノード電極
10 カソード電極
11 第1の主面
12 第2の主面
15 犠牲酸化膜
19 ポリシリコン膜
22 サイドウォール
81 マイクロトレンチ
91 第1導電型アノード電極領域
92 第2導電型アノード電極領域
100 半導体装置
Claims (12)
- 半導体基体と、
上部の一部に溝を有し、前記半導体基体の第1の主面上に配置された第1導電型のドリフト領域と、
前記溝の底部においては中央部を除いた角部の周囲のみに配置された第2導電型の電界緩和領域と、
前記溝に埋め込まれたアノード電極と、
前記半導体基体の前記第1の主面に対向する第2の主面上に配置されたカソード電極と
を備えることを特徴とする半導体装置。 - 前記溝の側面を覆って前記電界緩和領域が配置されていることを特徴とする請求項1に記載の半導体装置。
- 半導体基体の第1の主面上に第1導電型のドリフト領域を形成し、
イオン注入により、前記ドリフト領域の上部の一部に第2導電型の電界緩和領域を選択的に形成し、
前記電界緩和領域で周囲を囲まれた前記ドリフト領域及び前記電界緩和領域の内側部分をエッチングして、前記ドリフト領域の上部の一部に前記電界緩和領域で側面を囲まれた溝を形成し、
前記溝を埋め込んで前記ドリフト領域上にアノード電極を形成し、
前記半導体基体の前記第1の主面に対向する第2の主面上にカソード電極を形成する
ことを特徴とする半導体装置の製造方法。 - 前記溝を形成することには、
前記電界緩和領域で周囲を囲まれた前記ドリフト領域の表面と前記電界緩和領域の表面とが露出する開口部を有するエッチングマスクを形成し、
前記エッチングマスクの開口部に沿って、端部が前記電界緩和領域上に位置するようにサイドウォールを形成し、
前記エッチングマスクと前記サイドウォールをマスクにして、前記ドリフト領域及び前記電界緩和領域の内側部分をエッチングすること
が含まれることを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記溝を形成した後に、前記溝の側面に露出した前記電界緩和領域を酸化して犠牲酸化膜を形成し、
前記犠牲酸化膜をエッチング除去することにより、前記溝の底部の角部のみに前記電界緩和領域を残す
ことを特徴とする請求項3又は4に記載の半導体装置の製造方法。 - 前記溝を形成することは、前記溝の側面に露出する前記電界緩和領域をエッチングするために、前記溝の側面が底面に対してテーパをもつように前記溝を形成することである
ことを特徴とする請求項3に記載の半導体装置の製造方法。 - 半導体基体の第1の主面上に第1導電型のドリフト領域を形成し、
前記ドリフト領域の上部の一部に溝を形成し、
前記溝の底部においては中央部を除いた角部の周囲のみに第2導電型の電界緩和領域を形成し、
前記溝を埋め込んで前記ドリフト領域上にアノード電極を形成し、
前記半導体基体の前記第1の主面に対向する第2の主面上にカソード電極を形成する
ことを特徴とする半導体装置の製造方法。 - 前記溝を形成する際に、前記溝の底部にマイクロトレンチが形成されるエッチング条件を使用し、
前記電界緩和領域を形成することには、
イオン注入により、前記溝の内面に前記電界緩和領域を形成し、
前記溝の側面と底面に露出した前記電界緩和領域をエッチング除去することにより、前記溝の底部の角部のみに前記電界緩和領域を残すこと
が含まれることを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記溝の底部の角部のみに前記電界緩和領域を残すことには、
前記溝の側面と底面に露出した前記電界緩和領域を酸化して犠牲酸化膜を形成し、
前記犠牲酸化膜をエッチング除去すること
が含まれることを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記電界緩和領域を形成することは、前記ドリフト領域の表面に対して斜めの方向から前記溝の底部の角部及び側面にイオンを注入することによって、前記溝の底部の中央部を除いた前記角部及び前記側面に前記電界緩和領域を形成することである
ことを特徴とする請求項7に記載の半導体装置の製造方法。 - 半導体基体の第1の主面上に第1導電型のドリフト領域を形成し、
前記ドリフト領域の上部の一部に溝を形成し、
前記溝の側面上にサイドウォールを形成し、
前記サイドウォールが形成された溝の内部を埋め込んでアノード電極を形成し、
前記サイドウォールを除去し、
前記溝の側面と前記アノード電極との間にイオン注入することにより、前記溝の底部において角部の周囲のみに第2導電型の電界緩和領域を形成し、
前記半導体基体の前記第1の主面に対向する第2の主面上にカソード電極を形成する
ことを特徴とする半導体装置の製造方法。 - 半導体基体の第1の主面上に第1導電型のドリフト領域を形成し、
前記ドリフト領域の上部の一部に溝を形成し、
前記溝の底部において角部の周囲のみに第2導電型の電界緩和領域を形成し、
前記溝の内部及び前記ドリフト領域上にアノード電極を形成し、
前記アノード電極の前記溝の内部に埋め込まれた領域に、イオン注入によって第2導電型不純物をドープし、
前記溝が形成された領域の残余の領域において前記ドリフト領域上に形成された前記アノード電極に、イオン注入によって第1導電型不純物をドープし、
前記半導体基体の前記第1の主面に対向する第2の主面上にカソード電極を形成する
ことを特徴とする半導体装置の製造方法。
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JP2016046368A (ja) * | 2014-08-22 | 2016-04-04 | 日産自動車株式会社 | 半導体装置及びその製造方法 |
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CN106158985A (zh) * | 2016-09-12 | 2016-11-23 | 中国科学院微电子研究所 | 一种碳化硅结势垒肖特基二极管及其制作方法 |
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US11677023B2 (en) * | 2021-05-04 | 2023-06-13 | Infineon Technologies Austria Ag | Semiconductor device |
CN114628499A (zh) * | 2022-05-17 | 2022-06-14 | 成都功成半导体有限公司 | 一种带有沟槽的碳化硅二极管及其制备方法 |
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CN104718627B (zh) | 2017-07-25 |
JP6028807B2 (ja) | 2016-11-24 |
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EP2911205A4 (en) | 2016-03-02 |
EP2911205B1 (en) | 2020-12-09 |
US20150287775A1 (en) | 2015-10-08 |
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EP2911205A1 (en) | 2015-08-26 |
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