WO2013117077A1 - 一种沟槽场效应器件及其制备方法 - Google Patents

一种沟槽场效应器件及其制备方法 Download PDF

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Publication number
WO2013117077A1
WO2013117077A1 PCT/CN2012/078793 CN2012078793W WO2013117077A1 WO 2013117077 A1 WO2013117077 A1 WO 2013117077A1 CN 2012078793 W CN2012078793 W CN 2012078793W WO 2013117077 A1 WO2013117077 A1 WO 2013117077A1
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Prior art keywords
trench
layer
dielectric layer
thickness
field effect
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PCT/CN2012/078793
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English (en)
French (fr)
Inventor
周宏伟
高东岳
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无锡华润上华半导体有限公司
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Priority to US14/376,021 priority Critical patent/US9601336B2/en
Publication of WO2013117077A1 publication Critical patent/WO2013117077A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present invention relates to the field of semiconductor power device manufacturing technologies, and in particular, to a trench field effect device and a method for fabricating the same. Background technique
  • the trench MOSFET In many power management applications, in order to improve energy conversion efficiency, the trench MOSFET is required to operate at a frequency greater than 500 kHz, which requires a trench MOSFET with a lower gate. charge and smaller on-resistance, therefore, continue to decrease merit trench field effect device (i.e., a trench field effect device gate charge Q g the product of the oN resistance of R. n) has become a continuous optimization of the trench The goal pursued by field effect devices.
  • the technique of forming a thick oxygen layer at the bottom of the trench is generally used to reduce the gate charge and figure of merit of the trench field effect device.
  • One of the objects of the present invention is to reduce the figure of merit of trench field effect devices.
  • a method of fabricating a trench field effect device comprising the steps of:
  • the substrate comprising an epitaxial layer formed over the semiconductor substrate of the substrate and a trench formed in the epitaxial layer;
  • the epitaxial layers of the heavily doped polysilicon region and the trench sidewall are simultaneously oxidized to form a thick oxygen layer and a trench side wall dielectric layer simultaneously on the bottom and sidewalls of the trench;
  • the thickness of the thick oxide layer formed simultaneously is greater than the thickness of the trench sidewall dielectric layer, and the thick oxygen layer is used as the trench bottom gate dielectric layer of the trench field effect device.
  • the epitaxial layer is relatively lightly doped single crystal silicon.
  • the semiconductor substrate is a single crystal silicon substrate, and a doping concentration of the epitaxial layer is smaller than a doping concentration of the semiconductor substrate.
  • the doping concentration of the heavily doped polysilicon region is 20 times or more of the doping concentration of the epitaxial layer.
  • the epitaxial layer has a doping concentration of less than or equal to 5E17 cm- 3 .
  • the doping concentration of the heavily doped polysilicon region is greater than or equal to 1E19 cm- 3 .
  • the thick oxygen layer grows faster than the growth rate of the trench sidewall dielectric layer.
  • the oxidation is carried out by a thermal oxidation process under high pressure and wet oxygen conditions.
  • the pressure at the time of thermal oxidation is greater than a standard atmospheric pressure.
  • the heavily doped polysilicon region has a thickness ranging from 40 ⁇ ⁇ to 500 ⁇ ⁇ .
  • the thickness of the thick oxygen layer is 2-4 times the thickness of the trench sidewall dielectric layer.
  • the thickness of the thick oxygen layer is greater than or equal to 400 A and less than or equal to 6000 A.
  • the doping type of the heavily doped polysilicon region is N type.
  • the thickness of the sacrificial dielectric layer is in the range of 400 A to 2000 A.
  • the thick oxygen layer is formed on the sacrificial dielectric layer at the bottom of the trench, and the portion covered by the heavily doped polysilicon region is sacrificed. A layer and the thick oxygen layer together form a trench bottom gate dielectric layer in the gate dielectric layer of the trench field effect device.
  • the present invention further provides a trench field effect device formed by the method of any of the above.
  • the trench bottom dielectric layer and the trench sidewall dielectric layer are simultaneously formed, but the thickness of the gate dielectric layer is slightly lower than the trench due to stress and the like. Sidewall dielectric layer.
  • a thick oxygen layer is formed in the trench gate dielectric layer to increase the thickness of the gate dielectric layer at the bottom of the trench, and the heavily doped polysilicon is used in such as high voltage and wet.
  • the oxygen environment the oxidation rate of the relatively lightly doped single crystal silicon is faster, and the thick oxygen layer and the trench sidewall dielectric layer are formed synchronously on the bottom and the sidewall of the trench respectively.
  • the trench power field effect The fabrication process of the gate dielectric layer of the device is greatly simplified. Moreover, the thickness of the thick oxide layer can be 2-4 times the thickness of the gate dielectric layer of the trench sidewall, thereby reducing the capacitance between the drain and the gate of the trench field effect device, and reducing the trench field effect device. Excellent value.
  • 1 to 6 are schematic cross-sectional structural views showing a structural change of a process for fabricating a trench field effect device according to an embodiment of the present invention.
  • Fig. 7 is a schematic view showing the comparison of the doping contrast of a conventional trench field effect device and a trench field effect device according to an embodiment of the present invention.
  • Fig. 8 is a schematic structural view of a conventional trench field effect device.
  • FIG. 9 is a schematic structural view of a trench field effect device according to an embodiment of the invention.
  • 10 is a graph showing a gate charge of a trench field effect device as a function of gate voltage, wherein a gate charge of a trench field effect device according to an embodiment of the present invention is included The curve of the gate voltage change and the curve of the gate charge of a conventional trench field effect device as a function of the gate voltage.
  • FIG. 11 is a graph showing the merit of a trench field effect device as a function of gate voltage, wherein a trench value field device according to an embodiment of the present invention has a merit value as a function of gate voltage and a conventional trench.
  • the figure of merit of the field effect device as a function of gate voltage.
  • the preparation process is complicated. Applicant's research found that this is because the oxidation rate of lightly doped polysilicon is slightly faster than that of lightly doped single crystal silicon, but the difference is not large, and it is usually formed by polysilicon oxidation at the bottom of the trench to form a thick oxygen layer. At the same time, a considerable thickness of oxide layer is formed on the sidewall of the trench. Therefore, at this time, the thickness difference between the thick oxide layer at the bottom of the trench and the oxide layer on the sidewall of the trench is not large, and it is necessary to form a thick thick oxygen.
  • the thickness of the oxide layer which is often formed simultaneously on the sidewall is difficult to meet the predetermined target thickness requirement of the gate dielectric layer. If it is desired to form a gate dielectric layer of a desired thickness, the oxide layer on the sidewalls of the trench must be etched away, and then the gate dielectric layer is grown to form a trench sidewall dielectric layer.
  • the thickness of the oxide layer on the sidewall of the trench is not much different from that of the trench sidewall, thereby causing the trench to be etched while etching the sidewall of the trench sidewall.
  • the bottom oxide layer is also etched away, eventually making the effective thickness of the thick oxygen layer formed at the bottom of the trench using lightly doped polysilicon not sufficiently thick, and the effect of reducing the value of the trench field effect device is not very significant.
  • the present invention provides a method of fabricating a trench field effect device.
  • 1 to 6 are schematic cross-sectional structural views showing structural changes in a process of a trench field effect device according to an embodiment of the present invention. The basic process of the method for fabricating the trench field effect device according to an embodiment of the present invention will be described below with reference to Figs.
  • Step 1 A substrate is provided, the substrate comprising a body layer and a trench located in a surface of the body layer.
  • the substrate is used to prepare one or more trench field effect devices.
  • the body layer of the substrate includes: a semiconductor substrate 101, an epitaxial layer 102 on the surface of the semiconductor substrate 101, and an epitaxial layer 102.
  • patterning the epitaxial layer 102 to dope may form a well region 104, and the well region 104 may be used to form a body region.
  • the semiconductor substrate 101 is selected as a single crystal silicon substrate.
  • the semiconductor substrate in this embodiment may be formed based on various semiconductor elements, for example, the semiconductor substrate may be single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe); the semiconductor substrate may also be Formed from various composite semiconductor materials, for example, the semiconductor substrate may be formed of silicon carbide, indium antimonide, antimony telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, or any combination of the above materials. Substrate.
  • the semiconductor substrate may also be silicon-on-insulator (SOI).
  • the semiconductor substrate may also comprise other materials, such as a multilayer structure of epitaxial layer 102 or buried oxide layer.
  • a substrate can be formed from several examples, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • the epitaxial layer 102 may be formed by one-time growth on the semiconductor substrate 101, which may be an N-type or P-type epitaxial layer. Therefore, the material type of the epitaxial layer 102 and the material type of the semiconductor substrate 101 are basically In the same example, in this example, the epitaxial layer 102 is a single crystal silicon material.
  • a dielectric barrier layer 103 is formed on the surface of the epitaxial layer 102 by a process such as thermal oxidation or CVD (Chemical Vapor Deposition), and the dielectric barrier layer 103 serves as a barrier layer in the subsequent ion implantation process to prevent surface damage. .
  • the thickness of the dielectric barrier layer 103 is in the range of 400 A to 1000 ⁇ (for example, 600 A), and the specific thickness may be determined according to specific application requirements of the device.
  • the dielectric barrier layer 103 may be, but not limited to, silicon oxide.
  • the semiconductor substrate 101 may be N+ doped, the epitaxial layer 102 is N-doped, and the epitaxial layer 102 is used to form a drift region of the trench field effect device, and its doping concentration is smaller than that of the semiconductor substrate 101. The concentration, the doping concentration requirement of the epitaxial layer 102 will be further explained later.
  • the epitaxial layer 102 is doped by ion implantation or high energy ion implantation to form a well region 104 in the epitaxial layer, that is, an N-type well region or a P-type well region.
  • the doping type is N type
  • the doping ions may be phosphorus or other pentavalent elements
  • the doping type is P type
  • the doping ions may be boron or other trivalent elements.
  • the doping type is P-type.
  • a high-energy ion implanter can be used for implanting boron element, and after high-temperature annealing, a P-well region 104 is formed.
  • a photoresist layer is spin-coated on the dielectric barrier layer 103.
  • an anti-reflection layer may be formed between the photoresist layer and the dielectric barrier layer 103 (not shown in the drawing).
  • a photoresist pattern having a trench pattern is used as a mask, and a trench pattern opening is formed on the dielectric barrier layer 103 by a reactive ion etching process; further, the photoresist layer and the anti-resistance are removed by chemical cleaning or the like.
  • a reflective layer further using a dielectric barrier layer 103 having a trench pattern opening as a mask, using a method such as wet etching or dry etching to remove a material not covered by the dielectric barrier layer 103, in the layer of the epitaxial layer 102 A trench 105 as shown in FIG. 3 is formed.
  • Step 2 As shown in FIG. 4, a sacrificial dielectric layer 106 is formed on the bottom and sidewalls of the trench 105.
  • a sacrificial dielectric layer i.e., a sacrificial dielectric layer 106
  • a sacrificial dielectric layer 106 may be grown on the bottom and sidewalls (i.e., the inner walls of the trenches) of the trenches 105 by a thermal oxidation process.
  • the thickness of the sacrificial dielectric layer 106 is greater than or equal to 400 A and less than or equal to 2000 A, such as 1000 people.
  • a portion of the sacrificial dielectric layer 106 may be simultaneously overlying the dielectric barrier layer 103.
  • Step 3 As shown in FIG. 5, a heavily doped polysilicon region 107 is formed at the bottom of the trench 105, and a portion of the sacrificial dielectric layer not covered by the heavily doped polysilicon region 107 is removed.
  • the epitaxial layer of the sidewall of the trench is exposed (when the depth of the trench 105 is large, the exposed epitaxial layer may include an epitaxial layer of the sidewall portion corresponding to 102 and the well region 104).
  • a certain thickness of the in-situ heavily doped polysilicon layer may be deposited on the surface of the sacrificial dielectric layer 106 by a process such as CVD or PECVD (plasma enhanced chemical vapor deposition).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the polysilicon layer deposited at the bottom of the trench is relatively thick due to the structural features of the trench; or, when the polysilicon is deposited, the heavily doped polysilicon layer deposited may at least substantially fill the bottom of the trench 105.
  • the polysilicon etch process may be used to etch away the polysilicon layer on the dielectric barrier layer 103 and on the sidewalls of the trench 105, leaving only the in-situ heavily doped polysilicon at the bottom of the trench 105.
  • the layers are formed to form a heavily doped polysilicon region 107 as shown in FIG. It should be noted that, in the above process of etching back the polysilicon layer, the dielectric barrier layer on the surface of the dielectric barrier layer 103 and the sidewalls of the trench 105 may be etched back at the same time, thereby being only heavily doped.
  • a portion of the sacrificial dielectric layer 106 covered by the polysilicon region 107 is substantially retained, i.e., in this example, the sacrificial shield layer of the trench sidewalls over the heavily doped polysilicon region 107 is removed.
  • the heavily doped polysilicon region 107 is formed in a portion.
  • the thickness of the remaining heavily doped polysilicon region 107 may be greater than or equal to 400 A and less than or equal to 5000 A, for example, 2000 A.
  • the thickness of the heavily doped polysilicon region 107 can be controlled by an etch back process to control its thickness.
  • the thickness of the heavily doped polysilicon region 107 is at least greater than or equal to In the thickness of the polycrystalline silicon which is oxidized to form a thick oxygen layer, those skilled in the art, in the above teachings and teachings, select the thickness of the heavily doped polysilicon region 107 according to the thickness of the thick oxygen layer to be formed.
  • the doping type of the heavily doped polysilicon region 107 may be, but not limited to, an N-type.
  • the doping concentration of the heavily doped polysilicon region is greater than or equal to 1E19 cm- 3 , for example, the doping concentration thereof may be It is 5E19 cm- 3 .
  • Step 4 As shown in FIG. 6, the heavily doped polysilicon region 107 and the epitaxial layer of the trench sidewall are simultaneously oxidized to form a thick oxygen layer 108 in synchronization on the bottom and sidewalls of the trench, respectively. And the trench sidewall dielectric layer 109, the thickness of the thick oxide layer 108 formed simultaneously is greater than the thickness of the trench sidewall dielectric layer 109.
  • the oxidation rate of heavily doped polysilicon is generally much greater than the oxidation rate of relatively lightly doped single crystal silicon (eg, the oxidation rates of the two differ by an order of magnitude). Therefore, under the same oxidation process conditions, When the exposed epitaxial layer (trench sidewall portion) and the heavily doped polysilicon region 107 are simultaneously oxidized, the heavily doped polysilicon region 107 is at least partially oxidized to form a thick oxygen layer 108 as shown in FIG. The sidewalls are partially oxidized to form a trench sidewall dielectric layer 109 as shown in FIG.
  • the thickness of the thick oxide layer 108 will be much greater than the thickness of the trench sidewall dielectric layer 109.
  • the epitaxial layer 102 and the well region 104 of the epitaxial layer both are single crystal silicon epitaxial layers
  • doping concentration of less than or equal to 5E17 cm 'monocrystalline silicon e.g., 1 E17 cm- 3
  • the doping concentration of the heavily doped type polysilicon region 107 as compared to the trench sidewall doping concentration of 3 At least 20 times higher, the oxidation rate difference is greater.
  • the thermal oxidation process is used to simultaneously oxidize the mono-doped silicon of the heavily doped polysilicon region 107 and the sidewalls of the trench 105 at the bottom of the trench 105, both of which are The difference in oxidation rate is further improved.
  • the pressure parameter during thermal oxidation can be set to be greater than one standard atmospheric pressure (e.g., 1.2 standard atmospheric pressures), and the thermal oxidation temperature range is from 800 to 120 CTC (e.g., 850 ° C).
  • Those skilled in the art may select a specific thermal oxidation process condition, heavily doped polysilicon according to the thickness of the sidewall spacer dielectric layer to be formed and the thickness of the thick oxide layer 108 to be formed. Parameters such as the doping concentration of the region 107, the doping concentration of the epitaxial layer 102 and the well region 104 of the epitaxial layer.
  • the thickness of the thick oxide layer 108 is greater than or equal to 400 A and less than or equal to 6000 A (e.g., 0.4 microns), and the thickness of the thick oxide layer 108 is more than twice the thickness of the trench sidewall dielectric layer 109.
  • the thick oxide layer 108 and the underlying sacrificial dielectric layer 106 together form a trench bottom gate dielectric layer of the trench field effect device.
  • the thickness of the thick oxide layer 108 formed based on the method can be much greater than the thickness of the trench sidewall dielectric layer 109. Thereby, the figure of merit of the trench field effect device can be greatly reduced.
  • the thick oxygen layer 108 and the trench sidewall dielectric layer 109 can be formed synchronously, and the preparation process is relatively simplified.
  • trench field effect device e.g., forming a polysilicon gate in the trench
  • process steps of the trench field effect device may be continued to form a trench field effect device provided by an embodiment of the present invention.
  • the other process steps after the formation of the gate dielectric layer can be carried out by a conventional process, and therefore, it is not limited by the present invention and will not be described herein.
  • all of the heavily doped polysilicon regions 107 may be oxidized to form a thick oxygen layer 108 in step 4; in other embodiments, heavily doped polysilicon Area 107 may not be fully oxidized, therefore, in thick There may also be a heavily doped polysilicon layer (not shown in Figure 6) between the oxygen layer 108 and the sacrificial dielectric layer 106.
  • FIG. 7 is a schematic diagram showing the doping contrast simulation of a conventional trench field effect device and a trench field effect device according to an embodiment of the present invention.
  • the trench field effect device provided by the embodiment of the present invention has a thicker thickness of the trench bottom dielectric layer and a thicker gate dielectric layer than the conventional trench field effect device.
  • the thickness of the oxygen layer is 2-4 times the thickness of the trench sidewall dielectric layer, and under similar process conditions, the thickness of the trench bottom shield layer in the conventional trench field effect device and the trench sidewall dielectric layer The thickness is substantially the same.
  • the thickness of the trench bottom dielectric layer in the trench field effect device provided in the embodiment of the present invention is the thickness of the trench bottom dielectric layer in the conventional trench field effect device under similar process conditions. -4 times, thereby reducing the capacitance between the drain and the gate of the trench field effect device, reducing the figure of merit of the trench field effect device, and the process is simple.
  • FIG. 9 is a schematic structural diagram of a trench field effect device according to an embodiment of the present invention.
  • the trench field effect device includes:
  • a body layer comprising: a semiconductor substrate 101 > an epitaxial layer 102 on a surface of the semiconductor substrate 101;
  • the bottom of the trench 105 has a thick oxygen layer for forming a trench gate dielectric layer, and the sidewall of the trench 105 forms a trench sidewall dielectric layer
  • the thick oxide layer and the trench sidewall shield layer are formed by synchronous oxidation, and the thickness of the thick oxygen layer of the gate dielectric layer of the trench is 2-4 times of the thickness of the trench sidewall dielectric layer.
  • the trench field effect device of the embodiment of the present invention further comprises a conventional trench field effect device process:
  • a polysilicon gate 110 located in the trench 105;
  • a P+ contact region 111 located in the P-type well region 104 and an N+ source 112 between the P+ contact region 1 1 1 and the trench 105;
  • FIG. 8 is a schematic view showing the structure of a conventional trench field effect device.
  • the trench field effect device provided in the embodiment of the present invention is compared to the conventional trench.
  • the bottom of the trench 105 has a thick trench bottom gate dielectric layer, thereby reducing the capacitance between the gate and drain of the trench field effect device, thereby reducing the trench field effect.
  • the gate charge of the device greatly reduces the figure of merit of the trench field effect device.
  • Figure 10 is a graph showing the gate charge of a trench field effect device as a function of gate voltage, wherein the gate charge of the trench field effect device according to an embodiment of the present invention is gated.
  • the reference trench trench field device device voltage example 'ground is 65V.
  • curve 1 is a curve of gate charge as a function of gate voltage of a trench field effect device (such as the trench field effect device shown in FIG. 9) according to an embodiment of the present invention
  • curve 2 is a conventional trench field.
  • the gate charge of a effect device (such as the trench field effect device shown in Figure 8) as a function of gate voltage.
  • V gs 4.5 V
  • the gate charge Q g of the trench field effect device provided by the embodiment of the present invention is substantially reduced by 20 compared to the conventional trench field effect device. %.
  • FIG. 11 is a graph showing the relationship between the figure of merit of the trench field effect device and the gate voltage, and the curve of the merit of the trench field effect device according to an embodiment of the present invention as a function of the gate voltage and the conventional The merit of the trench field effect device as a function of the gate voltage.
  • the breakdown voltage of the trench field effect device is exemplarily 65V; wherein curve 3 is a curve of the merit value (RQ g ) of the conventional trench field effect device as a function of the gate voltage; A figure of the merit (RQ g ) of a trench field effect device as a function of gate voltage in accordance with an embodiment of the present invention.
  • relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, not necessarily: ⁇ and, 'terminology'
  • the package ⁇ ", 5 '" contains "or any of its ⁇ " which is intended to cover the exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other items not explicitly listed. Elements, or elements that are inherent to such a process, method, item, or device. Without further restrictions, the elements defined by the statement "including one" are not excluded. Including the stated There are other identical elements in the process, method, product or equipment of the element.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种沟槽场效应器件及其制备方法，该制备方法包括：提供基片，该基片包括形成在基片的半导体衬底之上的外延层以及形成于所述外延层中的沟槽；在所述沟槽底部和侧壁形成牺牲介质层；在所述沟槽底部形成重掺杂型多晶硅区域，并去除未被所述重掺杂型多晶硅区域覆盖的部分所述牺牲介质层以暴露所述沟槽侧壁的外延层；以及对所述重掺杂型多晶硅区域和沟槽侧壁的外延层同时进行氧化，以在沟槽的底部和侧壁上同步地分别形成厚氧层和沟槽侧壁栅介质层；其中，同步形成的所述厚氧层的厚度大于所述沟槽侧壁栅介质层的厚度，所述厚氧层用作所述沟槽场效应器件的沟槽底部栅介质层。该制备方法简单，并且制备形成的沟槽场效应器件的优值大大减小。

Description

一种沟槽场效应器件及其制备方法 技术领域
本发明涉及半导体功率器件制造技术领域， 尤其涉及一种沟槽场 效应器件及其制备方法。 背景技术
在很多电源管理应用中， 为了提高能量的转换效率， 要求其沟槽 场效应器件（ trench MOSFET )的工作频率要大于 500KHz , 这就要求 沟槽场效应器件 （trench MOSFET ) 具有较低的栅极电荷以及较小的 导通电阻， 因此， 不断降低沟槽场效应器件的优值 （即沟槽场效应器 件栅极电荷 Qg与导通电阻 R。n的乘积）已成为人们不断优化沟槽场效 应器件所追求的目标。 现有技术中， 人们通常利用在沟槽底部形成厚 氧层 （厚氧层的厚度大于沟槽侧壁栅介质层的厚度） 的技术来降低沟 槽场效应器件的栅极电荷和优值。
在现有技术中， 形成沟槽厚氧的方法很多， 例如局部热氧化 (LOCOS) , 高密度等离子淀积 (HDP)等， 也有文献利用轻掺杂的多晶 硅来形成沟槽底部的厚氧层， 但是， 在实际生产过程中发现， 采用上 述技术制备出的沟槽场效应器件的优值较高， 而且制备工艺较为复 杂。 发明内容
本发明的目的之一在于， 降低沟槽场效应器件的优值。
本发明的还一目的在于， 简化沟槽场效应器件的制备工艺。
为实现以上目的或者其他目的， 本发明公开了以下技术方案。
按照本公开的一方面， 提供一种沟槽场效应器件的制备方法， 其 包括步骤：
提供基片， 所述基片包括形成在所述基片的半导体衬底之上 的外延层以及形成于所述外延层中的沟槽；
在所述沟槽底部和侧壁形成牺牲介质层；
在所迷沟槽底部形成重掺杂型多晶硅区域， 并去除未被所述 重摻杂型多晶硅区域覆盖的部分所述牺牲介质层以暴露所述沟 槽側壁的外延层； 以及
对所述重掺杂型多晶硅区域和沟槽侧壁的外延层同时进行 氧化， 以在沟槽的底部和侧壁上同步地分别形成厚氧层和沟槽侧 壁栅介质层；
其中， 同步形成的所述厚氧层的厚度大于所述沟槽侧壁栅介质层 的厚度， 所述厚氧层用作所述沟槽场效应器件的沟槽底部栅介质层。
按照本发明一实施例的制备方法， 其中， 所述外延层为相对轻掺 杂的单晶硅。
进一步， 所述半导体衬底为单晶硅衬底， 所述外延层的掺杂浓度 小于所述半导体衬底的掺杂浓度。
进一步， 所述重掺杂型多晶硅区域的掺杂浓度是所述外延层的掺 杂浓度的 20倍以上。
按照本发明又一实施例的制备方法， 其中， 所述外延层的掺杂浓 度小于或等于 5E17 cm-3。
在之前所述任一实施例的制备方法， 进一步， 所述重掺杂型多晶 硅区域的掺杂浓度大于或等于 lE19cm-3。
在之前所述任一实施例的制备方法，进一步，在所述氧化过程中， 所述厚氧层的生长速度快于所述沟槽侧壁栅介质层的生长速度。
按照本发明还一实施例的制备方法， 其中， 所述氧化采用高压和 湿氧条件下的热氧化工艺。
在之前所述任一实施例的制备方法， 进一步， 热氧化时的压力大 于一个标准大气压。
在之前所述任一实施例的制备方法， 进一步， 所述重掺杂型多晶 硅区域的厚度范围为 40θΑ-500θ Α。
按照本发明再一实施例的制备方法， 其中， 所述厚氧层的厚度是 所述沟槽侧壁栅介质层的厚度的 2-4倍。
在之前所述任一实施例的制备方法， 进一步， 所述厚氧层的厚度 大于或等于 400A且小于或等于 6000A。
在之前所述任一实施例的制备方法， 进一步， 所述重掺杂型多晶 硅区域的掺杂类型为 N型。
在之前所述任一实施例的制备方法， 进一步， 所述牺牲介质层的 厚度在 400A-2000 A的范围内。 在之前所述任一实施例的制备方法， 进一步， 所述厚氧层形成于 所述沟槽底部的牺牲介质层之上， 被所述重掺杂型多晶硅区域覆盖的 部分所述牺牲 ^质层与所述厚氧层共同形成所述沟槽场效应器件的 栅介质层中的沟槽底部栅介质层。
按照本公开的又一方面， 本发明还提供一种采用上述任一所述的 方法制备形成的沟槽场效应器件。
与现有技术相比， 上述技术方案至少地具有以下优点：
传统的沟槽功率场效应器件制备方法中， 沟槽底部栅介质层与沟 槽侧壁栅介质层是同时形成的， 但是由于应力等因素， 使得沟槽底部 栅介质层厚度略低于沟槽侧壁栅介质层。 而本发明实施例的沟槽场效 应器件的制备方法中， 沟槽底部栅介质层中形成厚氧层以提高槽底部 栅介质层的厚度的同时， 利用重掺杂型多晶硅在诸如高压、 湿氧环境 下比相对轻掺杂的单晶硅氧化速率快的特点， 在沟槽的底部和侧壁上 同步地分别形成厚氧层和沟槽侧壁栅介质层， 因此， 沟槽功率场效应 器件的栅介质层的制备过程得到大大地简化。 并且， 厚氧层的厚度可 以达到在沟槽侧壁栅介质层的厚度 2-4倍， 进而可以减小该沟槽场效 应器件漏极和栅极间的电容， 降低了沟槽场效应器件的优值。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面 将对实施例或现有技术描述中所需要使用的附图作简单地介绍， 显而 易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本领域 普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些 附图获得其他实施例的附图。
图 1 -6是对应本发明一实施例的沟槽场效应器件制备方法过程的 结构变化的剖面结构示意图。
图 7是传统沟槽场效应器件与本发明一实施例的沟槽场效应器件 结构掺杂对比模拟示意图。
图 8是传统的沟槽场效应器件的结构示意图。
图 9是按照本发明一实施例的沟槽场效应器件的结构示意图。 图 10 是沟槽场效应器件的栅极电荷随栅极电压变化的曲线示意 图， 其中， 包括按照本发明一实施例的沟槽场效应器件的栅极电荷随 栅极电压变化的曲线以及传统的沟槽场效应器件的栅极电荷随栅极 电压变化的曲线。
图 11 是沟槽场效应器件的优值随栅极电压变化的曲线示意图， 其中， 包括按照本发明一实施例的沟槽场效应器件的优值随栅极电压 变化的曲线以及传统的沟槽场效应器件的优值随栅极电压变化的曲 线。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方 案进行清楚、 完整地描述， 显然， 所描述的实施例仅是本发明一部分 实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通 技术人员在没有做出创造性劳动前提下所获得的所有其他实施例， 都 属于本发明保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本发明， 但 是本发明还可以采用其他不同于在此描述的其他方式来实施， 本领域 技术人员可以在不违背本发明内涵的情况下做类似推广， 因此本发明 不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时， 为便于说明， 表示器件结构的剖面图会不依一般比例作局部放大， 而 且所述示意图只是示例性的， 其在此不应限制本发明保护的范围。 此 夕卜， 在实际制备中应包含长度、 宽度及深度的三维空间尺寸。
正如背景技术部分所述， 采用现有技术用轻掺杂的多晶硅形成厚 氧沟槽场效应器件的制备方法制备的沟槽场效应器件时， 制备工艺较 为复杂。 申请人研究发现， 这是由于轻掺杂的多晶硅的氧化速率虽然 比轻掺杂的单晶硅快一点， 但差别并不大， 而且， 通常在利用多晶硅 氧化在沟槽底部形成厚氧层的同时沟槽侧壁上也会形成相当厚度的 氧化层， 因此， 此时， 沟槽底部的厚氧层与沟槽侧壁的氧化层的厚度 差并不大， 在需要形成足够厚的厚氧层的情况下， 往往同时在侧壁形 成的氧化层的厚度难以符合栅介质层的预定目标厚度要求。 若需要形 成理想厚度的栅介质层， 必须先将沟槽侧壁上的氧化层刻蚀掉， 再生 长栅介质层以形成沟槽侧壁栅介质层。 这种方法中， 一方面， 需要对 侧壁的氧化层重新刻蚀并生长， 具有工艺复杂的缺点； 另一方面， 在 刻蚀沟槽侧壁上的氧化层的过程中， 由于沟槽底部氧化层与沟槽侧壁 氧化层的厚度也差别不大， 从而导致在刻蚀沟槽侧壁的氧化层的同时 沟槽底部氧化层也会被刻蚀掉， 最终使得利用轻掺杂的多晶硅在沟槽 底部形成的厚氧层的有效厚度并不足够厚， 沟槽场效应器件的优值降 低效果并不是十分明显。
有鉴于此， 本发明提供了一种沟槽场效应器件的制备方法。 图 1 -6所 示为对应本发明一实施例的沟槽场效应器件制备方法过程的结构变化的 剖面结构示意图。 以下结合图 1至图 6说明本发明一实施例的沟槽场效应 器件制备方法的基本过程。
首先， 步骤 1 : 提供基片， 所述基片包括本体层和位于所述本体 层表面内的沟槽。
如图 1所示， 该基片用于制备一个或多个沟槽场效应器件， 基片 的本体层包括： 半导体衬底 101、 位于半导体衬底 101表面上的外延 层 102以及位于外延层 102表面上的介质阻挡层 103。 进一步地， 在 该实施例中， 如图 2所示， 对外延层 102构图掺杂可以形成阱区 104 , 阱区 104可以用来形成体区。
在该实施例中， 半导体衬底 101选择为单晶硅衬底。 需要说明的 是， 本实施例中的半导体衬底可以基于各种半导体元素形成， 例如半 导体衬底可以为单晶、 多晶或非晶结构的硅或硅锗 （SiGe ) ； 半导体 衬底也可以由各种复合半导体材料形成， 例如， 半导体村底可以为碳 化硅、 锑化铟、 碲化铅、 砷化铟、 磷化铟、 碎化镓或锑化镓， 或者以 上材料的任意组合形成的衬底。 半导体衬底可以也可以是绝缘体上硅 ( SOI ) 此外， 半导体基片还可以包括其他的材料， 例如外延层 102 或埋氧层的多层结构。 虽然在此描述了可以形成基片的材料的几个示 例， 但是可以作为半导体基片的任何材料均落入本发明的精神和范 围。
在该实施例中， 外延层 102可为在半导体村底 101上一次性生长 形成， 其可以为 N型或 P型外延层， 因此， 外延层 102的材料类型与 半导体衬底 101 的材料类型基本相同， 在该实例中， 外延层 102为 单晶硅材料。 外延生长之后， 可采用热氧化或 CVD (化学气相沉积） 等工艺，在外延层 102表面形成一层介质阻挡层 103，介质阻挡层 103 在后续离子注入过程中用作阻挡层， 以防止表面损伤。 本发明实施例 中， 介质阻挡层 103的厚度在 400A-1000 Α的范围内 （例如 600 A ), 具体厚度可按照器件的具体应用要求确定， 具体地， 介质阻挡层 103 可以但不限于为氧化硅。 半导体衬底 101可以为 N+掺杂， 外延层 102 为 N-摻杂， 外延层 102用于形成沟槽场效应器件的漂移区， 其掺杂浓 度 （doping concentration ) 小于半导体衬底 101 的掺杂浓度， 外延层 102的掺杂浓度要求将在其后进一步说明。
以介质阻挡层 103为掩膜，采用离子注入或高能离子注入等工艺， 对外延层 102进行注入掺杂， 以形成外延层内的阱区 104, 即形成 N 型阱区或 P型阱区。 若掺杂类型为 N型， 掺杂离子可为磷或其他五价 元素， 若掺杂类型为 P型， 掺杂离子可为硼或其他三价元素。 本发明 实施例中以掺杂类型为 P型为例， 本实施例中可采用高能量离子注入 机进行硼元素的注入， 经高温退火后形成 P-阱区 104。
形成 P-阱区 104之后， 在介质阻挡层 103上旋涂光刻胶层， 为了 保证曝光精度， 还可在光刻胶层和介质阻挡层 103之间形成抗反射层 (图中未示出） ， 以减少不必要的反射； 之后采用具有沟槽图形的掩 膜版对光刻胶层进行曝光， 在光刻胶层表面上形成沟槽图案， 显影之 后得到具有沟槽图形的光刻胶层； 进一步以具有沟槽图形的光刻胶层 为掩膜， 采用反应离子刻蚀等工艺， 在介质阻挡层 103上形成沟槽图 形开口； 进一步采用化学清洗等方法去除光刻胶层和抗反射层； 进一 步以具有沟槽图形开口的介质阻挡层 103为掩膜， 采用湿法腐蚀或干 法刻蚀等方法， 去除未被介质阻挡层 103覆盖的材料， 在所述外延层 102层内形成如图 3所示的沟槽 105。
继续地， 步骤 2: 如图 4所示， 在沟槽 105底部和侧壁上形成牺 牲介质层 106。
形成沟槽 105之后， 可以但不限于采用热氧化工艺在沟槽 105底 部和侧壁（也即沟槽内壁）上生长一层牺牲介质层，即牺牲介质层 106。 在该实施例中， 牺牲介质层 106的厚度大于或等于 400A且小于或等 于 2000 A, 例如 1000 人。 如图 3所示， 牺牲介质层 106的一部分可 以同时覆盖于介质阻挡层 103上。
继续地， 步骤 3: 如图 5所示， 在沟槽 105底部形成重掺杂型多晶硅 区域 107，并去除未被重掺杂型多晶硅区域 107覆盖的部分牺牲介质层以 暴露沟槽側壁的外延层 （在沟槽 105 的深度较大时， 暴露的外延层可以 包括 102和阱区 104所对应的侧壁部分的外延层）。
在该实施例中，形成牺牲介质层 106之后，可采用 CVD或 PECVD (等离子体增强化学气相淀积）等工艺在牺牲介质层 106表面淀积一 定厚度的原位重掺杂多晶硅层， 采用淀积工艺时， 由于沟槽的结构特 征， 在沟槽底部沉积的多晶硅层相对较厚； 也或者， 在淀积多晶硅时， 淀积的重掺杂多晶硅层可以至少基本地填充沟槽 105的底部。 在其后 过程中， 可以利用多晶硅回刻蚀工艺， 将介质阻挡层 103之上以及沟 槽 105的侧壁上的多晶硅层刻蚀掉， 仅保留在沟槽 105的底部原位重 掺杂多晶硅层， 以形成如图 5所示的重掺杂型多晶硅区域 107。 需要 说明的是， 在以上回刻蚀多晶硅层的过程中， 可以同时回刻蚀去除介 质阻挡层 103的表面上以及沟槽 105侧壁上的介质阻挡层， 从而， 仅 未被重掺杂型多晶硅区域 107所覆盖的部分牺牲介质层 106基本地被 保留， 也即在该实例中， 位于重掺杂型多晶硅区域 107上方的沟槽侧 壁的牺牲介盾层被去除。 具体地， 重掺杂型多晶硅区域 107形成在部 在该实施例中， 保留的重掺杂型多晶硅区域 107的厚度可以大于 或等于 400A且小于或等于 5000 A， 例如， 2000 A。 重掺杂型多晶硅 区域 107的厚度可以通过回刻蚀工艺控制实现其厚度控制， 在欲形成 的厚氧层的厚度确定的情况下， 重掺杂型多晶硅区域 107的厚度至少 地大于或等于用于氧化形成厚氧层的多晶硅的厚度， 本领域技术人员 在以上教导和启示下， 根据欲形成的厚氧层的厚度， 选择确定重掺杂 型多晶硅区域 107的厚度。 重掺杂型多晶硅区域 107的掺杂类型可以 但不限于为 N型， 在该实施例中， 重掺杂型多晶硅区域的掺杂浓度大 于或等于 lE19 cm-3， 例如， 其掺杂浓度可以为 5E19 cm-3。
继续地， 步骤 4: 如图 6所示， 对重掺杂型多晶硅区域 107和沟 槽侧壁的外延层同时进行氧化， 以在沟槽的底部和侧壁上同步地分别 形成厚氧层 108和沟槽侧壁栅介质层 109， 同步形成的厚氧层 108的 厚度大于沟槽侧壁栅介质层 109的厚度。
在本发明中， 申请人发现， 在同一氧化工艺条件下， 重掺杂型多 晶硅的氧化速率通常远大于相对轻掺杂的单晶硅的氧化速率（例如二 者的氧化速率相差一个数量级）， 因此， 在同一氧化工艺条件下， 对 外露的外延层（沟槽側壁部分）和重掺杂型多晶硅区域 107 同步地进 行氧化时， 重掺杂型多晶硅区域 107至少部分地被氧化形成如图 6所 示的厚氧层 108， 沟槽側壁被部分地氧化形成如图 6所示的沟槽侧壁 栅介质层 109 , 厚氧层 108的厚度将远大于沟槽侧壁栅介质层 109的 厚度。 在一优选实施例中， 为使厚氧层 108的厚度与沟槽侧壁栅介质 层 109的厚度的差越大， 外延层 102和外延层的阱区 104 (均为单晶 硅外延层）的掺杂浓度设置为小于或等于 5E17 cm'3(例如， 1 E17 cm—3 )， 这样重掺杂型多晶硅区域 107的掺杂浓度相比于沟槽侧壁的单晶硅的 掺杂浓度至少高 20倍， 氧化速率差更大。
进一步， 优选地， 在高压和湿氧的环境下， 采用热氧化工艺对位 于所沟槽 105底部的重掺杂型多晶硅区域 107和沟槽 105侧壁的单晶 硅同步氧化时， 二者的氧化速率差进一步得到提高。 具体地， 热氧化 时的压力参数可以设置为大于一个标准大气压 （例如为 1.2个标准大 气压） ， 热氧化时的温.度范围为 800口至 120CTC (例如为 850°C ) 。 本领域技术人员在以上教导和启示下， 可以根据欲形成的侧壁栅介质 层的厚度以及欲形成的厚氧层 108的厚度， 来选择设置具体的热氧化 的工艺条件、 重掺杂型多晶硅区域 107的掺杂浓度、 外延层 102和外 延层的阱区 104的掺杂浓度等参数。
在一实施例中， 厚氧层 108的厚度大于或等于 400A且小于或等 于 6000 A (例如 0.4微米） ， 厚氧层 108的厚度是沟槽侧壁栅介质层 109的厚度的 2倍以上。 厚氧层 108与其下面的牺牲介质层 106共同 形成沟槽场效应器件的沟槽底部栅介质层， 基于该方法形成的厚氧层 108厚度能远大于沟槽侧壁栅介质层 109的厚度， 从而能够大大减小 沟槽场效应器件的优值。 并且， 厚氧层 108和沟槽侧壁栅介质层 109 可以同步地形成， 制备工艺相对简化。
进一步， 可以继续完成沟槽场效应器件的其他工艺步骤 （例如在 沟槽中形成多晶硅栅极） ， 以制备形成本发明实施例提供的沟槽场效 应器件。 栅介质层形成后的其他工艺步骤可以采用常规工艺方法， 因 此， 其不受本发明限制， 在此不再 赘述。
需要说明的是， 在以上实施例中， 如图 6所示， 步骤 4中可以对 所有的重掺杂型多晶硅区域 107全部氧化形成厚氧层 108 ; 在其他实 施例中， 重掺杂型多晶硅区域 107有可能未被全部氧化， 因此， 在厚 氧层 108与牺牲介质层 106之间可能还存在重掺杂型多晶硅层 (图 6 中未示出）。
参考图 7 , 图 7所示为传统沟槽场效应器件与本发明一实施例的 沟槽场效应器件结构掺杂对比模拟示意图。 从图 7可以看出， 本发明 实施例所提供的沟槽场效应器件相比于传统的沟槽场效应器件， 其沟 槽底部栅介质层的厚度大大增加， 沟槽底部栅介质层的厚氧层的厚度 为沟槽侧壁栅介质层厚度的 2-4倍， 而相似工艺条件下， 传统沟槽场 效应器件中沟槽底部栅介盾层的厚度与沟槽侧壁栅介质层的厚度基 本相同， 因此， 本发明实施例中所提供的沟槽场效应器件中沟槽底部 栅介质层的厚度为相似工艺条件下传统沟槽场效应器件中沟槽底部 栅介质层的厚度的 2-4倍， 从而减小了所述沟槽场效应器件漏极和栅 极间的电容， 降低了该沟槽场效应器件的优值， 而且工艺简单。
本发明实施例还公开了一种采用上述方法制备的沟槽场效应器 件， 如图 9所示， 图 9所示为按照本发明一实施例的沟槽场效应器件 的结构示意图， 该实施例的沟槽场效应器件包括：
本体层， 所述本体层包括： 半导体衬底 101 > 位于所述半导体衬 底 101表上的外延层 102;
位于所述外延层 102 内的阱区 104和沟槽 105， 其中， 沟槽 105 底部具有用于形成沟槽底部栅介质层的厚氧层， 沟槽 105的侧壁形成 沟槽侧壁介质层， 厚氧层与沟槽侧壁介盾层的是通过同步氧化形成， 沟槽底部栅介质层的厚氧层的厚度为沟槽侧壁栅介质层厚度的 2-4 倍。
除此之外， 本发明实施例的沟槽场效应器件还包括采用常规沟槽 场效应器件工艺形成的：
位于沟槽 105内的多晶硅栅极 110;
位于 P-型阱区 104内的 P+接触区 111 以及位于 P+接触区 1 1 1与 沟槽 105间 N+源极 112;
位于 P+电极 111表面的金属源极 113 , 且金属源极 113覆盖部分 N+源极 112; 以及
位于金属源极 113中间的、 多晶硅栅极 110之上的氧化层 1 14。 图 8所示为传统的沟槽场效应器件的结构示意图。 从图 8和图 9中 可以看出， 本发明实施例中所提供的沟槽场效应器件， 相较于传统的沟 槽场效应器件而言， 沟槽 105底部具有较厚的沟槽底部栅介质层， 从而 减小了所述沟槽场效应器件栅极和漏极间的电容， 进而减小了沟槽场效 应器件的栅极电荷， 大大降低了所述沟槽场效应器件的优值。
图 10所示为沟槽场效应器件的栅极电荷随栅极电压变化的曲线示意 图， 其中， 包括按照本发明一实施例的沟槽场效应器件的栅极电荷随栅 化的曲线。 参考图 沟槽场效 器件 穿电压示例' 地为 65V。 其 中， 曲线 1为按照本发明一实施例的沟槽场效应器件 （例如图 9所示的 沟槽场效应器件） 的栅极电荷随栅极电压变化的曲线； 曲线 2 为传统的 沟槽场效应器件 （例如图 8 所示的沟槽场效应器件） 的栅极电荷随栅极 电压变化的曲线。 从图 10可以看出， 在 Vgs=4.5V下， 相比于传统的沟槽 场效应器件而言， 本发明实施例所提供的沟槽场效应器件的栅极电荷 Qg 大致减少了 20%。
图 1 1 所示为沟槽场效应器件的优值随栅极电压变化的曲线示意 图， 其中， 包括按照本发明一实施例的沟槽场效应器件的优值随栅极 电压变化的曲线以及传统的沟槽场效应器件的优值随栅极电压变化 的曲线。 参考图 1 1， 沟槽场效应器件的击穿电压示例性地为 65V; 其 中， 曲线 3 为传统的沟槽场效应器件的优值 （RQg ) 随栅极电压变化 的曲线； 曲线 4 为按照本发明一实施例的沟槽场效应器件的优值 ( RQg ) 随栅极电压变化的曲线。 从图 1 1可以看出， 在 Vgs=4.5V下， 相比于传统的沟槽场效应器件而言， 本发明实施例所提供的沟槽场效 应器件的优值 （RQg ) 降低了 13%。
本说明书中各个部分采用递进的方式描述， 每个部分重点说明的都 是与其他部分的不同之处， 各个部分之间相同相似部分互相参见即可。
需要说明的是， 在本文中， 诸如第一和第二等之类的关系术语仅 仅用来将一个实体或者操作与另一个实体或操作区分开来， 而不一定 序: ^且，'术语"包^"、5'"包含"或者其任何^ "他变 在涵盖 排他 性的包含， 从而使得包括一系列要素的过程、 方法、 物品或者设备不 仅包括那些要素， 而且还包括没有明确列出的其他要素， 或者是还包 括为这种过程、 方法、 物品或者设备所固有的要素。 在没有更多限制 的情况下， 由语句 "包括一个 ...... "限定的要素， 并不排除在包括所述 要素的过程、 方法、 牯品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明， 使本领域专业技术人员能够实现 或使用本发明。 对这些实施例的多种修改对本领域的专业技术人员来 说将是显而易见的， 本文中所定义的一般原理可以在不脱离本发明的 精神或范围的情况下， 在其他实施例中实现。 因此， 本发明将不会被 限制于本文所示的实施例， 而是要符合与本文所公开的原理和新颖特 点相一致的最宽的范围。

Claims

权 利 要 求
1. 一种沟槽场效应器件的制备方法， 其特征在于， 该方法包括： 提供基片， 所述基片包括形成在所述基片的半导体村底之上的外延 层以及形成于所述外延层中的沟槽；
在所述沟槽底部和侧壁形成牺牲介质层；
在所述沟槽底部形成重掺杂型多晶硅区域， 并去除未被所述重掺杂 型多晶硅区域覆盖的部分所述牺牲介质层以暴露所述沟槽侧壁的外延 层； 以及
对所述重掺杂型多晶硅区域和沟槽侧壁的外延层同时进行氧化， 以 在沟槽的底部和侧壁上同步地分别形成厚氧层和沟槽侧壁栅介质层； 其中， 同步形成的所述厚氧层的厚度大于所述沟槽侧壁栅介质层的 厚度， 所述厚氧层用作所述沟槽场效应器件的沟槽底部栅介质层。
2. 根据权利要求 1所述的方法， 其特征在于， 所述外延层为相对轻 掺杂的单晶硅。
3. 根据权利要求 2所述的方法， 其特征在于， 所述半导体衬底为单 晶硅衬底， 所述外延层的掺杂浓度小于所述半导体衬底的掺杂浓度。
4. 根据权利要求 2所述的方法， 其特征在于， 所述重摻杂型多晶硅 区域的掺杂浓度是所述外延层的掺杂浓度的 20倍以上。
5. 根据权利要求 1或 4所述的方法， 其特征在于， 所述外延层的掺 杂浓度小于或等于 5E17 cnT3。
6. 根据权利要求 1或 4所述的方法， 其特征在于， 所述重掺杂型多 晶硅区域的掺杂浓度大于或等于 lE19cm-3。
7. 根据权利要求 1或 2所述的方法， 其特征在于， 在所述氧化过程 中， 所述厚氧层的生长速度快于所述沟槽侧壁栅介质层的生长速度。
8. 根据权利要求 1或 2所述的方法， 其特征在于， 所述氧化采用高 压和湿氧条件下的热氧化工艺。
9. 根据权利要求 8所述的方法， 其特征在于， 热氧化时的压力大于 一个标准大气压。
10. 根据权利要求 1或 2所述的方法， 其特征在于， 所述重掺杂型 多晶硅区域的厚度范围为 400A-5000 A。
11. 根据权利要求 1或 2所述的方法， 其特征在于， 所述厚氧层的 厚度是所述沟槽侧壁栅介质层的厚度的 2-4倍。
12. 根据权利要求 11所述的方法， 其特征在于， 所述厚氧层的厚度 大于或等于 400A且小于或等于 6000A。
13. 根据权利要求 1所述的方法， 其特征在于， 所述重掺杂型多晶 硅区域的掺杂类型为 N型。
14. 根据权利要求 1所述的方法， 其特征在于， 所述牺牲介质层的 厚度在 400A至 2000 A的范围内。
15. 根据权利要求 14所述的方法， 其特征在于， 所述厚氧层形成于 所述沟槽底部的牺牲介质层之上， 被所述重掺杂型多晶硅区域覆盖的部 分所述牺牲介质层与所述厚氧层共同形成所述沟槽场效应器件的栅介 质层中的沟槽底部栅介质层。
16. 一种采用权利要求 1 -15中任一项所述的方法制备形成的沟槽场 效应器件。
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