TW201535488A - 鰭狀場效電晶體裝置與其形成方法 - Google Patents

鰭狀場效電晶體裝置與其形成方法 Download PDF

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TW201535488A
TW201535488A TW104107861A TW104107861A TW201535488A TW 201535488 A TW201535488 A TW 201535488A TW 104107861 A TW104107861 A TW 104107861A TW 104107861 A TW104107861 A TW 104107861A TW 201535488 A TW201535488 A TW 201535488A
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layer
insulating material
air gap
forming
gate structure
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TWI544529B (zh
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Ru-Shang Hsiao
Rou-Han Kuo
Ting-Fu Lin
Sheng-Fu Yu
Tzung-Da Liu
Li-Yi Chen
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

本發明關於鰭狀場效電晶體裝置與其形成方法，且鰭狀場效電晶體裝置之側壁包含氣隙以具有低介電常數。在某些實施例中，方法包括：形成半導體材料鰭狀物於半導體基板上。閘極結構形成於半導體材料鰭狀物上，且閘極結構具有閘極介電層與其上的閘極材料層。側壁間隔物係形成以鄰接閘極結構的相反兩側。側壁間隔物各自包括與閘極結構鄰接之絕緣材料的第一層，以及絕緣材料的第二層，且絕緣材料的第一層與絕緣材料的第二層之間隔有氣隙。藉由形成具有氣隙之側壁間隔物的鰭狀場效電晶體裝置，可將低鰭狀場效電晶體裝置之寄生電容與對應的RC延遲。

Description

鰭狀場效電晶體裝置與其形成方法
本發明係關於鰭狀場效電晶體裝置，更特別關於側壁間隔物具有氣隙的鰭狀場效電晶體裝置與其形成方法。
積體晶片的尺寸持續縮小，而平面CMOS電晶體之尺寸受限於製程能力與材料的基本性質(比如漏電流與製程變數)而越來越難縮小。鰭狀場效電晶體(FinFET)裝置早已取代平面CMOS電晶體。近年來，FinFET裝置因進階技術進步而成為新技術節點(如小於或等於22nm)的可行選項。
FinFET裝置為三維結構，其導電通道區具有自基板隆起的半導體材料的鰭狀物。閘極結構包覆半導體材料之鰭狀物的三個側邊，以控制導電通道區中的電荷載子流。舉例來說，三閘極的FinFET結構中，閘極結構包覆半導體材料鰭狀物的三個側邊，以形成導電通道區於鰭狀物的三個側邊上。
本發明一實施例提供之鰭狀場效電晶體裝置的形成方法，包括：形成半導體材料鰭狀物於半導體基板上；形成閘極結構凸出半導體基板，且閘極結構位於半導體材料鰭狀物上，其中閘極結構包括閘極介電層與其上的閘極材料層；形成源極區與汲極區於閘極結構的相反兩端上，且源極區與汲極區 電性接觸半導體材料鰭狀物；以及形成多個側壁間隔物以鄰接閘極結構的相反兩側，其中側壁間隔物各自包括與閘極結構鄰接之絕緣材料的第一層，以及絕緣材料的第二層，且絕緣材料的第一層與絕緣材料的第二層之間隔有氣隙。
本發明一實施例提供之鰭狀場效電晶體裝置的形成方法，包括：形成一或多個半導體材料鰭狀物於隔離材料的部份之間的半導體基板上；形成虛置閘極結構凸出半導體基板，且虛置閘極結構位於一或多個半導體材料鰭狀物上；形成絕緣材料的第一層於虛置閘極結構的側壁與一或多個半導體材料鰭狀物的頂部上；形成虛置氣隙層於絕緣材料的第一層之側壁上；形成絕緣材料的第二層於虛置氣隙層上；同時移除虛置氣隙層與虛置閘極結構，其中移除虛置氣隙層將形成多個氣隙於絕緣材料的第一層與絕緣材料的第二層之間；形成閘極結構於虛置閘極結構被移除的位置中；以及形成源極區與汲極區於閘極結構的相反兩端上，且源極區與汲極區電性接觸一或多個半導體材料鰭狀物。
本發明一實施例提供之鰭狀場效電晶體裝置，包括：三維的半導體材料鰭狀物，自隔離材料之第一與第二部份之間的基板凸出；閘極結構，位於三維的半導體材料鰭狀物上，並設置以控制三維的半導體材料鰭狀物中的通道區內之電荷載子流；以及多個側壁間隔物，與閘極結構的兩個相反側壁鄰接，其中側壁間隔物各自包含與閘極結構鄰接的絕緣材料的第一層，以及絕緣材料的第二層，其中絕緣材料的第一層與絕緣材料的第二層之間隔有氣隙。
A-A’‧‧‧剖視線
h1、h2‧‧‧高度
100、200‧‧‧FinFET裝置
102‧‧‧半導體基板
103、103a、103b、502‧‧‧半導體材料鰭狀物
104、304‧‧‧源極區
105‧‧‧通道區
106、320‧‧‧汲極區
108、308‧‧‧閘極結構
110‧‧‧側壁間隔物
112‧‧‧絕緣材料的第一層
114‧‧‧氣隙
114a‧‧‧第一開口
114b‧‧‧第二開口
116‧‧‧絕緣材料的第二層
118‧‧‧源極與汲極接點
202、504‧‧‧隔離材料
204、316‧‧‧第二方向
206、314‧‧‧第一方向
300、500、600、700、900、1000‧‧‧立體圖
302、604‧‧‧閘極介電層
306‧‧‧介電層
310‧‧‧閘極材料層
318、800、802、806、904‧‧‧剖視圖
400‧‧‧方法
402、404、406、408、410、412、414、416、418、420‧‧‧步驟
702‧‧‧虛置閘極結構
704‧‧‧多晶矽
706‧‧‧圖案化的硬遮罩層
804‧‧‧虛置氣隙層
902‧‧‧蝕刻品
1002‧‧‧置換閘極結構
第1圖係某些實施例中FinFET裝置的剖視圖，其側壁間隔物具有氣隙。
第2圖係某些實施例中FinFET裝置的立體圖，其側壁間隔物具有氣隙。
第3A至3B圖係另一實施例中包含FinFET裝置的基板之示意圖，且FinFET裝置之側壁間隔物具有氣隙。
第4圖係某些實施例中FinFET裝置之形成方法的流程圖，且FinFET裝置之側壁間隔物具有氣隙。
第5-7、8A-8C、9A-9B、10圖係某些實施例中半導體基板的剖視圖，其顯示具有FinFET裝置的形成方法，且FinFET裝置之側壁間隔物具有氣隙。
下述揭露內容提供的不同實施例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明的多個實例中將採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
另一方面，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性 的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
鰭狀物場效電晶體(FinFET)裝置包含三維的半導體材料鰭狀物，其延伸於源極區與汲極區之間。閘極結構位於半導體材料鰭狀物上。FinFET裝置通常更包括側壁間隔物，其沿著閘極結構的側壁形成。側壁間隔物包含電性絕緣材料，設置以定義FinFET裝置之閘極結構與源極區(與汲極區)之間的橫向空間。
當積體晶片構件持續縮小，側壁間隔物的寄生電容增加，進而增加FinFET裝置的整體寄生電容。舉例來說，圍繞FinFET裝置的閘極結構之側壁間隔物其介電常數越大，閘極結構跟源極與汲極區之間(及閘極結構跟源極與汲極接點之間)的寄生電容也越大。寄生電容會導致RC延遲，並劣化FinFET裝置的效能。
綜上所述，本發明關於FinFET裝置與其形成方法，且FinFET裝置的側壁間隔物包含氣隙以降低其介電常數。在某些實施例中，上述方法包括形成半導體材料鰭狀物於半導體基板上。閘極結構係形成於半導體材料鰭狀物上，且包含閘極介電層與其上的閘極材料層。側壁間隔物係形成於鄰接閘極結構的相反兩側上。側壁間隔物各自包含與閘極結構鄰接之絕緣材料的第一層，以及與絕緣材料的第一層隔有氣隙之絕緣材料的第二層。藉由形成具有氣隙之側壁間隔物，可降低FinFET之寄生電容與對應的RC延遲。
第1圖係某些實施例中FinFET裝置100的剖視圖，其側壁間隔物包含氣隙。
FinFET裝置100包含半導體材料鰭狀物103(如矽)，其自半導體基板102突出如三維結構。半導體材料鰭狀物103包含橫向相隔之源極區104與汲極區106。源極區104與汲極區106為高掺雜區。舉例來說，源極區104與汲極區106之掺雜濃度介於1016cm-3至1018cm-3之間。源極區104與汲極區106之間隔有通道區105，且通道區105沿著半導體材料鰭狀物103延伸。
閘極結構108位於半導體基板102上，並跨越半導體材料鰭狀物103。舉例來說，閘極結構108可接觸半導體材料鰭狀物103的上表面與側壁。閘極結構108係設置以控制通道區105中的電荷載子流。
電性絕緣的側壁間隔物110鄰接閘極結構108的側壁。側壁間隔物110包含氣隙114，係設置使側壁間隔物110具有極低介電常數(比如k~1)。側壁間隔物110的低介電常數可降低閘極結構108與源極區104及汲極區106之間的寄生電容，並降低閘極結構108與源極與汲極接點118之間的寄生電容。降低寄生電容可減少RC延遲以改善FinFET裝置100的效能，進而增加FinFET裝置100的操作速度。
在某些實施例中，氣隙114位於絕緣材料的第一層112與絕緣材料的第二層116之間。舉例來說，絕緣材料的第一層112可位於閘極結構108的側壁上，以及半導體材料鰭狀物103的頂部上。氣隙114可與絕緣材料的第一層112鄰接，而絕緣材料的第二層116可與氣隙114鄰接。在某些實施例中，絕緣 材料的第一層112與絕緣材料的第二層116可包含氮化矽(SiN)。
在某些實施例中，氣隙114包含連續的空腔延伸於側壁間隔物110之第一開口114a與第二開口114b之間。在某些實施例中，氣隙114可包含L型的空腔，第一開口114a位於L型空腔的頂部，而第二開口114b位於L型空腔的底部。在其他實施例中，氣隙114可包含非連續的空腔於絕緣材料的第一層112與絕緣材料的第二層116之間。
第2圖係某些實施例中，FinFET裝置200的立體圖，且FinFET裝置200之側壁間隔物具有氣隙。
FinFET裝置200包含三維之半導體材料鰭狀物103，其位於半導體基板102上。在多種實施例中，半導體基板102可包含任何半導體主體如矽、矽鍺、絕緣層上矽、或類似物，比如半導體晶圓及/或半導體晶圓上的一或多個晶粒，或任何其他相關的半導體及/或磊晶層。
半導體材料鰭狀物103自半導體基板102突出如正型輪廓，其垂直延伸穿過隔離材料202。半導體材料鰭狀物103沿著源極區104與汲極區106之間的第一方向206橫向延伸。閘極結構108位於半導體基板102上，並橫跨半導體材料鰭狀物103。閘極結構108沿著第二方向204延伸，且第二方向204垂直於第一方向206。
電性絕緣的側壁間隔物110橫向鄰接閘極結構108的側壁。在某些實施例中，側壁間隔物110自閘極結構108之上表面延伸至下表面。在此實施例中，側壁間隔物110之高度大 於兩倍的側壁間隔物110之寬度。
第3A至3B圖係其他實施例中，具有FinFET裝置的基板之示意圖，且FinFET裝置之側壁間隔物具有氣隙。
第3A圖係某些實施例之立體圖300，其基板具有FinFET裝置，且FinFET裝置之側壁間隔物包含氣隙。第3B圖係沿著第3A圖之剖視線A-A’的剖視圖318。
基板包含之三維的半導體材料鰭狀物103a及103b自半導體基板102向外延伸。半導體材料鰭狀物103a及103b彼此相隔有隔離材料202，因此半導體材料鰭狀物103a及103b交錯於隔離材料202的部份之間。半導體材料鰭狀物103a及103b沿著源極區304與汲極區320之間的第一方向314延伸，且源極區304與汲極區320位於介電層306(如層間介電材料)中。在某些實施例中，介電層306可包含氧化物、低介電常數材料、或超低介電常數材料。
閘極結構308位於三維的半導體材料鰭狀物103a及103b上。閘極結構308沿著第二方向316延伸，且第二方向316垂直於第一方向314。閘極結構308位於交替的半導體材料鰭狀物103a及103b及隔離材料202的部份上。閘極結構308包含閘極材料層310，其與半導體材料鰭狀物103a及103b之間隔有閘極介電層302。在某些實施例中，閘極介電層302可包含氧化矽層(如SiO2)或高介電常數之介電層。在多種實施例中，閘極材料層310可包含多晶矽層或金屬閘極層(如鋁、氧化鋁、或類似物)。
側壁間隔物110可位於閘極結構308的相反兩側上。側壁間隔物110包含氣隙114於絕緣材料的第一層112與絕 緣材料的第二層116之間。氣隙114位於源極區104與汲極區106上，因此氣隙114的高度低於閘極結構308。舉例來說，氣隙114的高度h1低於閘極結構308的高度h2。
在某些實施例中，氣隙114包含L型的氣隙，其第一開口114a位於源極區104與汲極區106上的側壁間隔物110中，而第二開口114b位於垂直於側壁間隔物110上的側壁間隔物110之一側中。
第4圖係某些實施例中，形成FinFET裝置的方法400之流程圖，且FinFET裝置之側壁間隔物具有氣隙。
雖然下述的方法400具有一連串的步驟或事件，應理解的是這些步驟或事件的順序僅用以舉例而非侷限本發明。舉例來說，某些步驟之順序可與下述順序不同，及/或與下述或未提及的其他步驟同時執行。此外，本發明的一或多個實施例不需進行所有的步驟。另一方面，下述的一或多個步驟可分開進行。
步驟402形成一或多個半導體材料鰭狀物於半導體基板上。一或多半導體材料鰭狀物自半導體基板突出如三維結構。在某些實施例中，半導體材料鰭狀物彼此之間隔有隔離材料的部份。
在某些實施例中，步驟404可形成閘極介電層於一或多個半導體材料鰭狀物上。
步驟406形成虛置閘極結構於橫越一或多個半導體材料鰭狀物的位置上。虛置閘極結構自半導體基板突出，如同位於一或多個半導體材料鰭狀物上的第二鰭狀物。在某些實 施例中，虛置閘極結構可形成於閘極介電層上。
步驟408形成側壁間隔物於虛置閘極結構的相反兩側上，且側壁間隔物具有虛置氣隙層。
在某些實施例中，側壁間隔物的形成方法可為選擇性沉積絕緣材料(如SiN)的第一層於虛置閘極結構的側壁上，比如步驟410。接著進行步驟412，形成虛置氣隙層(如多晶矽)於絕緣材料的第一層上。步驟414形成絕緣材料(如SiN)的第二層於虛置氣隙層上。
步驟416移除虛置氣隙層與虛置閘極結構。在某些實施例中，可由相同蝕刻製程同時移除虛置閘極結構與虛置氣隙層。移除虛置氣隙層的結果為側壁間隔物具有空腔。氣隙可讓側壁間隔物具有低介電常數(k~1)。
步驟418形成置換閘極結構於被移除的虛置閘極結構之位置中。在某些實施例中，形成置換閘極結構的步驟包括在沉積置換閘極結構於閘極介電層上前，先沉積層間閘極介電層或高介電常數之閘極介電層於被移除的虛置閘極結構之位置中。
步驟420形成源極與汲極區於閘極結構之相反兩側的一或多個半導體材料鰭狀物中。側壁間隔物將定義源極與汲極區(或輕掺雜源極與汲極區)的位置。舉例來說，某些實施例進行佈植製程，可選擇性地佈植掺質至一或多個半導體材料鰭狀物中，以形成源極與汲極區。在此實施例中，側壁間隔物可作為佈植製程的遮罩層。
其他實施例中源極與汲極區的形成方法，係磊晶 成長掺雜的半導體材料於一或多個半導體材料鰭狀物中的源極與汲極凹陷中。舉例來說，某些實施例可形成源極凹陷與汲極凹陷，接著沉積磊晶材料於源極與汲極凹陷中，以形成源極與汲極區。
第5至10圖係某些實施例中，FinFET裝置之形成方法中半導體基板的剖視圖，且FinFET裝置之側壁間隔物具有氣隙。雖然第5至10圖對應方法400，但應理解第5至10圖之結構的形成方法並不限於方法400。
第5圖係某些實施例中，對應步驟402之半導體基板的立體圖500。
如立體圖500所示，一或多個半導體材料鰭狀物502係形成於半導體基板102上。一或多個半導體材料鰭狀物502係由半導體基板102向外突出如三維結構。一或多個半導體材料鰭狀物502之間隔有隔離材料504的部份，因此一或多個半導體材料鰭狀物502交錯於隔離材料504的部份之間。
在某些實施例中，一或多個半導體材料鰭狀物502之形成方法可為將半導體基板102選擇性露出至蝕刻品，以蝕刻半導體基板並形成溝槽。上述蝕刻品可為氫氧化四甲基銨(TMAH)、氫氧化鉀(KOH)、或類似物。接著形成隔離材料504(如氧化物)於半導體材料的部份之間的溝槽中。接著平坦化半導體基板102，並回蝕刻隔離材料504，使半導體材料的部份凸起為隔離材料504上的一或多個半導體材料鰭狀物502。
第6圖係某些實施例中，對應步驟404之半導體基板的立體圖600。
如立體圖600所示，閘極介電層604可選擇性地形成於一或多個半導體材料鰭狀物502上。在某些實施例中，閘極介電層604可包含氧化矽(SiO2)層或高介電常數之介電層。在其他實施例中，閘極介電層604可包含高介電常數之介電層如氧化鉿(HfO2)、氧化鈦(TiO2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta2O3)、或類似物。
第7圖係某些實施例中，對應步驟406之半導體基板的立體圖700。
如立體圖700所示，虛置閘極結構702係形成於一或多個三維的半導體材料鰭狀物502上。在某些實施例中，虛置閘極結構702之形成方法可為沉積多晶矽704於閘極介電層604上。接著形成圖案化的硬遮罩層706於多晶矽704上。在多種實施例中，圖案化的硬遮罩層706可包含任何合適硬遮罩材料如氧化物或氮化矽(SiN)。接著依據圖案化的硬遮罩層706蝕刻多晶矽704，以形成虛置閘極結構702於一或多個半導體材料鰭狀物502上。
第8A至8C圖係某些實施例中，對應步驟408之半導體基板的剖視圖。
如剖視圖800所示，形成絕緣材料的第一層112。絕緣材料的第一層112係連續膜，自虛置閘極結構702之側壁延伸至三維的半導體材料鰭狀物502及/或閘極介電層604上。在某些實施例中，絕緣材料的第一層112可包含氮化矽(SiN)。在某些實施例中，絕緣材料的第一層112之沉積方法可為化學氣相沉積、物理氣相沉積、或類似方法。
如剖視圖802所示，虛置氣隙層804係形成於絕緣材料的第一層112上。虛置氣隙層804係連續膜，並朝橫向與垂直方向延伸。在某些實施例中，虛置氣隙層804可包含多晶矽。在某些實施例中，虛置氣隙層804之沉積方法可為化學氣相沉積、物理氣相沉積、或類似方法。
如剖視圖806所示，絕緣材料的第二層116係形成於虛置氣隙層804上。絕緣材料的第二層116係連續膜，且朝橫向與垂直方向延伸。在某些實施例中，絕緣材料的第二層116之沉積方法可為化學氣相沉積、物理氣相沉積、或類似方法。
第9A至9B圖係某些實施例中，對應步驟416之半導體基板的立體圖與剖視圖。第9A圖係對應步驟416之半導體基板的立體圖900，而第9B圖係對應第9A圖之半導體基板的剖視圖904。
如立體圖900所示，露出基板至蝕刻品902。蝕刻品902係用以同時移除虛置閘極結構702與虛置氣隙層804。移除虛置氣隙層804可形成氣隙114於側壁間隔物110中，且氣隙114位於絕緣材料的第一層112與絕緣材料的第二層116之間。氣隙114可降低側壁間隔物110的介電常數。
蝕刻品902具有高蝕刻選擇比，其蝕刻虛置氣隙層804的速率，實質上高於蝕刻絕緣材料的第一層112與絕緣材料的第二層114之速率，兩種蝕刻速率的比值可大於五倍。如此一來，完全移除虛置氣隙層804後，可實質上完好保留絕緣材料的第一層112與絕緣材料的第二層114。在某些實施例中，蝕刻品902可包含濕式蝕刻品。在其他實施例中，蝕刻品902可包 含濕式蝕刻品與乾式蝕刻品的組合。
第10圖係某些實施例中，對應步驟418至420的半導體基板之立體圖1000。
如立體圖1000所示，置換閘極結構1002係形成於虛置閘極結構702被移除後的位置中。在某些實施例中，置換閘極結構1002之形成方法可為沉積金屬置換閘極至閘極介電層604上。在某些實施例中，金屬置換閘極1002可包含鋁，其形成方法可為沉積技術。在其他實施例中，金屬置換閘極1002的形成方法包括在沉積金屬置換閘極之前，先沉積置換換閘極介電層於一或多個半導體材料鰭狀物502上。在多種實施例中，置換閘極介電層可包含層間閘極介電層或高介電常數之閘極介電層。
如立體圖1000所示，選擇性移除半導體材料鰭狀物502以形成源極與汲極凹陷。源極與汲極凹陷的形成方法可為一或多道蝕刻製程，包含乾蝕刻製程及/或濕蝕刻製程(比如採用濕式蝕刻品如四氟化碳(CF4)、氫氟酸(HF)、氫氧化四甲基銨(TMAH)、或類似物)。接著形成源極區304與汲極區320，其形成方法為磊晶成長以沉積磊晶材料。在多種實施例中，磊晶材料可包含矽、矽鍺(SiGe)、碳化矽(SiC)、或類似物。可以理解的是，雖然圖式中的源極區304與汲極區320為鑽石狀，但源極區304與汲極區320一般可具有任何輪廓而不限於圖示形狀。
如此一來，本發明係關於FinFET裝置與其形成方法，且FinFET裝置包含氣隙使側壁間隔物具有低介電常數。
在某些實施例中，本發明關於鰭狀場效電晶體裝 置的形成方法，其包括：形成半導體材料鰭狀物於半導體基板上，以及形成閘極結構凸出半導體基板，且閘極結構位於半導體材料鰭狀物上，其中閘極結構包括閘極介電層與其上的閘極材料層。此方法更包括形成源極區與汲極區於閘極結構的相反兩端上，且源極區與汲極區電性接觸半導體材料鰭狀物。此方法更包括形成多個側壁間隔物以鄰接閘極結構的相反兩側，其中側壁間隔物各自包括與閘極結構鄰接之絕緣材料的第一層，以及絕緣材料的第二層，且絕緣材料的第一層與絕緣材料的第二層之間隔有氣隙。
在其他實施例中，本發明關於鰭狀場效電晶體裝置的形成方法，其包括：形成一或多個半導體材料鰭狀物於隔離材料的部份之間的半導體基板上，以及形成虛置閘極結構凸出半導體基板，且虛置閘極結構位於半導體材料鰭狀物上。此方法更包括形成絕緣材料的第一層於虛置閘極結構的側壁與半導體材料鰭狀物的頂部上；形成一虛置氣隙層於絕緣材料的第一層之側壁上；以及形成絕緣材料的第二層於虛置氣隙層上。此方法更包括同時移除虛置氣隙層與虛置閘極結構，其中移除虛置氣隙層將形成多個氣隙於絕緣材料的第一層與絕緣材料的第二層之間。此方法更包括形成源極區與汲極區於閘極結構的相反兩端上，且源極區與汲極區電性接觸半導體材料鰭狀物。
在又一實施例中，本發明關於鰭狀場效電晶體裝置，其包括：三維的半導體材料鰭狀物，自隔離材料之第一與第二部份之間的基板凸出。鰭狀場效電晶體裝置更包括閘極結 構，位於三維的半導體材料鰭狀物上，並設置以控制三維的半導體材料鰭狀物中的通道區內之電荷載子流。鰭狀場效電晶體裝置更包括多個側壁間隔物，與閘極結構的兩個相反側壁鄰接，其中側壁間隔物各自包含與閘極結構鄰接的絕緣材料的第一層，以及絕緣材料的第二層，其中絕緣材料的第一層與絕緣材料的第二層之間隔有氣隙。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧半導體基板
103‧‧‧半導體材料鰭狀物
104‧‧‧源極區
106‧‧‧汲極區
108‧‧‧閘極結構
110‧‧‧側壁間隔物
112‧‧‧絕緣材料的第一層
114‧‧‧氣隙
116‧‧‧絕緣材料的第二層
200‧‧‧FinFET裝置
202‧‧‧隔離材料
204‧‧‧第二方向
206‧‧‧第一方向

Claims (20)

  1. 一種鰭狀場效電晶體裝置的形成方法，包括：形成一半導體材料鰭狀物於一半導體基板上；形成一閘極結構凸出該半導體基板，且該閘極結構位於該半導體材料鰭狀物上，其中該閘極結構包括一閘極介電層與其上的一閘極材料層；形成一源極區與一汲極區於該閘極結構的相反兩端上，且該源極區與該汲極區電性接觸該半導體材料鰭狀物；以及形成多個側壁間隔物以鄰接該閘極結構的相反兩側，其中該些側壁間隔物各自包括與該閘極結構鄰接之一絕緣材料的第一層，以及一絕緣材料的第二層，且該絕緣材料的第一層與該絕緣材料的第二層之間隔有一氣隙。
  2. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中形成該些側壁間隔物之步驟包括：形成該絕緣材料的第一層於該閘極結構的側壁與該半導體材料鰭狀物的頂部上；形成一虛置氣隙層於該絕緣材料的第一層之側壁上；形成該絕緣材料的第二層於該虛置氣隙層的側壁上；以及移除該虛置氣隙層，以形成該氣隙於該絕緣材料的第一層與該絕緣材料的第二層之間。
  3. 如申請專利範圍第2項所述之鰭狀場效電晶體裝置的形成方法，其中形成該閘極結構之步驟包括：形成一虛置閘極結構於該半導體材料鰭狀物上；在形成該些側壁間隔物後，移除該虛置閘極結構； 沉積一層間閘極介電層或一高介電常數之閘極介電層於該虛置閘極結構移除後之位置中；以及沉積一金屬置換閘極於該層間閘極介電層或該高介電常數之閘極介電層上。
  4. 如申請專利範圍第3項所述之鰭狀場效電晶體裝置的形成方法，其中該虛置閘極結構與該虛置氣隙層係同時被移除。
  5. 如申請專利範圍第2項所述之鰭狀場效電晶體裝置的形成方法，其中該虛置氣隙層的移除製程採用濕式蝕刻品與乾式蝕刻品。
  6. 如申請專利範圍第2項所述之鰭狀場效電晶體裝置的形成方法，其中該虛置氣隙層包括多晶矽。
  7. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中該絕緣材料的第一層與該絕緣材料的第二層包括氮化矽。
  8. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中該氣隙包括L型的氣隙，且該氣隙與該閘極結構之間隔有該絕緣材料的第一層。
  9. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中該氣隙包括L型的氣隙，且具有一開口位於該側壁間隔物的一側中並垂直於部份該側壁間隔物上。
  10. 一種鰭狀場效電晶體裝置的形成方法，包括：形成一或多個半導體材料鰭狀物於隔離材料的部份之間的一半導體基板上；形成一虛置閘極結構凸出該半導體基板，且該虛置閘極結 構位於一或多個該半導體材料鰭狀物上；形成一絕緣材料的第一層於該虛置閘極結構的側壁與一或多個該半導體材料鰭狀物的頂部上；形成一虛置氣隙層於該絕緣材料的第一層之側壁上；形成一絕緣材料的第二層於該虛置氣隙層上；同時移除該虛置氣隙層與該虛置閘極結構，其中移除該虛置氣隙層將形成多個氣隙於該絕緣材料的第一層與該絕緣材料的第二層之間；以及形成一源極區與一汲極區於該閘極結構的相反兩端上，且該源極區與該汲極區電性接觸一或多個該半導體材料鰭狀物。
  11. 如申請專利範圍第10項所述之鰭狀場效電晶體裝置的形成方法，更包括：沉積一層間閘極介電層或一高介電常數之閘極介電層於該虛置閘極結構被移除的位置中；以及沉積一金屬置換閘極於該層間閘極介電層或該高介電常數之閘極介電層上。
  12. 如申請專利範圍第11項所述之鰭狀場效電晶體裝置的形成方法，其中該些氣隙包括L型氣隙，且該些氣隙與該閘極結構之間隔有該絕緣材料的第一層。
  13. 如申請專利範圍第10項所述之鰭狀場效電晶體裝置的形成方法，其中該虛置氣隙層的移除步驟為一蝕刻製程，且該蝕刻製程採用濕式蝕刻品與乾式蝕刻品。
  14. 如申請專利範圍第10項所述之鰭狀場效電晶體裝置的形成 方法，其中該虛置氣隙層包括多晶矽。
  15. 如申請專利範圍第10項所述之鰭狀場效電晶體裝置的形成方法，其中該絕緣材料的第一層與該絕緣材料的第二層包括氮化矽。
  16. 一種鰭狀場效電晶體裝置，包括：一三維的半導體材料鰭狀物，自一隔離材料之第一與第二部份之間的一基板凸出；一閘極結構，位於該三維的半導體材料鰭狀物上，並設置以控制該三維的半導體材料鰭狀物中的一通道區內之電荷載子流；以及多個側壁間隔物，與該閘極結構的兩個相反側壁鄰接，其中該些側壁間隔物各自包含與該閘極結構鄰接的一絕緣材料的第一層，以及一絕緣材料的第二層，其中該絕緣材料的第一層與該絕緣材料的第二層之間隔有一氣隙。
  17. 如申請專利範圍第16項所述之鰭狀場效電晶體裝置，其中該氣隙包括L型氣隙，且該氣隙與該閘極結構之間隔有該絕緣材料的第一層。
  18. 如申請專利範圍第16項所述之鰭狀場效電晶體裝置，其中該絕緣材料的第一層與該絕緣材料的第二層包括氮化矽。
  19. 如申請專利範圍第16項所述之鰭狀場效電晶體裝置，其中該側壁間隔物的高度，大於兩倍之該側壁間隔物的寬度。
  20. 如申請專利範圍第16項所述之鰭狀場效電晶體裝置，其中該氣隙包括L型氣隙，並具有一開口位於該側壁間隔物的一側中並垂直於部份該側壁間隔物上。
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