WO2013111496A1 - Procédé de fabrication d'une résistance de puce - Google Patents

Procédé de fabrication d'une résistance de puce Download PDF

Info

Publication number
WO2013111496A1
WO2013111496A1 PCT/JP2012/083569 JP2012083569W WO2013111496A1 WO 2013111496 A1 WO2013111496 A1 WO 2013111496A1 JP 2012083569 W JP2012083569 W JP 2012083569W WO 2013111496 A1 WO2013111496 A1 WO 2013111496A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
resistor
fuse
chip
resistance
Prior art date
Application number
PCT/JP2012/083569
Other languages
English (en)
Japanese (ja)
Inventor
博司 玉川
靖浩 近藤
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Publication of WO2013111496A1 publication Critical patent/WO2013111496A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C13/00—Resistors not provided for elsewhere
    • H01C13/02—Structural combinations of resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques
    • H01C17/12—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques by sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/22—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming

Definitions

  • the present invention relates to a method of manufacturing a chip resistor as a discrete component.
  • a chip resistor has a configuration including an insulating substrate such as ceramic, a resistance film formed by screen printing a material paste on the surface, and an electrode connected to the resistance film.
  • laser trimming has been performed in which a trimming groove is formed by irradiating the resistance film with a laser beam (see Patent Document 1).
  • Patent Document 2 Another conventional example of a chip resistor is disclosed in Patent Document 2.
  • the disclosed chip resistor has a configuration in which a pair of electrodes are provided on a lower surface of a metal chip-like resistor with a gap therebetween. This chip resistor cannot adjust the resistance value.
  • the conventional chip resistor Since the conventional chip resistor is adjusted so that the resistance value becomes a target value by laser trimming, it cannot cope with a wide range of resistance values.
  • chip resistors since chip resistors have been miniaturized year by year, it has been difficult to increase the resistance due to restrictions on the arrangement area of the resistance film even if high resistance products are developed.
  • chip resistors are prone to problems such as transport errors when mounted on the board unless the shape and dimensional accuracy is improved, improvements in shape and size accuracy and microfabrication accuracy are important in the manufacture of chip resistors. It was a challenge. *
  • the present invention has been made based on such a background, and it is a main object of the present invention to provide a method of manufacturing a chip resistor with improved shape dimensional accuracy and fine processing accuracy. Another object of the present invention is to provide a method of manufacturing a chip resistor having a small and accurate resistance value.
  • a step of forming a resistor film on a substrate, a step of forming a wiring film in contact with the surface of the resistor film, and a first step on the wiring film by photolithography A step of forming a resist pattern; a first etching step of etching the wiring film and the resistor film using the first resist pattern as a mask; and a step of etching the wiring film after the first etching step by photolithography.
  • Forming a plurality of resistors on the substrate by forming a second resist pattern thereon and partially etching the wiring film on the resistor film using the second resist pattern as a mask A chip resistor manufacturing method including a second etching step.
  • the first resist pattern includes a resistor region in which the plurality of resistors are to be formed, a pad region for external connection, and a fuse between the resistor region and the pad region.
  • a region is a resist pattern formed by the first etching step, and the plurality of resistors are electrically taken into the resistor circuit network in the fuse region by the first etching step, or from the resistor circuit network.
  • the first resist pattern includes a pair of pad regions, the electrical resistance between the pair of pad regions is measured after the second etching step, and the measurement is performed.
  • the chip resistor manufacturing method according to claim 2 further comprising: selecting a fuse to be cut from the plurality of fuses based on a measured electrical resistance; and a fuse cutting step of cutting the selected fuse. Is the method. *
  • the invention according to claim 4 is the method for manufacturing the chip resistor according to claim 3, further comprising a step of forming a cover film covering the plurality of fuses before the fuse cutting step.
  • a step of forming a protective film that covers the wiring film after the fuse cutting step, and a pad opening that exposes a part of the pad region to the protective film using photolithography is the method for manufacturing the chip resistor according to claim 3, further comprising a step of forming.
  • the invention according to claim 6 is the method of manufacturing a chip resistor according to claim 5, further comprising a step of plating and growing an external connection electrode in the pad opening.
  • the step of forming the protective film includes a step of forming a passivation film covering the wiring film by a CVD (chemical vapor deposition) method. It is a manufacturing method of a resistor.
  • the step of forming the protective film includes a step of forming a photosensitive resin coating film on the passivation film, and the step of forming the pad opening includes forming the coating film on the pad.
  • the method includes: exposing with an exposure pattern corresponding to the opening; developing the coating film after exposure; and etching and opening the passivation film using the developed coating film as a mask. It is a manufacturing method of the chip resistor described in 1. *
  • the invention according to claim 9 is a step in which the substrate includes a plurality of chip resistor regions, and a third resist pattern corresponding to a boundary region of the plurality of chip resistor regions is formed on the substrate by photolithography.
  • a third etching step of forming a groove having a predetermined depth from the front surface of the substrate in the boundary region of the substrate by etching using the third resist pattern as a mask, and until the back surface of the substrate reaches the groove The chip resistor manufacturing method according to any one of claims 1 to 8, further comprising a step of grinding and dividing the substrate into a plurality of chip resistors. *
  • the chip resistor according to claim 1 further comprising a step of forming an insulating film on the surface of the substrate before forming the resistor film. It is a manufacturing method.
  • the invention according to claim 11 further includes a step of measuring a sheet resistance value of the formed resistor film after forming the resistor film on the substrate. It is a manufacturing method of a chip resistor.
  • the invention according to claim 12 is the method for manufacturing a chip resistor according to claim 11, wherein the sheet resistance value of the resistor film is measured by a probe method using a probe probe.
  • the invention according to claim 13 is the chip resistor according to claim 11 or 12, wherein the step of measuring the sheet resistance value includes a step of calculating a film thickness of the resistor film based on the measured sheet resistance value. It is a manufacturing method.
  • the resistance circuit arrangement can be accurately made with a very fine pattern and the resistance value is stable. Further, it is possible to provide a chip resistance value with a small and accurate resistance value. Particularly, since the resistance circuit pattern is formed by photolithography, a fine and accurate pattern can be formed.
  • a chip resistor can be procured to desired resistance value, and it can be set as the manufacturing method which can attain the implementation
  • the fifth aspect of the present invention it is possible to provide a manufacturing method capable of manufacturing a chip resistor having a small and accurate resistance value and having good shape dimensional accuracy for mounting and ensuring reliability.
  • the sixth aspect of the present invention it is possible to provide a chip resistor manufacturing method capable of satisfactorily making external connection electrodes.
  • the reliability of the manufactured chip resistor can be improved by covering the manufactured chip resistor with a dense protective film.
  • the eighth aspect of the present invention it is possible to provide a manufacturing method that realizes accurate microfabrication for a small chip resistor.
  • the external dimension accuracy of the chip resistor can be improved by a photolithography process.
  • the substrate when the substrate is conductive, an accurate resistance value can be formed on the substrate.
  • the resistance resistance sheet is confirmed at this stage by measuring the sheet resistance value of the resistor film, so that the resistance wiring is formed into a desired shape in a later photolithography process. The resistance value can be stabilized.
  • the film thickness of the resistor film is calculated based on the measured sheet resistance value, when the sheet resistance value is not a desired value, the following chip resistor is controlled by the film thickness control.
  • the manufacturing process can be adjusted and improved, and a desired sheet resistance value can be obtained.
  • FIG. 1A is an illustrative perspective view showing an external configuration of a chip resistor 10 according to an embodiment of the present invention
  • FIG. 1B shows the chip resistor 10 mounted on a substrate. It is a side view which shows a state.
  • FIG. 2 is a plan view of the chip resistor 10, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view.
  • FIG. 3A is an enlarged plan view illustrating a part of the resistor network 14 shown in FIG.
  • FIG. 3B is a longitudinal sectional view in the length direction for explaining the configuration of the resistor R in the resistor network 14.
  • FIG. 1A is an illustrative perspective view showing an external configuration of a chip resistor 10 according to an embodiment of the present invention
  • FIG. 1B shows the chip resistor 10 mounted on a substrate. It is a side view which shows a state.
  • FIG. 2 is a plan view of the chip resistor 10, showing the arrangement
  • FIG. 3C is a longitudinal sectional view in the width direction drawn for explaining the configuration of the resistor R in the resistor network 14.
  • FIG. 4 is a diagram showing the electrical characteristics of the resistance film line 20 and the conductor film 21 with circuit symbols and electrical circuit diagrams.
  • 5A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and
  • FIG. 5B is a plan view of FIG. 2 is a diagram showing a cross-sectional structure taken along line BB in FIG.
  • FIG. 6 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG.
  • FIG. 7 is an electric circuit diagram of the resistor network 14.
  • FIG. 8 is a plan view of the chip resistor 30, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view.
  • FIG. 9 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. 8, and the connecting conductor film C and the fuse film F connected to the connecting conductor film C and the fuse film F.
  • FIG. 10 is an electric circuit diagram of the resistor network 14.
  • FIGS. 11A and 11B are electric circuit diagrams showing modifications of the electric circuit shown in FIG.
  • FIG. 12 is an electric circuit diagram of a resistor network 14 according to still another embodiment of the present invention.
  • FIG. 13 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying a specific resistance value.
  • FIG. 14 is a schematic plan view for explaining a main structure of a chip resistor 90 according to still another embodiment of the present invention.
  • FIG. 15 is a flowchart showing an example of the manufacturing process of the chip resistor 10.
  • FIG. 10 is an electric circuit diagram of the resistor network 14.
  • FIGS. 11A and 11B are electric circuit diagrams showing modifications of the electric circuit shown in FIG.
  • FIG. 12 is an electric circuit diagram of a resistor network 14 according to still another embodiment of the present invention.
  • FIG. 13 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying
  • FIG. 16 is a schematic cross-sectional view showing the fusing process of the fuse film F and the passivation film 22 and the resin film 23 formed thereafter.
  • FIG. 17 is an illustrative view showing processing steps for separating the wafer into individual chip resistors.
  • FIG. 18 is an illustrative view illustrating that a chip resistor is cut out from a wafer.
  • FIG. 19A is an illustrative perspective view showing an external configuration of a chip resistor 310 according to an embodiment of the first reference example, and FIG. 19B shows the chip resistor 310 mounted on a substrate. It is a side view which shows the state made.
  • FIG. 19A is an illustrative perspective view showing an external configuration of a chip resistor 310 according to an embodiment of the first reference example
  • FIG. 19B shows the chip resistor 310 mounted on a substrate. It is a side view which shows the state made.
  • FIG. 20 is a plan view of the chip resistor 310, showing the positional relationship between the first connection electrode 312, the second connection electrode 313, and the resistor network 314 and the configuration of the resistor network 314 in plan view.
  • FIG. 21A is an enlarged plan view of a part of the resistor network 314 shown in FIG.
  • FIG. 21B is a longitudinal sectional view in the length direction drawn for explaining the configuration of the resistor R in the resistor network 314.
  • FIG. 21C is a longitudinal sectional view in the width direction drawn to explain the configuration of the resistor R in the resistor network 314.
  • FIG. 22 is a diagram showing the electrical characteristics of the resistance film line 320 and the conductor film 321 with circuit symbols and electrical circuit diagrams.
  • FIG. 23A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 20, and
  • FIG. 2 is a diagram showing a cross-sectional structure taken along line BB in FIG.
  • FIG. 24 shows the arrangement relationship of the connection conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistance network 314 shown in FIG. 20, and the connection conductor film C and the fuse film F connected to the connection conductor film C and the fuse film F. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically.
  • FIG. 25 is an electrical circuit diagram of the resistor network 314.
  • FIG. 26 is a plan view of the chip resistor 330, showing the arrangement relationship of the first connection electrode 312, the second connection electrode 313, and the resistance network 314 and the configuration of the resistance network 314 in plan view.
  • FIG. 27 shows the arrangement relationship of the connection conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistance network 314 shown in FIG. 26, and the connection conductor film C and the fuse film F connected to the connection conductor film C and the fuse film F. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically.
  • FIG. 28 is an electrical circuit diagram of the resistor network 314.
  • FIGS. 29A and 29B are electric circuit diagrams showing modifications of the electric circuit shown in FIG. FIG.
  • FIG. 30 is an electric circuit diagram of a resistor network 314 according to still another embodiment of the first reference example.
  • FIG. 31 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying a specific resistance value.
  • FIG. 32 is an illustrative plan view for explaining a main structure of a chip resistor 390 according to still another embodiment of the first reference example.
  • FIG. 33 is a flowchart showing an example of the manufacturing process of the chip resistor 310.
  • FIG. 34 is a schematic cross-sectional view showing the fusing process of the fuse film F and the passivation film 322 and the resin film 323 to be formed thereafter.
  • FIG. 35 is an illustrative view showing a process of separating the chip resistors from the substrate.
  • FIG. 36 is an illustrative view for explaining that the chip resistor is cut out from the substrate.
  • FIG. 37 is a perspective view illustrating an appearance of a smartphone that is an example of an electronic device in which the chip resistor manufactured by the manufacturing method of the first reference example is used.
  • FIG. 38 is a schematic plan view showing the configuration of the electronic circuit assembly 510 housed inside the housing 502.
  • FIG. 1A is an illustrative perspective view showing an external configuration of a chip resistor 10 according to an embodiment of the present invention
  • FIG. 1B shows the chip resistor 10 mounted on a substrate. It is a side view which shows a state.
  • a chip resistor 10 according to an embodiment of the present invention includes a first connection electrode 12, a second connection electrode 13, and a resistor network 14 formed on a substrate 11. It has.
  • the substrate 11 has a substantially rectangular parallelepiped shape in plan view.
  • the length L in the long side direction is 0.3 mm
  • the width W in the short side direction is 0.15 mm
  • the thickness T is about 0.1 mm. It is a very small chip.
  • the substrate 11 may have a rounded corner shape with chamfered corners in plan view. *
  • the chip resistor 10 is obtained by forming a large number of chip resistors 10 in a lattice shape on a wafer and cutting the wafer into individual chip resistors 10.
  • the first connection electrode 12 is a rectangular electrode extending in the direction of the short side 111 provided along one short side 111 of the substrate 11.
  • the second connection electrode 13 is a rectangular electrode extending in the direction of the short side 112 provided along the other short side 112 on the substrate 11.
  • the resistance network 14 is provided in a central region (circuit formation surface or element formation surface) sandwiched between the first connection electrode 12 and the second connection electrode 13 on the substrate 11.
  • the first connection electrode 12, the second connection electrode 13, and the resistance network 14 are provided on the substrate 11 by using, for example, a semiconductor manufacturing process. Accordingly, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 11. In other words, the discrete chip resistor 10 can be manufactured using an apparatus and equipment for manufacturing a semiconductor device. In particular, the resistance network 14 having a fine and accurate layout pattern can be formed by using a photolithography process described later.
  • the substrate 11 may be other types of substrates such as a glass substrate, a ceramic substrate, and an insulating substrate. *
  • the first connection electrode 12 and the second connection electrode 13 each function as an external connection electrode.
  • the first connection electrode 12 and the second connection electrode 13 are respectively connected to a circuit (not shown) of the circuit board 15. ) And solder and are electrically and mechanically connected.
  • the first connection electrode 12 and the second connection electrode 13 that function as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable. *
  • FIG. 2 is a plan view of the chip resistor 10, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13 and the resistor network 14 and the configuration (layout pattern) of the resistor network 14 in plan view.
  • the chip resistor 10 includes a first connection electrode 12 having a substantially rectangular shape in a plan view and disposed so that a long side thereof extends along one short side 111 of the upper surface of the substrate, and the other short side 112 of the upper surface of the substrate.
  • a second connection electrode 13 having a substantially rectangular shape in plan view disposed so that its long side extends along the same, and a resistor network 14 provided in a rectangular region in plan view between the first connection electrode 12 and the second connection electrode 13; Is included. *
  • the resistor network 14 includes a plurality of unit resistors R (equal to the longitudinal direction of the substrate in the example of FIG. 2) having the same resistance value arranged in a matrix on the substrate 11.
  • the unit resistors R are arranged, and 44 unit resistors R are arranged along the column direction (width direction of the substrate), and a total of 352 unit resistors R are included.
  • a predetermined number of 1 to 64 of the large number of unit resistors R is electrically connected (by a wiring film formed of a conductor), and a plurality of unit resistors R corresponding to the number of unit resistors R connected.
  • Various resistance circuits are formed.
  • a plurality of types of formed resistance circuits are connected in a predetermined manner by a conductor film C (a wiring film formed of a conductor). *
  • a plurality of fuse films F (wiring films formed of conductors) that can be blown in order to electrically incorporate the resistor circuit into the resistor network 14 or to be electrically separated from the resistor network 14 are provided. ing.
  • the plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. More specifically, the plurality of fuse films F and the connecting conductor film C are arranged so as to be adjacent to each other, and arranged in a straight line.
  • FIG. 3A is an enlarged plan view of a part of the resistor network 14 shown in FIG. 2, and FIGS. 3B and 3C are diagrams for explaining the structure of the unit resistor R in the resistor network 14, respectively. It is the longitudinal cross-sectional view of the drawn length direction, and the longitudinal cross-sectional view of the width direction. A configuration of the unit resistor R will be described with reference to FIGS. 3A, 3B, and 3C.
  • An insulating layer (SiO 2 ) 19 is formed on the upper surface of the substrate 11 as a substrate, and a resistor film 20 is disposed on the insulating layer 19.
  • the resistor film 20 is formed of TiN, TiON, or TiSiON.
  • the resistor film 20 is a plurality of resistor films (hereinafter referred to as “resistor film lines”) extending linearly in parallel between the first connection electrode 12 and the second connection electrode 13.
  • the body membrane line 20 may be cut at a predetermined position in the line direction.
  • An aluminum film as a conductor film piece 21 is laminated on the resistor film line 20.
  • Each conductor film piece 21 is laminated on the resistor film line 20 with a predetermined interval R in the line direction.
  • each of the resistor film lines 20 in the region of the predetermined interval R forms a unit resistor R having a constant resistance value r.
  • the resistor film line 20 is short-circuited by the conductor film pieces 21. Therefore, a resistor circuit is formed which is formed by connecting in series the unit resistors R of the resistor r shown in FIG. *
  • the resistor network shown in FIG. 3A constitutes the resistor circuit shown in FIG. Yes. 3B and 3C
  • reference numeral 11 is a substrate
  • 19 is a silicon dioxide SiO2 layer as an insulating layer
  • 20 is a resistor film of TiN, TiON or TiSiON formed on the insulating layer 19.
  • 21 is an aluminum (Al) wiring film
  • 22 is a SiN film as a protective film
  • 23 is a polyimide layer as a protective layer.
  • the unit resistor R included in the resistor network 14 formed on the substrate 11 is laminated on the resistor film line 20 and the resistor film line 20 with a certain interval in the line direction.
  • a resistor film line 20 at a constant interval R where the conductor film pieces 21 are not laminated includes a plurality of conductor film pieces 21 and constitutes one unit resistor R.
  • the resistor film lines 20 constituting the unit resistor R are all equal in shape and size. Therefore, based on the characteristic that the resistor films of the same shape and the same size formed on the substrate have substantially the same value, the multiple unit resistors R arranged in a matrix on the substrate 11 have the same resistance value. Have. *
  • the conductor film piece 21 laminated on the resistor film line 20 forms a unit resistor R, and also serves as a connection wiring film for connecting a plurality of unit resistors R to form a resistor circuit.
  • Plays. 5A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor 10 shown in FIG. 2, and FIG. 5B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB of A). *
  • the fuse film F is also formed of the wiring film 21 laminated on the resistor film 20. That is, it is formed of aluminum (Al) which is the same metal material as the conductor film piece 21 in the same layer as the conductor film piece 21 laminated on the resistor film line 20 forming the unit resistor R. As described above, the conductor film piece 21 is also used as a connecting conductor film C for electrically connecting a plurality of unit resistors R in order to form a resistance circuit. *
  • the wiring film for forming the unit resistor R, the connecting wiring film for forming the resistor circuit, and the resistor network 14 are made of the same metal material (for example, aluminum). , By the same manufacturing process (eg sputtering and photolithography process). Thereby, the manufacturing process of the chip resistor 10 is simplified, and various wiring films can be simultaneously formed using a common mask. Furthermore, the alignment with the resistor film 20 is also improved.
  • FIG. 6 shows the arrangement relationship of the connecting conductor film C and the fuse film F for connecting a plurality of types of resistor circuits in the resistor network 14 shown in FIG. 2, and the connecting conductor film C and the plurality of fuse films F connected to the fuse film F. It is a figure which shows the connection relation with the resistance circuit of a kind schematically. Referring to FIG. 6, one end of a reference resistor circuit R8 included in the resistor network 14 is connected to the first connection electrode 12.
  • the reference resistor circuit R8 is composed of eight unit resistors R connected in series, and the other end is connected to the fuse film F1. *
  • resistor circuit R64 composed of 64 unit resistors R connected in series are connected to the fuse film F1 and the connecting conductor film C2.
  • the connecting conductor film C2 and the fuse film F4 are connected to one end and the other end of a resistor circuit R32 composed of 32 unit resistors R connected in series.
  • the fuse film F4 and the connecting conductor film C5 are connected to one end and the other end of a resistor circuit body R32 composed of 32 unit resistors R connected in series.
  • resistor circuit R16 composed of 16 unit resistors R connected in series are connected to the connecting conductor film C5 and the fuse film F6.
  • resistor circuit R8 composed of eight unit resistors R connected in series are connected to the fuse film F7 and the connecting conductor film C9.
  • the connecting conductor film C9 and the fuse film F10 are connected to one end and the other end of a resistor circuit R4 composed of four unit resistors R connected in series.
  • resistor circuit R2 formed of a series connection of two unit resistors R are connected to the fuse film F11 and the connecting conductor film C12.
  • resistor circuit body R1 including one unit resistor R are connected to the connecting conductor film C12 and the fuse film F13.
  • resistance circuit R / 2 composed of two unit resistors R connected in parallel are connected to the fuse film F13 and the connecting conductor film C15.
  • a resistance circuit R / 4 composed of four unit resistors R connected in parallel are connected to the connecting conductor film C15 and the fuse film F16.
  • One end and the other end of a resistor circuit R / 8 composed of eight unit resistors R connected in parallel are connected to the fuse film F16 and the connecting conductor film C18.
  • One end and the other end of a resistor circuit R / 16 composed of 16 unit resistors R connected in parallel are connected to the connecting conductor film C18 and the fuse film F19.
  • a resistor circuit R / 32 composed of 32 unit resistors R connected in parallel is connected to the fuse film F19 and the connecting conductor film C22.
  • the plurality of fuse films F and the connecting conductor film C are respectively a fuse film F1, a connecting conductor film C2, a fuse film F3, a fuse film F4, a connecting conductor film C5, a fuse film F6, a fuse film F7, and a connecting conductor.
  • Film C8 connecting conductor film C9, fuse film F10, fuse film F11, connecting conductor film C12, fuse film F13, fuse film F14, connecting conductor film C15, fuse film F16, fuse film F17, connecting conductor film C18
  • the fuse film F19, the fuse film F20, the connecting conductor film C21, and the connecting conductor film C22 are arranged in a straight line and connected in series. When each fuse film F is melted, the electrical connection with the connection conductor film C adjacently connected to the fuse film F is cut off.
  • the resistance network 14 is a reference composed of a series connection of eight unit resistors R provided between the first connection electrode 12 and the second connection electrode 13.
  • a resistance circuit of the resistance circuit R8 resistance value 8r
  • the fuse films F are connected in parallel to the plurality of types of resistor circuits other than the reference resistor circuit R8, and the plurality of types of resistor circuits are short-circuited by the fuse films F. That is, 12 types of 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse film F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the resistance network 14. *
  • the chip resistor 10 selectively melts the fuse film F with, for example, laser light according to a required resistance value.
  • the resistor circuit in which the fuse films F connected in parallel are melted is incorporated into the resistor network 14. Therefore, the entire resistance value of the resistance network 14 can be a resistance network having a resistance value in which resistance circuits corresponding to the blown fuse film F are connected in series.
  • the chip resistor 10 selectively blows a fuse film provided corresponding to a plurality of types of resistance circuits, thereby providing a plurality of types of resistance circuits (for example, F1, F4,.
  • a series connection of resistance circuits R64, R32, and R1) can be incorporated into the resistance network. Since the resistance values of the plurality of types of resistance circuits are determined, the resistance value of the resistance network 14 is digitally adjusted so that the chip resistor 10 having the required resistance value is obtained. Can do. *
  • the plurality of types of resistor circuits have unit resistors R having equal resistance values in series of 1, 2, 4, 8, 16, 32, and 64, in a geometric sequence.
  • a plurality of types of series resistor circuits connected by increasing the number of unit resistors R and two, four, eight, sixteen, and thirty-two unit resistors R having the same resistance value in parallel
  • a plurality of types of parallel resistance circuits are provided which are connected by increasing the number of unit resistors R in a sequence. These are connected in series while being short-circuited by the fuse film F. Therefore, by selectively fusing the fuse film F, the resistance value of the entire resistor network 14 can be set to an arbitrary resistance value within a wide range from a small resistance value to a large resistance value.
  • FIG. 8 is a plan view of a chip resistor 30 according to another embodiment of the present invention.
  • the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 4 and the plan view of the resistor network 14 are shown.
  • the configuration of is shown.
  • the difference between the chip resistor 30 and the chip resistor 10 described above is the connection mode of the unit resistors R in the resistor network 14. *
  • the resistor network 14 of the chip resistor 30 includes a large number of unit resistors R having the same resistance value arranged in a matrix on the substrate (in the configuration of FIG. 8, in the row direction (longitudinal direction of the substrate)). 8 unit resistors R are arranged along the vertical direction, 44 unit resistors R are arranged along the column direction (substrate width direction), and a total of 352 unit resistors R are included. is doing. A predetermined number of 1 to 128 of the large number of unit resistors R are electrically connected to form a plurality of types of resistor circuits. The formed plurality of types of resistance circuits are connected in parallel by a conductor film and a fuse film F as network connection means.
  • the plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. When the fuse film F is melted, a resistance circuit connected to the fuse film is formed. In this configuration, the resistor network 14 is electrically separated.
  • FIG. 9 illustrates the connection mode of the plurality of types of resistor circuits in the resistor network shown in FIG. 8, the arrangement relationship of the fuse films F connecting them, and the connection relationship of the plurality of types of resistor circuits connected to the fuse film F.
  • a reference resistor circuit R / 16 included in the resistor network 14 is connected to the first connection electrode 12.
  • the reference resistance circuit R / 16 is composed of 16 unit resistors R connected in parallel, and the other end is connected to a connection conductor film C to which the remaining resistance circuit is connected.
  • the fuse film F1 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R128 formed of 128 unit resistors R connected in series.
  • resistor circuit R64 composed of 64 unit resistors R connected in series are connected to the fuse film F5 and the connecting conductor film C.
  • resistor circuit R32 formed of a series connection of 32 unit resistors R are connected to the resistor film F6 and the connecting conductor film C.
  • resistor circuit R16 composed of 16 unit resistors R connected in series are connected to the fuse film F7 and the connecting conductor film C.
  • a resistor circuit R8 formed of a series connection of eight unit resistors R are connected to the fuse film F8 and the connecting conductor film C.
  • the fuse film F9 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R4 formed by connecting four unit resistors R in series.
  • the fuse film F10 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R2 formed by connecting two unit resistors R in series.
  • One end and the other end of a resistor circuit R1 formed by connecting one unit resistor R in series are connected to the fuse film F11 and the connecting conductor film C.
  • the fuse film F12 and the connecting conductor film C are connected to one end and the other end of a resistance circuit R / 2 formed by connecting two unit resistors R in parallel.
  • the fuse film F13 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R / 4 formed of four unit resistors R connected in parallel.
  • the fuse films F14, F15, and F16 are electrically connected, and the fuse films F14, F15, and F16 and the connection conductor C are connected to a resistor circuit R / 8 that includes eight unit resistors R connected in parallel. Are connected at one end and the other end.
  • the fuse films F17, F18, F19, F20, and F21 are electrically connected, and the fuse films F17 to F21 and the connecting conductor film C have a resistance circuit formed by parallel connection of 16 unit resistors R. One end and the other end of R / 16 are connected. *
  • the fuse film F includes 21 fuse films F 1 to F 21, all of which are connected to the second connection electrode 13. With this configuration, when any one of the fuse films F to which one end of the resistor circuit is connected is melted, the resistor circuit having one end connected to the fuse film F is electrically disconnected from the resistor network 14. . *
  • FIG. 9 The configuration of FIG. 9, that is, the configuration of the resistor network 14 provided in the chip resistor 30 is shown in an electric circuit diagram as shown in FIG. 10.
  • the resistance network 14 includes a reference resistance circuit R / 16, 12 types of resistance circuits R / 16, between the first connection electrode 14 and the second connection electrode 13.
  • a series connection circuit is formed with a parallel connection circuit of R / 8, R / 4, R / 2, R1, R2, R4, R8, R16, R32, R64, and R128. *
  • a fuse film F is connected in series to each of 12 types of resistance circuits other than the reference resistance circuit R / 16. Therefore, in the chip resistor 30 having the resistance network 14, if the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance corresponding to the blown fuse film F is obtained.
  • the circuit resistor circuit in which the fuse film F is connected in series
  • the resistance value of the chip resistor 10 can be adjusted.
  • the chip resistor 30 also electrically disconnects the plurality of types of resistor circuits from the resistor circuit network by selectively fusing fuse films provided corresponding to the plurality of types of resistor circuits. Can be separated. Since the resistance values of the plurality of types of resistance circuits are respectively determined, the resistance value of the resistance network 14 is digitally adjusted so that the chip resistor 30 having the required resistance value is obtained. Can do.
  • the plurality of types of resistor circuits have unit resistors R having the same resistance value in series of 1, 2, 4, 8, 16, 32, 64, and 128, in a geometric sequence.
  • the number of unit resistors R is increased and connected in series, as well as two, four, eight, and sixteen unit resistances R having the same resistance value in parallel.
  • a plurality of types of parallel resistance circuits connected with an increased number of unit resistors R Therefore, by selectively fusing the fuse film F, the resistance value of the entire resistance network 14 can be set to an arbitrary resistance value in a fine and digital manner.
  • the reference resistor circuit R / 16 and the resistor circuit having a small resistance value among the resistor circuits connected in parallel tend to flow overcurrent.
  • the rated current that can be passed through is designed to be large. Therefore, in order to disperse the current, the connection structure of the resistor network may be changed so that the electric circuit shown in FIG. 10 has the electric circuit configuration shown in FIG. That is, the resistance circuit connected in parallel without the reference resistance circuit R / 16 is a circuit including the configuration 140 in which a minimum resistance value is r and a plurality of resistance unit bodies R1 having the resistance value r are connected in parallel. Change it. *
  • FIG. 11B is an electric circuit diagram showing a specific resistance value, and is a circuit including a configuration 140 in which a plurality of series connections of 80 ⁇ unit resistors and fuse films F are connected in parallel. . Thereby, distribution of the flowing current can be achieved.
  • FIG. 12 is an electric circuit diagram showing a circuit configuration of a resistor network 14 provided in a chip resistor according to still another embodiment of the present invention. A feature of the resistor network 14 shown in FIG. 12 is that the circuit configuration is such that a series connection of a plurality of types of resistor circuits and a parallel connection of a plurality of types of resistor circuits are connected in series. *
  • a fuse film F is connected in parallel to each of the plurality of types of resistor circuits connected in series, and the plurality of types of resistor circuits connected in series are all fuse films. F is short-circuited. Therefore, when the fuse film F is melted, the resistance circuit short-circuited by the fuse film F is electrically incorporated into the resistance network 14.
  • a fuse film F is connected in series to each of a plurality of types of resistor circuits connected in parallel. Therefore, by fusing the fuse film F, the resistance circuit to which the fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance circuit.
  • a small resistance of 1 k ⁇ or less can be made on the parallel connection side, and a resistance circuit of 1 k ⁇ or more can be made on the series connection side. Therefore, a wide range of resistance circuits from a small resistance of several ⁇ to a large resistance of several M ⁇ can be made using the resistance network 14 configured with the same basic design.
  • fine adjustment of the resistance value can be performed on the fuse film of the resistance circuit on the parallel connection side. Can be carried out by fusing, and the accuracy of adjustment to a desired resistance value is increased.
  • FIG. 13 is an electric circuit diagram showing a specific configuration example of the resistor network 14 in the chip resistor having a resistance value of 10 ⁇ to 1M ⁇ . Also in the resistor network 14 shown in FIG. 13, a series connection of a plurality of types of resistor circuits short-circuited by the fuse film F and a parallel connection of a plurality of types of resistor circuits to which the fuse film F is connected in series are connected in series. It has a circuit configuration. *
  • an arbitrary resistance value of 10 to 1 k ⁇ can be set within an accuracy of 1% on the parallel connection side.
  • an arbitrary resistance value of 1 k to 1 M ⁇ can be set within an accuracy of 1% in the circuit on the serial connection side.
  • the fuse film F has been described only in the case of using the same layer as the connection conductor film C.
  • the conductive film C for connection is formed by further laminating another conductor film on the conductor film C.
  • the resistance value may be lowered.
  • the resistor film may be omitted and only the connecting conductor film C may be used. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.
  • FIG. 14 is a schematic plan view for explaining a main structure of a chip resistor 90 according to still another embodiment of the present invention.
  • the chip resistor 10 see FIGS. 1 and 2
  • the chip resistor 30 see FIG. 8
  • the relationship between the resistor film line 20 and the conductor film piece 21 constituting the resistor circuit is seen in a plan view.
  • the configuration shown in FIG. That is, as shown in FIG. 14A, the portion of the resistor film line 20 in the region of the predetermined interval R forms a unit resistor R having a constant resistance value r.
  • the conductor film pieces 21 are laminated on both sides of the unit resistor R, and the resistor film line 20 is short-circuited by the conductor film pieces 21. *
  • the resistor film line 20 includes a line-shaped resistor film line 20 having a width of 1.5 ⁇ m and extending linearly.
  • portions of the resistor film line 20 having a predetermined interval R ' form a unit resistor R' having a constant resistance value r '.
  • membrane line 20 can be comprised by the same length in what is shown to FIG. 14 (A) and what is shown to (B). . Therefore, the chip resistor 90 is formed by changing the layout pattern of each unit resistor R ′ constituting the resistor circuit included in the resistor network 14 so that the unit resistors R ′ can be connected in series. Is realized with high resistance. *
  • FIG. 15 is a flowchart showing an example of the manufacturing process of the chip resistor 10 described with reference to FIGS.
  • a manufacturing method of the chip resistor 10 will be described in detail according to the manufacturing process of the flowchart and with reference to FIGS. 1 to 7 as necessary.
  • Step S1 First, a substrate 11 (actually a wafer (see FIG. 17) before being cut into individual chip resistors 10) is placed in a predetermined processing chamber, and an insulating layer is formed on the surface thereof by, for example, thermal oxidation. A silicon dioxide (SiO 2) layer 19 is formed.
  • SiO 2 silicon dioxide
  • Step S2 Next, a resistor film 20 of TiN, TiON or TiSiON is formed over the entire surface of the insulating layer 19 by, for example, sputtering.
  • Step S3 Then, the resistance value of the resistor film 20 formed over the entire surface of the insulating layer 19 is measured. This measurement is performed, for example, by a four-probe method using a four-probe probe. By measuring and confirming the sheet resistance value of the resistor film 20 at this stage, it is possible to stabilize the resistance value of the resistance wiring that is formed into a desired shape in a later photolithography process. Further, the film thickness of the resistor film 20 may be calculated based on the measured sheet resistance value. The film thickness can be used for adjusting and improving the manufacturing process for the next chip resistor, and is useful for controlling the film thickness in the next chip resistor manufacturing process and obtaining a desired sheet resistance value. *
  • Step S4 Next, for example, an aluminum (Al) wiring film 21 is laminated over the entire surface of the resistor film 20 by, eg, sputtering.
  • the total film thickness of the two layers of the resistor film 20 and the wiring film 21 laminated may be about 8000 mm.
  • Step S5 Next, using a photolithography process, a resist pattern corresponding to the configuration of the resistive network 14 in plan view (layout pattern including the conductor film C and the fuse film F) is formed on the surface of the wiring film 21. (Formation of first resist pattern). *
  • Step S6 Then, the first etching process is performed. That is, using the first resist pattern formed in step S4 as a mask, the stacked two-layer film of the resistor film 20 and the wiring film 21 is etched by, for example, reactive ion etching (RIE). Then, the first resist pattern is peeled off after the etching.
  • Step S7 A second resist pattern is formed again using a photolithography process. In the second resist pattern formed in step S7, the wiring film 21 laminated on the resistor film 20 is selectively removed, and the unit resistor R (the region indicated by the thin dots in FIG. 2) is formed. It is a pattern for forming. *
  • Step S8 Using the second resist pattern formed in step S7 as a mask, only the wiring film 21 is selectively etched, for example, by wet etching (second etching step). After the etching, the second resist pattern is peeled off. Thereby, the layout pattern of the resistor network 14 shown in FIG. 2 is obtained.
  • Step S9 At this stage, the resistance value of the resistance network 14 formed on the substrate surface (the resistance value of the entire circuit network 14) is measured. This measurement is performed by, for example, the end of the resistor network 14 on the side where the multi-probe pin is connected to the first connection electrode 12 shown in FIG. 2, the end of the fuse film and the resistor network 14 on the side connected to the second connection electrode 13. Measured in contact with. By this measurement, the quality of the manufactured resistance network 14 in the initial state can be determined. *
  • the cover film 22a may be formed by a plasma CVD method.
  • a silicon nitride film (SiN film) having a thickness of about 3000 mm may be formed.
  • the cover film 22a covers the patterned wiring film 21, resistor film 20, and fuse film F. *
  • Step S11 From this state, laser trimming for selectively fusing the fuse film F and adjusting the chip resistor 10 to a desired resistance value is performed. That is, as shown in FIG. 16A, a laser beam is applied to the fuse film F selected according to the measurement result of the total resistance measurement performed in step S8, so that the fuse film F and the position below it are positioned. The resistor film 20 is melted. Thereby, the corresponding resistance circuit short-circuited by the fuse film F is incorporated in the resistance network 14, and the resistance value of the resistance network 14 can be adjusted to a desired resistance value.
  • the energy of the laser light is accumulated in the vicinity of the fuse film F by the action of the cover film 22a, so that the fuse film F and the resistor film 20 below the fuse film F are melted. *
  • Step S12 Next, as shown in FIG. 16B, a silicon nitride film is deposited on the cover film 22a by, for example, plasma CVD to form a passivation film 22.
  • the above-described cover film 22 a is integrated with the passivation film 22 in the final form and constitutes a part of the passivation film 22.
  • the passivation film 22 formed after the fuse film F and the underlying resistor film 20 are cut is opened in the opening 22b of the cover film 22a that is simultaneously destroyed when the fuse film F and the underlying resistor film 20 are melted. It enters and protects the cut surface of the fuse film F and the underlying resistor film 20. Therefore, the passivation film 22 prevents foreign matters from entering the cut portion of the fuse film F and moisture from entering.
  • the entire passivation film 22 may be formed to have a film thickness of, for example, about 8000 mm.
  • Step S13 Next, as shown in FIG. 16C, a resin film 23 is applied to the entire surface.
  • a resin film 23 for example, a photosensitive polyimide coating film is used.
  • Step S15 Thereafter, heat treatment (polyimide cure) for curing the resin film 23 is performed, and the polyimide film 23 is stabilized by the heat treatment.
  • Step S16 Next, the passivation film 22 is etched using the polyimide film 23 having a through hole at a position where the first connection electrode 12 and the second connection electrode 13 are to be formed as a mask. As a result, a pad opening that exposes the wiring film 21 in the region of the first connection electrode 12 and the region of the second connection electrode 13 is formed. Etching of the passivation film 22 may be performed by reactive ion etching (RIE). *
  • RIE reactive ion etching
  • Step S17 The resistance value measurement (after-measurement) for confirming that the multi-probe pin is brought into contact with the wiring film 21 exposed from the two pad openings and the resistance value of the chip resistor is a desired resistance value. Done.
  • Step S18 The first connection electrode 12 and the second connection electrode 13 as the external connection electrodes are grown in the two pad openings by, for example, electroless plating. *
  • Step S19 Thereafter, a third resist pattern is formed by photolithography to separate a large number (for example, 500,000) of chip resistors arranged on the wafer surface into individual chip resistors 10. .
  • the resist film is provided on the surface of the wafer so as to protect the chip resistors 10 in FIG. 18, for example, and is formed so as to be etched between the chip resistors 10. *
  • Step S20 Then, plasma dicing is executed.
  • the plasma dicing is etching using the third resist pattern as a mask, and a groove having a predetermined depth is formed between the chip resistors 10 from the surface of the wafer as a substrate. Thereafter, the resist film is peeled off.
  • Step S21 Then, as shown in FIG. 17A, for example, the protective tape 100 is attached to the surface. *
  • Step S22 Next, the back surface of the wafer is ground, and the chip resistors are separated into individual chip resistors 10 (FIGS. 17A and 17B).
  • Step S23 Then, as shown in FIG. 17C, a large number of chip resistors 10 having carrier tapes (thermal foam sheets) 200 pasted on the back side and separated into individual chip resistors are carrier It is held in a state of being arranged on the tape 200. On the other hand, the protective tape adhered to the surface is removed (FIG. 17D). *
  • Step S24 The thermally foamed sheet 200 is heated to swell the thermally foamed particles 201 contained therein, whereby each chip resistor 10 bonded to the surface of the carrier tape 200 is peeled off from the carrier tape 200.
  • Individually separated FIGGS. 17E and 17F.
  • the present invention is not limited to the manufacturing method of the embodiment described above, and various design changes can be made within the scope of the matters described in the claims. For example, a manufacturing process not specified in the claims is changed, omitted, or added, is also included in the scope of the present invention.
  • the film thickness of the resistor film can be managed by measuring the sheet resistance before patterning the resistor film.
  • the target film thickness can be achieved by adjusting the formation conditions (formation time) of the resistor film according to the deviation from the target film thickness.
  • a chip resistor having a small size and an accurate resistance value can be realized by fine processing by etching and combining resistance values by fuses.
  • A2 The method of manufacturing a chip resistor according to A1, further including a step of measuring a sheet resistance of the wiring film before the etching step.
  • A3 A method of manufacturing a chip resistor according to A1 or A2, wherein a plurality of types of chip resistors having different resistor film thicknesses are manufactured on the same production line. To achieve a wide resistance value range, a resistor film with a uniform thickness cannot be used. Therefore, according to the invention described in A3, the required resistance value range is divided into a plurality of (for example, three) resistance film of three types of film thickness. It is confirmed that the target film thickness is obtained by measuring the sheet resistance after forming the resistor film.
  • A4 In the etching step, the wiring film and the resistor film are etched with the same mask, and the wiring film on the resistor film is partially etched after the first etching process.
  • A4 it is possible to manufacture a chip resistor of a resistance circuit that is matched with a fine structure without any deviation in the layout of the resistance film and the wiring film.
  • the substrate has a plurality of chip resistor regions divided by boundary regions, and the chip resistors are separated by cutting the substrate along the boundary regions after the etching step.
  • the sheet resistance of the resistance film is measured in a state where the resistance film is formed for the plurality of chip resistors on the substrate.
  • the resistance value management of a plurality of chip resistors can be performed in a lump, and the manufacturing efficiency is good.
  • the step of separating the chip resistors is an etching step of forming a groove having a predetermined depth from the front surface of the substrate in the boundary region of the substrate, and until the back surface of the substrate reaches the groove.
  • A7 The method of manufacturing a chip resistor according to A1, wherein the sheet resistance value of the resistor film is measured by a probe method using a probe probe. According to the invention described in A7, by measuring the sheet resistance value of the resistor film at this stage, the sheet resistance value is confirmed, and the resistance value of the resistance wiring that is formed into a desired shape in a later photolithography process is obtained. Stabilization can be realized.
  • A8 The method of manufacturing a chip resistor according to A7, wherein the step of measuring the sheet resistance value includes a step of calculating a film thickness of the resistor film based on the measured sheet resistance value.
  • the film thickness of the resistor film is calculated based on the measured sheet resistance value, when the sheet resistance value is not a desired value, the next chip resistor is manufactured by controlling the film thickness. The process can be adjusted and improved, and a desired sheet resistance value can be obtained.
  • A9 it is easy to manufacture and a plurality of types of metal films (conductor films) can be easily formed at a time by a relatively small number of processes.
  • A10 The method for manufacturing a chip resistor according to any one of A1 to A9, wherein the resistor film is formed of TiN, TiON, or TiSiON. According to the invention described in A10, it is possible to provide a chip resistor that can satisfactorily form a resistor film.
  • A11 The method for manufacturing a chip resistor according to any one of A1 to A10, further including a step of forming an insulating film on a surface of the substrate before forming the resistor film.
  • the resistor film can be electrically separated from the substrate, and the resistance value by the resistor film can be set accurately.
  • FIG. 19A is an illustrative perspective view showing an external configuration of a chip resistor 310 according to an embodiment of the first reference example
  • FIG. 19B shows the chip resistor 310 mounted on a substrate. It is a side view which shows the state made.
  • a chip resistor 310 according to an embodiment of the first reference example includes a first connection electrode 312, a second connection electrode 313, and a resistor network formed on a substrate 311. 314.
  • the substrate 311 may have a rounded shape with chamfered corners in plan view.
  • the substrate can be formed of, for example, silicon, glass, ceramic or the like. *
  • the chip resistor 310 is obtained by forming a large number of chip resistors 310 in a grid pattern on a substrate, cutting the substrate, and separating the chip resistors 310 into individual chip resistors 310.
  • the first connection electrode 312 is a rectangular electrode extending in the direction of the short side 411 provided along one short side 411 of the substrate 311.
  • the second connection electrode 313 is a rectangular electrode extending in the direction of the short side 412 provided along the other short side 412 on the substrate 311.
  • the resistance network 314 is provided in a central region (circuit formation surface or element formation surface) sandwiched between the first connection electrode 312 and the second connection electrode 313 on the substrate 311.
  • One end side of the resistor network 314 is electrically connected to the first connection electrode 312, and the other end side of the resistor network 314 is electrically connected to the second connection electrode 313.
  • the first connection electrode 312, the second connection electrode 313, and the resistance network 314 can be provided on the substrate 311 using a microfabrication process.
  • the resistance network 314 having a fine and accurate layout pattern can be formed by using a photolithography process described later.
  • Each of the second and second connection electrodes 313 functions as an external connection electrode.
  • the first connection electrode 312 and the second connection electrode 313 are respectively connected to a circuit (not shown) of the circuit board 315.
  • solder and are electrically and mechanically connected are formed of at least a surface region of gold (Au) or surface in order to improve solder wettability and reliability. It is desirable to apply gold plating to the surface.
  • FIG. 20 is a plan view of the chip resistor 310, showing the arrangement relationship of the first connection electrode 312, the second connection electrode 313, and the resistor network 314 and the configuration (layout pattern) in plan view of the resistor network 314. ing.
  • the chip resistor 310 includes a first connection electrode 312 having a substantially rectangular shape in plan view and disposed so that a long side is along one short side 411 of the upper surface of the substrate 311, and the other short surface of the upper surface of the substrate 311.
  • a second connection electrode 313 having a substantially rectangular shape in plan view disposed so that the long side extends along the side 412, and a resistor network provided in a rectangular region in plan view between the first connection electrode 312 and the second connection electrode 313 314.
  • the resistor network 314 includes a plurality of unit resistors R (equal in the row direction (longitudinal direction of the substrate 311) in the example of FIG. 20) having the same resistance value arranged in a matrix on the substrate 311.
  • the unit resistors R are arranged, and 44 unit resistors R are arranged along the column direction (the width direction of the substrate 311), and a total of 352 unit resistors R are included.
  • a predetermined number of 1 to 64 of the large number of unit resistors R is electrically connected by the conductor film C (wiring film formed of a conductor), and the number of unit resistors R connected is determined.
  • a plurality of types of corresponding resistance circuits are formed.
  • a plurality of types of formed resistance circuits are connected in a predetermined manner by a conductor film C (a wiring film formed of a conductor). *
  • a plurality of fuse films F (wiring films formed of conductors) that can be blown in order to electrically incorporate the resistor circuit into the resistor network 314 or to electrically separate it from the resistor network 314 are provided.
  • the plurality of fuse films F are arranged along the inner side of the second connection electrode 313 so that the arrangement region is linear. More specifically, the plurality of fuse films F and the connecting conductor film C are arranged so as to be adjacent to each other, and arranged in a straight line.
  • FIGS. 21A is a plan view illustrating a part of the resistor network 314 shown in FIG. 20 in an enlarged manner.
  • FIGS. 21B and 21C are diagrams for explaining the structure of the unit resistor R in the resistor network 314, respectively. It is the longitudinal cross-sectional view of the drawn length direction, and the longitudinal cross-sectional view of the width direction. The configuration of the unit resistor R will be described with reference to FIGS. 21A, 21B, and 21C. *
  • An insulating layer (SiO 2 ) 319 is formed on the upper surface of the substrate 311, and the resistor film 320 is disposed on the insulating layer 319.
  • the resistor film 320 is formed of TiN, TiON, or TiSiON.
  • the resistor film 320 is a plurality of resistor films (hereinafter referred to as “resistor film lines”) extending linearly in parallel between the first connection electrode 312 and the second connection electrode 313.
  • the body membrane line 320 may be cut at a predetermined position in the line direction.
  • an aluminum film as the conductor film piece 321 is laminated. Each conductor film piece 321 is laminated on the resistor film line 320 with a constant interval R in the line direction.
  • each of the resistor film lines 320 in the region of the predetermined interval R forms a unit resistor R having a constant resistance value r.
  • the resistor film line 320 is short-circuited by the conductor film pieces 321. Therefore, a resistance circuit is formed which is formed by connecting in series the unit resistors R of the resistor r shown in FIG. *
  • reference numeral 311 is a substrate
  • 319 is a silicon dioxide SiO 2 layer as an insulating layer
  • 320 is a resistor of TiN, TiON or TiSiON formed on the insulating layer 319.
  • Reference numeral 321 denotes an aluminum (Al) wiring film
  • 322 denotes a SiN film as a protective film
  • 323 denotes a polyimide layer as a protective layer.
  • the unit resistor R included in the resistor network 314 formed on the substrate 311 is stacked on the resistor film line 320 and the resistor film line 320 at a certain interval in the line direction.
  • a resistor film line 320 at a constant interval R where the conductor film pieces 321 are not stacked constitutes one unit resistor R.
  • the resistor film lines 320 constituting the unit resistor R are all equal in shape and size. Therefore, based on the characteristic that the same-shaped and large-sized resistor films formed on the substrate have substantially the same value, the multiple unit resistors R arranged in a matrix on the substrate 311 have the same resistance value. Have. *
  • FIG. 23A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor 310 shown in FIG. 20, and FIG. It is a figure which shows the cross-sectional structure which follows BB of A). *
  • the fuse film F is also formed of a wiring film 321 laminated on the resistor film 320. That is, it is formed of aluminum (Al), which is the same metal material as the conductor film piece 321, in the same layer as the conductor film piece 321 laminated on the resistor film line 320 forming the unit resistor R. As described above, the conductor film piece 321 is also used as a connecting conductor film C for electrically connecting a plurality of unit resistors R in order to form a resistance circuit. *
  • a wiring film for forming the unit resistor R, a connecting wiring film for forming a resistor circuit, and a connecting wiring film for forming the resistor network 314 are formed using the same metal material (for example, aluminum) and the same manufacturing process (for example, sputtering and photo Lithographic process).
  • the manufacturing process of the chip resistor 310 is simplified, and various wiring films can be simultaneously formed using a common mask. Furthermore, the alignment with the resistor film 320 is also improved.
  • FIG. 24 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistor circuits in the resistor network 314 shown in FIG. 20, and the plurality of connecting conductor films C and the fuse film F connected to the connecting conductor film C and the fuse film F. It is a figure which shows the connection relation with the resistance circuit of a kind schematically. Referring to FIG. 24, one end of a reference resistor circuit R8 included in the resistor network 314 is connected to the first connection electrode 312. The reference resistor circuit R8 is composed of eight unit resistors R connected in series, and the other end is connected to the fuse film F1. *
  • resistor circuit R64 composed of 64 unit resistors R connected in series are connected to the fuse film F1 and the connecting conductor film C2.
  • the connecting conductor film C2 and the fuse film F4 are connected to one end and the other end of a resistor circuit R32 composed of 32 unit resistors R connected in series.
  • the fuse film F4 and the connecting conductor film C5 are connected to one end and the other end of a resistor circuit body R32 composed of 32 unit resistors R connected in series.
  • resistor circuit R16 composed of 16 unit resistors R connected in series are connected to the connecting conductor film C5 and the fuse film F6.
  • resistor circuit R8 composed of eight unit resistors R connected in series are connected to the fuse film F7 and the connecting conductor film C9.
  • the connecting conductor film C9 and the fuse film F10 are connected to one end and the other end of a resistor circuit R4 composed of four unit resistors R connected in series.
  • resistor circuit R2 formed of a series connection of two unit resistors R are connected to the fuse film F11 and the connecting conductor film C12.
  • resistor circuit body R1 including one unit resistor R are connected to the connecting conductor film C12 and the fuse film F13.
  • resistance circuit R / 2 composed of two unit resistors R connected in parallel are connected to the fuse film F13 and the connecting conductor film C15.
  • a resistance circuit R / 4 composed of four unit resistors R connected in parallel are connected to the connecting conductor film C15 and the fuse film F16.
  • One end and the other end of a resistor circuit R / 8 composed of eight unit resistors R connected in parallel are connected to the fuse film F16 and the connecting conductor film C18.
  • One end and the other end of a resistor circuit R / 16 composed of 16 unit resistors R connected in parallel are connected to the connecting conductor film C18 and the fuse film F19.
  • a resistor circuit R / 32 composed of 32 unit resistors R connected in parallel is connected to the fuse film F19 and the connecting conductor film C22.
  • the plurality of fuse films F and the connecting conductor film C are respectively a fuse film F1, a connecting conductor film C2, a fuse film F3, a fuse film F4, a connecting conductor film C5, a fuse film F6, a fuse film F7, and a connecting conductor.
  • Film C8 connecting conductor film C9, fuse film F10, fuse film F11, connecting conductor film C12, fuse film F13, fuse film F14, connecting conductor film C15, fuse film F16, fuse film F17, connecting conductor film C18
  • the fuse film F19, the fuse film F20, the connecting conductor film C21, and the connecting conductor film C22 are arranged in a straight line and connected in series. When each fuse film F is melted, the electrical connection with the connection conductor film C adjacently connected to the fuse film F is cut off.
  • the resistance network 314 is a reference composed of eight unit resistors R provided in series between the first connection electrode 312 and the second connection electrode 313.
  • the fuse films F are connected in parallel to the plurality of types of resistor circuits other than the reference resistor circuit R8, and the plurality of types of resistor circuits are short-circuited by the fuse films F. That is, 12 types of 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse film F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the resistance network 314. *
  • the chip resistor 310 selectively melts the fuse film F with, for example, laser light according to a required resistance value.
  • the resistance circuit in which the fuse films F connected in parallel are melted is incorporated into the resistance network 314. Therefore, the entire resistance value of the resistor network 314 can be a resistor network having a resistance value in which resistor circuits corresponding to the blown fuse film F are connected in series.
  • the chip resistor 310 selectively blows a fuse film provided corresponding to a plurality of types of resistor circuits, thereby providing a plurality of types of resistor circuits (for example, F1, F4,.
  • a series connection of resistance circuits R64, R32, and R1) can be incorporated into the resistance network. Since the resistance values of the plurality of types of resistance circuits are respectively determined, the resistance value of the resistance network 314 is digitally adjusted so that the chip resistor 310 having the required resistance value is obtained. Can do.
  • the plurality of types of resistor circuits have unit resistors R having equal resistance values in series of 1, 2, 4, 8, 16, 32, and 64, in a geometric sequence.
  • a plurality of types of series resistor circuits connected by increasing the number of unit resistors R and two, four, eight, sixteen, and thirty-two unit resistors R having the same resistance value in parallel
  • a plurality of types of parallel resistance circuits are provided which are connected by increasing the number of unit resistors R in a sequence. These are connected in series while being short-circuited by the fuse film F. Therefore, by selectively fusing the fuse film F, the resistance value of the entire resistance network 314 can be set to an arbitrary resistance value within a wide range from a small resistance value to a large resistance value.
  • FIG. 26 is a plan view of a chip resistor 330 according to another embodiment of the first reference example.
  • the arrangement relationship of the first connection electrode 312, the second connection electrode 313, and the resistance network 314 and the resistance network 314 are shown in FIG. A plan view configuration is shown.
  • the difference between the chip resistor 330 and the chip resistor 310 described above is the connection mode of the unit resistors R in the resistor network 314. *
  • a predetermined number of 1 to 128 of the large number of unit resistors R are electrically connected to form a plurality of types of resistor circuits.
  • the formed plurality of types of resistance circuits are connected in parallel by a conductor film and a fuse film F as network connection means.
  • the plurality of fuse films F are arranged along the inner side of the second connection electrode 313 so that the arrangement region is linear. When the fuse film F is blown, a resistance circuit connected to the fuse film is formed. This configuration is electrically separated from the resistor network 314. *
  • FIG. 27 illustrates a connection mode of a plurality of types of resistor circuits in the resistor network shown in FIG. 26, an arrangement relationship of fuse films F connecting them, and a connection relationship of a plurality of types of resistor circuits connected to the fuse film F.
  • one end of reference resistance circuit R / 16 included in resistance network 314 is connected to first connection electrode 312.
  • the reference resistance circuit R / 16 is composed of 16 unit resistors R connected in parallel, and the other end is connected to a connection conductor film C to which the remaining resistance circuit is connected.
  • the fuse film F1 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R128 formed of 128 unit resistors R connected in series.
  • resistor circuit R64 composed of 64 unit resistors R connected in series are connected to the fuse film F5 and the connecting conductor film C.
  • resistor circuit R32 formed of a series connection of 32 unit resistors R are connected to the resistor film F6 and the connecting conductor film C.
  • resistor circuit R16 composed of 16 unit resistors R connected in series are connected to the fuse film F7 and the connecting conductor film C.
  • a resistor circuit R8 formed of a series connection of eight unit resistors R are connected to the fuse film F8 and the connecting conductor film C.
  • the fuse film F9 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R4 formed by connecting four unit resistors R in series.
  • the fuse film F10 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R2 formed by connecting two unit resistors R in series.
  • One end and the other end of a resistor circuit R1 formed by connecting one unit resistor R in series are connected to the fuse film F11 and the connecting conductor film C.
  • the fuse film F12 and the connecting conductor film C are connected to one end and the other end of a resistance circuit R / 2 formed by connecting two unit resistors R in parallel.
  • the fuse film F13 and the connecting conductor film C are connected to one end and the other end of a resistor circuit R / 4 formed of four unit resistors R connected in parallel.
  • the fuse films F14, F15, and F16 are electrically connected, and the fuse films F14, F15, and F16 and the connection conductor C are connected to a resistor circuit R / 8 that includes eight unit resistors R connected in parallel. Are connected at one end and the other end.
  • the fuse films F17, F18, F19, F20, and F21 are electrically connected, and the fuse films F17 to F21 and the connecting conductor film C have a resistance circuit formed by parallel connection of 16 unit resistors R. One end and the other end of R / 16 are connected. *
  • the fuse film F is provided with 21 fuse films F1 to F21, all of which are connected to the second connection electrode 313. With this configuration, when any one of the fuse films F to which one end of the resistor circuit is connected is blown, the resistor circuit having one end connected to the fuse film F is electrically disconnected from the resistor network 314. . *
  • FIG. 27 The configuration of FIG. 27, that is, the configuration of the resistor network 314 provided in the chip resistor 330 is shown in FIG. 28 as an electrical circuit diagram.
  • the resistance network 314 In a state in which all the fuse films F are not blown, the resistance network 314 is connected between the first connection electrode 314 and the second connection electrode 313, the reference resistance circuit R / 16, the 12 types of resistance circuits R / 16, A series connection circuit is formed with a parallel connection circuit of R / 8, R / 4, R / 2, R1, R2, R4, R8, R16, R32, R64, and R128. *
  • a fuse film F is connected in series to each of 12 types of resistance circuits other than the reference resistance circuit R / 16. Therefore, in the chip resistor 330 having the resistor network 314, if the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance corresponding to the blown fuse film F is obtained.
  • the circuit (the resistance circuit in which the fuse film F is connected in series) is electrically separated from the resistance network 314, and the resistance value of the chip resistor 310 can be adjusted.
  • the chip resistor 330 also electrically fuses the plurality of types of resistor circuits from the resistor network by selectively fusing the fuse film provided corresponding to the plurality of types of resistor circuits. Can be separated. Since the resistance values of the plurality of types of resistance circuits are respectively determined, the resistance value of the resistance network 314 is digitally adjusted so that the chip resistor 330 having the required resistance value is obtained. Can do. *
  • the plurality of types of resistor circuits have unit resistors R having the same resistance value in series of 1, 2, 4, 8, 16, 32, 64, and 128, in a geometric sequence.
  • the number of unit resistors R is increased and connected in series, as well as two, four, eight, and sixteen unit resistances R having the same resistance value in parallel.
  • the resistance value of the entire resistor network 314 can be set to an arbitrary resistance value finely and digitally.
  • the reference resistor circuit R / 16 and the resistor circuit having a small resistance value among the resistor circuits connected in parallel tend to flow overcurrent.
  • the rated current that can be passed through is designed to be large. Therefore, in order to disperse the current, the connection structure of the resistor network may be changed so that the electric circuit shown in FIG. 28 has the electric circuit configuration shown in FIG. That is, the reference resistor circuit R / 16 is eliminated, and the resistor circuit connected in parallel is a circuit including a configuration 440 in which a minimum resistance value is r and a plurality of resistance unit bodies R1 having the resistance value r are connected in parallel. Change it. *
  • FIG. 29B is an electric circuit diagram showing a specific resistance value, and is a circuit including a configuration 440 in which a plurality of sets of 80 ⁇ unit resistors and fuse films F are connected in parallel. . Thereby, distribution of the flowing current can be achieved.
  • FIG. 30 is an electric circuit diagram showing a circuit configuration of a resistor network 314 provided in a chip resistor according to still another embodiment of the first reference example. A characteristic of the resistor network 314 shown in FIG. 30 is that the circuit configuration is such that a series connection of a plurality of types of resistor circuits and a parallel connection of a plurality of types of resistor circuits are connected in series. *
  • a fuse film F is connected to each resistor circuit in parallel to the plurality of types of resistor circuits connected in series, and the plurality of types of resistor circuits connected in series are all fuse films F. In short circuit condition. Therefore, when the fuse film F is blown, the resistance circuit short-circuited by the fuse film F is electrically incorporated into the resistance network 314.
  • a fuse film F is connected in series to each of a plurality of types of resistor circuits connected in parallel. Therefore, by fusing the fuse film F, the resistance circuit to which the fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance circuit.
  • a small resistance of 1 k ⁇ or less can be made on the parallel connection side, and a resistance circuit of 1 k ⁇ or more can be made on the series connection side. Therefore, a wide range of resistance circuits from a small resistance of several ⁇ to a large resistance of several M ⁇ can be created using the resistor network 314 configured with the same basic design.
  • fine adjustment of the resistance value can be performed on the fuse film of the resistance circuit on the parallel connection side. Can be carried out by fusing, and the accuracy of adjustment to a desired resistance value is increased.
  • FIG. 31 is an electric circuit diagram showing a specific configuration example of the resistor network 314 in the chip resistor having a resistance value of 10 ⁇ to 1M ⁇ . 31 also includes a series connection of a plurality of types of resistor circuits short-circuited by the fuse film F and a parallel connection of a plurality of types of resistor circuits to which the fuse film F is connected in series. It has a circuit configuration. *
  • an arbitrary resistance value of 10 to 1 k ⁇ can be set within an accuracy of 1% on the parallel connection side.
  • an arbitrary resistance value of 1 k to 1 M ⁇ can be set within an accuracy of 1% in the circuit on the serial connection side.
  • the fuse film F has been described only in the case of using the same layer as the connection conductor film C.
  • the conductive film C for connection is formed by further laminating another conductor film on the conductor film C.
  • the resistance value may be lowered.
  • the resistor film may be omitted and only the connecting conductor film C may be used. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.
  • FIG. 32 is an illustrative plan view for explaining a main structure of a chip resistor 390 according to still another embodiment of the first reference example.
  • the relationship between the resistor film line 320 and the conductor film piece 321 constituting the resistor circuit is seen in a plan view.
  • the configuration is as shown in FIG. That is, as shown in FIG. 32A, the portion of the resistor film line 320 in the region of the predetermined interval R forms a unit resistor R having a constant resistance value r.
  • the conductor film pieces 321 are laminated on both sides of the unit resistor R, and the resistor film line 320 is short-circuited by the conductor film pieces 321.
  • the layout of the resistor network 314 is changed, and the unit resistors constituting the resistor circuit included in the resistor network are shown in FIG.
  • the shape and size are as shown.
  • the resistor film line 320 includes a line-shaped resistor film line 320 having a width of 1.5 ⁇ m and extending linearly.
  • the resistor film line 320 portions having a predetermined interval R ′ form a unit resistor R ′ having a constant resistance value r ′.
  • stacked on the resistor film line 320 can be comprised by the same length also in what is shown to FIG. 32 (A) and what is shown to (B). . Therefore, the chip resistor 390 is formed by changing the layout pattern of each unit resistor R ′ constituting the resistor circuit included in the resistor network 314 so that the unit resistors R ′ can be connected in series. Is realized with high resistance. *
  • FIG. 33 is a flowchart showing an example of the manufacturing process of the chip resistor 310 described with reference to FIGS. Next, a manufacturing method of the chip resistor 310 will be described in detail according to the manufacturing process of the flowchart and with reference to FIGS. 19 to 25 as necessary.
  • Step S1 First, a substrate 311 (actually a wafer (see FIG. 35) before being cut into individual chip resistors 310) is placed in a predetermined processing chamber, and an insulating layer is formed on the surface thereof by, eg, thermal oxidation. A silicon dioxide (SiO2) layer as 319 is formed. *
  • SiO2 silicon dioxide
  • Step S2 Next, a resistor film 320 of TiN, TiON, or TiSiON is formed over the entire surface of the insulating layer 319, for example, by sputtering.
  • Step S3 Then, the resistance value of the resistor film 320 formed on the entire surface of the insulating layer 319 is measured. This measurement is performed, for example, by a four-probe method using a four-probe probe. By measuring and confirming the sheet resistance value of the resistor film 320 at this stage, it is possible to stabilize the resistance value of the resistance wiring that is formed into a desired shape in a later photolithography process. Further, the film thickness of the resistor film 320 may be calculated based on the measured sheet resistance value. The film thickness can be used for adjusting and improving the manufacturing process for the next chip resistor, and is useful for controlling the film thickness in the next chip resistor manufacturing process and obtaining a desired sheet resistance value. *
  • Step S4 Next, for example, an aluminum (Al) wiring film 321 is laminated over the entire surface of the resistor film 320 by sputtering, for example.
  • the total thickness of the two layers of the resistor film 320 and the wiring film 321 stacked may be about 8000 mm.
  • Step S5 Next, using a photolithography process, a resist pattern corresponding to the configuration of the resistive network 314 in plan view (layout pattern including the conductor film C and the fuse film F) is formed on the surface of the wiring film 321. (Formation of first resist pattern). *
  • Step S6 Then, the first etching process is performed. That is, using the first resist pattern formed in step S4 as a mask, the stacked two-layer film of the resistor film 320 and the wiring film 321 is etched by, for example, reactive ion etching (RIE). Then, the first resist pattern is peeled off after the etching.
  • Step S7 A second resist pattern is formed again using a photolithography process. In the second resist pattern formed in step S7, the wiring film 321 laminated on the resistor film 320 is selectively removed, and the unit resistor R (the region indicated by thin dots in FIG. 20) is formed. It is a pattern for forming. *
  • Step S8 Using the second resist pattern formed in step S7 as a mask, only the wiring film 321 is selectively etched by, for example, wet etching (second etching step). After the etching, the second resist pattern is peeled off. Thereby, the layout pattern of the resistor network 314 shown in FIG. 20 is obtained.
  • Step S9 At this stage, the resistance value of the resistance network 314 formed on the surface of the substrate 311 (the resistance value of the entire network 314) is measured. In this measurement, for example, the end of the resistor network 314 on the side where the multi-probe pin is connected to the first connection electrode 312 shown in FIG. 20, the end of the fuse film and the resistor network 314 on the side connected to the second connection electrode 313 Measured in contact with. By this measurement, the quality of the manufactured resistance network 314 in the initial state can be determined. *
  • a cover film 322a made of, for example, a nitride film is formed so as to cover the entire surface of the resistor network 314 formed on the substrate 311.
  • the cover film 322a may be formed by a plasma CVD method.
  • a silicon nitride film (SiN film) having a thickness of about 3000 mm may be formed.
  • the cover film 322 a covers the patterned wiring film 321, resistor film 320, and fuse film F. *
  • Step S11 From this state, laser trimming for selectively fusing the fuse film F and adjusting the chip resistor 310 to a desired resistance value is performed. That is, as shown in FIG. 34A, a laser beam is applied to the fuse film F selected in accordance with the measurement result of the total resistance measurement performed in step S8, and the fuse film F and the position below the fuse film F are measured. The resistor film 320 is melted. Thereby, the corresponding resistance circuit short-circuited by the fuse film F is incorporated in the resistance network 314, and the resistance value of the resistance network 314 can be adjusted to a desired resistance value.
  • the energy of the laser light is accumulated in the vicinity of the fuse film F by the action of the cover film 322a, so that the fuse film F and the underlying resistor film 320 are melted.
  • Step S12 Next, as shown in FIG. 34B, a silicon nitride film is deposited on the cover film 322a by, for example, plasma CVD to form a passivation film 322.
  • the above-described cover film 322a is integrated with the passivation film 322 in the final form, and constitutes a part of the passivation film 322.
  • the passivation film 322 formed after the fuse film F and the underlying resistor film 320 are cut is opened in the opening 322b of the cover film 322a that is destroyed at the same time as the fuse film F and the underlying resistor film 320 are melted.
  • the cut surface of the fuse film F and the underlying resistor film 320 is protected. Therefore, the passivation film 322 prevents foreign matter from entering the cut portion of the fuse film F and moisture from entering.
  • the entire passivation film 322 may be formed to have a film thickness of, for example, about 8000 mm. *
  • Step S13 Next, as shown in FIG. 34C, a resin film 323 is applied to the entire surface.
  • a resin film 323 for example, a photosensitive polyimide coating film 323 is used.
  • Step S14 The resin film 323 is subjected to an exposure process for a region corresponding to the opening of the first connection electrode 312 and the second connection electrode 313, and a subsequent development process, thereby patterning the resin film by photolithography. It can be performed. Thereby, pad openings for the first connection electrode 312 and the second connection electrode 313 are formed in the resin film 323.
  • Step S15 Thereafter, heat treatment (polyimide cure) for curing the resin film 323 is performed, and the polyimide film 323 is stabilized by the heat treatment.
  • Step S16 Next, the passivation film 322 is etched using the polyimide film 323 having a through hole at a position where the first connection electrode 312 and the second connection electrode 313 are to be formed as a mask. As a result, a pad opening that exposes the wiring film 321 in the region of the first connection electrode 312 and the region of the second connection electrode 313 is formed. Etching of the passivation film 322 may be performed by reactive ion etching (RIE). *
  • RIE reactive ion etching
  • Step S17 The resistance value measurement (after-measurement) for confirming that the multi-probe pin is brought into contact with the wiring film 321 exposed from the two pad openings and the resistance value of the chip resistor becomes a desired resistance value. Done.
  • Step S18 The first connection electrode 312 and the second connection electrode 313 as the external connection electrodes are grown in the two pad openings by, for example, electroless plating. *
  • Step S19 Thereafter, a third resist pattern is formed by photolithography in order to separate a large number (for example, 500,000) of chip resistors arranged on the wafer surface into individual chip resistors 310. .
  • the resist film is provided on the surface of the wafer to protect, for example, each chip resistor 310 in FIG. 36, and is formed so that the space between the chip resistors 310 is etched.
  • Step S20 Then, plasma dicing is executed. Plasma dicing is etching using the third resist pattern as a mask, and a groove having a predetermined depth from the surface of the substrate 311 is formed between the chip resistors 310. Thereafter, the resist film is peeled off. Step S21: Then, as shown in FIG. 35A, for example, the protective tape 400 is attached to the surface. *
  • Step S22 Next, the back surface of the wafer is ground, and the chip resistors are separated into individual chip resistors 310 (FIGS. 35A and 35B).
  • Step S23 As shown in FIG. 35C, a large number of chip resistors 310, each of which is separated into individual chip resistors, with a carrier tape (thermal foam sheet) 500 attached to the back side, It is held in a state of being arranged on the tape 500. On the other hand, the protective tape attached to the surface is removed (FIG. 35D). *
  • Step S24 The thermally foamed sheet 500 is heated to expand the thermally foamed particles 501 contained therein, whereby each chip resistor 310 adhered to the surface of the carrier tape 500 is peeled off from the carrier tape 500. They are separated individually (FIGS. 35E and 35F).
  • FIG. 37 is a perspective view showing an appearance of a smartphone which is an example of an electronic device using the chip resistor manufactured by the manufacturing method of the first reference example.
  • the smartphone 501 is configured by housing electronic components inside a flat rectangular parallelepiped casing 502.
  • the casing 502 has a pair of rectangular main surfaces on the front side and the back side, and the pair of main surfaces are joined by four side surfaces.
  • a display surface of a display panel 503 configured by a liquid crystal panel, an organic EL panel, or the like is exposed.
  • the display surface of the display panel 503 constitutes a touch panel and provides an input interface for the user.
  • the display panel 503 is formed in a rectangular shape that occupies most of one main surface of the housing 502.
  • Operation buttons 504 are arranged along one short side of the display panel 503.
  • a plurality (three) of operation buttons 504 are arranged along the short side of the display panel 503. The user can operate the smartphone 501 by operating the operation buttons 504 and the touch panel, and call and execute necessary functions.
  • a speaker 505 is disposed near another short side of the display panel 503.
  • the speaker 505 provides an earpiece for a telephone function and is also used as an acoustic unit for reproducing music data and the like.
  • a microphone 506 is disposed on one side surface of the housing 502 near the operation button 504. The microphone 506 can be used as a recording microphone as well as providing a mouthpiece for a telephone function. *
  • FIG. 38 is a schematic plan view showing the configuration of the electronic circuit assembly 510 housed inside the housing 502.
  • the electronic circuit assembly 510 includes a wiring board 511 and circuit components mounted on the mounting surface of the wiring board 511.
  • the plurality of circuit components include a plurality of integrated circuit elements (ICs) 512-520 and a plurality of chip components.
  • the plurality of ICs include a transmission processing IC 512, a one-segment TV reception IC 513, a GPS reception IC 514, an FM tuner IC 515, a power supply IC 516, a flash memory 517, a microcomputer 518, a power supply IC 519, and a baseband IC 520.
  • the plurality of chip components include chip inductors 521, 525, 535, chip resistors 522, 524, 533, chip capacitors 527, 530, 534, and chip diodes 528, 531.
  • the chip resistors 522, 524, and 533 are manufactured by the manufacturing method of the first reference example. *
  • the transmission processing IC 512 includes an electronic circuit that generates a display control signal for the display panel 503 and receives an input signal from a touch panel on the surface of the display panel 503.
  • a flexible wiring 509 is connected to the transmission processing IC 512 for connection with the display panel 503.
  • the 1Seg TV reception IC 513 incorporates an electronic circuit that constitutes a receiver for receiving radio waves of 1Seg broadcast (terrestrial digital television broadcast targeted for portable devices). In the vicinity of the one-segment TV reception IC 513, a plurality of chip inductors 521 and a plurality of chip resistors 522 are arranged.
  • the one-segment TV reception IC 513, the chip inductor 521, and the chip resistor 522 constitute a one-segment broadcast reception circuit 523.
  • the chip inductor 521 and the chip resistor 522 respectively have an inductance and a resistance that are accurately matched, and give a highly accurate circuit constant to the one-segment broadcasting reception circuit 523.
  • the GPS reception IC 514 includes an electronic circuit that receives radio waves from GPS satellites and outputs position information of the smartphone 501.
  • the FM tuner IC 515 constitutes an FM broadcast receiving circuit 526 together with a plurality of chip resistors 524 and a plurality of chip inductors 525 mounted on the wiring board 511 in the vicinity thereof.
  • the chip resistor 524 and the chip inductor 525 each have a resistance value and an inductance that are accurately adjusted, and give the FM broadcast receiving circuit 526 a highly accurate circuit constant.
  • the power supply IC 516 constitutes a power supply circuit 529 together with the chip capacitor 527 and the chip diode 528.
  • the flash memory 517 is a storage device for recording an operating system program, data generated inside the smartphone 501, data and programs acquired from the outside by a communication function, and the like.
  • the microcomputer 518 includes a CPU, a ROM, and a RAM, and is an arithmetic processing circuit that realizes a plurality of functions of the smartphone 501 by executing various arithmetic processes. More specifically, image processing and arithmetic processing for various application programs are realized by the operation of the microcomputer 518.
  • a plurality of chip capacitors 530 and a plurality of chip diodes 531 are mounted on the mounting surface of the wiring board 511.
  • the power supply IC 519 constitutes a power supply circuit 532 together with the chip capacitor 530 and the chip diode 531.
  • Baseband IC 520 constitutes baseband communication circuit 536 together with chip resistor 533, chip capacitor 534, and chip inductor 535.
  • the baseband communication circuit 536 provides a communication function for telephone communication and data communication.
  • the transmission processing IC 512 the GPS reception IC 514, the one-segment broadcast reception circuit 523, the FM broadcast reception circuit 526, the baseband communication circuit 536, the flash memory 517, and the like.
  • the microcomputer 518 performs arithmetic processing in response to an input signal input via the transmission processing IC 512, outputs a display control signal from the transmission processing IC 512 to the display panel 503, and causes the display panel 503 to perform various displays. . *
  • the microcomputer 518 executes arithmetic processing for outputting the received image to the display panel 503 and causing the received sound to be audible from the speaker 505. Further, when the position information of the smartphone 501 is required, the microcomputer 518 acquires the position information output from the GPS reception IC 514 and executes a calculation process using the position information.
  • the microcomputer 518 activates the FM broadcast reception circuit 526 and executes arithmetic processing for outputting the received sound from the speaker 505.
  • the flash memory 517 is used to store data acquired by communication, to store data created by calculation of the microcomputer 518 and input from the touch panel.
  • the microcomputer 518 writes data to the flash memory 517 and reads data from the flash memory 517 as necessary.
  • the function of telephone communication or data communication is realized by the baseband communication circuit 536.
  • the microcomputer 518 controls the baseband communication circuit 536 to perform processing for transmitting and receiving voice or data.
  • the first reference example is not limited to the manufacturing method of the embodiment described above, and various design changes are made within the scope of the matters described in the features of the invention according to (1) the first reference example. It is possible. For example, manufacturing processes that are not specified in the features A1 to A11 are changed, omitted, or added, are also included in the scope of the first reference example.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

Le problème à résoudre dans le cadre de la présente invention consiste à proposer un procédé de fabrication d'une résistance de puce qui présente une meilleure précision géométrique et une meilleure précision de micro-usinage. La solution proposée consiste en un procédé de fabrication d'une résistance de puce qui comprend : une étape qui consiste à former un film formant résistance sur un substrat; une étape qui consiste à former un film de câblage de sorte à être en contact avec la surface du film formant résistance; une étape consistant à former un premier motif de réserve sur le film de câblage par photolithographie; une première étape de gravure destinée à graver le film de câblage et le film formant résistance avec le premier motif de réserve comme masque; une étape destinée à former, après la première étape de gravure, un second motif de réserve sur le film de câblage par photolithographie; et une seconde étape de gravure destinée à former de multiples résistances sur le substrat en gravant partiellement le film de câblage sur le film formant résistance avec le second motif de réserve comme masque.
PCT/JP2012/083569 2012-01-27 2012-12-26 Procédé de fabrication d'une résistance de puce WO2013111496A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2012015572 2012-01-27
JP2012-015572 2012-01-27
JP2012042302 2012-02-28
JP2012-042302 2012-02-28
JP2012-268564 2012-12-07
JP2012268564A JP6184088B2 (ja) 2012-01-27 2012-12-07 チップ抵抗器の製造方法

Publications (1)

Publication Number Publication Date
WO2013111496A1 true WO2013111496A1 (fr) 2013-08-01

Family

ID=48873235

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/083569 WO2013111496A1 (fr) 2012-01-27 2012-12-26 Procédé de fabrication d'une résistance de puce

Country Status (2)

Country Link
JP (1) JP6184088B2 (fr)
WO (1) WO2013111496A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3059251B1 (fr) 2013-10-15 2019-04-03 Kaneka Corporation Procédé de fabrication de billes poreuses en cellulose

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6394604A (ja) * 1986-10-09 1988-04-25 松下電器産業株式会社 抵抗ネツトワ−クの抵抗体素子形成方法
JPS641972A (en) * 1987-06-23 1989-01-06 Kokusai Electric Co Ltd Specific resistance measuring apparatus having light cutting mechanism
JPH0961210A (ja) * 1995-08-22 1997-03-07 Murata Mfg Co Ltd 感温抵抗体の製造方法
JPH10326704A (ja) * 1997-05-16 1998-12-08 Guoju Co Ltd 薄膜抵抗器の製造方法
JP2001044001A (ja) * 1999-07-30 2001-02-16 Rohm Co Ltd 薄膜型抵抗器の構造及び抵抗値調整方法
JP2002025948A (ja) * 2000-07-10 2002-01-25 Canon Inc ウエハーの分割方法、半導体デバイス、および半導体デバイスの製造方法
JP2003218151A (ja) * 2002-01-24 2003-07-31 Seiko Epson Corp 無電解メッキバンプの形成方法、半導体装置及びその製造方法
JP2006502592A (ja) * 2002-12-23 2006-01-19 ローベルト　ボツシユ　ゲゼルシヤフト　ミツト　ベシユレンクテル　ハフツング 抵抗路の電気抵抗の調整方法
JP2010165780A (ja) * 2009-01-14 2010-07-29 Fujikura Ltd 薄膜抵抗素子の製造方法
JP2011059314A (ja) * 2009-09-09 2011-03-24 Hitachi Displays Ltd 液晶表示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039822B1 (fr) * 1969-05-29 1975-12-19
JPS4836626B1 (fr) * 1969-12-19 1973-11-06
JP3124613B2 (ja) * 1992-03-11 2001-01-15 ローム株式会社 薄膜抵抗器
JP3928763B2 (ja) * 1999-07-30 2007-06-13 ローム株式会社 薄膜型チップ抵抗器の製造方法
JP2003200523A (ja) * 2001-12-28 2003-07-15 Furukawa Circuit Foil Kk 抵抗層内蔵型銅張り積層板、それを用いたプリント回路基板
JP2003200524A (ja) * 2001-12-28 2003-07-15 Furukawa Circuit Foil Kk 抵抗層内蔵型銅張り積層板、それを用いたプリント回路基板
JP3848245B2 (ja) * 2002-11-29 2006-11-22 ローム株式会社 チップ抵抗器
JP2007036012A (ja) * 2005-07-28 2007-02-08 Rohm Co Ltd 大電力用チップ抵抗器

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6394604A (ja) * 1986-10-09 1988-04-25 松下電器産業株式会社 抵抗ネツトワ−クの抵抗体素子形成方法
JPS641972A (en) * 1987-06-23 1989-01-06 Kokusai Electric Co Ltd Specific resistance measuring apparatus having light cutting mechanism
JPH0961210A (ja) * 1995-08-22 1997-03-07 Murata Mfg Co Ltd 感温抵抗体の製造方法
JPH10326704A (ja) * 1997-05-16 1998-12-08 Guoju Co Ltd 薄膜抵抗器の製造方法
JP2001044001A (ja) * 1999-07-30 2001-02-16 Rohm Co Ltd 薄膜型抵抗器の構造及び抵抗値調整方法
JP2002025948A (ja) * 2000-07-10 2002-01-25 Canon Inc ウエハーの分割方法、半導体デバイス、および半導体デバイスの製造方法
JP2003218151A (ja) * 2002-01-24 2003-07-31 Seiko Epson Corp 無電解メッキバンプの形成方法、半導体装置及びその製造方法
JP2006502592A (ja) * 2002-12-23 2006-01-19 ローベルト　ボツシユ　ゲゼルシヤフト　ミツト　ベシユレンクテル　ハフツング 抵抗路の電気抵抗の調整方法
JP2010165780A (ja) * 2009-01-14 2010-07-29 Fujikura Ltd 薄膜抵抗素子の製造方法
JP2011059314A (ja) * 2009-09-09 2011-03-24 Hitachi Displays Ltd 液晶表示装置

Also Published As

Publication number Publication date
JP6184088B2 (ja) 2017-08-23
JP2013211520A (ja) 2013-10-10

Similar Documents

Publication Publication Date Title
US9972427B2 (en) Chip component and method of producing the same
US10593480B2 (en) Chip capacitor, circuit assembly, and electronic device
KR102071746B1 (ko) 칩 부품 및 그 제조 방법
JP2010165780A (ja) 薄膜抵抗素子の製造方法
JP2007036571A (ja) 半導体装置及びその製造方法
JP6584574B2 (ja) チップ部品およびその製造方法
JP6852120B2 (ja) チップ抵抗器
JP6184088B2 (ja) チップ抵抗器の製造方法
JP3435636B2 (ja) 可変インダクタンス素子
JP2000223318A (ja) 可変インダクタンス素子
JP2017130671A (ja) チップ部品
JP7063845B2 (ja) チップ抵抗器
JP6101465B2 (ja) チップ部品
TWI598790B (zh) 觸控模組及其製造方法
JP6535073B2 (ja) チップ部品
JP3641348B2 (ja) 半導体装置の製法
JP2003264230A (ja) 半導体装置及びその製造方法
JP2014072239A (ja) チップ部品
JP2003059725A (ja) Ｌｒ複合部品
US20080119037A1 (en) Method for manufacturing semiconductor device
JPH07263268A (ja) 電子部品の製造方法
JP2000133505A (ja) 抵抗体付き配線基板の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12866505

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12866505

Country of ref document: EP

Kind code of ref document: A1