WO2013111312A1 - Dispositif photovoltaïque, procédé de fabrication de celui-ci et module photovoltaïque - Google Patents

Dispositif photovoltaïque, procédé de fabrication de celui-ci et module photovoltaïque Download PDF

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WO2013111312A1
WO2013111312A1 PCT/JP2012/051726 JP2012051726W WO2013111312A1 WO 2013111312 A1 WO2013111312 A1 WO 2013111312A1 JP 2012051726 W JP2012051726 W JP 2012051726W WO 2013111312 A1 WO2013111312 A1 WO 2013111312A1
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layer
single crystal
silicon substrate
amorphous silicon
crystal silicon
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PCT/JP2012/051726
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English (en)
Japanese (ja)
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剛彦 佐藤
秀一 檜座
雅 酒井
松野　繁
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三菱電機株式会社
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Priority to JP2013555071A priority Critical patent/JP5745653B2/ja
Priority to PCT/JP2012/051726 priority patent/WO2013111312A1/fr
Publication of WO2013111312A1 publication Critical patent/WO2013111312A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a photovoltaic device such as a solar cell, a manufacturing method thereof, and a photovoltaic module, and more particularly to a photovoltaic device having a heterojunction, a manufacturing method thereof, and a photovoltaic module.
  • a p-type crystalline silicon substrate having a thickness of about 200 ⁇ m is used to increase the surface texture, n-type impurity diffusion layer, antireflection film, and surface electrode.
  • comb-shaped silver (Ag) electrodes are sequentially formed on the light-receiving surface side of the p-type crystalline silicon substrate.
  • a back electrode for example, an aluminum (Al) electrode
  • Al aluminum
  • the solvent components of the front electrode and the back electrode are volatilized, and the comb Ag electrode penetrates the antireflection film and is connected to the n-type impurity diffusion layer on the light receiving surface side of the p-type crystal silicon substrate. Further, in this firing, a part of the Al electrode diffuses into the p-type crystalline silicon substrate on the non-light-receiving surface side of the p-type crystalline silicon substrate to form a back surface field layer (BSF: Back Surface Field).
  • BSF Back Surface Field
  • This BSF layer forms an internal electric field at the junction surface with the p-type crystalline silicon substrate, pushes minority carriers generated near the BSF layer back into the p-type crystalline silicon substrate, and recombines carriers near the Al electrode. It has a suppressing effect.
  • the BSF layer formed by this diffusion has a thickness of several hundred nm to several ⁇ m when it is formed using a thermal process having an appropriate dopant concentration, and the open circuit voltage due to recombination within the BSF layer. This causes a decrease in short circuit current due to a decrease or light absorption.
  • Patent Documents 1 to 3 describe heterojunction solar cells in which a junction made of a thin impurity-doped silicon layer or a BSF layer is formed on a crystalline silicon substrate via a thin intrinsic semiconductor thin film (i layer). .
  • a thin intrinsic semiconductor thin film i layer.
  • the intrinsic semiconductor layer inserted between the crystalline silicon substrate and the impurity-doped silicon layer suppresses impurity diffusion between heterojunctions and can form a junction with a steep impurity profile, thus forming a good junction interface. A higher open circuit voltage can be obtained.
  • the intrinsic semiconductor thin film and the impurity-doped silicon layer can be formed at a low temperature of about 200 ° C., even when the thickness of the crystalline silicon substrate is thin, stress generated in the crystalline silicon substrate due to heat and warpage of the crystalline silicon substrate can be reduced. Can do. In addition, it can be expected that a decrease in substrate quality can be suppressed even for a crystalline silicon substrate that is easily deteriorated by heat.
  • amorphous silicon (a-Si) is usually used for the intrinsic semiconductor layer, but epitaxial growth may occur on the silicon substrate depending on the film formation conditions.
  • a-Si amorphous silicon
  • the a-Si layer is epitaxially grown on the substrate, defects and strains are likely to occur, so that the passivation effect between the substrate and the a-Si is reduced, resulting in a reduction in interface characteristics and a reduction in open circuit voltage.
  • intrinsic oxygen-containing amorphous silicon has a wider gap than ordinary intrinsic amorphous silicon. Therefore, an intrinsic oxygen-containing amorphous silicon (a-SiO (i)) layer is interposed between the silicon substrate and the impurity doped layer by interposing oxygen between the intrinsic semiconductor layer or the silicon substrate and the intrinsic semiconductor layer. If inserted, resistance is generated when carriers pass through the film due to the potential barrier of the intrinsic oxygen-containing amorphous silicon layer, leading to an increase in series resistance and a decrease in fill factor, resulting in a decrease in photoelectric conversion efficiency. It was.
  • a-SiO (i) intrinsic oxygen-containing amorphous silicon
  • the present invention has been made in view of the above, and an object thereof is to obtain a photovoltaic device excellent in photoelectric conversion efficiency, a manufacturing method thereof, and a photovoltaic module.
  • a photovoltaic device is obtained by doping an intrinsic oxygen-containing amorphous silicon layer and an impurity directly on a single crystal silicon substrate of one conductivity type.
  • crystal grains whose area in the plane direction of the single crystal silicon substrate increases from the surface of the single crystal silicon substrate to the transparent conductive layer as a starting point are scattered.
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the heterojunction solar cell according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the main part showing the configuration of the solar battery cell according to the first embodiment of the present invention.
  • FIG. 3 is a flowchart showing the method for manufacturing the solar battery cell according to the first embodiment of the present invention.
  • FIG. 4 is a vertical cross-sectional TEM image of the sample solar battery cell of the example.
  • FIG. 5: is sectional drawing which shows typically the structure of the board
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the heterojunction solar cell according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the main part showing the configuration of the solar battery cell according to the first embodiment of the present invention.
  • FIG. 3 is a flowchar
  • FIG. 6 is a flowchart showing a method for manufacturing a solar battery cell according to the second embodiment of the present invention.
  • FIG. 7 is sectional drawing which shows typically the structure of the board
  • FIG. 8 is a flowchart showing a method for manufacturing a solar battery cell according to the third embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a heterojunction solar battery cell (hereinafter sometimes referred to as a solar battery cell) that is the photovoltaic device according to the first embodiment.
  • the solar battery cell 10 includes an n-type single crystal silicon substrate 11 and a light-receiving surface side intrinsic amorphous oxygen-containing silicon layer 12 (hereinafter referred to as “light-receiving surface side”) that is sequentially stacked immediately above the light-receiving surface side of the n-type single crystal silicon substrate 11.
  • the solar battery cell 10 includes a back-side intrinsic amorphous silicon layer 16 and a conductive amorphous silicon layer that are sequentially stacked on the surface opposite to the light-receiving surface side (back surface) of the n-type single crystal silicon substrate 11.
  • a back-side transparent conductive layer 18 and a back-side electrode 19 As an n-type amorphous silicon layer 17 doped with a high concentration of impurities, a back-side transparent conductive layer 18 and a back-side electrode 19.
  • FIG. 2 is a cross-sectional view showing the main part of the configuration of the solar battery cell 10.
  • a thin a-SiO (i) layer 12 a thin p-type amorphous silicon layer 13, and a thin light-receiving surface side transparent conductive layer 14 are formed on an n-type single crystal silicon substrate 11. They are stacked in order. Thus, a heterojunction is formed between the n-type single crystal silicon substrate 11 and the thin p-type amorphous silicon layer 13 via the thin a-SiO (i) layer 12.
  • the impurity concentration distribution of the p-type amorphous silicon layer 13 can be freely set, and since the p-type amorphous silicon layer 13 is thin, Carrier recombination and light absorption can be suppressed, and a large short-circuit current can be obtained.
  • the a-SiO (i) layer 12 inserted between the n-type single crystal silicon substrate 11 and the p-type amorphous silicon layer 13 suppresses impurity diffusion between heterojunctions, and has a steep impurity profile. Therefore, a high open circuit voltage can be obtained by forming a good bonding interface.
  • the thin a-SiO (i) layer 12 and the thin p-type amorphous silicon layer 13 can be formed at a low temperature of about 200 ° C., even when the n-type single crystal silicon substrate 11 is thin, As a result, stress generated in the n-type single crystal silicon substrate 11 and warpage of the n-type single crystal silicon substrate 11 can be reduced. In addition, it is possible to suppress a decrease in substrate quality even for the n-type single crystal silicon substrate 11 that is easily deteriorated by heat.
  • fine irregularities 11a are formed on the surface of the n-type single crystal silicon substrate 11 on the light receiving surface side. Then, in the vertical cross section perpendicular to the in-plane direction of the n-type single crystal silicon substrate 11, the fine unevenness 11 a starts as a starting point and reaches the light-receiving surface-side transparent conductive layer 14 in the film thickness direction, from the n-type single crystal silicon substrate 11 to the light-receiving surface. Inverted triangular epitaxial growth layers 21 that electrically connect up to the side transparent conductive layer 14 with low resistance are formed scattered in the in-plane direction of the n-type single crystal silicon substrate 11.
  • the a-SiO (i) layer 12 Since the a-SiO (i) layer 12 has a wider gap than the normal p-type amorphous silicon layer 13, the a-SiO (i) layer 12 has an a ⁇ between the n-type single crystal silicon substrate 11 and the p-type amorphous silicon layer 13. Inserting the SiO (i) layer 12 causes resistance when carriers pass through the film due to the potential barrier of the a-SiO (i) layer 12, leading to an increase in series resistance and a decrease in fill factor, resulting in a decrease in photoelectric conversion efficiency. To do.
  • light receiving surface side transparent conductive layer 14 is reached in the film thickness direction starting from fine irregularities 11a, and from n-type single crystal silicon substrate 11 to light receiving surface side transparent conductive layer 14.
  • Epitaxially grown layers 21 that are electrically connected to each other are formed scattered in the in-plane direction of the n-type single crystal silicon substrate 11.
  • the area of the epitaxial growth layer 21 in the in-plane direction of the n-type single crystal silicon substrate 11 has a shape that increases from the n-type single crystal silicon substrate 11 side toward the light-receiving surface side transparent conductive layer 14 side.
  • the epitaxial growth layer 21 in which a part of the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 is epitaxially grown and crystallized (crystal grains) has a lower resistance than the case where the silicon layer is amorphous. It becomes. And since this crystal particle contacts the light-receiving surface side transparent conductive layer 14 in a wide area, the electrical connection of the p-type amorphous silicon layer 13 and the light-receiving surface side transparent conductive layer 14 becomes favorable.
  • the epitaxial growth layer 21 obtained by crystallizing the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 can increase the electric conductivity and reduce the potential barrier. It is possible to suppress an increase in series resistance up to the light receiving surface side transparent conductive layer 14 and a decrease in fill factor.
  • the silicon film crystallized by epitaxial growth reduces the passivation effect on the n-type single crystal silicon substrate 11.
  • the epitaxial growth layers 21 epitaxially grown on the a-SiO (i) layer 12 on the n-type single crystal silicon substrate 11 are scattered and arranged in the in-plane direction of the n-type single crystal silicon substrate 11. Then, it is connected to the n-type single crystal silicon substrate 11 in a narrow region. Therefore, the electrical connection and fill factor between the p-type amorphous silicon layer 13 and the light-receiving surface side transparent conductive layer 14 can be improved without reducing the passivation effect on the n-type single crystal silicon substrate 11.
  • the p-type amorphous silicon layer 13 of the epitaxial growth layer 21 is epitaxially grown with respect to the area where the portion of the epitaxial growth layer 21 where the a-SiO (i) layer 12 is epitaxially grown contacts the n-type single crystal silicon substrate 11. Since the area where the portion thus made contacts the light-receiving surface side transparent conductive layer 14 is 10 times or more larger, the fill factor can be reliably improved without deteriorating the passivation effect on the n-type single crystal silicon substrate 11.
  • FIG. 3 is a flowchart illustrating a method for manufacturing the solar battery cell 10 according to the first embodiment.
  • an n-type single crystal silicon substrate 11 having a resistivity of 1 ⁇ cm and a plane orientation of (100) as a substrate is prepared, and wire saw damage during slicing is removed in an alkaline solution (step S10).
  • etching is performed in a depth region of about 50 nm to 2 ⁇ m from the surface again in an alkaline solution, so that the height and width are about 3 nm to 5 nm. Fine irregularities 11a are formed (step S20, step S30).
  • Isopropyl alcohol adhering to the surface of the n-type single crystal silicon substrate 11 by the immersion process in isopropyl alcohol partially acts as an etching mask during etching in an alkaline solution, and can form the fine irregularities 11a. . That is, an organic solvent is applied to the surface of the n-type single crystal silicon substrate 11, and then the n-type single crystal silicon substrate 11 is etched with an alkaline solution. Fine irregularities 11 a can be formed on the surface of the type single crystal silicon substrate 11.
  • isopropyl alcohol may be applied to the surface of the n-type single crystal silicon substrate 11 by a spray method, a spin coat method, or the like.
  • a silazane-based organic solvent, a surfactant, or the like may be used as a material used as an etching mask. In this case, the same unevenness as described above can be formed.
  • the fine irregularities 11a are formed after the wire saw damage removing process in order to reduce the influence of the metal contamination in the wire saw damage.
  • the wire saw damage is not removed.
  • the n-type single crystal silicon substrate 11 may be immersed in isopropyl alcohol and then etched with an alkaline solution to serve as both removal of wire saw damage and formation of fine irregularities 11a.
  • an a- film having a film thickness of about 2 nm to 3 nm is formed in an RF plasma CVD chamber of 13.56 to 60 MHz.
  • the SiO (i) layer 12 is formed on the light receiving surface side of the n-type single crystal silicon substrate 11 (step S40).
  • the reaction gas flow rate is silane 10 to 100 sccm, hydrogen 500 to 1000 sccm, carbon dioxide gas 5 Film formation was performed at ⁇ 20 sccm, and an a-SiO (i) layer 12 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer starting from the fine irregularities 11 a on the surface of the n-type single crystal silicon substrate 11 is formed in the a-SiO (i) layer 12. Formed in the direction.
  • This epitaxial growth layer on which a-SiO (i) is epitaxially grown is formed to be exposed from the surface of the a-SiO (i) layer 12.
  • a p-type amorphous silicon layer 13 having a thickness of about 20 nm is formed on the a-SiO (i) layer 12 in an RF plasma CVD chamber of 13.56-60 MHz (step S50).
  • the reaction gas flow rate is 5 to 50 sccm for silane, 500 to 2000 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with diborane diluted with hydrogen at 10 to 50 sccm, and a p-type amorphous silicon layer 13 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer is formed in the p-type amorphous silicon layer 13 from the surface of the epitaxial growth layer formed in the a-SiO (i) layer 12 inside the p-type amorphous silicon layer 13. It is formed in the film thickness direction.
  • the fine unevenness 11a on the surface of the n-type single crystal silicon substrate 11 reaches the light-receiving surface side transparent conductive layer 14 as a starting point, and the n-type single crystal silicon substrate 11 to the light-receiving surface side transparent conductive layer 14 are electrically connected.
  • An inverted triangular epitaxial growth layer 21 connected with a low resistance is formed.
  • a back side intrinsic amorphous silicon layer 16 having a film thickness of about 2 nm to 3 nm is formed on the back side of the n-type single crystal silicon substrate 11 in an RF plasma CVD chamber of 13.56 to 60 MHz (step S60).
  • film formation is performed with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., a gas pressure of 400 to 600 Pa, a reactive gas flow rate of 10 to 100 sccm, and hydrogen of 500 to 1000 sccm.
  • the back side intrinsic amorphous silicon layer 16 was formed by RF plasma CVD.
  • an n-type amorphous silicon layer 17 which is a back surface high-concentration impurity doped silicon layer having a film thickness of about 20 nm is formed on the back side intrinsic amorphous silicon layer 16 in a 13.56 to 60 MHz RF plasma CVD chamber.
  • a BSF structure is formed on the back side of the n-type single crystal silicon substrate 11 (step S70).
  • the reaction gas flow rate is 5 to 50 sccm for silane, 50 to 200 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with phosphine diluted with hydrogen at 10 to 50 sccm to form an n-type amorphous silicon layer 17.
  • annealing (forming gas annealing) is performed at 200 ° C. for 10 minutes in an inert gas atmosphere containing 5% hydrogen (step S80). Suppression of recombination due to hydrogen at the substrate interface of the n-type single crystal silicon substrate 11 by annealing at a temperature equal to or higher than the temperature at which the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 are formed. The effect can be improved.
  • a light-receiving surface side transparent conductive layer 14 made of indium tin oxide (ITO) having a thickness of about 70 nm to 90 nm is formed on the p-type amorphous silicon layer 13 by sputtering.
  • the back side transparent conductive layer 18 made of indium tin oxide (ITO) with a film thickness of about 70 nm to 90 nm is formed on the n-type amorphous silicon layer 17 by sputtering (step S90).
  • a silver (Ag) electrode is formed on the light receiving surface side transparent conductive layer 14 by screen printing and heated to form the light receiving surface side collector electrode 15. Further, silver (Ag) with a film thickness of about 100 nm is formed on the entire surface of the back surface side transparent conductive layer 18 by a sputtering method to form the back surface electrode 19 (step S100).
  • the heterojunction solar cell 10 according to the first embodiment is manufactured.
  • Example 1 a heterojunction solar cell was produced by the above process.
  • a conventional heterojunction solar cell was fabricated by the same process as above except that immersion in isopropyl alcohol and formation of fine irregularities by etching in alkali were not performed after the wire saw damage removing step.
  • Example 1 in which the fine irregularities 11a are formed on the surface of the n-type single crystal silicon substrate 11, the n-type single crystal silicon in the vertical section perpendicular to the in-plane direction of the n-type single crystal silicon substrate 11 is obtained.
  • An inverted triangle shape that reaches the light-receiving surface side transparent conductive layer 14 starting from the fine irregularities 11a on the surface of the substrate 11 and electrically connects the n-type single crystal silicon substrate 11 to the light-receiving surface side transparent conductive layer 14 with low resistance.
  • the epitaxial growth layer 21 was confirmed.
  • FIG. 4 is a vertical cross-sectional TEM image of the sample of Example 1. Fine irregularities having a height difference of about 3 nm to 5 nm are formed on the surface of the n-type single crystal silicon substrate 11, and the p-type amorphous silicon is formed from the a-SiO (i) layer 12 on a relatively large region of the height difference. An inverted triangular epitaxial growth layer 21 is formed over the layer 13. Such a shape is achieved by selecting the alkali etching conditions in the formation process of the fine irregularities 11a of the n-type single crystal silicon substrate 11 and the formation conditions of the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13. Has been.
  • the inverted triangular epitaxial growth layer 21 has a p-type amorphous silicon layer 13 whose growth rate in the (111) direction is high in the n-type single crystal silicon substrate 11 whose principal surface has a (100) plane orientation.
  • the epitaxial growth layer 21 can receive light in an area 10 times or more larger than the area in contact with the starting point (the fine irregularities 11a) of the surface of the n-type single crystal silicon substrate 11.
  • the shape is in contact with the surface-side transparent conductive layer 14. That is, when the surface orientation of the main surface of the n-type single crystal silicon substrate 11 is the (100) plane, the fine irregularities 11a are formed on the surface of the n-type single crystal silicon substrate 11 using the anisotropy. Becomes easy.
  • the crystal grains of the a-SiO (i) layer 12 are also epitaxially grown on the main surface of the n-type single crystal silicon substrate 11, so that the n-type single crystal silicon is utilized by utilizing the film formation conditions with a high (111) plane growth rate. Crystal grains whose area increases in the film thickness direction from the surface of the substrate 11 through the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 to the light-receiving surface side transparent conductive layer 14 can be formed. .
  • An advantage of this shape is that the potential barrier of the a-SiO (i) layer 12 itself is reduced.
  • the conductivity can be further improved by epitaxially growing a part of the p-type amorphous silicon layer 13.
  • the epitaxial growth layer 21 receives light in such a shape that the area of the epitaxial growth layer 21 in the in-plane direction of the n-type single crystal silicon substrate 11 is widened in the film thickness direction from the n-type single crystal silicon substrate 11 side to the light-receiving surface side transparent conductive layer 14 side. By connecting to the surface side transparent conductive layer 14, it contributes also to the improvement of the contact resistance.
  • An amorphous intrinsic oxygen-containing silicon film has an effect of suppressing recombination on the substrate surface.
  • the region of the epitaxial growth layer 21 is small at the interface of the n-type single crystal silicon substrate 11. It is preferable.
  • the inverted triangular epitaxial growth layer 21 of the p-type amorphous silicon layer 13 is formed by overlapping crystals grown from different growth regions when the region of the epitaxial growth layer 21 spreads in the surrounding amorphous region. Defects are likely to occur. When a defect occurs in the epitaxial growth layer, the open circuit voltage is lowered.
  • the regions of the inverted triangular epitaxial growth layer 21 are separated from each other by n-type single crystal silicon while maintaining a distance at which the crystals grown from different growth regions do not contact each other in the plane of the n-type single crystal silicon substrate 11. It is preferable that they are arranged so as to spread in the plane of the substrate 11. Specifically, the distance between the inverted triangular substrate-side vertices is preferably larger than 1.5 times the thickness of the p-type amorphous silicon layer and smaller than 500 nm.
  • the solar cell by changing the distance between the epitaxial growth layers, if it is smaller than 1.5 times the thickness of the p-type amorphous silicon layer, an overlap with the adjacent epitaxial crystal layer occurs and defects are easily formed. When it is larger than 500 nm, the series resistance is not sufficiently reduced.
  • the thickness of the a-SiO (i) layer 12 is 2 to 3 nm, and the height difference of the fine unevenness 11a is 3 nm to 5 nm, but the height difference of the fine unevenness is the a-SiO (i) layer 12. Is required to be smaller than twice the film thickness of the a-SiO (i) layer 12. The uniformity of the growth of the a-SiO (i) layer 12 in the plane of the n-type single crystal silicon substrate 11 is disturbed by the fine irregularities 11a, which contributes to the formation of the epitaxial growth layer 21.
  • the a-SiO (i) layer 12 is less disturbed, and the epitaxial growth layer 21 is formed starting from the fine irregularities 11a. It will not be done. If the height difference of the fine irregularities 11a is larger than twice the film thickness of the a-SiO (i) layer 12, the a-SiO (i) layer 12 uniformly covers the fine irregularities 11a, so that the epitaxial growth layer 21 is not formed.
  • the current-voltage characteristics of the sample of Example 1 and the sample of Comparative Example 1 were evaluated by irradiation with light of 100 mW / cm 2 in the AM1.5 spectrum.
  • the open circuit voltage was 715 mV and the fill factor was 0.75.
  • the open circuit voltage is 715 mV
  • the fill factor is 0.79
  • the value of the open circuit voltage is the same by forming the fine irregularities 11 a on the surface of the n-type single crystal silicon substrate 11. Although it was a value, the fill factor was 0.04 high.
  • Embodiment 1 a heterojunction solar cell excellent in photoelectric conversion efficiency can be realized.
  • the conductivity type of the substrate is n-type, but it may be p-type.
  • FIG. FIG. 5 is a cross-sectional view schematically illustrating the configuration of the substrate surface on the light-receiving surface side of the solar battery cell that is the photovoltaic device according to the second embodiment.
  • the solar cell according to the second embodiment is in accordance with the first embodiment, except that the surface of the n-type single crystal silicon substrate 11 has a pyramid texture, and an epitaxial growth layer 21 is provided in the gap of the pyramid texture. It has the same configuration as the solar battery cell 10. Therefore, below, it demonstrates paying attention to the characteristic part of the photovoltaic cell concerning Embodiment 2.
  • a random pyramid texture 31 is formed on the surface of an n-type single crystal silicon substrate 11 as shown in FIG.
  • the epitaxial growth layer 21 described in the first embodiment is provided on the flat inter-texture flat portion 32 which is a gap between the respective pyramidal textures 31 (not shown).
  • fine irregularities 11a are formed on the surface of the inter-texture flat portion 32, and the epitaxial growth layer 21 starts from the fine irregularities 11a on the surface of the inter-texture flat portion 32. It is formed by epitaxial growth. That is, the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 are provided with the epitaxial growth layers 21 that are formed starting from minute irregularities on the surface of the inter-texture flat portion 32. .
  • the light receiving surface side from the n-type single crystal silicon substrate 11 provided with the epitaxial growth layer 21 similarly to the solar battery 10 according to the first embodiment, the light receiving surface side from the n-type single crystal silicon substrate 11 provided with the epitaxial growth layer 21.
  • the effect of reducing the series resistance up to the transparent conductive layer 14 and the effect of suppressing the reduction of the fill factor are obtained.
  • FIG. 6 is a flowchart showing a method for manufacturing a solar battery cell according to the second embodiment.
  • an n-type single crystal silicon substrate 11 having a resistivity of 1 ⁇ cm and a principal plane orientation of (100) is prepared as a substrate, and wire saw damage during slicing is removed in an alkaline solution (step S110).
  • the n-type single crystal silicon substrate 11 is immersed in an alkaline solution to which isopropyl alcohol has been added to form a pyramidal texture 31 on the surface of the n-type single crystal silicon substrate 11 (step S120).
  • the n-type single crystal silicon substrate 11 finishes the texture formation in a slightly shorter time than the pyramidal texture 31 is formed without gaps on the entire surface, and a flat surface of 100 nm to 1 ⁇ m is formed between the pyramidal textures 31.
  • a shape having a (100) plane gap region is formed. If it is difficult to form a texture gap by controlling the texture formation time, once multiple ordinary pyramidal textures without flats are formed, and then isotropic with a mixture of hydrofluoric acid and nitric acid Etching is performed to form a rounded groove (groove having a vertical cross-sectional shape with a rounded inner wall) in the gap of the pyramidal texture, and then the rounded groove is rounded by etching with an alkaline solution. A flat part can also be formed in the gap. In this method, the width of the gap can be easily controlled by controlling the concentration and time of the mixed solution of hydrofluoric acid and nitric acid and the concentration and time of the alkaline solution.
  • etching is performed in a depth region of about 50 nm to 2 ⁇ m from the surface again in an alkaline solution, whereby a flat texture leaving the (100) plane is left.
  • the fine irregularities 11a having a height and width of about 3 nm to 5 nm are formed in the intermediate flat portion 32 (steps S130 and S140).
  • Isopropyl alcohol adhering to the surface of the n-type single crystal silicon substrate 11 by the immersion process in isopropyl alcohol partially acts as an etching mask during etching in an alkaline solution, and can form the fine irregularities 11a. .
  • isopropyl alcohol may be applied to the surface of the n-type single crystal silicon substrate 11 by a spray method, a spin coat method, or the like.
  • a silazane-based organic solvent, a surfactant, or the like may be used as a material used as an etching mask. In this case, the unevenness 11a similar to the above can be formed.
  • the reaction gas flow rate is 10 to 100 sccm for silane, 500 to 1000 sccm for hydrogen, and 5 carbon dioxide gas in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed at ⁇ 20 sccm, and an a-SiO (i) layer 12 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer 21 is formed in the thickness direction of the a-SiO (i) layer 12 inside the a-SiO (i) layer 12, starting from the fine irregularities 11 a on the surface of the inter-texture flat portion 32. It is formed.
  • This epitaxial growth layer on which a-SiO (i) is epitaxially grown is formed to be exposed from the surface of the a-SiO (i) layer 12.
  • a p-type amorphous silicon layer 13 having a thickness of about 20 nm is formed on the a-SiO (i) layer 12 in an RF plasma CVD chamber of 13.56-60 MHz (step S160).
  • the reaction gas flow rate is set to 5 to 50 sccm for silane, 500 to 2000 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with diborane diluted with hydrogen at 10 to 50 sccm, and a p-type amorphous silicon layer 13 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer is formed in the p-type amorphous silicon layer 13 from the surface of the epitaxial growth layer formed in the a-SiO (i) layer 12 inside the p-type amorphous silicon layer 13. It is formed in the film thickness direction.
  • the fine unevenness 11a on the surface of the texture-to-texture flat portion 32 reaches the light-receiving surface side transparent conductive layer 14 as a starting point, and the electrical resistance between the n-type single crystal silicon substrate 11 and the light-receiving surface side transparent conductive layer 14 is low.
  • an inverted triangular epitaxial growth layer 21 is formed which is connected by
  • a back side intrinsic amorphous silicon layer 16 having a film thickness of about 2 nm to 3 nm is formed on the back side of the n-type single crystal silicon substrate 11 in a 13.56 to 60 MHz RF plasma CVD chamber (step S170).
  • film formation is performed with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., a gas pressure of 400 to 600 Pa, a reactive gas flow rate of 10 to 100 sccm of silane, and 500 to 1000 sccm of hydrogen.
  • the back side intrinsic amorphous silicon layer 16 was formed by RF plasma CVD.
  • an n-type amorphous silicon layer 17 which is a back surface high-concentration impurity doped silicon layer having a film thickness of about 20 nm is formed on the back side intrinsic amorphous silicon layer 16 in a 13.56 to 60 MHz RF plasma CVD chamber.
  • a BSF structure is formed on the back side of the n-type single crystal silicon substrate 11 (step S180).
  • the reaction gas flow rate is set to 5 to 50 sccm for silane, 50 to 200 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with phosphine diluted with hydrogen at 10 to 50 sccm to form an n-type amorphous silicon layer 17.
  • annealing (forming gas annealing) is performed at 200 ° C. for 10 minutes in an inert gas atmosphere containing 5% hydrogen (step S190). Suppression of recombination due to hydrogen at the substrate interface of the n-type single crystal silicon substrate 11 by annealing at a temperature equal to or higher than the temperature at which the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 are formed. The effect can be improved.
  • a light-receiving surface side transparent conductive layer 14 made of indium tin oxide (ITO) having a thickness of about 70 nm to 90 nm is formed on the entire surface of the p-type amorphous silicon layer 13 by sputtering.
  • a back side transparent conductive layer 18 made of indium tin oxide (ITO) having a film thickness of about 70 nm to 90 nm is formed on the entire surface of the n-type amorphous silicon layer 17 by sputtering (step S200).
  • a silver (Ag) electrode is formed on the light receiving surface side transparent conductive layer 14 by screen printing and heated to form the light receiving surface side collector electrode 15. Further, silver (Ag) having a film thickness of about 100 nm is formed on the entire surface of the back-side transparent conductive layer 18 by a sputtering method to form the back-side electrode 19 (step S210).
  • the heterojunction solar cell according to the second embodiment is manufactured.
  • Example 2 a heterojunction solar cell was manufactured by the above process.
  • a conventional heterojunction solar cell was fabricated by the same process as above except that immersion in isopropyl alcohol and formation of fine irregularities by etching in alkali were not performed after the pyramidal texture formation step.
  • the current-voltage characteristics of the sample of Example 2 and the sample of Comparative Example 2 were evaluated by irradiation with light of 100 mW / cm 2 in the AM1.5 spectrum.
  • the open circuit voltage was 713 mV and the fill factor was 0.76.
  • the open circuit voltage is 713 mV
  • the fill factor is 0.78
  • the fine irregularities 11 a are formed in the gap region of the random pyramid texture 31 on the surface of the n-type single crystal silicon substrate 11.
  • the value of the open circuit voltage was the same, but the fill factor was 0.02 higher.
  • the fine unevenness 11a is formed in the gap region between the pyramidal textures 31 formed on the surface of the n-type single crystal silicon substrate 11, thereby receiving light from the fine unevenness on the surface of the n-type single crystal silicon substrate 11. It can be said that the inverted triangular epitaxial growth layer 21 reaching the surface-side transparent conductive layer 14 is formed, and the series resistance from the n-type single crystal silicon substrate 11 to the light-receiving surface-side transparent conductive layer 14 is reduced.
  • a heterojunction solar cell excellent in photoelectric conversion efficiency can be realized as in the first embodiment.
  • FIG. 7 is a cross-sectional view schematically illustrating the configuration of the substrate surface on the light-receiving surface side of the solar battery cell that is the photovoltaic device according to the third embodiment.
  • the solar cell according to the third embodiment has the reverse pyramid texture on the surface of the n-type single crystal silicon substrate 11 and has the epitaxial growth layer 21 on the terrace portion of the reverse pyramid texture.
  • 1 has the same configuration as the solar battery cell 10 according to FIG. Therefore, below, it demonstrates paying attention to the characteristic part of the photovoltaic cell concerning Embodiment 3.
  • an inverted pyramid texture 41 is formed on the surface of an n-type single crystal silicon substrate 11 as shown in FIG. And it has the epitaxial growth layer 21 as described in Embodiment 1 on the flat terrace part 42 which is the space
  • minute irregularities 11 a are formed (not shown) as in the first embodiment, and the epitaxial growth layer 21 is formed by epitaxial growth starting from the minute irregularities on the surface of the terrace portion 42.
  • the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 are provided with the epitaxially grown layers 21 formed starting from the minute irregularities 11 a on the surface of the terrace portion 42.
  • the light receiving surface side from the n-type single crystal silicon substrate 11 provided with the epitaxial growth layer 21 similarly to the solar cell 10 according to the first embodiment, the light receiving surface side from the n-type single crystal silicon substrate 11 provided with the epitaxial growth layer 21.
  • the effect of reducing the series resistance up to the transparent conductive layer 14 and the effect of suppressing the reduction of the fill factor are obtained.
  • the fine irregularities 11a on the (111) surface of the terrace portion 42 having the inverted pyramid structure, the anti-reflection effect, the short-circuit current, and the open-circuit with respect to the n-type single crystal silicon substrate 11 on which the inverted pyramid texture 41 is formed.
  • the effect of improving voltage and fill factor can be achieved.
  • FIG. 8 is a flowchart showing a method for manufacturing a solar battery cell according to the third embodiment.
  • an n-type single crystal silicon substrate 11 having a resistivity of 1 ⁇ cm and a principal plane orientation of (100) is prepared as a substrate, and wire saw damage during slicing is removed in an alkaline solution (step S310).
  • a silicon nitride film for example, is formed on the surface of the n-type single crystal silicon substrate 11 as an etching resistant film for forming the inverted pyramid texture 41 (step S320).
  • a plurality of openings serving as etching holes arranged vertically and horizontally in a matrix form at a pitch of 5 ⁇ m to 20 ⁇ m are formed in the etching resistant film by laser processing to form an etching mask for forming an inverted pyramid texture ( Step S330).
  • the laser intensity at this time is such a laser intensity that the silicon nitride film in the laser irradiation part is completely lost and damage to the n-type single crystal silicon substrate 11 is minimized.
  • the n-type single crystal silicon substrate 11 is immersed in hydrofluoric acid, and isotropic etching is performed on the lower region of the opening and the n-type single crystal silicon substrate 11 in the vicinity thereof starting from the opening. In the isotropic etching, the etching is terminated so that the portions etched in a substantially hemispherical shape from adjacent openings do not overlap.
  • the n-type single crystal silicon substrate 11 is immersed in an alkaline solution to which isopropyl alcohol is added, and anisotropic etching is performed to form an inverted pyramidal texture 41 on the surface of the n-type single crystal silicon substrate 11 (step S340).
  • the substantially hemispherical side surface formed by isotropic etching has an inverted pyramid shape that leaves an (111) plane by anisotropic etching.
  • the anisotropic etching is terminated slightly before the flat (100) plane gap region (terrace portion 42) between the inverted pyramid textures 41 completely disappears, and between the inverted pyramid textures 41,
  • the shape is such that it has a flat (100) terrace portion 42 of 100 nm to 1 ⁇ m.
  • the silicon nitride film used as the etching mask is removed with hydrofluoric acid.
  • etching is performed in a depth region of about 50 nm to 2 ⁇ m from the surface again in an alkaline solution, whereby a flat terrace leaving the (100) plane is left.
  • the fine irregularities 11a having a height and width of about 3 nm to 5 nm are formed on the portion 42 (steps S350 and S360).
  • Isopropyl alcohol adhering to the surface of the n-type single crystal silicon substrate 11 by the immersion process in isopropyl alcohol partially acts as an etching mask during etching in an alkaline solution, and can form the fine irregularities 11a. .
  • isopropyl alcohol may be applied to the surface of the n-type single crystal silicon substrate 11 by a spray method, a spin coat method, or the like.
  • a silazane-based organic solvent, a surfactant, or the like may be used as a material used as an etching mask. In this case, the fine unevenness 11a similar to the above can be formed.
  • the reaction gas flow rate is 10 to 100 sccm for silane, 500 to 1000 sccm for hydrogen, and 5 carbon dioxide gas in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed at ⁇ 20 sccm, and an a-SiO (i) layer 12 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer 21 is formed in the film thickness direction of the a-SiO (i) layer 12 inside the a-SiO (i) layer 12, starting from the fine irregularities 11 a on the surface of the terrace portion 42.
  • the This epitaxial growth layer on which a-SiO (i) is epitaxially grown is formed to be exposed from the surface of the a-SiO (i) layer 12.
  • a p-type amorphous silicon layer 13 having a thickness of about 20 nm is formed on the a-SiO (i) layer 12 in an RF plasma CVD chamber of 13.56-60 MHz (step S160).
  • the reaction gas flow rate is set to 5 to 50 sccm for silane, 500 to 2000 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with diborane diluted with hydrogen at 10 to 50 sccm, and a p-type amorphous silicon layer 13 was formed by RF plasma CVD.
  • an inverted triangular epitaxial growth layer is formed in the p-type amorphous silicon layer 13 from the surface of the epitaxial growth layer formed in the a-SiO (i) layer 12 inside the p-type amorphous silicon layer 13. It is formed in the film thickness direction.
  • the light receiving surface side transparent conductive layer 14 is reached starting from the fine irregularities 11a on the surface of the terrace portion 42, and the n type single crystal silicon substrate 11 and the light receiving surface side transparent conductive layer 14 are electrically connected with low resistance.
  • An inverted triangular epitaxial growth layer 21 is formed.
  • a back side intrinsic amorphous silicon layer 16 having a film thickness of about 2 nm to 3 nm is formed on the back side of the n-type single crystal silicon substrate 11 in a 13.56 to 60 MHz RF plasma CVD chamber (step S170).
  • film formation is performed with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., a gas pressure of 400 to 600 Pa, a reactive gas flow rate of 10 to 100 sccm of silane, and 500 to 1000 sccm of hydrogen.
  • the back side intrinsic amorphous silicon layer 16 was formed by RF plasma CVD.
  • an n-type amorphous silicon layer 17 which is a back surface high-concentration impurity doped silicon layer having a film thickness of about 20 nm is formed on the back side intrinsic amorphous silicon layer 16 in a 13.56 to 60 MHz RF plasma CVD chamber.
  • a BSF structure is formed on the back side of the n-type single crystal silicon substrate 11 (step S180).
  • the reaction gas flow rate is set to 5 to 50 sccm for silane, 50 to 200 sccm for hydrogen, and 1% in an atmosphere with an RF output of 20 to 100 mW / cm 2 , a substrate temperature of 100 to 200 ° C., and a gas pressure of 400 to 600 Pa.
  • Film formation was performed with phosphine diluted with hydrogen at 10 to 50 sccm to form an n-type amorphous silicon layer 17.
  • annealing (forming gas annealing) is performed at 200 ° C. for 10 minutes in an inert gas atmosphere containing 5% hydrogen (step S410). Suppression of recombination due to hydrogen at the substrate interface of the n-type single crystal silicon substrate 11 by annealing at a temperature equal to or higher than the temperature at which the a-SiO (i) layer 12 and the p-type amorphous silicon layer 13 are formed. The effect can be improved.
  • a light-receiving surface side transparent conductive layer 14 made of indium tin oxide (ITO) having a thickness of about 70 nm to 90 nm is formed on the p-type amorphous silicon layer 13 by sputtering.
  • the back side transparent conductive layer 18 made of indium tin oxide (ITO) having a film thickness of about 70 nm to 90 nm is formed on the n-type amorphous silicon layer 17 by sputtering (step S420).
  • a silver (Ag) electrode is formed on the light receiving surface side transparent conductive layer 14 by screen printing and heated to form the light receiving surface side collector electrode 15. Further, silver (Ag) having a film thickness of about 100 nm is formed on the entire surface of the back surface side transparent conductive layer 18 by a sputtering method to form the back surface electrode 19 (step S430).
  • the heterojunction solar cell according to the third embodiment is manufactured.
  • Example 3 a heterojunction solar cell was produced by the above process.
  • a conventional heterojunction solar cell was fabricated by the same process as described above except that immersion in isopropyl alcohol and formation of fine irregularities by etching in alkali were not performed after the reverse pyramid texture formation process, and a comparative example Three samples were used.
  • the current-voltage characteristics of the sample of Example 3 and the sample of Comparative Example 3 were evaluated by irradiation with light of 100 mW / cm 2 in the AM1.5 spectrum.
  • the open circuit voltage was 715 mV and the fill factor was 0.76.
  • the open circuit voltage is 715 mV
  • the fill factor is 0.78
  • the fine unevenness 11 a is formed on the terrace portion 42 of the inverted pyramid texture 41 on the surface of the n-type single crystal silicon substrate 11.
  • fine irregularities on the surface of the n-type single crystal silicon substrate 11 are formed by forming fine irregularities 11a on the terrace portion 42 between the inverted pyramidal textures 41 formed on the surface of the n-type single crystal silicon substrate 11. This is because an inverted triangular epitaxial growth layer 21 reaching the light receiving surface side transparent conductive layer 14 is formed, and the series resistance from the n-type single crystal silicon substrate 11 to the light receiving surface side transparent conductive layer 14 is reduced. .
  • a heterojunction solar cell excellent in photoelectric conversion efficiency can be realized as in the first embodiment.
  • one light receiving surface side collecting electrode 15 and the other back surface electrode 19 of adjacent heterojunction solar cells may be electrically connected.
  • the photovoltaic device according to the present invention is useful for realizing a photoelectric conversion device having a heterojunction and having excellent photoelectric conversion efficiency.
  • Heterojunction solar cells (solar cells) 11 n-type single crystal silicon substrate 11a fine irregularities 12 light-receiving surface side intrinsic amorphous oxygen-containing silicon layer (a-SiO (i) layer) 13 p-type amorphous silicon layer 14 light-receiving surface-side transparent conductive layer 15 light-receiving surface-side collector electrode 16 back-side intrinsic amorphous silicon layer 17 n-type amorphous silicon layer 18 back-side transparent conductive layer 19 back-side electrode 21 epitaxial growth layer 31 Pyramid texture 32 Flat part between textures 41 Reverse pyramid texture 42 Terrace part

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Abstract

La présente invention concerne un dispositif photovoltaïque formé par empilement, dans l'ordre qui suit, d'une couche intrinsèque de silicium amorphe contenant de l'oxygène, d'une couche conductrice de silicium amorphe dopé aux impuretés, et d'une couche conductrice transparente, directement sur un substrat en silicium monocristallin d'un type de conductivité. Les particules de cristal, dont la superficie augmente dans le sens de la surface du substrat en silicium monocristallin commençant au niveau de la surface du substrat en silicium monocristallin et atteignant la couche conductrice transparente, sont dispersées à l'intérieur de la couche intrinsèque de silicium amorphe contenant de l'oxygène et de la couche conductrice de silicium amorphe. Ceci permet d'obtenir un dispositif photovoltaïque ayant un excellent rendement de conversion photoélectrique.
PCT/JP2012/051726 2012-01-26 2012-01-26 Dispositif photovoltaïque, procédé de fabrication de celui-ci et module photovoltaïque WO2013111312A1 (fr)

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WO2017010029A1 (fr) * 2015-07-13 2017-01-19 パナソニックＩｐマネジメント株式会社 Dispositif de conversion photoélectrique
WO2018180486A1 (fr) * 2017-03-29 2018-10-04 パナソニック株式会社 Cellule solaire et procédé de production de cellule solaire
JP2019057619A (ja) * 2017-09-21 2019-04-11 株式会社カネカ バックコンタクト型太陽電池
US11515443B2 (en) * 2018-03-19 2022-11-29 Shangrao Jinko Solar Technology Development Co., Ltd Tandem solar cell manufacturing method

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JPH11112011A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd 光起電力素子の製造方法
JP2002009312A (ja) * 2000-06-16 2002-01-11 Fuji Electric Corp Res & Dev Ltd 非単結晶薄膜太陽電池の製造方法
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JPH11112011A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd 光起電力素子の製造方法
JP2002009312A (ja) * 2000-06-16 2002-01-11 Fuji Electric Corp Res & Dev Ltd 非単結晶薄膜太陽電池の製造方法
JP2011023526A (ja) * 2009-07-15 2011-02-03 Mitsubishi Electric Corp 光起電力装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017010029A1 (fr) * 2015-07-13 2017-01-19 パナソニックＩｐマネジメント株式会社 Dispositif de conversion photoélectrique
WO2018180486A1 (fr) * 2017-03-29 2018-10-04 パナソニック株式会社 Cellule solaire et procédé de production de cellule solaire
JPWO2018180486A1 (ja) * 2017-03-29 2019-11-07 パナソニック株式会社 太陽電池セル及び太陽電池セルの製造方法
US11430904B2 (en) 2017-03-29 2022-08-30 Panasonic Holdings Corporation Solar cell and method of manufacturing solar cell
JP2019057619A (ja) * 2017-09-21 2019-04-11 株式会社カネカ バックコンタクト型太陽電池
US11515443B2 (en) * 2018-03-19 2022-11-29 Shangrao Jinko Solar Technology Development Co., Ltd Tandem solar cell manufacturing method

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