WO2013069548A1 - Signal line driver circuit and liquid crystal display device - Google Patents

Signal line driver circuit and liquid crystal display device Download PDF

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Publication number
WO2013069548A1
WO2013069548A1 PCT/JP2012/078412 JP2012078412W WO2013069548A1 WO 2013069548 A1 WO2013069548 A1 WO 2013069548A1 JP 2012078412 W JP2012078412 W JP 2012078412W WO 2013069548 A1 WO2013069548 A1 WO 2013069548A1
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WIPO (PCT)
Prior art keywords
signal
effect transistor
field
potential
pulse
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Ceased
Application number
PCT/JP2012/078412
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English (en)
French (fr)
Inventor
Hiroyuki Miyake
Seiko Inoue
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020147015176A priority Critical patent/KR101984739B1/ko
Priority to CN201280055035.4A priority patent/CN103918025B/zh
Publication of WO2013069548A1 publication Critical patent/WO2013069548A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0434—Flat panel display in which a field is applied parallel to the display plane
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time

Definitions

  • One embodiment of the present invention relates to a signal line driver circuit.
  • One embodiment of the present invention relates to a liquid crystal display device.
  • One of known liquid crystal display devices is a liquid crystal display device employing a driving method in which a plurality of pixel circuits are provided in rows and columns and in which the polarity of the potential of one of a pair of electrodes in each liquid crystal element and the polarity of the potential of the other electrode are inverted evey frame period on a row-by-row basis (e.g., Patent Document 1 ).
  • Employing the driving method can reduce driving voltage of a signal line driver circuit provided in a liquid crystal display device while preventing burn-in of a display image due to liquid crystal elements.
  • Patent Document 1 discloses a technique in which the potentials of a plurality of common signal lines are controlled with a signal line driver circuit such as a common signal line driver circuit so that the potential of the other of the pair of electrodes of each liquid crystal element is inverted every frame period.
  • the signal line driver circuit shown in Patent Document 1 is provided with a shift register and a plurality of circuits including a latch unit and a buffer unit.
  • the buffer unit outputs, as a common signal, a signal the potential of which is controlled in accordance with data stored in the latch unit.
  • Patent Document 1 Japanese Published Patent Application No. 2006-276541
  • a conventional signal line driver circuit has a problem of easily causing a malfunction.
  • an object of one embodiment of the present invention is to prevent a malfunction from occuring.
  • a signal having a function as a driving signal is generated by a circuit that includes a latch unit, a buffer unit, and a switch unit for controlling rewriting of data stored in the latch unit, whereby a change in the data stored in the latch unit is suppressed.
  • the switch unit has a function of controlling rewriting of data stored in the latch unit in accordance with a first control signal and a second control signal.
  • data is rewritten in a period during which pulses of a set signal and a reset signal are not input, whereby a change in the potential that is the data stored in the latch unit is suppressed.
  • One embodiment of the present invention is the signal line driver circuit that includes a shift register, a selection circuit, and a driving signal output circuit.
  • the selection circuit has a function of determining which a first pulse signal or a second pulse signal is output at the same potential level as a pulse signal input from the shift register, in accordance with a first clock signal and a second clock signal.
  • the driving signal output circuit has functions of generating and outputting a driving signal for controlling a potential of a signal line in accordance with the first and second pulse signals input from the selection circuit and first and second control signals.
  • the driving signal output circuit includes a latch unit configured to rewrite and store first data and second data in accordance with the first and second pulse signals, a buffer unit configured to set a potential of the driving signal in accordance with the first data and the second data and output the driving signal, and a switch unit configured to control rewriting of the first data by being turned on or off in accordance with the first control signal and the second control signal.
  • One embodiment of the present invention is the signal line driver circuit that includes a shift register, a selection circuit, and a driving signal output circuit.
  • the selection circuit has a function of determining which a first pulse signal or a second pulse signal is output at the same potential level as a pulse signal input from the shift register, in accordance with a first clock signal and a second clock signal.
  • the driving signal output circuit has functions of generating and outputting a driving signal for controlling a potential of a signal line in accordance with the first and second pulse signals input from the selection circuit and first to fifth control signals.
  • the driving signal output circuit includes a first latch unit configured to rewrite and store first data and second data in accordance with the first and second pulse signals, a second latch unit configured to rewrite and store third data and fourth data in accordance with the first and second pulse signals, a first buffer unit configured to set a potential of the first signal in accordance with the first data and the second data and output the first signal, a second buffer unit configured to set a potential of the second signal in accordance with the third data and the fourth data and output the second signal, a first switch unit configured to control rewriting of the first data by being turned on or off in accordance with the first control signal and the second control signal, a second switch unit configured to control rewriting of the third data by being turned on or off in accordance with the first control signal and the third control signal, a third switch unit to which the second signal is input as the fourth control signal and that is configured to control rewriting of the second data stored in the first latch unit by being turned on or off in accordance with the fourth control signal, a fourth switch unit to which
  • the potential of the other of a pair of electrodes in each liquid crystal element of pixel circuits is controlled by using the signal line driver circuit. Accordingly, a plurality of pixel circuits are provided in rows and columns and which the polarity of the potential of one of a pair of electrodes in each liquid crystal element and the polarity of the potential of the other electrode are inverted evey frame period on a row-by-row basis; accordingly, the voltage of a gate signal is reduced.
  • the liquid crystal element includes liquid crystal which exhibits a blue phase.
  • a liquid crystal display device that operates at higher speed can be provided.
  • a change in the potential that is the data stored in a latch unit and a change in the potential of a signal output from a signal line driver circuit can be suppressed; therefore, a malfunction can be prevented from occurring.
  • FIG. 1 illustrates an example of a signal line driver circuit.
  • FIG. 2 illustrates an example of a selection circuit.
  • FIGS. 3A and 3B illustrate an example of a driving signal output circuit.
  • FIG. 4 illustrates an example of a signal line driver circuit.
  • FIGS. 5 A and 5B illustrate an example of a driving signal output circuit.
  • FIG. 6 is a timing chart for illustrating an example of a method for driving a signal line driver circuit.
  • FIGS. 7A and 7B illustrate an example of a liquid crystal display device.
  • FIGS. 8A and 8B illustrate an example of a pulse output circuit.
  • FIGS. 9A and 9B illustrate an example of a selection circuit.
  • FIGS. 10A and 10B illustrate an example of a driving signal output circuit.
  • FIGS. 1 1 A and 1 1 B illustrate an example of a liquid crystal display device.
  • FIGS. 12A and 12B illustrate an example of a liquid crystal display device.
  • FIG. 13 illustrates an example of a signal line driver circuit.
  • FIGS. 14A and 14B illustrate an example of a pulse output circuit.
  • FIGS. 15A and 15B illustrate an example of a driving signal output circuit.
  • FIG. 16 is a timing chart for illustrating an example of a method for driving a signal line driver circuit.
  • FIG. 17 is a timing chart for illustrating an example of a method for driving a signal line driver circuit.
  • FIG. 18 is a timing chart for illustrating an example of operation of a pixel circuit.
  • FIG. 19 is a schematic cross-sectional view illustrating a structural example of a liquid crystal display device.
  • FIGS. 20A to 20D each illustrate an example of an electronic device.
  • FIG. 1 an example of a signal line driver circuit that has a function of outputting a plurality of driving signals will be described with reference to FIG. 1 , FIG. 2, FIGS. 3A and 3B, FIG. 4, FIGS. 5A and 5B, and FIG. 6.
  • the signal line driver circuit of this embodiment includes a shift register (also referred to as SR) 101 , a plurality of selection circuits (also referred to as SEL) 1 12 (in FIG. 1 , the selection circuits ⁇ ⁇ 2_Z (Z is a natural number), 1 12_Z+1 , and 1 12_Z+2), and a plurality of driving signal output circuits (also referred to as DO) 1 13 (in FIG. 1 , the driving signal output circuits U 3_Z, 113_Z+1 , and 1 13_Z+2).
  • each signal line is provided with the selection circuit 1 12 and the driving signal output circuit 1 13.
  • a pulse signal generated by the driving signal output circuit 113 is output through a corresponding signal line.
  • a start pulse singal SP is input to the shift register 101.
  • the shift register 101 has a function of outputting a plurality of pulse signals (also referred to as SROUT), the potentials of which are controlled, in accordance with the start pulse singal SP.
  • SROUT pulse signals
  • a pulse signal is input as a pulse signal SELIN from the shift register 101 to the selection circuit 112. Further, a clock signal SECL and a clock signal RECL are input to the selection circuit 112. For example, different pulse signals are input to the plurality of selection circuits 1 12.
  • the selection circuit 112 outputs a pulse signal SELOUT1 and a pulse signal SELOUT2, as illustrated in FIG. 2.
  • the selection circuit 1 12 has a function of determining which the pulse signal SELOUT 1 or the pulse signal SELOUT2 is output at the same potential level as the pulse signal SELIN, depending on the pulse signal SELIN, the clock signal SECL, and the clock signal RECL
  • the selection circuit 1 12 includes a plurality of field-effect transistors.
  • switching of the plurality of field-effect transistors can determine which the pulse signal SELOUT1 or the pulse signal SELOUT2 is output at the same potential level as the pulse signal SELIN.
  • a clock signal GCLK l and a clock signal GCLK2 are input as the clock signal SECL and the clock signal RECL, respectively.
  • a clock signal FCLK 1 and a clock signal FCLK2 are input as the clock signal SECL and the clock signal RECL, respectively.
  • a set signal SIN, a reset signal RIN, a control signal CTL1 , and a control signal CTL2 are input to the driving signal output circuit 113.
  • the driving signal output circuit 1 13 outputs a signal DOUT1 and a signal DOUT2 as illustrated in FIG. 3A.
  • the signal DOUT1 serves as a driving signal.
  • the driving signal output circuit 113 has a function of generating and outputting a driving signal in accordance with the set signal SIN, the reset signal RIN, the control signal CTL1, and the control signal CTL2. For example, the driving signal is output to a wiring for controlling the potential of a signal line.
  • the driving signal output circuit 113 includes a plurality of field-effect transistors.
  • the driving signal output circuit 113 includes a latch unit (also referred to as LAT) 121 , a first buffer unit (also referred to as BUF 1 ) 122, a second buffer unit (also referred to as BUF2) 123, and a switch unit (also referred to as SW) 124.
  • LAT latch unit
  • BUF 1 first buffer unit
  • BUF2 second buffer unit
  • SW switch unit
  • the set signal SIN and the reset signal RIN are input to the latch unit 121.
  • the latch unit 121 has a function of rewriting and storing data Dl and data D2 in accordance with the set signal SIN and the reset signal RIN.
  • the first buffer unit 122 has functions of setting the potential of the signal DOUTl in accordance with the data Dl and the data D2 stored in the latch unit 121 and outputting the signal DOUTl .
  • the potential of the signal DOUTl changes in the range from a potential VCH to a potential VCL (a potential which is lower than the potential VCH).
  • the second buffer unit 123 has functions of setting the potential of the signal
  • the potential of the signal DOUT2 changes in the range from a potential VDD to a potential VSS.
  • the potential VDD is higher than the potential VSS and is the potential of a high-level signal (also referred to as a potential VH).
  • the potential VSS is lower than or equal to a ground potential and is the potential of a low-level signal (also referred to as a potential VL).
  • control signal CTL1 and the control signal CTL2 are input to the switch unit 124.
  • the switch unit 124 has a function of controlling rewriting of the data Dl stored in the latch unit 121 by being turned on or off in accordance with the control signal CTL1 and the control signal CTL2.
  • control signal CTL1 a signal with a period during which an interval between successive pulses is shorter than that of a start pulse signal can be used.
  • the pulse signal SELOUT1 is input from the selection circuit 1 12 as the set signal SIN
  • the pulse signal SELOUT2 is input from the selection circuit 1 12 as the reset signal RIN.
  • the latch unit 121 has a function of rewriting and storing the data D l and the data D2 in accordance with the pulse signal SELOUT 1 and the pulse signal SELOUT2.
  • a clock signal C _1 is input as the control signal CTLl of the driving signal output circuit 1 13_Z illustrated in FIG. 1.
  • a clock signal CK_2 is input as the control signal CTLl of the driving signal output circuit I I3_Z+I .
  • a clock signal C _3 is input as the control signal CTL l of the driving signal output circuit 1 13_Z+2.
  • the signal DOUT1 of the driving signal output circuit 1 13_Z illustrated in FIG. 1 serves as a driving signal DRV_Z.
  • the signal DOUT1 of the driving signal output circuit 1 I 3_Z+1 serves as a driving signal DRV_Z+1.
  • the signal DOUT1 of the driving signal output circuit 1 13_Z+2 serves as a driving signal DRV Z+2.
  • the signal DOUT2 of the driving signal output circuit 1 13_Z is input.
  • a period in which the data Dl can be rewritten can be longer; therefore, a malfunction of a signal line driver circuit can be more effectively suppressed.
  • Connection relations of the plurality of driving signal output circuits 113 provided in the signal line driver circuit illustrated in FIG. 1 may be those shown in FIG. 4.
  • a set signal SIN, a reset signal RIN, a control signal CTL l , a control signal CTL2, and a control signal CTL3 are input to a driving signal output circuit 113.
  • the driving signal output circuit 1 1 3 outputs a signal DOUT1 , a signal DOUT2, and a signal DOUT3 as illustrated in FIG. 5A.
  • the driving signal output circuit 1 13 has a function of generating and outputting a driving signal in accordance with the set signal SIN, the reset signal RIN, and control signals CTL1 to CTL5.
  • the driving signal output circuit 1 13 includes, as illustrated in FIG. 5B, a first latch unit (also referred to as LATl ) 1 3 l a, a second latch unit (also referred to as LAT2) 131 b, a first buffer unit (also referred to as BUF 1 1 ) 132a, a second buffer unit (also referred to as BUF12) 132b, a first switch unit (also referred to as SW l ) 133a, a second switch unit (also referred to as SW2) 133b, a third switch unit (also referred to as SW3) 133c, a fourth switch unit (also referred to as SW4) 133d, and a third buffer unit (also referred to as BUF 13) 134.
  • the set signal SIN and the reset signal RIN are input to the first latch unit 131a.
  • the first latch unit O la has a function of rewriting and storing data Dl l and data D22 in accordance with the set signal SIN and the reset signal RIN.
  • the set signal SIN and the reset signal RIN are input to the second latch unit
  • the second latch unit 131b has a function of rewriting and storing data D13 and data D24 in accordance with the set signal SIN and the reset signal RIN.
  • the first buffer unit 132a has a function of setting the potential of the signal DOUT1 in accordance with the data Dl l and the data D22 stored in the first latch unit 131 a and outputting the signal DOUT1 .
  • the potential of the signal DOUT1 changes in the range from a potential VDD (VH) to a potential VSS (VL).
  • the second buffer unit 132b has a function of setting the potential of the signal DOUT2 in accordance with the data D13 and the data D24 stored in the second latch unit 131 b and outputting the signal DOUT2.
  • the potential of the signal DOUT2 changes in the range from the potential VDD (VH) to the potential VSS (VL).
  • the control signal CTL 1 and the control signal CTL2 are input to the first switch unit 133a.
  • the first switch unit 133a has a function of controlling rewriting of the data Dl 1 stored in the first latch unit O l a by being turned on or off in accordance with the control signal CTL 1 and the control signal CTL2.
  • the control signal CTL1 and the control signal CTL3 are input to the second switch unit 133b.
  • the second switch unit 133b has a function of controlling rewriting of the data D13 stored in the second latch unit 131 b by being turned on or off in accordance with the control signal CTL1 and the control signal CTL3.
  • the signal DOUT2 is input to the third switch unit 133c as the control signal CTL4.
  • the third switch unit 133c has a function of controlling rewriting of the data D22 stored in the first latch unit 131 a by being turned on or off in accordance with the control signal CTL4.
  • the signal DOUT1 is input to the fourth switch unit 133d as the control signal CTL5.
  • the fourth switch unit 133d has a function of controlling rewriting of the data D24 stored in the second latch unit 131 b by being turned on or off in accordance with the control signal CTL5.
  • the signal DOUT2 and the signal DOUT1 are input as the control signal CTL4 of the third switch unit 133c and the control signal CTL5 of the fourth switch unit 133d, respectively, so that the potential VDD or the potential VSS can keep being supplied as the potential of the data D22 of the first latch unit and the potential of the data D24 of the second latch unit; accordingly, the potential of the data D22 of the first latch unit and the potential of the data D24 of the second latch unit can be kept.
  • the third buffer unit 134 has a function of setting the potential of the signal DOUT3 in accordance with the signal DOUT1 and the signal DOUT2 and outputting the signal DOUT3.
  • the signal DOUT3 is a driving signal whose potential changes in the range from a potential VCH to a potential VCL.
  • one of the pulse signals SELOUT1 of the plurality of selection circuits 1 12 is input as the set signal SIN, and one of the pulse signals SELOUT2 of the plurality of selection circuits 1 12 is input as the reset signal RIN.
  • the pulse signal SELOUT1 of the selection circuit 1 12_Z+1 is input as the set signal SIN
  • the pulse signal SELOUT2 of the selection circuit 1 12_Z+1 is input as the reset signal RIN.
  • a clock signal CK_1 is input as the control signal CTL1 of the driving signal output circuit 113_Z illustrated in FIG. 4.
  • a clock signal CK_2 is input as the control signal CTL1 of the driving signal output circuit 1 13_Z+1 .
  • a clock signal CK_3 is input as the control signal CTL 1 of the driving signal output circuit 1 13_Z+2.
  • the signal DOUT1 of the driving signal output circuit 113_Z is input.
  • the control signal CTL3 of the driving signal output circuit 1 13_Z+2 illustrated in FIG. 4 the signal DOUT2 of the driving signal output circuit 113_Z is input.
  • the clock signal GCLK1 is input as the control signal CTL2 of the driving signal output circuit 113_Z+2
  • the clock signal GCLK2 is input as the control signal CTL3 of the driving signal output circuit 1 13_Z+2
  • a period in which the data Dl 1 and the data D 13 illustrated in FIG. 5B can be rewritten can be longer; therefore, a malfunction of a signal line driver circuit can be more effectively suppressed.
  • the signal DOUT3 of the driving signal output circuit 1 13_Z+1 serves as a driving signal DRV_Z+1.
  • the signal DOUT3 of the driving signal output circuit 1 13_Z+2 serves as a driving signal DRV_Z+2.
  • the shift register 101 , the selection circuits 1 12, and the driving signal output circuits 1 13 may be formed using field-effect transistors having the same polarity, which simplifies a manufacturing process in comparison with the case where a signal line driver circuit is formed using field-effect transistors having different polarities.
  • the duty ratio of each of the clock signals CK_1 to C _3 is 25 %, and the clock signals C _1 to CK_3 are sequentially delayed by a quarter of one cycle period.
  • the duty ratio of each of the clock signasl FCL 1 , FCL 2, GCLK l , and GCLK2 is 50 %.
  • the clock signal FCLK2 is an inverted signal of the clock signal FCLK1
  • the clock signal GCL 2 is an inverted signal of the clock signal GCLK l .
  • a double wave line in the timing chart means abbreviation.
  • a pulse of the start pulse singal SP is input to the shift register 101 in a period Ti l .
  • a pulse of a pulse signal SROUT_Z is input to the selection circuit 1 12_Z in a period T12
  • a pulse of a pulse signal SROUT_Z+l is input to the selection circuit 1 12_Z+1 in a period T13
  • a pulse of a pulse signal SROUT_Z+2 is input to the selection circuit 1 12_Z+2 in a period T14.
  • the clock signal FCLK1 is at a low level
  • the clock signal FCLK2 is at a high level
  • the clock signal GCLKl is at a high level
  • the clock signal GCLK2 is at a low level.
  • the selection circuits 1 12_Z and 112_Z+2 each output the input pulse of the pulse signal SROUT_Z or the pulse signal SROUT_Z+2 as a pulse of the pulse signal SELOUTI .
  • the selection circuit 1 12_Z+1 outputs an input pulse of the pulse signal
  • the pulses of the pulse signals SELOUT I are input to the driving signal output circuit 1 13_Z and the driving signal output circuit 1 13_Z+2 as pulses of the set signals SIN.
  • the potential VDD and the potential VSS are written as the data D l and the data D2, respectively. Accordingly, the potential of the signal DOUTl becomes the potential VCH and the potential of the signal DOUT2 becomes the potential VH.
  • the signal DOUTl of the driving signal output circuit 1 13_Z becomes the potential VCH in the period T12
  • the signal DOUTl of the driving signal output circuit 113_Z 2 becomes the potential VCH in the period T 14.
  • the pulse of the pulse signal SELOUT2 is input to the driving signal output circuit 1 13_Z+1 as a pulse of the reset signal R1N.
  • the potential VSS and the potential VDD are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUTl becomes the potential VCL and the potential of the signal DOUT2 becomes the potential VL.
  • the signal DOUTl of the driving signal output circuit 113_Z+1 (driving signal DRV_Z+1) becomes the potential VCL in the period Tl 3.
  • the control signal CTL1 and the control signal CTL2 that are input to the driving signal output circuit 113 to which the pulse of the set signal SIN is input become high level in accordance with the clock signals CK_1 to C _3, the clock signals FCLK 1 and FCLK2, and the clock signals GCLK 1 and GCLK2.
  • the potential VDD is written to the driving signal output circuit 1 13 to which the potential VDD has been written as the data Dl , which is data rewriting. Accordingly, a change in the potential of the data Dl can be small until a pulse of the start pulse singal SP is input to the shift register 101 again.
  • a pulse of the start pulse singal SP is input to the shift register 101 again in a period T 18.
  • a pulse of the pulse signal SROUT_Z is input to the selection circuit 1 12_Z in a period T19
  • a pulse of the pulse signal SROUT_Z+l is input to the selection circuit 1 12_Z+1 in a period T20
  • a pulse of the pulse signal SROUT_Z+2 is input to the selection circuit 1 12_Z+2 in a period T21 .
  • the clock signal FCLK 1 is at a high level
  • the clock signal FCLK2 is at a low level
  • the clock signal GCL l is at a low level
  • the clock signal GCLK2 is at a high level.
  • the selection circuits 112_Z and 112_Z+2 each output the input pulse of the pulse signal SROUT_Z or the pulse signal SROUT_Z+2 as a pulse of the pulse signal SELOUT2.
  • the selection circuit 1 12_Z+1 outputs the input pulse of the pulse signal
  • the potential VDD and the potential VSS are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUT1 becomes the potential VCH and the potential of the signal DOUT2 becomes the potential VH.
  • the potential VSS and the potential VDD are written as the data Dl and the data D2, respectively.
  • the potential of the signal DOUT1 becomes the potential VCL and the potential of the signal DOUT2 becomes the potential VL.
  • the clock signal FCLK1 and the clock signal GCLKl may be the same signal, and the clock signal FCLK2 and the clock signal GCLK2 may also be the same signal.
  • the signal DRV_Z+1 corresponds to a shifted Z-th signal DRV Z.
  • FIG. 1 As described with reference to FIG. 1 , FIG. 2, FIGS. 3 A and 3B, FIG. 4, FIGS.
  • one example of the signal line driver circuit of this embodiment includes a shift register, a plurality of selection circuits to which different pulse signals are input from the shift register and each of which determines which a first pulse signal or a second pulse signal is output at the same potential level as the pulse signal, and driving signal output circuits to which the first pulse signals and the second pulse signals of the different selection circuits are input.
  • a plurality of driving signals can ' be output.
  • a driving signal output circuit of one example of the signal line driver circuit of this embodiment by providing a switch unit for contolling rewriting of data stored in a latch unit, the data can be rewritten even in a period during which a pulse of a pulse signal is not output from the shift register. Accordingly, for example, a change in the potential that is a first data, due to leakage current of a field-effect transistor in the driving signal output circuit can be prevented. Therefore, a malfunction of the signal line driver circuit can be suppressed.
  • the signal line driver circuit of this embodiment can be applied to a semiconductor device for controlling driving of a plurality of circuits with the use of a plurality of signal lines, such as a liquid crystal display device or electronic paper.
  • a signal line driver circuit that outputs a driving signal through a common signal line and an example of a liquid crystal display device provided with the signal line driver circuit will be described.
  • a liquid crystal display device illustrated in FIG. 7A includes a signal line driver circuit 201 , a signal line driver circuit 202, a signal line driver circuit 203, data signal lines DL_1 to DL_7 (Y is a natural number of 2 or more), gate signal lines GL_1 to GL X (X is a natural number of 2 or more), common signal lines CL_1 to CL X, and a plurality of pixel circuits 210 arranged in rows and 7 columns.
  • the signal line driver circuit 201 has a function of generating a plurality of data signals DS (data signals DS_1 to DS_F).
  • the signal line driver circuit 201 has a function of controlling driving of the pixel circuit 210 by controlling the potentials of the plurality of data signal lines DL (data signal lines DL_1 to DL_F) with the use of the plurality of data signals DS.
  • the signal line driver circuit 202 has a function of generating a plurality of gate signals GS (gate signals GS_1 to GS_ ).
  • the signal line driver circuit 202 has a function of controlling driving of the pixel circuit 210 by controlling the potentials of the plurality of gate signal lines GL (gate signal lines GL_1 to GL_X) with the use of the plurality of gate signals GS.
  • the signal line driver circuit 203 has a function of generating a plurality of common singals CS (common singals CS_1 to CS_ ).
  • the signal line driver circuit 203 has a function of controlling driving of the pixel circuit 210 by controlling the potentials of the plurality of common signal lines CL (common signal lines CL_1 to CL_X) with the use of the plurality of common singals CS.
  • the signal line driver circuit 203 can be the signal line driver circuit in Embodiment 1 , for example.
  • the plurality of pixel circuits 210 each include a field-effect transistor 21 1 , a liquid crystal element 212 including a pair of electrodes and a liquid crystal layer, and a capacitor 213. Note that the capacitor 213 is not necessarily provided. [0091 ]
  • one of a source and a drain of the field-effect transistor 211 is electrically connected to the data signal line DL_N (one of the plurality of data signal lines DL).
  • a gate of the field-effect transistor 21 1 is electrically connected to the gate signal line GL_ (one of the plurality of gate signal lines GL).
  • one of the pair of electrodes of the liquid crystal element 212 is electrically connected to the other of the source and the drain of the field-effect transistor 21 1 of the pixel circuit 210 in the M-th row and the N-th column.
  • the other of the pair of electrodes of the liquid crystal element 212 is electrically connected to the common signal line CL_M(one of the plurality of common signal lines CL).
  • the alignment of liquid crystal included in the liquid crystal layer is controlled in accordance with voltage applied to the pair of electrodes.
  • one of a pair of electrodes of the capacitor 213 is electrically connected to the other of the source and the drain of the field-effect transistor 21 1 in the pixel circuit 210 in the M-th row and the N-th column.
  • the potential VSS is applied to the other of the pair of electrodes of the capacitor 213.
  • the signal line driver circuit 203 includes a shift register 230 (shift register 230 in FIG. 7B), a plurality of selection circuits 232 (in FIG. 7B, only selection circuits 232_1 to 232_4 are illustrated), and a plurality of driving signal output circuits 233 (in FIG. 7B, only driving signal output circuits 233_1 to 233_4 are illustrated). Further, the shift register 230 includes pulse output circuits 231_1 to 231_ Note that in this embodiment, the case where the selection circuits 232_1 to 232_X and the driving signal output circuits 233_1 to 233_X are provided is described. Note that in FIGS. 7 A and 7B, Xis a natural number of 3 or more.
  • each component of the signal line driver circuit illustratd in FIG. 7B is described with reference to FIGS. 8A and 8B, FIGS. 9A and 9B, and FIGS. 10A and 10B.
  • FIGS. 8A and 8B are diagrams for describing a configuration example of the pulse output circuit of the shift register 230 illustrated in FIG. 7B.
  • a set signal LIN_F, a reset signal RIN F, a clock signal CL_F, a clock signal CLp_F, and an initialization signal INI_RES are input to the pulse output circuit 231.
  • the pulse output circuit illustrated in FIG. 8A outputs a signal FOUT.
  • the signal FOUT corresponds to a pulse signal SROUT of the shift register 230.
  • the initialization signal INI_RES is a signal used for initialization of the pulse output circuit, for example.
  • a pulse of the initialization signal INI_RES is input to the pulse output circuit, whereby the pulse output circuit is initialized. Note that it is not always necessary to input the initialization signal INI_RES to the pulse output circuit.
  • a configuration of a pulse output circuit 231_ +1 is the same as the other pulse output circuits, except that the reset signal RIN_F is not input.
  • the pulse output circuit 23 1 illustrated in FIG. 8A includes field-effect transistors 31 1 to 319, a capacitor 321 , and a capacitor 322, as illustrated in FIG. 8B.
  • the potential VDD is " applied to one of a source and a drain of the field-effect transistor 31 1 .
  • the set signal LIN_F is input to a gate of the field-effect transistor 3 1 1 .
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 312.
  • the set signal LIN_F is input to a gate of the field-effect transistor 312.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 313.
  • the other of the source and the drain of the field-effect transistor 313 is electrically connected to the other of the source and the drain of the field-effect transistor 3 12.
  • the reset signal RIN_F is applied to a gate of the field-effect transistor 313.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 3 14.
  • the other of the source and the drain of the field-effect transistor 314 is electrically connected to the other of the source and the drain of the field-effect transistor 312.
  • the initialization signal IN1_RES is input to a gate of the field-effect transistor 314. Note that it is not always necessary to provide the field-effect transistor 314.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 315.
  • the other of the source and the drain of the field-effect transistor 315 is electrically connected to the other of the source and the drain of the field-effect transistor 312.
  • the clock signal CLp_F is input to a gate of the field-effect transistor 315.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 316.
  • the other of the source and the drain of the field-effect transistor 316 is electrically connected to the other of the source and the drain of the field-effect transistor 311 .
  • a gate of the field-effect transistor 316 is electrically connected to the other of the source and the drain of the field-effect transistor 312.
  • One of a source and a drain of the field-effect transistor 317 is electrically connected to the the other of the source and the drain of the field-effect transistor 31 1.
  • the potential VDD is applied to a gate of the field-effect transistor 317.
  • the clock signal CL_F is input to one of a source and a drain of the field-effect transistor 318.
  • a gate of the field-effect transistor 318 is electrically connected to the other of the source and the drain of the field-effect-transistor 317.
  • the potential of the other of the souce and the drain of the field-effect transistor 31 8 corresponds to the potential of the signal FOUT.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 319.
  • the other of the source and the drain of the field-effect transistor 319 is electrically connected to the other of the source and the drain of the field-effect transistor 3 18.
  • a gate of the field-effect transistor 319 is electrically connected to the other of the source and the drain of the field-effect transistor 312.
  • the potential VSS is applied to one of a pair of electrodes of the capacitor 321.
  • the other of the pair of electrodes of the capacitor 321 is electrically connected to the other of the source and the drain of the field-effect transistor 312. It is not always necessary to provide the capacitor 321 .
  • One of a pair of electrodes of the capacitor 322 is electrically connected to the gate of the field-effect transistor 31 8.
  • the other of the pair of electrodes of the capacitor 322 is electrically connected to the other of the source and the drain of the field-effect transistor 318. It is not always necessary to provide the capacitor 322.
  • the pulse output circuit illustrated in FIG. 8B when the field-effect transistors 31 1 and 312 are turned on in accordance with the set signal LIN_F and the field-effect transistor 318 is turned on, the potential of the signal FOUT becomes substantially equal to the potential of the clock signal CL_F. In this case, the field-effect transistor 319 is in an off state.
  • the pulse output circuit illustrated in FIG. 8B when the field-effect transistor 313 is turned on in accordance with the reset signal RIN_F and the field-effect transistor 319 is turned on, the potential of the signal FOUT becomes substantially equal to the potential VSS. In this case, since the field-effect transistor 313 is in an on state and the field-effect transistor 316 is in an on state, the field-effect transistor 31 8 is in an off state. Accordingly, the pulse output circuit outputs a pulse signal.
  • a start pulse singal SP is input as the set signal LIN_F of the pulse output circuit 231_1.
  • a wiring for inputting the start pulse singal SP to the signal line driver circuit 203 may be electrically connected to a protection circuit.
  • the signal FOUT of the pulse output circuit 231_A " -1 is input as the set signal LIN_F of the pulse output circuit 23 ⁇ _K ⁇ K is a natural number larger than or equal to 2 and smaller than or equal to X).
  • the signal FOUT of the pulse output circuit 231_ +1 is input as the reset signal RIN_F of the pulse output circuit 231_
  • a clock signal CLK 1 and a clock signal CLK2 are input as the clock signal CL_F and the clock signal CLp_F, respectively.
  • the clock signal CLK 1 is input as the clock signal CL_F and the clock signal CLK2 is input as the clock signal CLp_F to every fourth pulse output circuit from the pulse output circuit 231 _1.
  • the clock signal CLK2 and a clock signal CLK3 are input as the clock signal CL_F and the clock signal CLp_F, respectively.
  • the clock signal CLK2 is input as the clock signal CL_F and the clock signal CLK3 is input as the clock signal CLp_F to every fourth pulse output circuit from the pulse output circuit 231_2.
  • the clock signal CL 3 and the clock signal CL 4 are input as the clock signal CL_F and the clock signal CLp_F, respectively.
  • the clock signal CL 3 is input as the clock signal CL_F and the clock signal CLK4 is input as the clock signal CLp_F to every fourth pulse output circuit from the pulse output circuit 231_3.
  • the clock signal CL 4 and the clock signal CLK l are input as the clock signal CL_F and the clock signal CLp_F, respectively.
  • the clock signal CLK4 is input as the clock signal CL_F and the clock signal CLKl is input as the clock signal CLp_F to every fourth pulse output circuit from the pulse output circuit 231_4.
  • each of wirings for inputting the clock signals CLKl to CLK4 may be electrically connected to a protection circuit.
  • FIGS. 9A and 9B are diagrams for describing an example of a configuration of the selection circuit.
  • a pulse signal SELIN, a clock signal SECL, and a clock signal RECL are input to the selection circuit 232, as illustrated in FIG. 9A.
  • the selection circuit 232 outputs a pulse signal SELOUT1 and a pulse signal SELOUT2.
  • the selection circuit 232 has a function of determining which the pulse signal SELOUT1 or the pulse signal SELOUT2 is output at the same potential level as the pulse signal SELIN in accordance with the clock signal SECL and the clock signal RECL.
  • the selection circuit 232 illustrated in FIG. 9A includes field-effect transistors 331 to 336 as illustrated in FIG. 9B.
  • the pulse signal SELIN is input to one of a source and a drain of the field-effect transistor 331.
  • the potential of the other of the source and the drain of the field-effect transistor 331 corresponds to the potential of the pulse signal SELOUT1.
  • the pulse signal SELIN is input to one of a source and a drain of the field-effect transistor 332.
  • the potential of the other of the source and the drain of the field-effect transistor 332 corresponds to the potential of the pulse signal SELOUT2.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 333.
  • the other of the source and the drain of the field-effect transistor 333 is electrically connected to the other of the source and the drain of the field-effect transistor 33 1.
  • the clock signal RECL is input to a gate of the field-effect transistor 333.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 334.
  • the other of the source and the drain of the field-effect transistor 334 is electrically connected to the other of the source and the drain of the field-effect transistor 332.
  • the clock signal SECL is input to a gate of the field-effect transistor 334.
  • the clock signal SECL is input to one of a source and a drain of the field-effect transistor 335.
  • the other of the source and the drain of the field-effect transistor 335 is electrically connected to a gate of the field-effect transistor 331.
  • the potential VDD is applied to a gate of the field-effect transistor 335. Note that it is not always necessary to provide the field-effect transistor 335.
  • the clock signal RECL is input to one of a source and a drain of the field-effect transistor 336.
  • the other of the source and the drain of the field-effect transistor 336 is electrically connected to a gate of the field-effect transistor 332.
  • the potential VDD is applied to a gate of the field-effect transistor 336. It is not always necessary to provide the field-effect transistor 336.
  • the pulse signal SELIN is output as the pulse signal SELOUT l by turning on the field-effect transistor 33 1 in accordance with the clock signal SECL. At this time, the field-effect transistor 332 is in an off state and the field-effect transistor 334 is in an on state.
  • the pulse signal SELIN is output as the pulse signal SELOUT2 by turning on the field-effect transistor 332 in accordance with the clock signal RECL. At this time, the field-effect transistor 331 is in an off state and the field-effect transistor 333 is in an on state.
  • a start pulse singal SP is input as the pulse signal SELIN of the selection circuit 232_1 illustrated in FIG. 7B.
  • the signal FOUT of the pulse output circuit 231_ ⁇ — 1 is input as the pulse signal SELIN of the selection circuit 232_K.
  • the clock signal FCLK1 is input as the clock signal SECL of the selection circuit 232_Q ⁇ Q is an odd number larger than or equal to 1 and smaller than or equal to X).
  • the clock signal FCLK2 is input as the clock signal RECL of the selection circuit 232_g.
  • the clock signal GCL 1 is input as the clock signal SECL of the selection circuit 232_R (R is an even number larger than or equal to 2 and smaller than or equal to X).
  • the clock signal GCL 2 is input as the clock signal RECL of the selection circuit 232_R.
  • each of wirings for inputting FCL 1 , the clock signal FCLK2, the clock signal GCLK 1 , and the clock signal GCLK2 may be electrically connected to a protection circuit.
  • FIGS. 10A and 10B are diagrams for describing an example of the driving signal output circuit.
  • a set signal SINJD, a reset signal RIN_D, a control signal CTL1_D, a control signal CTL2_D, and an initialization signal INI RES are input to the driving signal output circuit 233.
  • the driving signal output circuit 233 is initialized. Note that it is not always necessary to input the initialization signal INI RES to the driving signal output circuit 233.
  • the driving signal output circuit 233 outputs a signal DOUT1 and a signal DOUT2.
  • the signal DOUTl is a common signal output from the driving signal output circuit 233. A wiring for outputting the signal DOUTl may be electrically connected to a protection circuit.
  • the driving signal output circuit 233 illustrated in FIG. 10A includes a latch unit, a first buffer unit, a second buffer unit, and a switch unit, similarly to the driving signal output circuit illustrated in FIGS. 3A and 3B. The further details are described below.
  • the driving signal output circuit 233 illustrated in FIG. 10A includes field-effect transistors 351 to 364, a capacitor 371 , and a capacitor 372. Note that the field-effect transistors 351 to 364 are n-channel transistors.
  • the field-effect transistor 351 is provided in the latch unit. The potential
  • VDD is applied to one of a source and a drain of the field-effect transistor 351.
  • the set signal SIN_D is input to a gate of the field-effect transistor 351.
  • the field-effect transistor 352 is provided in the latch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 352.
  • the reset signal RIN_D is input to a gate of the field-effect transistor 352.
  • the field-effect transistor 353 is provided in the latch unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 353.
  • the other of the source and the drain of the field-effect transistor 353 is electrically connected to the other of the source and the drain of the field-effect transistor 352.
  • the set signal SIN_D is input to a gate of the field-effect transistor 353.
  • the field-effect transistor 354 is provided in the latch unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 354.
  • the other of the source and the drain of the field-effect transistor 354 is electrically connected to the other of the source and the drain of the field-effect transistor 351 .
  • the reset signal RIN_D is input to a gate of the field-effect transistor 354.
  • the field-effect transistor 355 is provided in the first buffer unit.
  • a potential TCOMH is applied to one of a source and a drain of the field-effect transistor 355.
  • the potential of the other of the source and the drain of the field-effect transistor 355 corresponds to the potential of the signal DOUT1.
  • the field-effect transistor 356 is provided in the first buffer unit.
  • a potential TCOML is applied to one of a source and a drain of the field-effect transistor 356.
  • the other of the source and the drain of the field-effect transistor 356 is electrically connected to the other of the source and the drain of the field-effect transistor 355.
  • a gate of the field-effect transistor 356 is electrically connected to the other of the source and the drain of the field-effect transistor 352.
  • Each of the potential TCOMH and the potential TCOML is a potential for setting the potential of a common signal.
  • the potential TCOMH is higher than the potential TCOML.
  • the field-effect transistor 357 is provided in the second buffer unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 357.
  • the potential of the other of the source and the drain of the field-effect transistor 357 corresponds to the potential of the signal DOUT2.
  • the field-effect transistor 358 is provided in the second buffer unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 358.
  • the other of the source and the drain of the field-effect transistor 358 is electrically connected to the other of the source and the drain of the field-effect transistor 357.
  • a gate of the field-effect transistor 358 is electrically connected to the other of the source and the drain of the field-effect transistor 352.
  • the field-effect transistor 359 is provided in the switch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 359.
  • the control signal CTLI D is input to a gate of the field-effect transistor 359.
  • the field-effect transistor 360 is provided in the switch unit. One of a source and a drain of the field-effect transistor 360 is electrically connected to the other of the source and the drain of the field-effect transistor 359. The other of the source and the drain of the field-effect transistor 360 is electrically connected to the other of the source and the drain of the field-effect transistor 351.
  • the control signal CTL2_D is input to a gate of the field-effect transistor 360.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 361.
  • the other of the source and the drain of the field-effect transistor 361 is electrically connected to the other of the source and the drain of the field-effect transistor 351.
  • a gate of the field-effect transistor 361 is electrically connected to the other of the source and the drain of the field-effect transistor 352. Note that it is not always necessary to provide the field-effect transistor 361.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 362.
  • the other of the source and the drain of the field-effect transistor 362 is electrically connected to the other of the source and the drain of the field-effect transistor 352.
  • a gate of the field-effect transistor 362 is electrically connected to the other of the source and the drain of the field-effect transistor 357. Note that it is not always necessary to provide the field-effect transistor 362.
  • One of a source and a drain of the field-effect transistor 363 is electrically connected to the other of the source and the drain of the field-effect transistor 3 1.
  • the other of the source and the drain of the field-effect transistor 363 is electrically connected to a gate of the field-effect transistor 355 and a gate of the field-effect transistor 357.
  • the potential VDD is applied to a gate of the field-effect transistor 363. Note that it is not always necessary to provide the field-effect transistor 363.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 364.
  • the other of the source and the drain of the field-effect transistor 364 is electrically connected to the gate of the field-effect transistor 356 and the gate of the field-effect transistor 358.
  • the initialization signal INI_RES is input to a gate of the field-effect transistor 364. Note that it is not always necessary to provide the field-effect transistor 364.
  • the potential VSS is applied to one of a pair of electrodes of the capacitor 371.
  • the other of the pair of electrodes of the capacitor 371 is electrically connected to the gate of the field-effect transistor 356 and the gate of the field-effect transistor 358. Note that it is not always necessary to provide the capacitor 371.
  • One of a pair of electrodes of the capacitor 372 is electrically connected to the gate of the field-effect transistor 355 and the gate of the field-effect transistor 357.
  • the other of the pair of electrodes of the capacitor 372 is electrically connected to the other of the source and the drain of the field-effect transistor 357. Note that it is not always necessary to provide the capacitor 372.
  • the driving signal output circuit illustrated in FIG. 10B by turning on the field-effect transistors 351 and 353 in accordance with the set signal SIN_D and turning on the field-effect transistor 355, the potential of the signal DOUTl becomes substantially equal to the potential TCOMH. In this case, the field-effect transistor 356 is in an off state.
  • the driving signal output circuit illustrated in FIG. 10B by turning on the field-effect transistors 352 and 354 in accordance with the reset signal RIN_D and turning on the field-effect transistor 356, the potential of the signal DOUTl becomes substantially equal to the potential TCOML. In this case, the field-effect transistor 355 is in an off state.
  • the pulse signal SELOUT1 of the selection circuit 232_ is input as the set signal SIN_D of the driving signal output circuit 233_ illustrated in FIG. 7B.
  • the pulse signal SELOUT2 of the selection circuit 232_ is input as the reset signal RIN_D of the driving signal output circuit 233_ .
  • the clock signal CL 4 is input as the control signal CTL 1_D of the driving signal output circuit 233_1.
  • the clock signal CL 4 is input as the control signal CTL 1_D to every fourth driving signal output circuit from the driving signal output circuit 233_1.
  • the clock signal CL 1 is input as the control signal CTL 1_D of the driving signal output circuit 233_2.
  • the clock signal CLKI is input as the control signal CTL1_D to every fourth driving signal output circuit from the driving signal output circuit 233_2.
  • the clock signal CLK2 is input as the control signal CTL1_D of the driving signal output circuit 233_3.
  • the clock signal CLK2 is input as the control signal CTL1_D to every the fourth driving signal output circuit from the driving signal output circuit 233_3.
  • the clock signal CL 3 is input as the control signal CTL 1_D of the driving signal output circuit 233_4 ⁇
  • the clock signal CL 3 is input as the control signal CTL 1 _D to every the fourth driving signal output circuit from the driving signal output circuit 233_4.
  • the clock signal FCL 1 is input as the control signal CTL2_D of the driving signal output circuit 233_1 .
  • the clock signal GCLK 1 is input as the control signal CTL2_D of the driving signal output circuit 233_2.
  • the signal DOUT2 of the driving signal output circuit 233_ -2 (L is a natural number larger than or equal to 3 and smaller than or equal to X) is input as the control signal CTL2_D of the driving signal output circuit 233_Z.
  • the signal DOUT1 of the driving signal output circuit 233_ corresponds to the common singal CS_
  • a liquid crystal display device of this embodiment can have a configuration illustrated in FIG. 11 A.
  • the liquid crystal display device illustrated in FIG. 11 A has a configuration in which the plurality of gate signal lines GL and the plurality of common signal lines CL are electrically connected to the signal line driver circuit 203.
  • FIG. 1 1 B illustrates an example of a configuration of the signal line driver circuit 203 in this case.
  • the shift register 230 illustrated in FIG. 1 IB is provided in the signal line driver circuit 202.
  • the plurality of selection circuits 232 and the plurality of driving signal output circuits 233 are provided for the signal line driver circuit 203. With this configuration, even when shift registers are not provided in the signal line driver circuit 203, the pulse signal SROUT can be output to the selection circuit 232 of the signal line driver circuit 203 with the shift register 230 of the signal line driver circuit 202.
  • the liquid crystal display device of this embodiment can have a configuration illustrated in FIG. 12A.
  • the liquid crystal display device illustrated in FIG. 12A includes a signal line driver circuit 204, instead of the signal line driver circuit 202 and the signal line driver circuit 203.
  • FIG. 12B illustrates an example of a configuration of the signal line driver circuit 204.
  • the signal line driver circuit 204 illustrated in FIG. 12B has the configuration of the signal line driver circuit illustrated in FIG. 7B and has a function of outputting the gate signals GS_1 to GS_
  • the signal FOUT of the pulse output circuit 23 ⁇ _M corresponds to the gate signal GS_
  • the signal line driver circuit illustrated in FIG. 7B can have another configuration.
  • FIG. 13 illustrates another example of the configuration of the signal line driver circuit illustrated in FIG. 7B.
  • a signal line driver circuit illustrated in FIG. 13 and the signal line driver circuit illustrated in FIG. 7B are different in a configuration of a pulse output circuit of a shift register and a configuration of a driving signal output circuit.
  • an initialization signal INI_RES1 and an initialization signal iNI_RES2 are input instead of the initialization signal INI_RES.
  • the initialization signals INI_RES1 and INI_RES2 are used in the case where the potentials of a plurality of connection portions in a circuit are separately initialized, for example. Pulses of the initialization signals INI_RES1 and INI_RES2 are input to the pulse output circuit, whereby the pulse output circuit is initialized. Note that the initialization signals INI_RES 1 and 1N1_RES2 have different waveforms. It is not always necessary to input the initialization signals INI_RES 1 and INI_RES2 to the pulse output circuit.
  • the pulse output circuit illustrated in FIG. 14A has a field-effect transistor 320 in addition to the configuration of the pulse output circuit illustrated in FIG. 8B, as shown in FIG. 14B.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 320.
  • the other of the source and the drain of the field-effect transistor 320 is electrically connected to the gate of the field-effect transistor 319.
  • the initialization signal INI_RES2 is input to a gate of the field-effect transistor 320.
  • the initialization signal INI_RES1 is input to the gate of the field-effect transistor 314, instead of the initialization signal INI_RES.
  • FIG. 13 An example of a configuration of the driving signal output circuit illustrated in FIG. 13 is described with reference to FIGS. 15A and 15B.
  • a set signal SIN_D, a reset signal RIN D, control signals CTL1_D to CTL4_D, and initialization signals INI_RES1 and INI_RES2 are input to the driving signal output circuit 233 in FIG. 15A. Pulses of the initialization signals INI_RES1 and INI_RES2 are input to the driving signal output circuit, whereby the driving signal output circuit is initialized. It is not always necessary to input the initialization signals INI_RES1 and INI_RES2 are input to the driving signal output circuit. As illustrated in FIG. 15 A, the plurality of driving signal output circuits 233 illustrated in FIG. 13 each have a function of outputting a signal SCOUT, a signal RCOUT, and a signal DOUT.
  • DOUT is a common signal.
  • the driving signal output circuit illustrated in FIG. 15A includes a first latch unit storing the data Dl 1 and the data D22, a second latch unit storing the data D13 and the data D24, a first buffer unit, a second buffer unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a third buffer unit. The further details are described below.
  • the driving signal output circuit illustrated in FIG. 15A includes field-effect transistors 431 to 444, a capacitor 451 , a capacitor 452, field-effect transistors 461 to 474, a capacitor 481 , and a capacitor 482, as illustrated in FIG. 15B.
  • the field-effect transistor 431 is provided in the first latch unit.
  • the field-effect transistor 461 is provided in the second latch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 431 and one of a source and a drain of the field-effect transistor 461.
  • the set signal SIN_D is input to a gate of the field-effect transistor 431 and a gate of the field-effect transistor 461.
  • the potential of the other of the source and the drain of the field-effect transistor 431 corresponds to the data Dl 1.
  • the potential of the other of the. source and the drain of the field-effect transistor 461 corresponds to the data D24.
  • the field-effect transistor 432 is provided in the first latch unit.
  • the field-effect transistor 462 is provided in the second latch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 432 and one of a source and a drain of the field-effect transistor 462.
  • the reset signal RTN_D is input to a gate of the field-effect transistor 432 and a gate of the field-effect transistor 462.
  • the potential of the other of the source and the drain of the field-effect transistor 432 corresponds to the data D22.
  • the potential of the other of the source and the drain of the field-effect transistor 462 corresponds to the data D 13.
  • the field-effect transistor 433 is provided in the first latch unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 433.
  • the other of the source and the drain of the field-effect transistor 433 is electrically connected to the other of the source and the drain of the field-effect transistor 432.
  • the set signal SIN_D is input to a gate of the field-effect transistor 433.
  • the field-effect transistor 463 is provided in the second latch unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 463.
  • the other of the source and the drain of the field-effect transistor 463 is electrically connected to the other of the source and the drain of the field-effect transistor 461.
  • the reset signal R1N_D is input to a gate of the field-effect transistor 463.
  • the field-effect transistor 434 is provided in the first buffer unit.
  • the field-effect transistor 464 is provided in the second buffer unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 434 and one of a source and a drain of the field-effect transistor 464.
  • the potential of the other of the source and the drain of the field-effect transistor 434 corresponds to the potential of the signal SCOUT.
  • the potential of the other of the source and the drain of the field-effect transistor 464 corresponds to the potential of the signal RCOUT.
  • the field-effect transistor 435 is provided in the first buffer unit.
  • the field-effect transistor 465 is provided in the second buffer unit.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 435 and one of a source and a drain of the field-effect transistor 465.
  • the other of the source and the drain of the field-effect transistor 435 is electrically connected to the other of the source and the drain of the field-effect transistor 434.
  • the other of the source and the drain of the field-effect transistor 465 is electrically connected to the other of the source and the drain of the field-effect transistor 464.
  • the field-effect transistor 436 is provided in the first switch unit.
  • the field-effect transistor 466 is provided in the second switch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 436 and one of a source and a drain of the field-effect transistor 466.
  • the control signal CTL 1 _D is input to a gate of the field-effect transistor 436 and a gate of the field-effect transistor 466.
  • the field-effect transistor 437 is provided in the first switch unit.
  • the field-effect transistor 467 is provided in the second switch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 437 and one of a source and a drain of the field-effect transistor 467.
  • the control signal CTL2_D is input to a gate of the field-effect transistor 437 and a gate of the field-effect transistor 467.
  • the field-effect transistor 438 is provided in the first switch unit. One of a source and a drain of the field-effect transistor 438 is electrically connected to the other of the source and the drain of the field-effect transistor 436 and the other of the source and the drain of the field-effect transistor 437. The other of the source and the drain of the field-effect transistor 438 is electrically connected to the other of the source and the drain of the field-effect transistor 431.
  • the control signal CTL3_D is input to a gate of the field-effect transistor 438.
  • the field-effect transistor 468 is provided in the second switch unit. One of a source and a drain of the field-effect transistor 468 is electrically connected to the other of the source and the drain of the field-effect transistor 466 and the other of the source and the drain of the field-effect transistor 467. The other of the source and the drain of the field-effect transistor 468 is electrically connected to the other of the source and the drain of the field-effect transistor 462.
  • the control signal CTL4_D is input to a gate of the field-effect transistor 468.
  • the field-effect transistor 439 is provided in the third switch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 439.
  • the other of the source and the drain of the field-effect transistor 439 is electrically connected to the other of the source and the drain of the field-effect transistor 432.
  • the signal RCOUT is input to a gate of the field-effect transistor 439 as the control signal CTL5_D.
  • the field-effect transistor 469 is provided in the fourth switch unit.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 469.
  • the other of the source and the drain of the field-effect transistor 469 is electrically connected to the other of the source and the drain of the field-effect transistor 461.
  • the signal SCOUT is input to a gate of the field-effect transistor 469 as a control signal CTL6_D.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 440.
  • the other of the source and the drain of the field-effect transistor 440 is electrically connected to the other of the source and the drain of the field-effect transistor 431 .
  • a gate of the field-effect transistor 440 is electrically connected to the other of the source and the drain of the field-effect transistor 432.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 470.
  • the other of the source and the drain of the field-effect transistor 470 is electrically connected to the other of the source and the drain of the field-effect transistor 462.
  • a gate of the field-effect transistor 470 is electrically connected to the other of the source and the drain of the field-effect transistor 461.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 441.
  • the other of the source and the drain of the field-effect transistor 441 is electrically connected to the other of the source and the drain of the field-effect transistor 432.
  • a gate of the field-effect transistor 441 is electrically connected to the other of the source and the drain of the field-effect transistor 434. It is not always necessary to provide the field-effect transistor 441.
  • the potential VSS is applied to one of a source and a drain of the field-effect transistor 471.
  • the other of the source and the drain of the field-effect transistor 471 is electrically connected to the other of the source and the drain of the field-effect transistor 463.
  • a gate of the field-effect transistor 471 is electrically connected to the other of the source and the drain of the field-effect transistor 464. It is not always necessary to provide the field-effect transistor 471.
  • One of a source and a drain of the field-effect transistor 442 is electrically connected to the other of the source and the drain of the field-effect transistor 431 .
  • the other of the source and the drain of the field-effect transistor 442 is electrically connected to a gate of the field-effect transistor 434.
  • the potential VDD is applied to a gate of the field-effect transistor 442. It is not always necessary to provide the field-effect transistor 442.
  • One of a source and a drain of the field-effect transistor 472 is electrically connected to the other of the source and the drain of the field-effect transistor 462.
  • the other of the source and the drain of the field-effect transistor 472 is electrically connected to a gate of the field-effect transistor 464.
  • the potential VDD is applied to a gate of the field-effect transistor 472. It is not always necessary to provide the field-effect transistor 472.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 443 and one of a source and a drain of the field-effect transistor 473.
  • the other of the source and the drain of the field-effect transistor 443 is electrically connected to a gate of the field-effect transistor 435.
  • the other of the source and the drain of the field-effect transistor 473 is electrically connected to a gate of the field-effect transistor 465.
  • the initialization signal INI_RES1 is input to a gate of the field-effect transistor 443.
  • the initialization signal INI_RES2 is input to a gate of the field-effect transistor 473. It is not always necessary to provide the field-effect transistor 443 and the field-effect transistor 473.
  • the potential VDD is applied to one of a source and a drain of the field-effect transistor 444 and one of a source and a drain of the field-effect transistor 474.
  • the other of the source and the drain of the field-effect transistor 444 is electrically connected to the other of the source and the drain of the field-effect transistor 43 1 .
  • the other of the source and the drain of the field-effect transistor 474 is electrically connected to the other of the source and the drain of the field-effect transistor 462.
  • the initialization signal 1NI_RES2 is input to a gate of the field-effect transistor 444.
  • the initialization signal 1 I_RES 1 is input to a gate of the field-effect transistor 474. It is not always necessary to provide the field-effect transistor 444 and the field-effect transistor 474.
  • the potential VSS is applied to one of a pair of electrodes of the capacitor 45 1.
  • the other of the pair of electrodes of the capacitor 451 is electrically connected to the gate of the field-effect transistor 435.
  • the potential VSS is applied to one of a pair of electrodes of the capacitor 481.
  • the other of the pair of electrodes of the capacitor 481 is electrically connected to the gate of the field-effect transistor 465.
  • One of a pair of electrodes of the capacitor 452 is electrically connected to the gate of the field-effect transistor 434.
  • the other of the pair of electrodes of the capacitor 452 is electrically connected to the other of the source and the drain of the field-effect transistor 434.
  • One of a pair of electrodes of the capacitor 482 is electrically connected to the gate of the field-effect transistor 464.
  • the other of the pair of electrodes of the capacitor 482 is electrically connected to the other of the source and the drain of the field-effect transistor 464.
  • a field-effect transistor 491 is provided in the third buffer unit.
  • the potential TCOMH is applied to one of a source and a drain of the field-effect transistor 491.
  • the potential TCOMH is higher than the potential VDD.
  • the potential of the other of the source and the drain of the field-effect transistor 491 corresponds to the potential of a signal COUT.
  • the signal SCOUT is input to a gate of the field-effect transistor 491.
  • the field-effect transistor 492 is provided in the third buffer unit.
  • the potential TCOML is applied to one of a source and a drain of the field-effect transistor 492.
  • the potential TCOML is lower than the potential VSS.
  • the other of the source and the drain of the field-effect transistor 492 is electrically connected to the other of the source and the drain of the field-effect transistor 491.
  • the signal RCOUT is input to a gate of the field-effect transistor 492.
  • the field-effect transistor 43 1 and the field-effect transistor 433 are turned on in accordance with the set signal SIN_D, the potential VDD is written as the data Dl l of the first latch unit, the field-effect transistor 434 is turned on, the potential of the signal SCOUT becomes the potential VH, and the signal SCOUT becomes high level.
  • the potential VSS is written as the data D22 of the first latch unit, and thus the field-effect transistor 435 is in an off state.
  • the field-effect transistor 461 is turned on in accordance with the set signal SIN_D, the potential VDD is written as the data D24 of the second latch unit, the field-effect transistor 465 is turned on, the potential of the signal RCOUT becomes the potential VL, and the signal RCOUT becomes low level. In this case, the field-effect transistor 464 is in an off state.
  • the field-effect transistor 432 is turned on in accordance with the reset signal RIN_D, the potential VDD is written as the data D22 of the first latch unit, the field-effect transistor 435 is turned on, the potential of the signal SCOUT becomes the potential VL, and the signal SCOUT becomes low level.
  • the field-effect transistor 440 is in an on state and the field-effect transistor 431 is in an off state; accordingly, the field-effect transistor 434 is in an off state.
  • the field-effect transistor 462 is turned on in accordance with the reset signal RIN_D, the field-effect transistor 464 is turned on, the potential of the signal RCOUT becomes the potential VH, and the signal RCOUT becomes high level.
  • the potential VSS is written as the data D24 of the second latch unit, and thus the field-effect transistor 465 is in an off state.
  • signals input as the set signal SIN D, the reset signal RIN_D, the control signal CTL1_D, and the control signal CTL2_D are the same as the corresponding signals input to each of the plurality of driving signal output circuits illustrated in FIG. 7B.
  • the clock signal FCL 1 is input as the control signal CTL3_D of the driving signal output circuit 233_1 illustrated in FIG. 13.
  • the clock signal GCLK1 is input as the control signal CTL3_D of the driving signal output circuit 233_2.
  • the signal SCOUT of the driving signal output circuit 233_Z,-2 is input as the control signal CTL3_D of the driving signal output circuit 233_I.
  • the clock signal FCLK2 is input as the control signal CTL4_D of the driving signal output circuit 233_1.
  • the clock signal GCLK2 is input as the control signal CTL4_D of the driving signal output circuit 233_2.
  • the signal RCOUT of the driving signal output circuit 233_Z-2 is input as the control signal CTL4_D of the driving signal output circuit 233_L.
  • the duty ratio of each of the clock signals CLKl to CLK4 is 25 %, and the clock signals CLK l to CLK4 are sequentially delayed by a quarter of one cycle period.
  • the duty ratio of each of the clock signasl FCL 1 , FCLK2, GCLK 1 , and GCLK2 is 50 %.
  • the clock signal FCLK1 is an inverted signal of the clock signal GCLK 1
  • the clock signal FCLK2 is an inverted signal of the clock signal FCLK1
  • the clock signal GCLK2 is an inverted signal of the clock signal GCLK 1 .
  • a pulse of the start pulse singal SP is input to the shift register 230 and the selection circuit 232_1 in a period T21.
  • a pulse of the pulse signal SROUT_l is input to the selection circuit 232_2 in a period T22
  • a pulse of the pulse signal SROUT_2 is input to the selection circuit 232_3 in a period T23
  • a pulse of a pulse signal SROUT_3 is input to the selection circuit 232_4 in a period T24
  • a pulse of a pulse signal SROUT_4 is input to the selection circuit 232_5 in a period T25.
  • the clock signal FCLK1 is at a low level
  • the clock signal FCLK2 is at a high level
  • the clock signal GCLK 1 is at a high level
  • the clock signal GCLK2 is at a low level.
  • the selection circuit 232_£> outputs the input pulse of the pulse signal SROUT as a pulse of the pulse signal SELOUT2.
  • the selection circuit 232_R outputs the input pulse of the pulse signal SROUT as a pulse of the pulse signal SELOUT1 .
  • the pulse of the pulse signal SELOUT1 is input to the driving signal output circuit 233_R as a pulse of the set signal SIN_D.
  • the potential VDD and the potential VSS are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUTl becomes the potential TCOMH and the potential of the signal DOUT2 becomes the potential VH.
  • the signal DOUTl of the driving signal output circuit 233_2 (the common singal CS_2) becomes the potential TCOMH in the period T22.
  • the signal DOUTl of the driving signal output circuit 233_4 (the common singal CS_4) becomes the potential TCOMH in the period T24.
  • the pulse of the pulse signal SELOUT2 is input to the driving signal output circuit 233_Q as a pulse of the reset signal RJN_D.
  • the driving signal output circuit 233_Q to which the pulse of the reset signal RIN_D is input the potential VSS and the potential VDD are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUTl becomes the potential TCOML and the potential of the signal DOUT2 becomes the potential VL.
  • the signal DOUTl of the driving signal output circuit 233_1 (the common singal CS_1) becomes the potential TCOML in the period T21.
  • the signal DOUTl of the driving signal output circuit 233_3 (the common singal CS_3) becomes the potential TCOML in the period T23.
  • the control signal CTL1 and the control signal CTL2 that are input to the driving signal output circuit 233_R become high level in accordance with the clock signals CL 1 to CLK4, the clock signals FCLK1 and FCLK2, and the clock signals GCL 1 and GCLK2.
  • the potential VDD is written to the driving signal output circuit 233_R, which is data rewriting.
  • the operation in the periods T26 to T29 may be repeated. Accordingly, a change in the potential of the data D l can be small until a pulse of the start pulse singal SP is input to the shift register 230 again.
  • a pulse of the start pulse singal SP is input to the shift register 230 and the selection circuit 232_1 again in a period T30.
  • a pulse of the pulse signal SROUT l is input to the selection circuit 232_2 in a period T31
  • a pulse of the pulse signal SROUT_2 is input to the selection circuit 232_3 in a period T32
  • a pulse of the pulse signal SROUT_3 is input to the selection circuit 232_4 in a period T33.
  • the clock signal FCLK1 is at a high level
  • the clock signal FCLK2 is at a low level
  • the clock signal GCL l is at a low level
  • the clock signal GCLK2 is at a high level.
  • the selection circuit 232_g outputs the input pulse of the pulse signal SROUT as a pulse of the pulse signal SELOUT 1.
  • the selection circuit 232_R outputs the input pulse of the pulse signal SROUT as a pulse of the pulse signal SELOUT2.
  • the potential VDD and the potential VSS are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUT1 becomes the potential TCOMH and the potential of the signal DOUT2 becomes the potential VH.
  • the potential VSS and the potential VDD are written as the data Dl and the data D2, respectively. Accordingly, the potential of the signal DOUTl becomes the potential TCOML and the potential of the signal DOUT2 becomes the potential VL.
  • the clock signal FCLK 1 and the clock signal GCLK1 may be the same signal and the clock signal FCLK2 and the clock signal GCL 2 may be the same signal, for example.
  • the signal DOUT1 of the driving signal output circuit_AT is a signal which is formed by shifting the signal DOUT 1 of the driving signal output circuit_/ - l
  • the signal DOUT2 of the driving signal output circuit_K is a signal which is formed by shifting the signal DOUT2 of the driving signal output circuit_ -l .
  • the potential of the other of the pair of electrodes of the liquid crystal element 212 (also referred to as VLC2) becomes the potential TCOML because of the common singal CS_ input through the common signal line CL_M in the pixel circuit 210.
  • the potential of the other of the pair of electrodes of the liquid crystal element 212 is switched no later than the completion of inputting a pulse of the gate signal GS M.
  • the potential of the other of the pair of electrodes of the liquid crystal element 212 may be switched while a pulse of the gate signal GS M is being input.
  • a pulse of the gate signal GS_ is input through the gate signal line GL_ and in the pixel circuit 210, the field-effect transistor 21 1 is turned on.
  • the potential of one of the pair of electrodes of the liquid crystal element 212 (also referred to as a potential VLC 1) is substantially equal to the potential of the data signal DS input through the data signal line DL_N.
  • the potential VLC1 corresponds to a potential +VDATA. Accordingly, a voltage applied between the pair of electrodes of the liquid crystal element 212 is +VDATA-TCOML. Thus, data is written to the pixel circuit 210.
  • the field-effect transistor 21 1 is turned off.
  • the pixel circuit 210 electric charges accumulated at one of the pair of electrodes of the liquid crystal element 212 are held.
  • the alignment of liquid crystal included in the liquid crystal layer is controlled in accordance with a voltage applied between the pair of electrodes of the liquid crystal element 212; thus, the pixel circuit 210 is in a display state.
  • the potential of the other of the pair of electrodes of the liquid crystal element 212 (also referred to as VLC2) becomes the potential TCOMH in the pixel circuit 210.
  • the potential VLC 1 which is the potential of the liquid crystal element 212 is substantially equal to the potential of the data signal DS input through the data signal line DL_N.
  • the potential VLC 1 corresponds to a potential -VDATA. Accordingly, a voltage applied to the pair of electrodes of the liquid crystal element 212 is TCOMH- VDATA.
  • the field-effect transistor 21 1 is turned off.
  • the pixel circuit 210 electric charges accumulated at one of the pair of electrodes of the liquid crystal element 212 are held.
  • the alignment of liquid crystal included in the liquid crystal layer is controlled in accordance with a voltage applied between the pair of electrodes of the liquid crystal element 212; thus, the pixel circuit 210 is in a display state.
  • the polarities of a data signal and a common signal are inverted every frame period, whereby the amplitude of the data signal can be small; accordingly, the amplitude of the gate signal can be small. That is, driving voltage can be lowered, and therefore, power consumption can be reduced.
  • one example of the liquid crystal display device of this embodiment can employ a driving method in which by controlling the potential of a common signal line with a signal line driver circuit, the polarity of the potential of one of a pair of electrodes of each of liquid crystal elements and the polarity of the potential of the other electrode are inverted every frame period in pixel circuits on a row-by-row basis.
  • the signal line driver circuit described in Embodiment 1 is used as a signal line driver circuit for controlling the potential of a common signal line. Accordingly, first data of a latch unit can be rewritten even in a period during which a pulse of a start pulse signal is not input to a shift register. Thus, for example, a change in potential, which is first data, due to leakage current of a field-effect transistor in the driving signal output circuit can be prevented. Therefore, a malfunction of the liquid crystal display device can be suppressed.
  • An example of the liquid crystal display device of this embodiment is a horizontal-electric-field mode liquid crystal display device and includes conductive layers 701 a to 701 c, an insulating layer 702, semiconductor layers 703a and 703b, conductive layers 704a to 704d, an insulating layer 705, a coloring layer 706, an insulating layer 707, structure bodies 708a to 708d, a conductive layer 709, a conductive layer 710, an insulating layer 722, an insulating layer 723, and a liquid crystal layer 750, as illustrated in FIG. 19.
  • the conductive layers 701a to 701c are provided over a plane surface of a substrate 700.
  • the conductive layer 701a is provided in a signal line driver circuit part 800.
  • the conductive layer 701 a has a function as a gate of a field-effect transistor in a signal line driver circuit.
  • the conductive layer 701 b is provided in a pixel circuit part 801.
  • the conductive layer 701b has a function as a gate of a field-effect transistor in a pixel circuit.
  • the conductive layer 701 c is provided in the pixel circuit part 801 .
  • the conductive layer 701 c has a function as the other of a pair of electrodes of a capacitor in the pixel circuit.
  • the insulating layer 702 is provided over the conductive layers 701 a to 701 c.
  • the insulating layer 702 has functions as a gate insulating layer in the field-effect transistor of the signal line driver circuit, a gate insulating layer in the field-effect transistor of the pixel circuit, and a dielectric layer in the capacitor of the pixel circuit.
  • the semiconductor layer 703a overlaps the conductive layer 701 a with the insulating layer 702 laid therebetween.
  • the semiconductor layer 703a has a function as a layer where a channel is formed (also referred to as a channel formation layer) in the field-effect transistor of the signal line driver circuit.
  • the semiconductor layer 703b overlaps the conductive layer 701 b with the insulating layer 702 laid therebetween.
  • the semiconductor layer 703b has a function as a channel formation layer included in the field-effect transistor of the pixel circuit.
  • the conductive layer 704a is electrically connected to the semiconductor layer 703a.
  • the conductive layer 704a has a function as one of a source and a drain of the field-effect transistor of the signal line driver circuit.
  • the conductive layer 704b is electrically connected to the semiconductor layer 703a.
  • the conductive layer 704b has a function as the other of the source and the drain of the field-effect transistor of the signal line driver circuit.
  • the conductive layer 704c is electrically connected to the semiconductor layer
  • the conductive layer 704c has a function as one of a source and a drain of the field-effect transistor of the pixel circuit.
  • the conductive layer 704d is electrically connected to the semiconductor layer 703b.
  • the conductive layer 704d overlaps the conductive layer 701 c with the insulating layer 702 laid therebetween.
  • the conductive layer 704d has a function as the other of the source and the drain of the field-effect transistor of the pixel circuit and one of the pair of electrodes of the capacitor of the pixel circuit.
  • the insulating layer 705 is provided over the semiconductor layers 703a and 703b and the conductive layers 704a to 704d.
  • the insulating layer 705 has a function as an insulating layer for protecting the field-effect transistors (also referred to as a protective insulating layer).
  • the coloring layer 706 is provided over the insulating layer 705.
  • the coloring layer 706 has a function as a color filter.
  • the insulating layer 707 is provided over the insulating layer 705 with the coloring layer 706 laid therebetween.
  • the insulating layer 707 has a function as a planarization layer.
  • the structure bodies 708a to 708d are provided over the insulating layer 707.
  • the alignment of liquid crystal in a liquid crystal element can be efficiently controlled.
  • the conductive layer 709 is provided over the insulating layer 707 and electrically connected to the conductive layer 704d through an opening penetrating the insulating layer 705 and the insulating layer 707.
  • the conductive layer 709 has a comb-shaped portion. A tooth of the comb-shaped portion of the conductive layer 709 is provided over the insulating layer 707 with the structure body 708b or the structure body 708d laid therebetween.
  • the conductive layer 709 has a function as one of the pair of electrodes of the liquid crystal element in the pixel circuit.
  • the conductive layer 710 is provided over the insulating layer 707.
  • the conductive layer 710 has a comb-shaped portion.
  • a tooth of the comb-shaped portion of the conductive layer 710 and the tooth of the comb-shaped portion of the conductive layer 709 are alternately provided in parallel.
  • the tooth of the comb-shaped portion of the conductive layer 710 is provided over the insulating layer 707 with the structure body 708a or 708c laid therebetween.
  • the conductive layer 710 has a function as the other of the pair of electrodes of the liquid crystal element in the pixel circuit.
  • the conductive layers 709 and 710 overlap the coloring layer 706 with the insulating layer 707 laid therebetween.
  • the insulating layer 722 is provided on a plane surface of a substrate 720.
  • the insulating layer 722 has a function as a planarization layer.
  • the insulating layer 723 is provided on a plane surface of the insulating layer 722.
  • the insulating layer 723 has a function as a protective insulating layer.
  • the liquid crystal layer 750 is provided over the conductive layers 709 and
  • the field-effect transistor may be a channel-stop field-effect transistor or a top-gate field-effect transistor.
  • a glass substrate or a plastic substrate, for example, can be used as each of the substrates 700 and 720.
  • a layer formed using a metal material such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, or scandium can be used for the conductive layers 701a to 701c.
  • the conductive layers 701 a to 701 c can also be formed by stacking layers of materials which can be applied to the conductive layers 701a to 701c.
  • the insulating layer 702 can be, for example, a layer including a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide.
  • the insulating layer 702 can also be formed by stacking layers of materials which can be applied to the insulating layer 702.
  • each of the semiconductor layers 703a and 703b for example, it is possible to use an oxide semiconductor layer or a semiconductor layer containing a semiconductor which belongs to Group 14 (e.g., silicon).
  • Group 14 e.g., silicon
  • a semiconductor layer including an oxide semiconductor can be single crystal, polycrystalline (also referred to as polycrystal), or amorphous, for example.
  • metal oxide including zinc and one or both of indium and gallium, metal oxide including another metal element instead of part or all of gallium in the given metal oxide, or the like can be given.
  • In-based metal oxide Zn-based metal oxide, In-Zn-based metal oxide, In-Ga-Zn-based metal oxide, or the like can be used as the metal oxide.
  • metal oxide including another metal element instead of part or all of Ga (gallium) in the In-Ga-Zn-based metal oxide may be used.
  • a metal element that can be bound to oxygen atoms more than gallium can be used; for example, one or more of titanium, zirconium, hafnium, germanium, and tin, or the like can be used. Further, as another metal element, one or more of lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium, or the like can be also used. The above metal elements each have a function as a stabilizer. Note that the amount of the metal element is the amount at which the metal oxide can serve as a semiconductor. A metal element that can be bound to oxygen atoms more than gallium is used and oxygen is supplied to the metal oxide, whereby oxygen vacancies in the metal oxide can be reduced. [0292]
  • In-Sn-Zn-based metal oxide is obtained.
  • titanium is used instead of part of Ga (gallium) contained in the In-Ga-Zn-based metal oxide, In-Ti-Ga-Zn-based metal oxide is obtained.
  • the oxide semiconductor layer may be an oxide semiconductor layer including CAAC-OS (c-axis aligned crystalline oxide semiconductor).
  • the crystal amorphous mixed phase structure includes crystal parts in an amorphous phase and is not a completely single crystal structure or a completely amorphous Structure.
  • a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS is formed or a normal vector of a surface of the CAAC-OS, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis.
  • a simple term "perpendicular” includes a range from 85° to 95°.
  • a simple term “parallel” includes a range from -5° to 5°.
  • a change in electric characteristics due to irradiation with visible light or ultraviolet light can be reduced; thus, the transistor has high reliability.
  • an oxide semiconductor layer is used as the semiconductor layers 703a and 703b
  • dehydration or dehydrogenation is performed; thus, impurities such as hydrogen, water, a hydroxyl group, and a hydride (also referred to as hydrogen compound) are removed from the oxide semiconductor layer, and in addition, oxygen is supplied to the oxide semiconductor layer.
  • a layer containing oxygen is used as the layer in contact with the oxide semiconductor layer, and heat treatment is performed; thus, the oxide semiconductor layer can be highly purified.
  • heat treatment is performed at a temperature higher than or equal to 350 °C and lower than the strain point of the substrate, preferably higher than or equal to 350 °C and lower than or equal to 450 °C. Heat treatment may be further performed in a later step.
  • a heat treatment apparatus for the heat treatment for example, an electric furnace or an apparatus for heating an object by heat conduction or heat radiation from a heater such as a resistance heater can be used; for example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used.
  • RTA rapid thermal annealing
  • GRTA gas rapid thermal annealing
  • LRTA lamp rapid thermal annealing
  • a high-purity oxygen gas, a high-purity N 2 0 gas, or ultra-dry air having a dew point -40 °C or lower, preferably -60 °C or lower
  • the oxygen gas or the N2O gas do not contain water, hydrogen, and the like.
  • the purity of the oxygen gas or the N 2 0 gas which is introduced into the heat treatment apparatus is preferably equal to or more than 6N, more preferably equal to or more than 7N (i.e., the impurity concentration of the oxygen gas or the N 2 0 gas is preferably equal to or lower than 1 ppm, more preferably equal to or lower than 0.1 ppm).
  • the introduction of a high-purity oxygen gas, a high-purity N 2 0 gas, or ultra-dry air may be performed at the time of the above heat treatment.
  • the carrier density of the oxide semiconductor layer can be lower than 1 x 10 14 /cm 3 , preferably lower than 1 ⁇ 10 12 /cm 3 , further preferably lower than 1 x l O" /cm 3 .
  • the off-state current of the field-effect transistor per micrometer of channel width can be 10 aA (1 x 10 -1 7 A) or less, 1 aA (1 x 10 ⁇ 1 8 A) or less, 10 zA (1 x 10 ⁇ 20 A) or less, further 1 zA (1 x 10 -21 A) or less, and furthermore 100 yA ( 1 x 10 ⁇ 22 A) or less. It is preferable that the off-state current of the field-effect transistor be as low as possible; the lower limit of the off-state current of the field-effect transistor in this embodiment is estimated to be about 10°° ⁇ / ⁇ .
  • a layer formed using a metal material such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, or ruthenium can be used for the conductive layers 704a to 704d.
  • the conductive layers 704a to 704d can also be formed by stacking layers whose materials can be applied to the conductive layers 704a to 704d.
  • the insulating layer 705 can be an oxide insulating layer containing silicon oxide, aluminum oxide, hafnium oxide, or the like.
  • the coloring layer 706 can be a layer which includes dye or pigment, for example, and which transmits light with the wavelength range of red, light with the wavelength range of green, and light with the wavelength range of blue.
  • the coloring layer 706 can be a layer which includes dye or pigment, for example, and which transmits light with the wavelength range of cyan, magenta, or yellow.
  • Each of the insulating layers 707 and 722 can be a layer of an organic insulating material or an inorganic insulating material, for example.
  • the structure bodies 708a to 708d can be formed using an organic insulating material or an inorganic insulating material, for example.
  • the conductive layer 709 can be a layer of metal oxide which transmits light, for example.
  • metal oxide including indium, or the like can be used.
  • the conductive layer 709 can also be formed by stacking layers whose materials can be applied to the conductive layer 709.
  • the conductive layer 710 can be a layer of metal oxide through which light passes, for example.
  • metal oxide including indium or the like can be used.
  • the conductive layer 710 can also be formed by stacking layers whose materials can be applied to the conductive layer 710.
  • the insulating layer 723 can be, for example, a layer including a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide.
  • the liquid crystal layer 750 can be a layer including liquid crystal exhibiting a blue phase, for example.
  • a layer including liquid crystal exhibiting a blue phase contains a liquid crystal composition including liquid crystal exhibiting a blue phase, a chiral agent, a liquid-crystalline monomer, a non-liquid-crystalline monomer, and a polymerization initiator.
  • the liquid crystal exhibiting a blue phase has a short response time, and has optical isotropy that contributes to the exclusion of the alignment process and reduction of viewing angle dependence. Therefore, with the liquid crystal exhibiting a blue phase, the operation speed can be increased.
  • the liquid crystal composition can be a composition shown in Table 1, for example.
  • Table 1 As mixture ratios between the liquid crystal materials, the mixture ratio between the liquid crystal and the chiral agent; the mixture ratio between the liquid crystal and the chiral agent, the liquid-crystalline monomer, and the non-liquid-crystalline monomer; and the mixture ratio of the liquid crystal, the chiral agent, the liquid-crystalline monomer, and the non-liquid-crystalline monomer to the polymerization initiator are shown.
  • Liquid Crystal 30 90.5 92 99.8
  • CPP-3FF is an abbreviation of 4-(trans-4-n-propylcyclohexyl)-3',4'-difluoro- l,r-biphenyl.
  • PEP-5CNF is an abbreviation of 4-n-pentylbenzoic acid 4-cyano-3-fluorophenyl.
  • PEP-5FCNF is an abbreviation of 4-rc-pentylbenzoic acid 4-cyano-3,5-difluorophenyl ester.
  • ISO-(60BA) 2 is an abbreviation of l ,4:3,6-dianhydro-2,5-bis[4-(rc-hexyl-l -oxy)benzoic acidjsorbitol.
  • RM257-06 is an abbreviation of l ,4-bis-[4-(6-acryloyloxy-n-hexyl-l -oxy)benzoyloxy]-2-methylbenzene.
  • DMeAc is an abbreviation of «-dodecyl methacrylate.
  • DMPAP is an abbreviation of 2,2-dimethoxy-2-phenylacetophenone.
  • a liquid crystal composition can also be a composition shown in Table 2, for example..
  • CPEP-5FCNF is an abbreviation of 4-(trans-4-/7-pentylcyclohexyl)benzoic acid 4-cyano-3,5-difluorophenyl ester.
  • PEP-3FCNF is an abbreviation of 4-cyano-3,5-difluorophenyl 4- «-propylbenzoate.
  • R-DOL-Pn is an abbreviation of
  • a liquid crystal composition can also be a composition shown in Table 3, for example.
  • PPEP-5FCNF is an abbreviation of 4-(4-n-pentylphenyl)benzoic acid 4-cyano-3,5-difluorophenyl.
  • a signal line driver circuit is provided over the same substrate as a pixel circuit, as described with reference to FIG. 19.
  • the number of wirings for connecting the pixel circuit and the signal line driver circuit can be reduced.
  • a liquid crystal element is formed using liquid crystal exhibiting a blue phase, which results in higher operation speed of the liquid crystal display device.
  • FIGS. 20A to 20D are schematic diagrams of structural examples of the electronic device of this embodiment.
  • An electronic device illustrated in FIG. 20A is an example of a personal digital assistant.
  • the digital assistant illustrated in FIG. 20A has a housing 1011 and a panel 1012 and a button 1013 that are provided for the housing 101 1.
  • the housing 101 1 may be provided with a connection terminal for connecting the electronic device illustrated in FIG. 20A to an external device and/or a button used to operate the electronic device illustrated in FIG. 20A.
  • the panel 1012 has a function as a display panel.
  • the panel 1012 can be the liquid crystal display device in Embodiments 2 and
  • the panel 1012 may have a function as a touch panel.
  • data may be input in such a manner that an image of a keyboard is displayed on the panel 1012 and then touched with a finger.
  • the button 1013 is provided for the housing 1011 .
  • the electronic device can be turned on or off by pressing the button 1013.
  • the electronic device illustrated in FIG. 20A has functions as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.
  • An electronic device illustrated in FIG. 20B is an example of a folding digital assistant.
  • the electronic device illustrated in FIG. 20B has a housing 1021 a, a housing 1021 b, a panel 1022a provided for the housing 1021a, a panel 1022b provided for the housing 1021 b, a hinge 1023, a button 1024, a connection terminal 1025, and a storage media inserting portion 1026.
  • the housing 1021 a and the housing 1021 b are connected by the hinge 1023.
  • the panels 1022a and 1022b each have a function as a display panel.
  • the panels 1022a and 1022b may display different images or one image.
  • the electronic device illustrated in FIG. 20B may be operated in a state where the panels 1022a and 1022b are arranged vertically or horizontally.
  • the panels 1022a and 1022b can be the liquid crystal display device in Embodiments 2 and 3.
  • one or both of the panels 1022a and 1022b may have a function as a touch panel.
  • data may be input in such a manner that art image of a keyboard is displayed on one or both of the panels 1022a and 1022b and then touched with a finger.
  • the housing 1021a or the housing 1021b can be moved to overlap the housing 1021a with the housing 1021b, for example; that is, the electronic device can fold.
  • the button 1024 is provided for the housing 1021 b. Note that the housing 1021 a may also be provided with the button 1024. For example, when the button 1024 which has a function as a power button is provided and pushed, whether power is supplied to circuits in the electronic device can be controlled.
  • connection terminal 1025 is provided for the housing 1021 a.
  • the housing 1021 b may be provided with the connection terminal 1025.
  • a plurality of connection terminals 1025 may be provided on one or both of the housings 1021a and the housing 1021 b.
  • the connection terminal 1025 is a terminal for connecting the electronic device illustrated in FIG. 20B to another device.
  • the storage media inserting portion 1026 is provided for the housing 1021a. Note that the storage medium insertion portion 1026 may be provided on the housing 1021 b. Alternatively, the plurality of recording medium insertion portions 1026 may be provided for one or both of the housings 1021 a and 1021 b. For example, a card-type recording medium is inserted into the storage media inserting portion so that data can be read to the electronic device from the card-type recording medium or data stored in the electronic device can be written to the card-type recording medium.
  • the electronic device illustrated in FIG. 20B has functions as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.
  • FIG. 20C An electronic device illustrated in FIG. 20C is an example of a stationary digital assistant.
  • the stationary digital assistant illustrated in FIG. 20C has a housing 1031, and a panel 1032 and a button 1033 that are provided for the housing 1031 .
  • the panel 1032 has functions as a display panel and a touch panel.
  • the panel 1032 can be provided for a deck portion 1034 of the housing 1031.
  • the panel 1032 can be the liquid crystal display device in Embodiments 2 and
  • the housing 1031 may be provided with one or more of a ticket slot from which a ticket or the like is dispensed, a coin slot, and a bill slot.
  • the button 1033 is provided for the housing 1031. For example, when the button 1033 which has a function as a power button is provided and pushed, whether power is supplied to circuits in the electronic device can be controlled.
  • the electronic device illustrated in FIG. 20C has, for example, a function as an automated teller machine, an information communication terminal for ordering a ticket or the like (also referred to as a multi-media station), or a game machine.
  • FIG. 20D illustrates an example of a stationary digital assistant.
  • the electronic device illustrated in FIG. 20D has a housing 1041 , a panel 1042 provided for the housing 1041 , a button 1044, and a connection terminal 1045, and a support base 1043 supporting the housing 1041 .
  • connection terminal for connecting the housing 1041 to an external device and/or a button used to operate the electronic device illustrated in FIG. 20D may be provided.
  • the panel 1042 has a function as a display panel.
  • the panel 1042 may have a function as a touch panel.
  • the panel 1042 can be the liquid crystal display device in Embodiments 2 and
  • the button 1044 is provided for the housing 1041 .
  • the button 1044 which has a function as a power button is provided and pushed, whether power is supplied to circuits in the electronic device can be controlled.
  • the connection terminal 1045 is provided for the housing 1041.
  • the connection terminal 1045 is a terminal for connecting the electronic device illustrated in FIG. 20D to another device.
  • connecting the electronic device illustrated in FIG. 20D and a personal computer with the connection terminal 1045 enables the panel 1042 to display an image corresponding to a data signal input from the personal computer.
  • a displayed image of the electronic device can be enlarged, in which case a plurality of viewers can recognize the image at the same time with ease.
  • the electronic device illustrated in FIG. 20D has, for example, a function as a digital photo frame, an output monitor, a personal computer, or a television set.
  • provision of a panel having the liquid crystal display device of the above embodiments enhances operation speed of the panel. Accordingly, for example, an electronic device that can operate (e.g., reproduce a moving image) at high speed can be provided.
  • 101 shift register; 1 12: selection circuit; 1 13 : driving signal output circuit; 121 : latch unit; 122: buffer unit; 123 : buffer unit; 124: switch unit; 131 a: latch unit; 131 b: latch unit; 132a: buffer unit; 132b: buffer unit; 133a to 133d: switch unit; 134: buffer unit; 201 : signal line driver circuit; 202: signal line driver circuit; 203 : signal line driver circuit; 204: signal line driver circuit; 210: pixel circuit; 211 : field-effect transistor; 212: liquid crystal element; 213: capacitor; 230: shift register; 231 : pulse output circuit; 232: selection circuit; 233: driving signal output circuit; 31 1 to 319: field-effect transistor; 321 : capacitor; 322: capacitor; 331 to 336: field-effect transistor; 351 to 364: field-effect transistor; 371 : capacitor; 372: capacitor; 431 to 444: field-effect transistor; 451 : capacitor

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  • Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11137813B2 (en) 2014-03-14 2021-10-05 Semiconductor Energy Laboratory Co., Ltd. Analog arithmetic circuit, semiconductor device, and electronic device
US12581741B2 (en) 2014-02-21 2026-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6830765B2 (ja) 2015-06-08 2021-02-17 株式会社半導体エネルギー研究所 半導体装置
JP7050460B2 (ja) 2016-11-22 2022-04-08 株式会社半導体エネルギー研究所 表示装置
CN112955946B (zh) 2018-11-09 2025-05-02 株式会社半导体能源研究所 显示装置及电子设备
TWI714365B (zh) * 2019-03-07 2020-12-21 友達光電股份有限公司 移位暫存器與電子裝置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303769A1 (en) * 2007-06-07 2008-12-11 Mitsubishi Electric Corporation Image display device and drive circuit
US20090225063A1 (en) * 2008-03-05 2009-09-10 Takumi Shigaki Display device
US20100245724A1 (en) * 2009-03-26 2010-09-30 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and method for manufacturing the same

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198861A (ja) 1984-03-23 1985-10-08 Fujitsu Ltd 薄膜トランジスタ
JPH0244256B2 (ja) 1987-01-28 1990-10-03 Kagaku Gijutsucho Mukizaishitsu Kenkyushocho Ingazn2o5deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho
JPH0244260B2 (ja) 1987-02-24 1990-10-03 Kagaku Gijutsucho Mukizaishitsu Kenkyushocho Ingazn5o8deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho
JPS63210023A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓４Ｏ↓７で示される六方晶系の層状構造を有する化合物およびその製造法
JPH0244258B2 (ja) 1987-02-24 1990-10-03 Kagaku Gijutsucho Mukizaishitsu Kenkyushocho Ingazn3o6deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho
JPH0244262B2 (ja) 1987-02-27 1990-10-03 Kagaku Gijutsucho Mukizaishitsu Kenkyushocho Ingazn6o9deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho
JPH0244263B2 (ja) 1987-04-22 1990-10-03 Kagaku Gijutsucho Mukizaishitsu Kenkyushocho Ingazn7o10deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho
JPH05251705A (ja) 1992-03-04 1993-09-28 Fuji Xerox Co Ltd 薄膜トランジスタ
JP3479375B2 (ja) 1995-03-27 2003-12-15 科学技術振興事業団 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法
WO1997006554A2 (en) 1995-08-03 1997-02-20 Philips Electronics N.V. Semiconductor device provided with transparent switching element
JP3625598B2 (ja) 1995-12-30 2005-03-02 三星電子株式会社 液晶表示装置の製造方法
US7196699B1 (en) * 1998-04-28 2007-03-27 Sharp Kabushiki Kaisha Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power
JP4170454B2 (ja) 1998-07-24 2008-10-22 Ｈｏｙａ株式会社 透明導電性酸化物薄膜を有する物品及びその製造方法
JP2000150861A (ja) 1998-11-16 2000-05-30 Tdk Corp 酸化物薄膜
JP3276930B2 (ja) 1998-11-17 2002-04-22 科学技術振興事業団 トランジスタ及び半導体装置
TW460731B (en) 1999-09-03 2001-10-21 Ind Tech Res Inst Electrode structure and production method of wide viewing angle LCD
US6856307B2 (en) * 2000-02-01 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and method of driving the same
JP3813463B2 (ja) * 2000-07-24 2006-08-23 シャープ株式会社 液晶表示装置の駆動回路及びそれを用いた液晶表示装置並びにその液晶表示装置を用いた電子機器
JP4089858B2 (ja) 2000-09-01 2008-05-28 国立大学法人東北大学 半導体デバイス
KR20020038482A (ko) 2000-11-15 2002-05-23 모리시타 요이찌 박막 트랜지스터 어레이, 그 제조방법 및 그것을 이용한표시패널
JP3997731B2 (ja) 2001-03-19 2007-10-24 富士ゼロックス株式会社 基材上に結晶性半導体薄膜を形成する方法
JP2002289859A (ja) 2001-03-23 2002-10-04 Minolta Co Ltd 薄膜トランジスタ
JP2003076332A (ja) * 2001-08-31 2003-03-14 Sanyo Electric Co Ltd 表示パネルの駆動回路
JP3925839B2 (ja) 2001-09-10 2007-06-06 シャープ株式会社 半導体記憶装置およびその試験方法
JP4090716B2 (ja) 2001-09-10 2008-05-28 雅司 川崎 薄膜トランジスタおよびマトリクス表示装置
US7061014B2 (en) 2001-11-05 2006-06-13 Japan Science And Technology Agency Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
JP4164562B2 (ja) 2002-09-11 2008-10-15 独立行政法人科学技術振興機構 ホモロガス薄膜を活性層として用いる透明薄膜電界効果型トランジスタ
JP4083486B2 (ja) 2002-02-21 2008-04-30 独立行政法人科学技術振興機構 ＬｎＣｕＯ（Ｓ，Ｓｅ，Ｔｅ）単結晶薄膜の製造方法
US7049190B2 (en) 2002-03-15 2006-05-23 Sanyo Electric Co., Ltd. Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
JP3933591B2 (ja) 2002-03-26 2007-06-20 淳二 城戸 有機エレクトロルミネッセント素子
US7339187B2 (en) 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
JP2004022625A (ja) 2002-06-13 2004-01-22 Murata Mfg Co Ltd 半導体デバイス及び該半導体デバイスの製造方法
US7105868B2 (en) 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
US7067843B2 (en) 2002-10-11 2006-06-27 E. I. Du Pont De Nemours And Company Transparent oxide semiconductor thin film transistors
JP4166105B2 (ja) 2003-03-06 2008-10-15 シャープ株式会社 半導体装置およびその製造方法
JP2004273732A (ja) 2003-03-07 2004-09-30 Sharp Corp アクティブマトリクス基板およびその製造方法
JP4108633B2 (ja) 2003-06-20 2008-06-25 シャープ株式会社 薄膜トランジスタおよびその製造方法ならびに電子デバイス
JP4393812B2 (ja) * 2003-07-18 2010-01-06 株式会社半導体エネルギー研究所 表示装置及び電子機器
US7262463B2 (en) 2003-07-25 2007-08-28 Hewlett-Packard Development Company, L.P. Transistor including a deposited channel region having a doped portion
US7145174B2 (en) 2004-03-12 2006-12-05 Hewlett-Packard Development Company, Lp. Semiconductor device
KR20070116888A (ko) 2004-03-12 2007-12-11 도꾸리쯔교세이호징 가가꾸 기쥬쯔 신꼬 기꼬 아몰퍼스 산화물 및 박막 트랜지스터
US7297977B2 (en) 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
US7282782B2 (en) 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
US7211825B2 (en) 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
EP1622111A1 (en) * 2004-07-28 2006-02-01 Deutsche Thomson-Brandt Gmbh Line driver circuit for active matrix display device
JP2006100760A (ja) 2004-09-02 2006-04-13 Casio Comput Co Ltd 薄膜トランジスタおよびその製造方法
US7285501B2 (en) 2004-09-17 2007-10-23 Hewlett-Packard Development Company, L.P. Method of forming a solution processed device
US7298084B2 (en) 2004-11-02 2007-11-20 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
CA2585063C (en) 2004-11-10 2013-01-15 Canon Kabushiki Kaisha Light-emitting device
US7791072B2 (en) 2004-11-10 2010-09-07 Canon Kabushiki Kaisha Display
EP2453481B1 (en) 2004-11-10 2017-01-11 Canon Kabushiki Kaisha Field effect transistor with amorphous oxide
US7829444B2 (en) 2004-11-10 2010-11-09 Canon Kabushiki Kaisha Field effect transistor manufacturing method
BRPI0517560B8 (pt) 2004-11-10 2018-12-11 Canon Kk transistor de efeito de campo
US7453065B2 (en) 2004-11-10 2008-11-18 Canon Kabushiki Kaisha Sensor and image pickup device
US7863611B2 (en) 2004-11-10 2011-01-04 Canon Kabushiki Kaisha Integrated circuits utilizing amorphous oxides
US7579224B2 (en) 2005-01-21 2009-08-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film semiconductor device
TWI505473B (zh) 2005-01-28 2015-10-21 半導體能源研究所股份有限公司 半導體裝置，電子裝置，和半導體裝置的製造方法
US7608531B2 (en) 2005-01-28 2009-10-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and method of manufacturing semiconductor device
US7858451B2 (en) 2005-02-03 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
US7948171B2 (en) 2005-02-18 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20060197092A1 (en) 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
US8681077B2 (en) 2005-03-18 2014-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device, driving method and electronic apparatus thereof
WO2006105077A2 (en) 2005-03-28 2006-10-05 Massachusetts Institute Of Technology Low voltage thin film transistor with high-k dielectric material
JP4896420B2 (ja) 2005-03-30 2012-03-14 株式会社 日立ディスプレイズ 表示装置
US7645478B2 (en) 2005-03-31 2010-01-12 3M Innovative Properties Company Methods of making displays
US8300031B2 (en) 2005-04-20 2012-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element
JP2006344849A (ja) 2005-06-10 2006-12-21 Casio Comput Co Ltd 薄膜トランジスタ
US7402506B2 (en) 2005-06-16 2008-07-22 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7691666B2 (en) 2005-06-16 2010-04-06 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7507618B2 (en) 2005-06-27 2009-03-24 3M Innovative Properties Company Method for making electronic devices using metal oxide nanoparticles
KR100711890B1 (ko) 2005-07-28 2007-04-25 삼성에스디아이 주식회사 유기 발광표시장치 및 그의 제조방법
JP2007059128A (ja) 2005-08-23 2007-03-08 Canon Inc 有機ｅｌ表示装置およびその製造方法
JP2007073705A (ja) 2005-09-06 2007-03-22 Canon Inc 酸化物半導体チャネル薄膜トランジスタおよびその製造方法
JP4280736B2 (ja) 2005-09-06 2009-06-17 キヤノン株式会社 半導体素子
JP5116225B2 (ja) 2005-09-06 2013-01-09 キヤノン株式会社 酸化物半導体デバイスの製造方法
JP4850457B2 (ja) 2005-09-06 2012-01-11 キヤノン株式会社 薄膜トランジスタ及び薄膜ダイオード
EP3614442A3 (en) 2005-09-29 2020-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor layer and manufactoring method thereof
JP5037808B2 (ja) 2005-10-20 2012-10-03 キヤノン株式会社 アモルファス酸化物を用いた電界効果型トランジスタ、及び該トランジスタを用いた表示装置
KR20090115222A (ko) 2005-11-15 2009-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 제조방법
TWI292281B (en) 2005-12-29 2008-01-01 Ind Tech Res Inst Pixel structure of active organic light emitting diode and method of fabricating the same
US7867636B2 (en) 2006-01-11 2011-01-11 Murata Manufacturing Co., Ltd. Transparent conductive film and method for manufacturing the same
JP4977478B2 (ja) 2006-01-21 2012-07-18 三星電子株式会社 ＺｎＯフィルム及びこれを用いたＴＦＴの製造方法
US7576394B2 (en) 2006-02-02 2009-08-18 Kochi Industrial Promotion Center Thin film transistor including low resistance conductive thin films and manufacturing method thereof
US7977169B2 (en) 2006-02-15 2011-07-12 Kochi Industrial Promotion Center Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof
KR20070101595A (ko) 2006-04-11 2007-10-17 삼성전자주식회사 ＺｎＯ ＴＦＴ
US20070252928A1 (en) 2006-04-28 2007-11-01 Toppan Printing Co., Ltd. Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof
JP5028033B2 (ja) 2006-06-13 2012-09-19 キヤノン株式会社 酸化物半導体膜のドライエッチング方法
JP4609797B2 (ja) 2006-08-09 2011-01-12 Ｎｅｃ液晶テクノロジー株式会社 薄膜デバイス及びその製造方法
JP4999400B2 (ja) 2006-08-09 2012-08-15 キヤノン株式会社 酸化物半導体膜のドライエッチング方法
KR101277975B1 (ko) * 2006-09-07 2013-06-27 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 구비한 데이터 드라이버,액정표시장치
JP4332545B2 (ja) 2006-09-15 2009-09-16 キヤノン株式会社 電界効果型トランジスタ及びその製造方法
JP4274219B2 (ja) 2006-09-27 2009-06-03 セイコーエプソン株式会社 電子デバイス、有機エレクトロルミネッセンス装置、有機薄膜半導体装置
JP5164357B2 (ja) 2006-09-27 2013-03-21 キヤノン株式会社 半導体装置及び半導体装置の製造方法
US7622371B2 (en) 2006-10-10 2009-11-24 Hewlett-Packard Development Company, L.P. Fused nanocrystal thin film semiconductor and method
US7772021B2 (en) 2006-11-29 2010-08-10 Samsung Electronics Co., Ltd. Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
JP2008140684A (ja) 2006-12-04 2008-06-19 Toppan Printing Co Ltd カラーｅｌディスプレイおよびその製造方法
KR101303578B1 (ko) 2007-01-05 2013-09-09 삼성전자주식회사 박막 식각 방법
US8207063B2 (en) 2007-01-26 2012-06-26 Eastman Kodak Company Process for atomic layer deposition
KR100851215B1 (ko) 2007-03-14 2008-08-07 삼성에스디아이 주식회사 박막 트랜지스터 및 이를 이용한 유기 전계 발광표시장치
US7795613B2 (en) 2007-04-17 2010-09-14 Toppan Printing Co., Ltd. Structure with transistor
KR101325053B1 (ko) 2007-04-18 2013-11-05 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
KR20080094300A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법과 박막 트랜지스터를포함하는 평판 디스플레이
KR101334181B1 (ko) 2007-04-20 2013-11-28 삼성전자주식회사 선택적으로 결정화된 채널층을 갖는 박막 트랜지스터 및 그제조 방법
CN101663762B (zh) 2007-04-25 2011-09-21 佳能株式会社 氧氮化物半导体
KR101345376B1 (ko) 2007-05-29 2013-12-24 삼성전자주식회사 ＺｎＯ 계 박막 트랜지스터 및 그 제조방법
JP2009015286A (ja) * 2007-06-07 2009-01-22 Mitsubishi Electric Corp 画像表示装置及び駆動回路
JP5215158B2 (ja) 2007-12-17 2013-06-19 富士フイルム株式会社 無機結晶性配向膜及びその製造方法、半導体デバイス
WO2009130919A1 (ja) * 2008-04-23 2009-10-29 シャープ株式会社 アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機
JP4623179B2 (ja) 2008-09-18 2011-02-02 ソニー株式会社 薄膜トランジスタおよびその製造方法
JP5451280B2 (ja) 2008-10-09 2014-03-26 キヤノン株式会社 ウルツ鉱型結晶成長用基板およびその製造方法ならびに半導体装置
US8395740B2 (en) 2009-01-30 2013-03-12 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device having blue phase liquid crystal and particular electrode arrangement
TWI604594B (zh) * 2009-08-07 2017-11-01 半導體能源研究所股份有限公司 半導體裝置及包括該半導體裝置之電話、錶、和顯示裝置
JP5649858B2 (ja) * 2009-10-23 2015-01-07 京セラディスプレイ株式会社 液晶表示装置、液晶表示パネルの駆動装置および液晶表示パネル

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303769A1 (en) * 2007-06-07 2008-12-11 Mitsubishi Electric Corporation Image display device and drive circuit
US20090225063A1 (en) * 2008-03-05 2009-09-10 Takumi Shigaki Display device
US20100245724A1 (en) * 2009-03-26 2010-09-30 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12581741B2 (en) 2014-02-21 2026-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
US11137813B2 (en) 2014-03-14 2021-10-05 Semiconductor Energy Laboratory Co., Ltd. Analog arithmetic circuit, semiconductor device, and electronic device

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