WO2013053420A1 - Leistungshalbleiterchip mit metallischen formkörpern zum kontaktieren mit dickdrähten oder bändchen sowie verfahren zu dessen herstellung - Google Patents

Leistungshalbleiterchip mit metallischen formkörpern zum kontaktieren mit dickdrähten oder bändchen sowie verfahren zu dessen herstellung Download PDF

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Publication number
WO2013053420A1
WO2013053420A1 PCT/EP2012/003787 EP2012003787W WO2013053420A1 WO 2013053420 A1 WO2013053420 A1 WO 2013053420A1 EP 2012003787 W EP2012003787 W EP 2012003787W WO 2013053420 A1 WO2013053420 A1 WO 2013053420A1
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WIPO (PCT)
Prior art keywords
power semiconductor
semiconductor chip
shaped body
potential
layer
Prior art date
Application number
PCT/EP2012/003787
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English (en)
French (fr)
Inventor
Martin Becker
Ronald Eisele
Frank Osterwald
Jacek Rudzki
Original Assignee
Danfoss Silicon Power Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Priority to CN201280050678.XA priority Critical patent/CN103890924B/zh
Priority to JP2014533780A priority patent/JP5837697B2/ja
Priority to US14/346,458 priority patent/US9318421B2/en
Priority to EP12769904.9A priority patent/EP2766922A1/de
Publication of WO2013053420A1 publication Critical patent/WO2013053420A1/de
Priority to US15/095,802 priority patent/US9613929B2/en

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Definitions

  • the invention relates to a power semiconductor chip having at least one upper-side potential surface.
  • Power modules typically consist of several semiconductors, many of which, e.g. Diodes are flowed perpendicular to the chip surface of the load current.
  • the underside of the semiconductor is contacted with a solder joint or partially also with a sintered or diffusion-brazed joint.
  • the top of the semiconductor has a metallization or metal layer optimized for the bonding process of thick A-aluminum wires.
  • a metallization or metal layer optimized for the bonding process of thick A-aluminum wires.
  • the semiconductors are becoming thinner and thinner to reduce electrical losses.
  • power semiconductors are on the market with only about 70 ⁇ total thickness.
  • Research institutes have already been able to submit the first extreme wafer densities down to 1 ⁇ .
  • a major influence on the limitation of the service life of a power module is the chip-side chip contacting.
  • a very robust sintered connection on the underside of a chip only leads to a small increase in module lifetime, since the failure of the aluminum wires on the top of the semiconductor is the limiting factor.
  • Al bonding technology has been established in power electronics production lines for many years. Continuous optimization of the bonding process has increased the expected lifetime of this compound. However, this high level is approximately at the physical limit of the load capacity of an aluminum weld joint, so that large life-expectancy steps can only be realized by new concepts in packaging and assembly (AVT). This need is also reinforced by the fact that the sintering technology on the bottom side of the semiconductor already shows a double-digit increase in lifetime expectancy (relative to soldering technology).
  • the invention now seeks to improve the life of a power module, in particular of the power semiconductor chip, by improving the contacts on the top potential surface (s). At the same time, the yield is to be increased by a more stable and less fractured training.
  • the thin layers or shaped bodies form a mechanical protection of the surfaces, in particular over the potential surfaces, for example in force-fitting contacting test methods (high-current tests at the wafer level).
  • This enables reliable electrical testing of the semiconductors before the top-side contacting of the semiconductor has been realized.
  • the surface of the metallic layer which is materially bonded to the semiconductor, is contacted with special spring tools, without the risk of destroying the fine surface structures of the semiconductor.
  • FIG. 1 is a schematic perspective overall and a detailed view of a power semiconductor chip with upper contacting according to the invention
  • Fig. 2 is a plan view of the molded body held on a carrier layer
  • Fig; 3 is a schematic view along a section in the line from a to a in FIG. 2.
  • the power semiconductor chip 10 according to the invention with top potential surfaces preferably has at least one electrically conductive shaped body 24, 25 covering a potential surface.
  • the shaped body 24 is shown as a layer layer surrounding a further shaped body 25, below which a plurality of potential areas may lie, which may then be joined to the layer, for example four in the corner areas, or even two opposite ones, as it is the sectional view indicates. Also, the case that even the potential surface of the power semiconductor chip 10 almost has the annular shape of the layer is not excluded.
  • the power semiconductor chip 10 has potential surfaces on the upper side, onto which the molded bodies are preferably provided with good electrical and thermal conductivity (consisting of Cu, Ag, Au, Al, Mo, W and their alloys).
  • the moldings will be about 30 ⁇ to 300 ⁇ strong. Both thin semiconductors in the range of 30 ⁇ moldings between 30 ⁇ and 40 ⁇ , as well as for thicker semiconductor chips of 150 ⁇ - 200 ⁇ correspondingly slightly thicker shaped body between ⁇ and 150 ⁇ thickness in question; Such a shaped body is fastened by means of a bonding layer 1 in low-temperature sintering technology (or diffusion-soldered or glued) on the metallization layer 10b of the semiconductor. The shaped body does not project beyond the dimensions of the power semiconductor chip 10.
  • a further shaped body 30 can be fastened on the underside of the power semiconductor chip 10. It has the same layer thickness as the molded body 24, 25 on the upper side of the power semiconductor chip 10.
  • the connection 2 between the lower molded body 30 and the power semiconductor chip 10 corresponds to the connection technology between the chip and the molded body 24, 25 at the top.
  • each potential surface of the semiconductor e.g., emitter and gate
  • each potential surface of the semiconductor is electrically contacted with the lower surface of the molded body via a connection.
  • an electrical potential of the semiconductor has multiple areas (e.g., so-called gate finger segmented emitter areas), then it is an option to provide a corresponding number of individual moldings.
  • the shaped body can also partially form individual islands 25 (variants 1 and 2), it is advantageous to use a carrier material 20a which ensures the cohesion of the wafer during assembly.
  • This support material could be a temperature-resistant plastic, for example polyamide or polyimide, which withstands both high temperatures and, as an insulator, prevents a flow of current between the different potential surfaces 24, 25.
  • the individual shaped bodies on the potential surfaces 24, 25 consist for example of a thin copper sheet (30-300 ⁇ ), which is coated on the side assigned to the chip with an oxidation-inhibiting protective layer 23 (Ag or Au).
  • the carrier material 20a and the shaped bodies 24, 25 form a common carrier foil with structured fins, ie, for example, the annular fins obtained by etching as in FIG. 2.
  • the upper side of the carrier film 20a can also have a plurality of mold body surfaces which simultaneously cover the potential which is the same on the upper side of the potential surfaces, or moldings which simultaneously cover the same . reflect the electrical contact surfaces 11, 12 of the semiconductor, and which are tightly sintered on them.
  • These shaped bodies are preferably electrically contacted by metallic conductors in the form of wires, strips, wire bundles, braid or fabric strips 50 on the upper side of the individual shaped bodies 24, 25.
  • metallic conductors in the form of wires, strips, wire bundles, braid or fabric strips 50 on the upper side of the individual shaped bodies 24, 25.
  • a preferred embodiment is copper thick wire bonding (eg up to 600 ⁇ m in diameter).
  • FIG. 3 it can be seen how metallic shaped bodies 24, 25 are arranged above the chip potential areas 11, 12, 13. Also underneath the chip 10, a shaped body with a carrier foil with the side facing the chip can be connected over the whole area to the underside of the semiconductor.
  • the surface of the platelet may have an oxidation-protective layer. With the aid of the sintering or diffusion soldering technique, a cohesive connection with the metallization layer 10c on the underside of the semiconductor is ultimately realized.
  • the shaped body can have a layer thickness on the underside of the semiconductor, which generates a balanced mechanical stress in combination with the shaped bodies on the chip top side. This means that after the addition of lower-side plate and upper-side molded body, a very small resulting deformation of the semiconductor is produced.
  • a preferred solution is to make both layers the same thickness and of the same material. This consists either of pure copper, which projects all the way to the chip edges, or of a large framed copper island, which has a very narrow (a few ⁇ ) polyamide film circumferentially, as can be seen in Fig. 2.
  • the top-side contact foil can contact all semiconductor elements of an unsealed wafer composite in multiple juxtaposition. As a result, a particularly low-tolerance coverage of all the conductor surfaces of the contact foil with the potential surfaces of the semiconductor is achieved. This results in a more cost-effective parallel processing compared to the serial assembly of a respective semiconductor element and a single contact foil. After the connection of the wafer-contact foil to the semiconductor wafer by low-temperature sintering, soldering or gluing is a conventional separation z. B. possible by sawing.
  • the advantages of using the power semiconductor chips having at least one upper-side potential surface and contacting thick wires or tapes, with a connection layer on the potential surfaces, and at least one metallic molded body on the connection layer (s), the lower flat side facing the potential surface, and a connection method The compound layer according to coated is formed, and the material composition and thickness of which is selected in accordance with the order of the related thick wires or ribbons on the molding top in the order are the following:
  • the moldings allow a top-side contacting by thick copper wires for thin semiconductor elements.
  • the moldings protect the sensitive thinly metallized surfaces of the semiconductors (typically only about 3-4 ⁇ m) in copper thick-wire bonding.
  • the shaped bodies ensure a better current density distribution over the entire cross section of the chip surface.
  • the moldings protect the sensitive surface structure of the semiconductor during frictional contact by resilient contacts. This facilitates the non-destructive, electrical quality inspection in the production lines.
  • a bottom foil and molded body layer prevents the bowl effect (deformation of the semiconductor element) by symmetrizing the mechanical stresses.
  • Top and bottom carrier foils carry shaped body fields which can cover a whole wafer and thus enable cost-effective and precise parallel occupation of all contact surfaces with moldings.
  • FIG. 1 shows the power semiconductor chip 10 according to the invention, with top potential surfaces 11, 12, 13 (see FIG. 3) of only two potential surfaces 11, 13; 12 covering moldings 24, 25 are electrically and cohesively contacted by a bonding layer 1.
  • the potential surfaces 11 and 13 have the same potential and can therefore be contacted together with an electrically conductive, circumferential guide surface of the shaped body 24, as can be seen approximately square in FIG. 2 with a central recess. Further surfaces to be contacted are possible with a shaping as in FIG. 2 under the entire upper-side extent of the shaped body. They would then be added after applying a compound layer 1 then also the Forrn Sciences 24.
  • a separate mold body 25 is provided on a potential surface 12 of a different potential, for example a gate. Both mold bodies 24, 25 are held on a contact foil 20a, which has passages on the underside in the region of the moldings 24, 25.
  • the molded body or bodies 24, 25 are provided with good electrical and thermal conductivity of metal, for example, the molded body 24, 25 comprises a material of the group Cu, Ag, Au, Al, Mo, W or their alloys, the alloys comprising one or more Metals of the aforementioned group may have.
  • the shaped body 24, 25 will have between 15 ⁇ and 500 ⁇ thickness, preferably 30 ⁇ and 300 ⁇ m. Again advantageous between 75 ⁇ and 150 ⁇ m thickness.
  • thin semiconductors in the range of 30 ⁇
  • moldings between 30 and 40 ⁇ , as well as for thicker semiconductor chips of 150 ⁇ - 200 ⁇ correspondingly thicker shaped body between ⁇ and 150 ⁇ thickness in question.
  • the molded body can fulfill its stabilizing function.
  • molded body thicknesses of one quarter to one half of the wire diameter are proposed.
  • the additional molded body 30 provided on the lower side of the power semiconductor chip 10 next to the upper-side molded body 24, 25 is attached to the power semiconductor chip 10 as well as the upper one by low-temperature sintering technology, diffusion soldering or gluing.
  • connection to be joined has, under each shaped body 24, 25, a smaller projection area than the shaped body 24, 25, leaving an edge of the shaped body which is fixed on an organic non-conductive carrier foil 20a, which in turn rests on the power semiconductor chip 10 can be fixed after accurate application.
  • the carrier film 20a can cover the regions of the chip surface which are not to be joined. It should not extend beyond the outer boundary of the chip.
  • the connecting layer 1 of sintered material in the dimensions is selected to be slightly smaller than both shaped body as potential surface, and still carrier film 20a over the edges of the potential surfaces 3787
  • thermal expansion properties of an upper-side molded article 24, 25 can be compensated for by selecting a dissimilar material and a different thickness for another molded article 30 on the underside of the power semiconductor chip 10 to achieve low resulting total strain.
  • the molding should not reach the edge of the power semiconductor chip 10. This would require elaborate isolation.
  • a proposed method for applying moldings to a power semiconductor chip uses an electrically insulating, the thermal stress during bonding resisting carrier sheet 20a with a number of moldings 24, 25. These are applied simultaneously to the power semiconductor chip before joining, as well as a number of moldings 24, 25 for a plurality of power semiconductor chips 10 for low-tolerance coverage of the top and - with a further carrier sheet, or an electrically conductive film - can also find the bottom use.
  • bonding layer NTV or diffusion soldering
  • bonding layer NTV or diffused soldering
  • bonding layer NTV or diffused soldering
  • first copper conductive surface e.g., emitter
  • second copper face e.g., gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Textile Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Leistungshalbleiterchip (10) mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten (50) oder Bändchen, mit einer Verbindungsschicht (1) auf den Potentialflächen, und wenigstens einem metallischen Formkörper (24, 25) auf der oder den Verbindungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht (1) gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte (50) oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist.

Description

LEISTUNGSHALBLEITERCHIP MIT METALLISCHEN FORMKÖRPERN UM KONTAKTIEREN MIT ' DICKDRÄHTEN ODER BÄNDCHEN SOWIE VERFAHREN ZU DESSEN HERSTELLUNG
Die Erfindung betrifft einen Leistungshalbleiterchip mit wenigstens einer oberseitigen Potentialfläche. Leistungsmodule bestehen in der Regel aus mehreren Halbleitern, von denen viele, wie z.B. Dioden senkrecht zur Chipfläche vom Laststrom durchflössen werden.
Um langlebige und robuste Module zu entwickeln, werden speziell an die obere und untere Verbindungsstelle des Halbleiters (Oberseite und Unterseite) hohe thermische und elektrische Anforderungen gestellt. Üblicherweise wird die Unterseite des Halbleiters mit einer Lotverbindung oder teilweise auch mit einer gesinterten oder diffu- sionsgelöteten Verbindung kontaktiert.
Die Oberseite des Halbleiters weist stahdardgemäß eine Metallisierung oder Metallschicht auf, die für den Bondprozess dicker AJuminiumdrähte optimiert ist. Trotz solcher dehnungsintensiven Metallisierungsschichten auf der Ober- und Unterseite des Halbleiters, werden die Halbleiter zur Reduzierung der elektrischen Verluste dennoch immer dünner. Aktuell sind Leistungshalbleiter auf dem Markt mit nur ca. 70μίη Gesamtdicke. Forschungsinstitute konnten bereits erste extreme Waferdün- nungen bis auf 1 Ομπι vorlegen.
Nachteile des Standes der Technik
Einen großen Einfluss auf die Begrenzung der Lebensdauer eines Leistungsmoduls hat die pberseitige Chipkontaktierung. Eine sehr robuste Sinterverbindung auf der Unterseite eines Chips verhilft nur zu einer geringen Erhöhung der Modullebenszeit, da das Versagen der Aluminiumdrähte auf der Oberseite des Halbleiters den limitierenden Faktor darstellt.
Die Al-Bondtechnologie ist seit vielen Jahren in den Fertigungslinien der Leistungselektronik etabliert. Ein stetiges Optimieren des Bondprozesses hat für einen Anstieg der zu erwartenden Lebenszeit dieser Verbindung gesorgt. Dieses hohe Niveau befindet sich jedoch annähernd an der physikalischen Grenze der Belastbarkeit einer Aluminiumschweißverbindung, so dass große Schritte in der Lebenszeiterwartung nur durch neue Konzepte in der Aufbau- und Verbindungstechnik (AVT) realisiert werden können. Diese Notwendigkeit wird auch durch die Tatsache, dass die Sintertechnologie auf der Unterseite des Halbleiters bereits jetzt (relativ zu der Löttechnologie gesehen) einen zweistelligen Anstieg im Faktor der Lebenszeiterwartung zeigt, bestärkt.
Darüber hinaus zeigen sich im Prozess Schwierigkeiten beim Handling der bis zu 70μπι dünnen Halbleiter (die in Zukunft bei noch dünneren Halbleiter stark ansteigen werden !). Die sehr dünne Siliziumschicht ist damit sowohl bei der Parametrierung der Fertigungs- und Prüfprozesse, als auch bei der Gestaltung der Aufbaukonzepte ein größer werdendes Ausbeuterisiko in der Fertigung. Die Bruchgefahr ist nicht nur bei therrnomechanischen Spannungen gegeben, ferner auch bei leichten Belastungen in den Fertigungsprozessen (z.B. Aufsetzen der Kontaktnadel für Hochstromtests auf Waferlevel).
Die Erfindung strebt nun an, die Lebensdauer eines Leistungsmoduls, insbesondere des Leistungshalbleiterchips zu verbessern, indem die Kontakte auf der/den oberseitigen Potentialfläche(n) verbessert werden. Gleichzeitig ist die Ausbeute durch eine stabilere und weniger bruchgefahrdete Ausbildung zu erhöhen.
Verbesserung des Standes der Technik
Erfindungsgemäß wird dies durch die Merkmale des Hauptanspruchs gelöst. Um den Umstieg auf diese neue Technologie für die oberseitige Kontaktierung zu realisieren, werden notwendige Modifikationen zunächst am Aufbau des Leistungsmoduls beschrieben.
Diese Modifikationen ermöglichen den Umstieg der oberseitigen Kontaktierung auf die Dickdraht-Kupferbondtechnologie, was für eine drastische Zunahme der Lastwechselfestigkeit sorgt. Darüber hinaus sorgen die Modifikationen auch für eine Reduzierung der Bruchgefahr, die aufgrund der thermomechanischen Spannungen des Halbleiters und der mechanischen Belastungen aus dem Fertigungsprozess hervorgerufen werden.
Bewirkt wird dies durch die Anordnung metallischer Layer oder Formkörpern wenigstens oberhalb und bevorzugt auch unterhalb des Halbleiters, der dadurch symmetrisch thermomechanisch gespannt wird.
Weiter bilden die dünnen Layer oder Formkörper einen mechanischen Schutz der Oberflächen insbesondere über den Potentialflächen, zum Beispiel bei kraftschlüssig kontaktierenden Prüfverfahren (Hochstromtests auf Waferlevel). Das ermöglicht eine sichere elektrische Prüfung der Halbleiter, bevor die oberseitige Kontaktierung des Halbleiters realisiert wurde. Für die elektrische Prüfung wird die Oberfläche des mit dem Halbleiter stoffschlüssig verbundenen metallischen Layers mit speziellen Federtools kontaktiert, ohne dass die Gefahr besteht, die feinen Oberflächenstrukturen des Halbleiters zu zerstören. 2012/003787
- 4 -
Weitere Vorteile und Merkmale der Erfindung ergeben sich aus nachfolgender Beschreibung eines bevorzugten Ausführungsbeispiels anhand der beigefügten Abbildung.
Dabei zeigt:
Fig. 1 ein schematische perspektivische Gesamt- und eine Detaildarstellung eines Leistungshalbleiterchips mit oberer Kontaktierung nach der Erfindung,
Fig. 2 eine Draufsicht auf den Formkörper gehalten an einer Trägerschicht, und
Fig; 3 eine schematische Darstellung entlang eines Schnittes in der Linie von a zu a in Fig. 2.
Der erfindungsgemäße Leistungshalbleiterchip 10 mit oberseitigen Potentialflächen weist bevorzugt wenigstens einen, eine Potentialfläche bedeckenden, elektrisch leitenden Formkörper 24, 25 auf. In Figur 2 ist der Formkörper 24 als ringförmig einen weiteren Formkörper 25 umgebende Layerschicht dargestellt, unter der mehrere Po- tentialfiächen liegen können, die dann mit dem Layer gefügt werden können, zum Beispiel vier in den Eckbereichen, oder auch nur zwei gegenüberliegende, wie es die Schnittdarstellung andeutet. Auch der Fall, dass schon die Potentialfläche des Leistungshalbleiterchips 10 annährend die ringförmige Formgebung des Layers aufweist, ist nicht ausgeschlossen.
Der Leistungshalbleiterchip 10 weist auf der Oberseite Potentialflächen auf, auf die die Formkörper vorzugsweise elektrisch und thermisch gut leitend (aus Cu, Ag, Au, AI, Mo, W und ihren Legierungen bestehend) aufgefügt werden. Die Formkörper werden etwa 30μπι bis 300μπι stark sein. Dabei kommen sowohl für dünne Halbleiter im Bereich von 30μιη Formkörper zwischen 30μπι und 40μπι, wie auch für dickere Halbleiterchips von 150μπι - 200μπι entsprechend etwas dickere Formkörper zwischen ΙΟΟμπι und 150 μιη Dicke in Frage; Ein solcher Formkörper wird mit Hilfe einer Verbindungsschicht 1 in Niedertemperatur-Sintertechnologie (oder diffusionsgelötet oder geklebt) auf der Metallisierungsschicht 10b des Halbleiters befestigt. Der Formkörper überragt dabei die Abmessungen des Leistungshalbleiterchips 10 nicht.
Optional kann in einer bevorzugten Ausführungsform ein weiterer Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 befestigt werden. Er hat dieselbe Schichtstärke wie der Formkörper 24, 25 auf der Oberseite des Leistungshalbleiterchips 10. Die Verbindung 2 zwischen dem unteren Formkörper 30 und dem Leistungshalbleiterchip 10 entspricht der Verbindungstechnologie zwischen Chip und dem Formkörper 24, 25 an der Oberseite.
Dabei können Leistungshalbleiterchips, die auf der Oberfläche mehrere elektrische unterschiedliche Potentialflächen aufweisen, Formkörper 24, 25 in der gleichen Anzahl erhalten, wie sie unterschiedliche Potentiale aufweisen. Dabei wird jede Potentialfläche des Halbleiters (z.B. Emitter und Gate) mit der Unterseite des Formkörpers elektrisch über eine Verbindung kontaktiert.
Falls jedoch ein elektrisches Potential des Halbleiters über mehrere Flächen (z.B. durch sog. Gatefinger segmentierte Emitterflächen) verfügt, dann ist es eine Option, dass auch eine entsprechende Anzahl von einzelnen Formkörpern vorgesehen wird.
Da der Formkörper teilweise auch einzelne Inseln 25 bilden kann (Variante 1 und 2), ist es von Vorteil, ein Trägermaterial 20a zu verwenden, das für den Zusammenhalt des Plättchens bei der Bestückung sorgt.
Dieses Trägermaterial könnte ein temperaturbeständiger Kunststoff, zum Beispiel Polyamid oder auch Polyimid sein, das sowohl hohen Temperaturen standhält, als auch als Isolator einen Stromfluss zwischen den unterschiedlichen Potentialflächen 24, 25 verhindert. Die einzelnen Formkörper auf den Potentialflächen 24, 25 bestehen z.B. aus einem dünnen Kupferblech (30-300μιη), das auf der dem Chip zugewiesenen Seite mit einer oxidationshemmenden Schutzschicht 23 (Ag oder Au) beschichtet ist. Das Trägermaterial 20a und die Formkörper 24, 25 bilden eine gemeinsame Trägerfolie mit strukturierten Leitflächen, d.h. zum Beispiel der durch Ätzen gewonnenen ringförmigen Leitflächen wie in Fig. 2. Die Oberseite der Trägerfolie 20a kann auch mehrere, die oberseitigen Potentialflächen gleichen Potentials gleichzeitig überdeckende Formkörperflächen aufweisen, oder Formkörper, die. die elektrischen Kontaktflächen 11, 12 des Halbleiters widerspiegeln, und die passgenau auf ihnen fest versintert werden.
Diese Formkörper werden elektrisch vorzugweise durch metallische Leiter in Form von Drähten, Bändern, Drahtbündeln, Geflecht oder Gewebebändern 50 auf der Oberseite der einzelnen Formkörper 24, 25 kontaktiert Eine bevorzugte Ausführung ist dabei das Kupferdickdrahtbonden (z. B. bis 600μπι Durchmesser).
In der Fig. 3 ist zu erkennen, wie metallische Formkörper 24, 25 oberhalb der Chip- Potentialflächen 11, 12, 13 angeordnet werden. Auch unterhalb des Chips 10 kann ein Formkörper mit einer Trägerfolie mit der dem Chip zugewandten Seite vollflächig mit der Unterseite des Halbleiters verbunden werden. Für die Verbindung kann die Oberfläche des Plättchens eine vor Oxidation schützende Schicht aufweisen. Mit Hilfe der Sinter- oder Diffusionslöttechnik wird letztlich eine stoffschlüssige Verbindung mit der Metallisierungsschicht 10c auf der Unterseite des Halbleiters realisiert.
Darüber hinaus kann der Formkörper auf der Unterseite des Halbleiters eine Schichtstärke aufweisen, die in Kombination mit den Formkörpern auf der Chipoberseite eine ausgeglichene mechanische Spannung erzeugt. Dies bedeutet, dass nach der Fügung von unterseitigem Plättchen und oberseitigen Formkörper eine sehr geringe resultierende Verformung des Halbleiters entsteht.
Eine bevorzugte Lösung ist, beide Schichten gleich dick und aus dem gleichen Material herzustellen. Dieses besteht entweder aus reinem Kupfer, das vollflächig bis an die Chipkanten ragt, oder aus einer großen gerahmten Kupferinsel, die umlaufend eine sehr schmale (wenige ΙΟΟμπι) Polyamidfolie aufweist, wie dies in Fig. 2 zu erkennen ist.
Es ist aber auch möglich, die Dehnungseigenschaften einer oberseitigen Schicht aus einem bestimmten Material mit einem gegebenen thermischen Aiisdehnungskoeffi- zienten und Elastizitätsmodul durch Anordnung eines anderen Materials mit anderen Eigenschaften auszugleichen. So kann eine oberseitige, relativ dicke Kupferschicht durch eine ünterseitige dünne Schicht aus Molybdän kompensiert werden. Die Verbindung 3 (Fig. 1) zwischen den unteren Formkörpern und der Substratoberfläche entspricht auch in der Technologie (Sintern, Diffusionslöten, Kleben) derjenigen, die bei den anderen genannten Verbindungsschichten Einsatz findet.
Die oberseitige Kontaktfolie kann in multipler Aneinanderreihung alle Halbleiterelemente eines ungesagten Waferverbunds kontaktieren. Dadurch wird eine besonders toleranzarme Überdeckung aller Leiterflächen der Kontaktfolie mit den Potentialflächen des Halbleiters erreicht. Es ergibt sich eine kostengünstigere Parallelverarbeitung gegenüber der seriellen Bestückung von jeweils einem Halbleiterelement und einer Einzel-Kontaktfolie. Nach der Verbindung der Wafer-Kontaktfolie mit dem Halbleiter- Wafer durch Niedertemperatursintern, Löten oder Kleben ist eine übliche Vereinzelung z. B. durch Sägen möglich.
Ein vergleichbarer Vorgang ist mit einer Wafer-Kontaktfolie für die Unterseite des Halbieiterelementes im Waferverbund möglich. So können nach der oberseitigen und der unterseitigen Folienkontaktierung durch die übliche Vereinzelung z. B. durch Sägen die einzelnen Halbleiterelemente mit beidseitiger Beschichtung gewonnen werden.
Die Vorteile durch die Verwendung der Leistungshalbleiterchips mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten oder Bändchen, mit einer Verbindungsschicht auf den Potentialflächen, und wenigstens einen metallischen Formkörper auf der oder den Verbindungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist, sind folgende :
Die Formkörper ermöglichen eine oberseitige Kontaktierung durch dicke Kupferdrähte auch für dünne Halbleiterelemente.
Die Formkörper schützen die sensiblen dünn metallisierten Oberflächen der Halbleiter (typisch nur ca. 3-4 μηι) beim Kupfer-Dickdraht-Bonden. Die Formkörper sorgen für eine bessere Stromdichteverteilung auf dem gesamten Querschnitt der Chipoberfläche.
Die Formkörper schützen die sensible Oberflächenstruktur des Halbleiters beim kraftschlüssigen Kontaktieren durch federnde Kontakte. Das erleichtert die nicht zerstörende, elektrische Qualitätsprüfung in den Fertigungslinien.
Eine unterseitige Folien- und Formkörperschicht verhindert durch eine Symmetrisie- rung der mechanischen Spannungen den Schüsseleffekt (Verformung des Halbleiterelementes)
Ober- und unterseitige Trägerfolien tragen Formkörperfelder, die einen ganzen Wa- fer überdecken können und so kostengünstig und präzise die parallele Belegung aller Kontaktflächen mit Formkörpern ermöglichen.
Die Fig. 1 zeigt den erfindungsgemäßen Leistungshalbleiterchip 10, wobei oberseitigen Potentialflächen 11, 12, 13 (siehe Fig. 3) von nur zwei die Potentialflächen 11, 13; 12 bedeckenden Formkörpern 24, 25 elektrisch und stoffschlüssig über eine Verbindungsschicht 1 kontaktiert sind. Die Potentialflächen 11 und 13 besitzen das gleiche Potential und können daher mit einer elektrisch leitenden, umlaufenden Leitflä- che des Formkörpers 24, wie sie in Fig. 2 annähernd quadratisch mit mittiger Ausnehmung zu erkennen ist, gemeinsam kontaktiert werden. Weitere zu kontaktierende Flächen sind bei einer Formgebung wie in Fig. 2 unter der ganzen oberseitigen Erstreckung des Formkörpers möglich. Auf sie würde nach Aufbringen einer Verbindungsschicht 1 dann ebenfalls der Forrnkörper 24 gefügt werden.
Ein separater Forrnkörper 25 wird auf einer Potentialfläche 12 anderen Potentials, beispielsweise einem Gate vorgesehen. Beide Forrnkörper 24, 25 werden auf einer Kontaktfolie 20a gehalten, die an der Unterseite im Bereich der Formkörper 24, 25 Durchlässe aufweist.
Der oder die Formkörper 24, 25 sind elektrisch und thermisch gut leitend aus Metall vorgesehen, z.B. weist der Formkörper 24, 25 ein Material der Gruppe Cu, Ag, Au, AI, Mo, W oder ihrer Legierungen auf, wobei die Legierungen eines oder mehrere Metalle der vorgenannten Gruppe aufweisen können. Der Formkörper 24, 25 wird zwischen 15μπι und 500μηι Dicke besitzen, bevorzugt 30μπι und 300μm. Wiederum vorteilhaft zwischen 75μη und 150μm Dicke. Dabei kommen sowohl für dünne Halbleiter (im Bereich von 30μπι) Formkörper zwischen 30 und 40μιη, wie auch für dickere Halbleiterchips von 150μπι - 200μπι entsprechend etwas dickere Formkörper zwischen ΙΟΟμπι und 150 μιη Dicke in Frage. Schon wenn eine Dicke entsprechend einem Viertel des Durchmessers der beim Dickdrahtbonden verwendeten Drahtdurchmesser erreicht wird, kann der Formkörper seine stabilisierende Funktion erfüllen. Entsprechend werden Formkörperdicken Von einem Viertel bis zur Hälfte der Drahtdurchmesser vorgeschlagen.
Der neben dem oberseitigen Formkörper 24, 25 vorgesehene weitere Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 wird ebenso wie der obere mit Niedertemperatur-Sintertechnologie, Difrusionslötung oder Kleben an dem Leistungshalbleiterchip 10 angesetzt.
Entsprechend der Anzahl der mit verschiedenen Potentialen versehenen oberseitigen Potentialflächen 11, 13; 12 kann die gleiche oder eine größere Anzahl von Formkörpern 24, 25 eingesetzt werden. Es kann idealerweise ein Formkörper für alle Potentialflächen des gleichen Potentials Verwendung finden, oder auch nur örtlich zueinander passende geringere Teilanzahlen von Potentialflächen werden mit einem gemeinsamen Formkörper 24, 25 kontaktiert und gefügt.
Die einfachste Variante verwendet einen Formkörper pro Potentialfläche, wobei die Dimensionen der Festkörper dann eng an die Dimensionen der Potentialflächen an- gepasst sind. Vorteilhaft ist, dass die zu fügende Verbindung unter jedem Formkörper 24, 25 eine geringere Projektionsfläche als der Formkörper 24, 25 aufweist, wobei ein Rand des Formkörpers verbleibt, der auf einer organischen nicht-leitenden Trägerfolie 20a fixiert ist, die ihrerseits wieder auf dem Leistungshalbleiterchips 10 nach passgenauen Aufbringen fixiert werden kann.
Dabei kann die Trägerfolie 20a die nicht zu fügenden Bereiche der Chipoberfläche klebend bedecken. Sie sollte sich aber nicht über die Außenberandung des Chips erstrecken. In Fig. 3 ist der Fall dargestellt, wo die Verbindungsschicht 1 aus Sintermaterial in den Dimensionen geringfügig kleiner als sowohl Formkörper wie Potentialfläche gewählt ist, und noch Trägerfolie 20a über die Ränder der Potentialflächen auf 3787
- lo deren Randbereiche ragt. Dies kann die Randbereiche beim Fügen entlasten. Eine weitere Variante belässt einige Potentialflächen, z. B. Steueranschlüsse, frei von Formkörpern, um diese direkt zu kontaktieren.
Schließlich können die thermischen Ausdehnungseigenschaften eines oberseitigen Formkörpers 24, 25 durch Wahl eines ungleichartigen Materials und einer anderen Dicke für einen weiteren Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 zur Erreichung geringer resultierender Gesamtdehnung ausgeglichen werden. Der Formkörper sollte dabei nicht den Rand des Leistungshalbleiterchips 10 erreichen. Dies würde aufwändige Isolation nötig machen.
Ein vorgeschlagenes Verfahren zum Aufbringen von Formkörpern auf einen Leistungshalbleiterchip verwendet ein elektrisch isolierendes, der thermischen Belastung beim Bonden widerstehendes Trägerblatt 20a mit einer Anzahl von Formkörpern 24, 25. Diese werden so gleichzeitig auf den Leistungshalbleiterchip vor dem Fügen aufgebracht, wobei ebenso eine Anzahl von Formkörpern 24, 25 für eine Vielzahl von Leistungshalbleiterchips 10 zur toleranzarmen Überdeckung der Oberseite und - mit einem weiteren Trägerblatt, bzw. einer elektrisch leitfahigen Folie - auch der Unterseite Verwendung finden kann.
P T/EP2012/003787
- 11 -
Bezugszeichen :
1 : Verbindungsschicht (NTV oder Diffusionslöten)
2: Verbindungsschicht (NTV oder Diffuslonslöten)
3: Verbindungsschicht (NTV oder Diffuslonslöten)
10: Chip
10a: Silizium
10b: oberseitige Chipmetallisierung
10c: unterseitige Chipmetallisierung
4, 25: Formkörper auf der Oberseite des Halbleiters (Kontaktfolie mit mehreren Leitflächen)
20a: Trägerfolie aus z.B. Polyamid
20b: Kleberzwischen Formkörper und Trägerfolie
20c: Kleber zwischen Trägerfolie und Chipoberseite
23: unterseitige Oxidationsschutzschlcht der Kupferleltflächen
24: erste Kupferleitfläche (z.B. Emitter)
25: zweite Kupferleltfläche (z.B. Gate)
0: Formkörper unterhalb des Halbleiters
30a: Polyamid
30b: Kleber
30c: Kleber
34a: Kupferinsel aus dünnem Kupferblech
34b: Kupferblech
36: unterseitige OxIdatJonsschutzschicht der Kupferinsel / des Kupferbleches
37: oberseitige Oxidationsschutzschlcht der Kupferinsel / des Kupferbleches
0: Kupferdrähte
0: Substratoberfläche

Claims

Patentansprüche
1. Leistungshalbleiterchip (10) mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten (50) oder Bändchen, gekennzeichnet durch
- eine Verbindungsschicht (1) auf den Potentialflächen, und
- wenigstens einen metallischen Formkörper (24, 25) auf der oder den Verbin- dungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht (1) gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte (50) oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist.
2. Leistungshalbleiterchip nach Anspruch 1, dadurch gekennzeichnet, dass ein an der unteren Flachseite Silber- oder Nickel Gold-beschichteter Formkörper (24, 25) aus Material der Gruppe Cu, Ag, Au, AI, Mo, W oder ihren Legierungen besteht, wobei die Legierungen eines oder mehrere Metalle der vorgenannten Gruppe aufweisen.
3. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die zu fugende Verbindung unter jedem Formkörper (24, 25) eine geringere Projektionsfläche als der Formkörper (24, 25) aufweist, wobei ein Rand der Formkörper (24, 25) verbleibt, der auf einer organischen, nicht-leitenden Trägerfolie (20a) fixiert ist.
4. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Trägerfolie (20a) die nicht zu fügenden Bereiche der Chip- oberfläche haftend bedeckt.
5. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Trägerfolie (20a) sich nicht über die Außenberandung des Chips erstreckt.
6. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass neben dem oberseitigen Formkörper (24, 25) ein weiterer Formkörper (30) auf der Unterseite des Leistungshalbleiterchips (10) vorgesehen und mittels einer Verbindungsschicht (2) zur Verbindung mittels Niedertemperatur-Sintertechnologie, Diffüsionslötung oder Kleben an den Leistungshalbleiterchip (10) angesetzt ist.
7. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass eine der Anzahl der mit verschiedenen Potentialen versehenen oberseitigen Potentialflächen entsprechende Anzahl von Fonnkörpern (24, 25) auf der Oberseite des Leistungshalbleiterchips vorgesehen ist.
8. Verfahren zum Aufbringen von Formkörpem auf einen Leistungshalbleiterchip, dadurch gekennzeichnet, dass ein elektrisch isolierendes, der thermischen Belastung beim Fügen widerstehendes Trägerblatt (20a) für alle Formkörper (24, 25), die auf einen ungesägten Waferverbund aufgebracht werden sollen, zum Transfer der Formkörper (24, 25) auf die oberseitigen Potentialflächen verwendet wird.
PCT/EP2012/003787 2011-10-15 2012-09-10 Leistungshalbleiterchip mit metallischen formkörpern zum kontaktieren mit dickdrähten oder bändchen sowie verfahren zu dessen herstellung WO2013053420A1 (de)

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US14/346,458 US9318421B2 (en) 2011-10-15 2012-09-10 Power semiconductor chip with a metallic moulded body for contacting thick wires or strips and method for the production thereof
EP12769904.9A EP2766922A1 (de) 2011-10-15 2012-09-10 Leistungshalbleiterchip mit metallischen formkörpern zum kontaktieren mit dickdrähten oder bändchen sowie verfahren zu dessen herstellung
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US9318421B2 (en) 2016-04-19
US20160225738A1 (en) 2016-08-04
EP2766922A1 (de) 2014-08-20
US9613929B2 (en) 2017-04-04
US20140225247A1 (en) 2014-08-14
JP2014532308A (ja) 2014-12-04
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JP5837697B2 (ja) 2015-12-24
CN103890924B (zh) 2017-02-15

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