DE202011110547U1 - Leistungshalbleiterchip mit oberseitigen Potentialflächen - Google Patents

Leistungshalbleiterchip mit oberseitigen Potentialflächen Download PDF

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DE202011110547U1
DE202011110547U1 DE202011110547.8U DE202011110547U DE202011110547U1 DE 202011110547 U1 DE202011110547 U1 DE 202011110547U1 DE 202011110547 U DE202011110547 U DE 202011110547U DE 202011110547 U1 DE202011110547 U1 DE 202011110547U1
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power semiconductor
semiconductor chip
potential
shaped body
layer
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DE202011110547.8U
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Danfoss Silicon Power GmbH
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Danfoss Silicon Power GmbH
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Abstract

Leistungshalbleiterchip (10) mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten (50) oder Bändchen, gekennzeichnet durch – eine Verbindungsschicht (1) auf den Potentialflächen, und – wenigstens einen metallischen Formkörper (24, 25) auf der oder den Verbindungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht (1) gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte (50) oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist.

Description

  • Die Erfindung betrifft einen Leistungshalbleiterchip mit wenigstens einer oberseitigen Potentialfläche. Leistungsmodule bestehen in der Regel aus mehreren Halbleitern, von denen viele, wie z. B. Dioden senkrecht zur Chipfläche vom Laststrom durchflossen werden.
  • Um langlebige und robuste Module zu entwickeln, werden speziell an die obere und untere Verbindungsstelle des Halbleiters (Oberseite und Unterseite) hohe thermische und elektrische Anforderungen gestellt. Üblicherweise wird die Unterseite des Halbleiters mit einer Lotverbindung oder teilweise auch mit einer gesinterten oder diffusionsgelöteten Verbindung kontaktiert.
  • Die Oberseite des Halbleiters weist standardgemäß eine Metallisierung oder Metallschicht auf, die für den Bondprozess dicker Aluminiumdrähte optimiert ist. Trotz solcher dehnungsintensiven Metallisierungsschichten auf der Ober- und Unterseite des Halbleiters, werden die Halbleiter zur Reduzierung der elektrischen Verluste dennoch immer dünner. Aktuell sind Leistungshalbleiter auf dem Markt mit nur ca. 70 μm Gesamtdicke. Forschungsinstitute konnten bereits erste extreme Waferdünnungen bis auf 10 μm vorlegen.
  • Einen großen Einfluss auf die Begrenzung der Lebensdauer eines Leistungsmoduls hat die oberseitige Chipkontaktierung. Eine sehr robuste Sinterverbindung auf der Unterseite eines Chips verhilft nur zu einer geringen Erhöhung der Modullebenszeit, da das Versagen der Aluminiumdrähte auf der Oberseite des Halbleiters den limitierenden Faktor darstellt.
  • Die Al-Bondtechnologie ist seit vielen Jahren in den Fertigungslinien der Leistungselektronik etabliert. Ein stetiges Optimieren des Bondprozesses hat für einen Anstieg der zu erwartenden Lebenszeit dieser Verbindung gesorgt. Dieses hohe Niveau befindet sich jedoch annähernd an der physikalischen Grenze der Belastbarkeit einer Aluminiumschweißverbindung, so dass große Schritte in der Lebenszeiterwartung nur durch neue Konzepte in der Aufbau- und Verbindungstechnik (AVT) realisiert werden können. Diese Notwendigkeit wird auch durch die Tatsache, dass die Sintertechnologie auf der Unterseite des Halbleiters bereits jetzt (relativ zu der Löttechnologie gesehen) einen zweistelligen Anstieg im Faktor der Lebenszeiterwartung zeigt, bestärkt.
  • Darüber hinaus zeigen sich im Prozess Schwierigkeiten beim Handling der bis zu 70 μm dünnen Halbleiter (die in Zukunft bei noch dünneren Halbleiter stark ansteigen werden!). Die sehr dünne Siliziumschicht ist damit sowohl bei der Parametrierung der Fertigungs- und Prüfprozesse, als auch bei der Gestaltung der Aufbaukonzepte ein größer werdendes Ausbeuterisiko in der Fertigung. Die Bruchgefahr ist nicht nur bei thermomechanischen Spannungen gegeben, ferner auch bei leichten Belastungen in den Fertigungsprozessen (z. B. Aufsetzen der Kontaktnadel für Hochstromtests auf Waferlevel).
  • Die Erfindung strebt nun an, die Lebensdauer eines Leistungsmoduls, insbesondere des Leistungshalbleiterchips zu verbessern, indem die Kontakte auf der/den oberseitigen Potentialflächen) verbessert werden. Gleichzeitig ist die Ausbeute durch eine stabilere und weniger bruchgefährdete Ausbildung zu erhöhen.
  • Erfindungsgemäß wird dies durch die Merkmale des Hauptanspruchs gelöst. Um den Umstieg auf diese neue Technologie für die oberseitige Kontaktierung zu realisieren, werden notwendige Modifikationen zunächst am Aufbau des Leistungsmoduls beschrieben.
  • Diese Modifikationen ermöglichen den Umstieg der oberseitigen Kontaktierung auf die Dickdraht-Kupferbondtechnologie, was für eine drastische Zunahme der Lastwechselfestigkeit sorgt. Darüber hinaus sorgen die Modifikationen auch für eine Reduzierung der Bruchgefahr, die aufgrund der thermomechanischen Spannungen des Halbleiters und der mechanischen Belastungen aus dem Fertigungsprozess hervorgerufen werden.
  • Bewirkt wird dies durch die Anordnung metallischer Layer oder Formkörpern wenigstens oberhalb und bevorzugt auch unterhalb des Halbleiters, der dadurch symmetrisch thermomechanisch gespannt wird.
  • Weiter bilden die dünnen Layer oder Formkörper einen mechanischen Schutz der Oberflächen insbesondere über den Potentialflächen, zum Beispiel bei kraftschlüssig kontaktierenden Prüfverfahren (Hochstromtests auf Waferlevel). Das ermöglicht eine sichere elektrische Prüfung der Halbleiter, bevor die oberseitige Kontaktierung des Halbleiters realisiert wurde. Für die elektrische Prüfung wird die Oberfläche des mit dem Halbleiter stoffschlüssig verbundenen metallischen Lagers mit speziellen Federtools kontaktiert, ohne dass die Gefahr besteht, die feinen Oberflächenstrukturen des Halbleiters zu zerstören.
  • Weitere Vorteile und Merkmale der Erfindung ergeben sich aus nachfolgender Beschreibung eines bevorzugten Ausführungsbeispiels anhand der beigefügten Abbildung. Dabei zeigt:
  • 1 ein schematische perspektivische Gesamt- und eine Detaildarstellung eines Leistungshalbleiterchips mit oberer Kontaktierung nach der Erfindung,
  • 2 eine Draufsicht auf den Formkörper gehalten an einer Trägerschicht, und
  • 3 eine schematische Darstellung entlang eines Schnittes in der Linie von a zu a in 2.
  • Der erfindungsgemäße Leistungshalbleiterchip 10 mit oberseitigen Potentialflächen weist bevorzugt wenigstens einen, eine Potentialfläche bedeckenden, elektrisch leitenden Formkörper 24, 25 auf. In 2 ist der Formkörper 24 als ringförmig einen weiteren Formkörper 25 umgebende Layerschicht dargestellt, unter der mehrere Potentialflächen liegen können, die dann mit dem Layer gefügt werden können, zum Beispiel vier in den Eckbereichen, oder auch nur zwei gegenüberliegende, wie es die Schnittdarstellung andeutet. Auch der Fall, dass schon die Potentialfläche des Leistungshalbleiterchips 10 annährend die ringförmige Formgebung des Lagers aufweist, ist nicht ausgeschlossen.
  • Der Leistungshalbleiterchip 10 weist auf der Oberseite Potentialflächen auf, auf die die Formkörper vorzugsweise elektrisch und thermisch gut leitend (aus Cu, Ag, Au, Al, Mo, W und ihren Legierungen bestehend) aufgefügt werden. Die Formkörper werden etwa 30 μm bis 300 μm stark sein. Dabei kommen sowohl für dünne Halbleiter im Bereich von 30 μm Formkörper zwischen 30 μm und 40 μm, wie auch für dickere Halbleiterchips von 150 μm–200 μm entsprechend etwas dickere Formkörper zwischen 100 μm und 150 μm Dicke in Frage.
  • Ein solcher Formkörper wird mit Hilfe einer Verbindungsschicht 1 in Niedertemperatur-Sintertechnologie (oder diffusionsgelötet oder geklebt) auf der Metallisierungsschicht 10b des Halbleiters befestigt. Der Formkörper überragt dabei die Abmessungen des Leistungshalbleiterchips 10 nicht.
  • Optional kann in einer bevorzugten Ausführungsform ein weiterer Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 befestigt werden. Er hat dieselbe Schichtstärke wie der Formkörper 24, 25 auf der Oberseite des Leistungshalbleiterchips 10. Die Verbindung 2 zwischen dem unteren Formkörper 30 und dem Leistungshalbleiterchip 10 entspricht der Verbindungstechnologie zwischen Chip und dem Formkörper 24, 25 an der Oberseite.
  • Dabei können Leistungshalbleiterchips, die auf der Oberfläche mehrere elektrische unterschiedliche Potentialflächen aufweisen, Formkörper 24, 25 in der gleichen Anzahl erhalten, wie sie unterschiedliche Potentiale aufweisen. Dabei wird jede Potentialfläche des Halbleiters (z. B. Emitter und Gate) mit der Unterseite des Formkörpers elektrisch über eine Verbindung kontaktiert.
  • Falls jedoch ein elektrisches Potential des Halbleiters über mehrere Flächen (z. B. durch sog. Gatefinger segmentierte Emitterflächen) verfügt, dann ist es eine Option, dass auch eine entsprechende Anzahl von einzelnen Formkörpern vorgesehen wird.
  • Da der Formkörper teilweise auch einzelne Inseln 25 bilden kann (Variante 1 und 2), ist es von Vorteil, ein Trägermaterial 20a zu verwenden, das für den Zusammenhalt des Plättchens bei der Bestückung sorgt.
  • Dieses Trägermaterial könnte ein temperaturbeständiger Kunststoff, zum Beispiel Polyamid oder auch Polyimid sein, das sowohl hohen Temperaturen standhält, als auch als Isolator einen Stromfluss zwischen den unterschiedlichen Potentialflächen 24, 25 verhindert. Die einzelnen Formkörper auf den Potentialflächen 24, 25 bestehen z. B. aus einem dünnen Kupferblech (30–300 μm), das auf der dem Chip zugewiesenen Seite mit einer oxidationshemmenden Schutzschicht 23 (Ag oder Au) beschichtet ist. Das Trägermaterial 20a und die Formkörper 24, 25 bilden eine gemeinsame Trägerfolie mit strukturierten Leitflächen, d. h. zum Beispiel der durch Ätzen gewonnenen ringförmigen Leitflächen wie in 2.
  • Die Oberseite der Trägerfolie 20a kann auch mehrere, die oberseitigen Potentialflächen gleichen Potentials gleichzeitig überdeckende Formkörperflächen aufweisen, oder Formkörper, die die elektrischen Kontaktflächen 11, 12 des Halbleiters widerspiegeln, und die passgenau auf ihnen fest versintert werden.
  • Diese Formkörper werden elektrisch vorzugweise durch metallische Leiter in Form von Drähten, Bändern, Drahtbündeln, Geflecht oder Gewebebändern 50 auf der Oberseite der einzelnen Formkörper 24, 25 kontaktiert. Eine bevorzugte Ausführung ist dabei das Kupferdickdrahtbonden (z. B. bis 600 μm Durchmesser).
  • In der 3 ist zu erkennen, wie metallische Formkörper 24, 25 oberhalb der Chip-Potentialflächen 11, 12, 13 angeordnet werden. Auch unterhalb des Chips 10 kann ein Formkörper mit einer Trägerfolie mit der dem Chip zugewandten Seite vollflächig mit der Unterseite des Halbleiters verbunden werden. Für die Verbindung kann die Oberfläche des Plättchens eine vor Oxidation schützende Schicht aufweisen. Mit Hilfe der Sinter- oder Diffusionslöttechnik wird letztlich eine stoffschlüssige Verbindung mit der Metallisierungsschicht 10c auf der Unterseite des Halbleiters realisiert.
  • Darüber hinaus kann der Formkörper auf der Unterseite des Halbleiters eine Schichtstärke aufweisen, die in Kombination mit den Formkörpern auf der Chipoberseite eine ausgeglichene mechanische Spannung erzeugt. Dies bedeutet, dass nach der Fügung von unterseitigem Plättchen und oberseitigen Formkörper eine sehr geringe resultierende Verformung des Halbleiters entsteht.
  • Eine bevorzugte Lösung ist, beide Schichten gleich dick und aus dem gleichen Material herzustellen. Dieses besteht entweder aus reinem Kupfer, das vollflächig bis an die Chipkanten ragt, oder aus einer großen gerahmten Kupferinsel, die umlaufend eine sehr schmale (wenige 100 μm) Polyamidfolie aufweist, wie dies in 2 zu erkennen ist.
  • Es ist aber auch möglich, die Dehnungseigenschaften einer oberseitigen Schicht aus einem bestimmten Material mit einem gegebenen thermischen Ausdehnungskoeffizienten und Elastizitätsmodul durch Anordnung eines anderen Materials mit anderen Eigenschaften auszugleichen. So kann eine oberseitige, relativ dicke Kupferschicht durch eine unterseitige dünne Schicht aus Molybdän kompensiert werden.
  • Die Verbindung 3 (1) zwischen den unteren Formkörpern und der Substratoberfläche entspricht auch in der Technologie (Sintern, Diffusionslöten, Kleben) derjenigen, die bei den anderen genannten Verbindungsschichten Einsatz findet.
  • Die oberseitige Kontaktfolie kann in multipler Aneinanderreihung alle Halbleiterelemente eines ungesägten Waferverbunds kontaktieren. Dadurch wird eine besonders toleranzarme Überdeckung aller Leiterflächen der Kontaktfolie mit den Potentialflächen des Halbleiters erreicht. Es ergibt sich eine kostengünstigere Parallelverarbeitung gegenüber der seriellen Bestückung von jeweils einem Halbleiterelement und einer Einzel-Kontaktfolie. Nach der Verbindung der Wafer-Kontaktfolie mit dem Halbleiter-Wafer durch Niedertemperatursintern, Löten oder Kleben ist eine übliche Vereinzelung z. B. durch Sägen möglich.
  • Ein vergleichbarer Vorgang ist mit einer Wafer-Kontaktfolie für die Unterseite des Halbleiterelementes im Waferverbund möglich. So können nach der oberseitigen und der unterseitigen Folienkontaktierung durch die übliche Vereinzelung z. B. durch Sägen die einzelnen Halbleiterelemente mit beidseitiger Beschichtung gewonnen werden.
  • Die Vorteile durch die Verwendung der Leistungshalbleiterchips mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten oder Bändchen, mit einer Verbindungsschicht auf den Potentialflächen, und wenigstens einen metallischen Formkörper auf der oder den Verbindungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist, sind folgende:
    • • Die Formkörper ermöglichen eine oberseitige Kontaktierung durch dicke Kupferdrähte auch für dünne Halbleiterelemente.
    • • Die Formkörper schützen die sensiblen dünn metallisierten Oberflächen der Halbleiter (typisch nur ca. 3–4 μm) beim Kupfer-Dickdraht-Bonden.
    • • Die Formkörper sorgen für eine bessere Stromdichteverteilung auf dem gesamten Querschnitt der Chipoberfläche.
    • • Die Formkörper schützen die sensible Oberflächenstruktur des Halbleiters beim kraftschlüssigen Kontaktieren durch federnde Kontakte. Das erleichtert die nicht zerstörende, elektrische Qualitätsprüfung in den Fertigungslinien.
    • • Eine unterseitige Folien- und Formkörperschicht verhindert durch eine Symmetrisierung der mechanischen Spannungen den Schüsseleffekt (Verformung des Halbleiterelementes)
    • • Ober- und unterseitige Trägerfolien tragen Formkörperfelder, die einen ganzen Wafer überdecken können und so kostengünstig und präzise die parallele Belegung aller Kontaktflächen mit Formkörpern ermöglichen.
  • Die 1 zeigt den erfindungsgemäßen Leistungshalbleiterchip 10, wobei oberseitigen Potentialflächen 11, 12, 13 (siehe 3) von nur zwei die Potentialflächen 11, 13; 12 bedeckenden Formkörpern 24, 25 elektrisch und stoffschlüssig über eine Verbindungsschicht 1 kontaktiert sind. Die Potentialflächen 11 und 13 besitzen das gleiche Potential und können daher mit einer elektrisch leitenden, umlaufenden Leitfläche des Formkörpers 24, wie sie in 2 annähernd quadratisch mit mittiger Ausnehmung zu erkennen ist, gemeinsam kontaktiert werden. Weitere zu kontaktierende Flächen sind bei einer Formgebung wie in 2 unter der ganzen oberseitigen Erstreckung des Formkörpers möglich. Auf sie würde nach Aufbringen einer Verbindungsschicht 1 dann ebenfalls der Formkörper 24 gefügt werden.
  • Ein separater Formkörper 25 wird auf einer Potentialfläche 12 anderen Potentials, beispielsweise einem Gate vorgesehen. Beide Formkörper 24, 25 werden auf einer Kontaktfolie 20a gehalten, die an der Unterseite im Bereich der Formkörper 24, 25 Durchlässe aufweist.
  • Der oder die Formkörper 24, 25 sind elektrisch und thermisch gut leitend aus Metall vorgesehen, z. B. weist der Formkörper 24, 25 ein Material der Gruppe Cu, Ag, Au, Al, Mo, W oder ihrer Legierungen auf, wobei die Legierungen eines oder mehrere Metalle der vorgenannten Gruppe aufweisen können.
  • Der Formkörper 24, 25 wird zwischen 15 μm und 500 μm Dicke besitzen, bevorzugt 30 μm und 300 μm. Wiederum vorteilhaft zwischen 75 μm und 150 μm Dicke. Dabei kommen sowohl für dünne Halbleiter (im Bereich von 30 μm) Formkörper zwischen 30 und 40 μm, wie auch für dickere Halbleiterchips von 150 μm–200 μm entsprechend etwas dickere Formkörper zwischen 100 μm und 150 μm Dicke in Frage. Schon wenn eine Dicke entsprechend einem Viertel des Durchmessers der beim Dickdrahtbonden verwendeten Drahtdurchmesser erreicht wird, kann der Formkörper seine stabilisierende Funktion erfüllen. Entsprechend werden Formkörperdicken von einem Viertel bis zur Hälfte der Drahtdurchmesser vorgeschlagen.
  • Der neben dem oberseitigen Formkörper 24, 25 vorgesehene weitere Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 wird ebenso wie der obere mit Niedertemperatur-Sintertechnologie, Diffusionslötung oder Kleben an dem Leistungshalbleiterchip 10 angesetzt.
  • Entsprechend der Anzahl der mit verschiedenen Potentialen versehenen oberseitigen Potentialflächen 11, 13; 12 kann die gleiche oder eine größere Anzahl von Formkörpern 24, 25 eingesetzt werden. Es kann idealerweise ein Formkörper für alle Potentialflächen des gleichen Potentials Verwendung finden, oder auch nur örtlich zueinander passende geringere Teilanzahlen von Potentialflächen werden mit einem gemeinsamen Formkörper 24, 25 kontaktiert und gefügt.
  • Die einfachste Variante verwendet einen Formkörper pro Potentialfläche, wobei die Dimensionen der Festkörper dann eng an die Dimensionen der Potentialflächen angepasst sind. Vorteilhaft ist, dass die zu fügende Verbindung unter jedem Formkörper 24, 25 eine geringere Projektionsfläche als der Formkörper 24, 25 aufweist, wobei ein Rand des Formkörpers verbleibt, der auf einer organischen nicht-leitenden Trägerfolie 20a fixiert ist, die ihrerseits wieder auf dem Leistungshalbleiterchips 10 nach passgenauen Aufbringen fixiert werden kann.
  • Dabei kann die Trägerfolie 20a die nicht zu fügenden Bereiche der Chipoberfläche klebend bedecken. Sie sollte sich aber nicht über die Außenberandung des Chips erstrecken. In 3 ist der Fall dargestellt, wo die Verbindungsschicht 1 aus Sintermaterial in den Dimensionen geringfügig kleiner als sowohl Formkörper wie Potentialfläche gewählt ist, und noch Trägerfolie 20a über die Ränder der Potentialflächen auf deren Randbereiche ragt. Dies kann die Randbereiche beim Fügen entlasten. Eine weitere Variante belässt einige Potentialflächen, z. B. Steueranschlüsse, frei von Formkörpern, um diese direkt zu kontaktieren.
  • Schließlich können die thermischen Ausdehnungseigenschaften eines oberseitigen Formkörpers 24, 25 durch Wahl eines ungleichartigen Materials und einer anderen Dicke für einen weiteren Formkörper 30 auf der Unterseite des Leistungshalbleiterchips 10 zur Erreichung geringer resultierender Gesamtdehnung ausgeglichen werden. Der Formkörper sollte dabei nicht den Rand des Leistungshalbleiterchips 10 erreichen. Dies würde aufwändige Isolation nötig machen.
  • Ein vorgeschlagenes Verfahren zum Aufbringen von Formkörpern auf einen Leistungshalbleiterchip verwendet ein elektrisch isolierendes, der thermischen Belastung beim Bonden widerstehendes Trägerblatt 20a mit einer Anzahl von Formkörpern 24, 25. Diese werden so gleichzeitig auf den Leistungshalbleiterchip vor dem Fügen aufgebracht, wobei ebenso eine Anzahl von Formkörpern 24, 25 für eine Vielzahl von Leistungshalbleiterchips 10 zur toleranzarmen Überdeckung der Oberseite und – mit einem weiteren Trägerblatt, bzw. einer elektrisch leitfähigen Folie – auch der Unterseite Verwendung finden kann.
  • Bezugszeichenliste
    • 1
    Verbindungsschicht (NTV oder Diffusionslöten)
    2
    Verbindungsschicht (NTV oder Diffusionslöten)
    3
    Verbindungsschicht (NTV oder Diffusionslöten)
    10
    Chip
    10a
    Silizium
    10b
    oberseitige Chipmetallisierung
    10c
    unterseitige Chipmetallisierung
    24, 25
    Formkörper auf der Oberseite des Halbleiters (Kontaktfolie mit mehreren Leitflächen)
    20a
    Trägerfolie aus z. B. Polyamid
    20b
    Kleber zwischen Formkörper und Trägerfolie
    20c
    Kleber zwischen Trägerfolie und Chipoberseite
    23
    unterseitige Oxidationsschutzschicht der Kupferleitflächen
    24
    erste Kupferleitfläche (z. B. Emitter)
    25
    zweite Kupferleitfläche (z. B. Gate)
    30
    Formkörper unterhalb des Halbleiters
    30a
    Polyamid
    30b
    Kleber
    30c
    Kleber
    34a
    Kupferinsel aus dünnem Kupferblech
    34b
    Kupferblech
    36
    unterseitige Oxidationsschutzschicht der Kupferinsel/des Kupferbleches
    37
    oberseitige Oxidationsschutzschicht der Kupferinsel/des Kupferbleches
    50
    Kupferdrähte
    60
    Substratoberfläche

Claims (7)

  1. Leistungshalbleiterchip (10) mit wenigstens einer oberseitigen Potentialfläche und kontaktierenden Dickdrähten (50) oder Bändchen, gekennzeichnet durch – eine Verbindungsschicht (1) auf den Potentialflächen, und – wenigstens einen metallischen Formkörper (24, 25) auf der oder den Verbindungsschicht(en), dessen zur Potentialfläche gewandte untere Flachseite zur Fügung mit einem Verbindungsverfahren der Verbindungsschicht (1) gemäß beschichtet ausgebildet ist, und dessen Materialzusammensetzung und Dicke derjenigen der im Kontaktverfahren verwandten Dickdrähte (50) oder Bändchen auf der Formkörper-Oberseite in der Größenordnung entsprechend gewählt ist.
  2. Leistungshalbleiterchip nach Anspruch 1, dadurch gekennzeichnet, dass ein an der unteren Flachseite Silber- oder Nickel/Gold-beschichteter Formkörper (24, 25) aus Material der Gruppe Cu, Ag, Au, Al, Mo, W oder ihren Legierungen besteht, wobei die Legierungen eines oder mehrere Metalle der vorgenannten Gruppe aufweisen.
  3. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die zu fügende Verbindung unter jedem Formkörper (24, 25) eine geringere Projektionsfläche als der Formkörper (24, 25) aufweist, wobei ein Rand der Formkörper (24, 25) verbleibt, der auf einer organischen, nicht-leitenden Trägerfolie (20a) fixiert ist.
  4. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Trägerfolie (20a) die nicht zu fügenden Bereiche der Chipoberfläche haftend bedeckt.
  5. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Trägerfolie (20a) sich nicht über die Außenberandung des Chips erstreckt.
  6. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass neben dem oberseitigen Formkörper (24, 25) ein weiterer Formkörper (30) auf der Unterseite des Leistungshalbleiterchips (10) vorgesehen und mittels einer Verbindungsschicht (2) zur Verbindung mittels Niedertemperatur-Sintertechnologie, Diffusionslötung oder Kleben an den Leistungshalbleiterchip (10) angesetzt ist.
  7. Leistungshalbleiterchip nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass eine der Anzahl der mit verschiedenen Potentialen versehenen oberseitigen Potentialflächen entsprechende Anzahl von Formkörpern (24, 25) auf der Oberseite des Leistungshalbleiterchips vorgesehen ist.
DE202011110547.8U 2011-10-15 2011-10-15 Leistungshalbleiterchip mit oberseitigen Potentialflächen Expired - Lifetime DE202011110547U1 (de)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4216259A1 (de) * 2022-01-24 2023-07-26 Hitachi Energy Switzerland AG Halbleiterbauelement, halbleitermodul und herstellungsverfahren

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4216259A1 (de) * 2022-01-24 2023-07-26 Hitachi Energy Switzerland AG Halbleiterbauelement, halbleitermodul und herstellungsverfahren
WO2023138873A1 (en) 2022-01-24 2023-07-27 Hitachi Energy Switzerland Ag Semiconductor device, semiconductor module and manufacturing method

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