WO2013046643A1 - 不揮発性記憶素子のデータ書き込み方法及び不揮発性記憶装置 - Google Patents
不揮発性記憶素子のデータ書き込み方法及び不揮発性記憶装置 Download PDFInfo
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- WO2013046643A1 WO2013046643A1 PCT/JP2012/006093 JP2012006093W WO2013046643A1 WO 2013046643 A1 WO2013046643 A1 WO 2013046643A1 JP 2012006093 W JP2012006093 W JP 2012006093W WO 2013046643 A1 WO2013046643 A1 WO 2013046643A1
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- G—PHYSICS
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0073—Write using bi-directional cell biasing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
Definitions
- the present invention relates to a data writing method of a resistance change type nonvolatile memory element whose resistance value changes in accordance with an applied electric signal, and a nonvolatile memory device that implements the method.
- the nonvolatile memory element as described above has a very simple structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode. Then, the resistance change layer changes to the high resistance state or the low resistance state only by applying a predetermined electrical pulse having a voltage larger than a certain threshold value between the upper and lower electrodes. Information is recorded by associating these different resistance states with data.
- the variable resistance nonvolatile memory element has a simple structure and operation, and is expected to be capable of further miniaturization and cost reduction.
- the state change between the high resistance state and the low resistance state can occur on the order of 100 ns or less, it has attracted attention from the viewpoint of high speed operation.
- nonvolatile memory elements are roughly classified into two types depending on the material (resistance change material) used for the resistance change layer.
- One of them is a resistance to perovskite materials (for example, Pr (1-x) Ca x MnO 3 (PCMO), LaSrMnO 3 (LSMO), GdBaCo x O y (GBCO)) disclosed in Patent Document 1 and the like.
- It is a non-volatile memory element used for the change material.
- the other is a nonvolatile memory element using a binary transition metal oxide as a variable resistance material. Since the binary transition metal oxide has a very simple composition and structure as compared with the perovskite material described above, composition control and film formation in the manufacturing process are easy. In addition, there is an advantage that the compatibility with the semiconductor manufacturing process is relatively good, and many studies have been made in recent years.
- nonvolatile memory elements have the property that after information is electrically stored, the information is retained without being volatilized (disappeared, degraded, or changed) even when the power is turned off.
- volatile memory elements it is inevitable that the stored information changes within a finite time.
- Resistance variable nonvolatile memory elements are no exception, and have the property that information once stored gradually changes over time. In this case, the change in information is observed as a change with time in the set resistance value. Generally, when a certain long time (for example, 100 hours or more) elapses, the stored information is deteriorated by gradually changing the high resistance state to the low resistance state or the low resistance state to the high resistance state. The phenomenon is known.
- This phenomenon is a phenomenon in which the set resistance value changes randomly within a short period of time within a few minutes after applying an electrical pulse to the nonvolatile memory element, and tantalum (Ta) oxide is used as a resistance change material. It has been observed in non-volatile memory elements. The same phenomenon has been reported in a variable resistance nonvolatile memory element using nickel (Ni) oxide (Non-Patent Document 2: Danielle limini et al., Appl. Phys. Lett., Vol. 96). 2010, pp. 53503), which is considered to be a phenomenon that generally occurs in a resistance change type nonvolatile memory element.
- a main object of the present invention is to provide a method for writing data in a nonvolatile memory element capable of suppressing the influence of the above-described fluctuation and a nonvolatile memory device that implements the method.
- a method for writing data in a nonvolatile memory element includes a first electrode, a second electrode, and the first electrode and the second electrode.
- a data write method for a non-volatile memory element comprising a resistance change layer made of a metal oxide interposed between the first electrode and the second electrode, wherein the resistance of the non-volatile memory element is between the first electrode and the second electrode.
- the nonvolatile memory element A determination step of determining whether or not a resistance state is the second state; and when the determination step determines that the resistance state of the nonvolatile memory element is not the second state, the first electrode And a third applying step
- a nonvolatile memory device includes a first electrode, a second electrode, and the first electrode and the second electrode. And between the first electrode and the second electrode, the resistance state of the nonvolatile memory element is changed from the first state to the first state between the first electrode and the second electrode.
- the first voltage pulse for changing to the second state is applied, and then, between the first electrode and the second electrode, the same voltage as the first voltage pulse and the first voltage
- a determination unit that determines whether or not there is the non-volatility by the determination unit When it is determined that the resistance state of the memory element is not the second state, the resistance state of the nonvolatile memory element is changed from the first state to the second state between the first electrode and the second electrode. And a rewriting unit for applying a third voltage pulse for changing to the state.
- the influence of fluctuation can be suppressed and the data retention characteristics can be improved.
- FIG. 1A is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 1B is a cross-sectional view showing a local region formed in the second metal oxide layer of the nonvolatile memory element.
- FIG. 2 is a diagram for explaining the formation of filaments in the resistance change layer.
- FIG. 3 is a circuit configuration diagram when a voltage pulse is applied to the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 4 is a diagram showing fluctuations in the resistance value of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 1A is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 1B is a cross-sectional view showing a local region formed in the second metal oxide layer of the nonvolatile memory element.
- FIG. 2 is a diagram for explaining the formation
- FIG. 5 is a diagram plotting the maximum value and the minimum value of the resistance value variation in the high resistance state of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 6 is a diagram showing the relationship between the current value and the normal distribution of the current value when the nonvolatile memory element according to Embodiment 1 of the present invention is in the high resistance state.
- FIG. 7A is a flowchart showing a procedure of data write processing of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 7B is a flowchart corresponding to a summary of procedures in the flowchart of FIG. 7A.
- FIG. 8 is a diagram for explaining a voltage pulse application state in the write process and the verify read process.
- FIG. 8 is a diagram for explaining a voltage pulse application state in the write process and the verify read process.
- FIG. 9 is a diagram showing the relationship between the effective voltage and the current value when a positive voltage pulse is applied to a single nonvolatile memory element in a high resistance state.
- FIG. 10 is a diagram illustrating the relationship between the effective voltage and the resistance value when a positive voltage pulse is applied to a single nonvolatile memory element in a high resistance state.
- FIG. 11 is a diagram illustrating the relationship between the effective voltage and the current value when a negative voltage pulse is applied to a single nonvolatile memory element in a low resistance state.
- FIG. 12 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 13 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 3 of the present invention.
- FIG. 14 is a diagram showing fluctuations in the resistance value of a conventional nonvolatile memory element.
- This non-volatile memory element is a resistor having a bipolar switching characteristic that increases in resistance when a positive voltage is applied to the upper electrode with respect to the lower electrode and decreases in resistance when a negative voltage is applied. This is a change-type nonvolatile memory element.
- Fig. 14 shows the measurement results.
- a load resistance of 6.4 k ⁇ is connected in series to the manufactured nonvolatile memory element
- an electrical pulse of +2.5 V and 100 ns and an electrical pulse of ⁇ 2.0 V and 100 ns are alternately used.
- a high resistance state (about 120 k ⁇ ) was set by applying an electrical pulse of +100 V and 100 ns to the nonvolatile memory element.
- the nonvolatile memory element was kept at room temperature, and how the resistance value changed with time (that is, fluctuation) was examined.
- the resistance value of the nonvolatile memory element repeatedly increases and decreases repeatedly even though the voltage is maintained at room temperature and a voltage large enough to cause a resistance change is not applied. I understand. Specifically, the resistance value drastically decreases to about 50 k ⁇ 200 seconds after the last electric pulse is applied, and then increases after 1000 seconds and reaches 200 k ⁇ .
- the initially set resistance value (about 120 k ⁇ ) greatly increases / decreases in a short time, there is a possibility that a data read error occurs.
- a nonvolatile memory element having a set resistance value of 120 k ⁇ whose measurement results are shown in FIG. 14 will be described as an example.
- 60 k ⁇ which is half of the set resistance value, is set as a threshold value (data judgment point, reference level), and the case where it is 60 k ⁇ or more is defined as a high resistance state, and the case where it is smaller than 60 k ⁇ is defined as a low resistance state.
- the resistance value of the nonvolatile memory element when the resistance value of the nonvolatile memory element is read at about 1000 seconds after the resistance value is set (that is, the resistance value of the nonvolatile memory element is set to 120 k ⁇ ), the resistance value becomes 50 k ⁇ . Therefore, it is determined that the resistance state is low. On the other hand, when reading out after 2000 seconds, the resistance value exceeds 200 k ⁇ , so that it is determined to be in the high resistance state. As described above, depending on the data read timing, the data in the same nonvolatile memory element becomes “1” or “0”.
- the present inventors have devised a data writing method or the like that can suppress the influence of such fluctuation and improve data retention characteristics in a resistance change type nonvolatile memory element by repeating experiments and considerations. did.
- One aspect of the data writing method includes a first electrode, a second electrode, and a resistance change layer made of a metal oxide and interposed between the first electrode and the second electrode.
- a method of writing data in a nonvolatile memory element wherein a resistance state of the nonvolatile memory element is changed between a first state and a second state between the first electrode and the second electrode.
- the determination step determines that the resistance state of the nonvolatile memory element is not the second state, the resistance state of the nonvolatile memory element is between the first electrode and the second electrode. Applying a third voltage pulse for changing the voltage from the first state to the second state.
- the first state may be a low resistance state
- the second state may be a high resistance state in which a resistance value of the nonvolatile memory element is higher than that of the low resistance state. That is, the data writing method according to the present invention may be applied to high resistance writing.
- the absolute value of the voltage value of the second voltage pulse is determined by applying a voltage between the first electrode and the second electrode when the resistance state of the nonvolatile memory element is the high resistance state.
- the first electrode and the second electrode when the non-volatile memory element is at least a minimum voltage at which current starts to flow and the resistance state of the nonvolatile memory element is the high-resistance state.
- the voltage is preferably not more than the maximum voltage that does not cause dielectric breakdown of the nonvolatile memory element when a voltage is applied between them.
- the minimum voltage is preferably 0.6V
- the maximum voltage is preferably 1.3V.
- the first state may be a high resistance state
- the second state may be a low resistance state in which a resistance value of the nonvolatile memory element is lower than that of the high resistance state. That is, the data writing method according to the present invention may be applied to low resistance writing.
- the absolute value of the voltage value of the second voltage pulse is determined by applying a voltage between the first electrode and the second electrode when the resistance state of the nonvolatile memory element is the low resistance state.
- the first electrode and the second electrode when the non-volatile memory element is equal to or higher than a minimum voltage at which current starts to flow and the resistance state of the nonvolatile memory element is the low-resistance state.
- the voltage be equal to or lower than the maximum voltage that does not cause the resistance of the nonvolatile memory element to be lowered when a voltage is applied therebetween.
- the minimum voltage is preferably 0.05V
- the maximum voltage is preferably 0.75V.
- the third voltage pulse may have the same voltage value as the first voltage pulse, or the third voltage pulse may be changed to the first voltage pulse.
- the absolute value of the voltage value may be larger than that.
- the metal oxide may be tantalum oxide
- the nonvolatile memory element is a voltage pulse applied between the first electrode and the second electrode.
- the bipolar memory element in which the resistance state of the nonvolatile memory element changes from the first state to the second state or from the second state to the first state in accordance with the polarity of May be.
- the variable resistance layer has a stacked structure including a first metal oxide layer containing a first metal oxide and a second metal oxide layer containing a second metal oxide.
- the oxygen deficiency of the first metal oxide layer may be greater than the oxygen deficiency of the second metal oxide layer, and the second metal oxide layer may be the second metal
- the oxide layer may include a filament that is a current path for passing a current having a high current density locally, and the second metal oxide layer is included in the second metal oxide layer. A region having a locally high oxygen defect concentration may be included.
- a nonvolatile memory device includes a first electrode, a second electrode, a resistance change layer formed of a metal oxide, interposed between the first electrode and the second electrode. And a first voltage pulse for changing the resistance state of the nonvolatile memory element from the first state to the second state between the first electrode and the second electrode After that, a second voltage having the same polarity as the first voltage pulse and having a smaller absolute voltage value than the first voltage pulse is provided between the first electrode and the second electrode.
- a writing unit that applies a voltage pulse; a determination unit that determines whether a resistance state of the nonvolatile memory element is the second state after the second voltage pulse is applied; and the determination The resistance state of the nonvolatile memory element is not the second state due to the portion If it is determined, a third voltage pulse for changing the resistance state of the nonvolatile memory element from the first state to the second state is provided between the first electrode and the second electrode. And a rewriting unit to be applied.
- FIG. 1A is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
- the nonvolatile memory element 100 of this embodiment includes a substrate 101, an interlayer insulating film 102 formed on the substrate 101, and a first electrode formed on the interlayer insulating film 102. 103, a second electrode 105, and a resistance change layer 104 sandwiched between the first electrode 103 and the second electrode 105.
- the nonvolatile memory element 100 includes the substrate 101 and the interlayer insulating film 102, but these components are not necessarily required.
- the resistance change layer 104 has a stacked structure of a first metal oxide layer 104a containing a first metal oxide and a second metal oxide layer 104b containing a second metal oxide.
- the first metal oxide layer 104a includes an oxygen-deficient tantalum oxide
- the second metal oxide layer 104b also includes a tantalum oxide.
- the oxygen content of the second metal oxide layer 104b is higher than the oxygen content of the first metal oxide layer 104a.
- the oxygen deficiency of the first metal oxide layer 104a is greater than the oxygen deficiency of the second metal oxide layer 104b. Therefore, the resistance value (more specifically, specific resistance) of the second metal oxide layer 104b is larger than the resistance value (more specifically, specific resistance) of the first metal oxide layer 104a.
- the composition of the first metal oxide layer 104a is TaO x and the second metal oxide layer 104b is TaO y , it is preferable that 0 ⁇ x ⁇ 2.5 and x ⁇ y are satisfied. Furthermore, in order to stably realize the resistance change operation of the nonvolatile memory element 100, it is more desirable to satisfy 2.1 ⁇ y and 0.8 ⁇ x ⁇ 1.9.
- the composition of the metal oxide layer can be measured using Rutherford backscattering method or the like.
- an initial break voltage equal to or higher than a predetermined voltage is applied between the first electrode 103 and the second electrode 105 immediately after manufacture (initial break).
- a state in which the high resistance state and the low resistance state can be transitioned reversibly is obtained.
- the local region 110 is considered to include a filament 112 composed of oxygen defect sites. That is, the second metal oxide layer 104b has a region having a locally high oxygen defect concentration inside.
- the filament 112 is a current path (a conductive path) through which a current having a high current density flows locally.
- illustration of the substrate 101 and the interlayer insulating film 102 in FIG. 1A is omitted.
- a resistance change occurs in the second metal oxide layer 104b in contact with the second electrode 105 and having a higher oxygen concentration.
- the nonvolatile memory element 100 changes to a high resistance state, and conversely, the voltage of the first electrode 103 is changed.
- the nonvolatile memory element 100 changes to a low resistance state.
- the nonvolatile memory element 100 includes, as an example, the resistance state of the nonvolatile memory element 100 according to the polarity of the voltage pulse applied between the first electrode 103 and the second electrode 105. Is a bipolar memory element that transitions from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state.
- the “resistance state of the nonvolatile memory element” strictly means “the resistance state of the resistance change layer”.
- oxygen deficiency refers to the stoichiometric composition of metal oxide (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). The ratio of oxygen deficient with respect to the amount of oxygen constituting the oxide. A metal oxide having a stoichiometric composition is more stable and has a higher resistance value than a metal oxide having another composition.
- the oxide having the stoichiometric composition according to the above definition is Ta 2 O 5 , and can be expressed as TaO 2.5 .
- the oxygen excess metal oxide has a negative oxygen deficiency.
- the oxygen deficiency is described as including a positive value, 0, and a negative value.
- An oxide with a low degree of oxygen deficiency has a high resistance value because it is closer to a stoichiometric oxide, and an oxide with a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.
- the “oxygen content” is the ratio of oxygen atoms to the total number of atoms.
- the oxygen content of Ta 2 O 5 is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.
- the oxygen content has a corresponding relationship with the degree of oxygen deficiency.
- the oxygen deficiency of the second metal oxide layer 104b is determined by the first metal oxide layer 104b. It is smaller than the oxygen deficiency of the physical layer 104a.
- the metal constituting the resistance change layer 104 may be a metal other than tantalum.
- a metal constituting the resistance change layer 104 a transition metal or aluminum (Al) can be used.
- the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
- the composition of the first metal oxide layer 104a is HfO x
- x is 0.9 or more and 1.6 or less
- the second metal oxide layer 104b When the composition is HfO y and y is larger than the value of x, the resistance value of the variable resistance layer can be stably changed at high speed.
- the thickness of the second metal oxide layer 104b may be 3 to 4 nm.
- the composition of the first metal oxide layer 104a is ZrO x
- x is 0.9 or more and 1.4 or less
- the second metal oxide layer 104b When the composition is ZrO y and y is larger than the value of x, the resistance value of the variable resistance layer can be stably changed at high speed.
- the thickness of the second metal oxide layer 104b may be 1 to 5 nm.
- a different metal may be used for the first metal constituting the first metal oxide layer 104a and the second metal constituting the second metal oxide layer 104b.
- the second metal oxide layer 104b may have a lower oxygen deficiency, that is, higher resistance than the first metal oxide layer 104a.
- the standard of the second metal is used.
- the electrode potential may be lower than the standard electrode potential of the first metal.
- the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction is likely to occur in the second metal oxide layer 104b having a relatively low standard electrode potential.
- the resistance change phenomenon is caused by the fact that a redox reaction occurs in the minute local region 110 formed in the second metal oxide layer 104b having a high resistance and the filament (conductive path) 112 is changed. It is considered that the resistance value (oxygen deficiency) of the metal oxide layer 104b changes.
- a metal oxide whose standard electrode potential is lower than that of the first metal oxide for the second metal oxide layer 104b, a redox reaction occurs more in the second metal oxide layer 104b. It becomes easy to do.
- aluminum oxide Al 2 O 3
- oxygen-deficient tantalum oxide (TaO x ) may be used for the first metal oxide layer 104a
- aluminum oxide Al 2 O 3
- the resistance change phenomenon in the resistance change layer 104 having the laminated structure is caused by an oxidation-reduction reaction in the minute local region 110 formed in the second metal oxide layer 104b having high resistance. It is considered that the resistance value of the second metal oxide layer 104b changes when the filament (conductive path) 112 in the local region 110 changes.
- the second electrode 105 connected to the second metal oxide layer 104b having a smaller oxygen deficiency is, for example, a second metal oxide such as platinum (Pt), iridium (Ir), or palladium (Pd).
- the standard electrode potential is higher than that of the metal constituting the layer 104b and the material constituting the first electrode 103.
- the first electrode 103 connected to the first metal oxide layer 104a having a higher oxygen deficiency includes, for example, tungsten (W), nickel (Ni), tantalum (Ta), titanium (Ti),
- a material having a lower standard electrode potential than the metal forming the first metal oxide layer 104a such as aluminum (Al), tantalum nitride (TaN), or titanium nitride (TiN), may be used.
- the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.
- the dielectric constant of the second metal oxide layer 104b is preferably larger than the dielectric constant of the first metal oxide layer 104a.
- the band gap of the second metal oxide layer 104b is preferably smaller than the band gap of the first metal oxide layer 104a.
- a material with a higher relative dielectric constant is easier to break down (initial break) than a material with a lower relative dielectric constant, and a material with a smaller band gap is more likely to break down than a material with a larger band gap. Since it is easy, an initial break voltage can be made low.
- the insulation of the second metal oxide layer 104b By using, for the second metal oxide layer 104b, a metal oxide that satisfies one or both of the above conditions (that is, conditions relating to the dielectric constant and the band gap), the insulation of the second metal oxide layer 104b.
- the breakdown electric field strength is smaller than that of the first metal oxide layer 104a, and the initial break voltage can be reduced.
- FIG. 1 of Non-Patent Document 3 J. McPherson et al., IEDM 2002, p. 633-636
- the dielectric breakdown electric field strength (Breakdown Strength) of the metal oxide layer This is because there is a correlation that the dielectric breakdown electric field strength decreases as the dielectric constant increases.
- FIG. 2 of Non-Patent Document 3 there is a correlation between the breakdown field strength of the metal oxide layer and the band gap that the breakdown field strength increases as the band gap increases. This is because there is a relationship.
- FIG. 2 is a diagram for explaining the formation of the filament 112 described above, and shows an example of a result of simulation using a percolation model.
- the filament (conductive path) 112 is formed by connecting oxygen defect sites in the variable resistance layer 104 (particularly in the second metal oxide layer 104b).
- the percolation model assumes a random distribution such as oxygen defect sites (hereinafter simply referred to as “defect sites”) in the resistance change layer 104. If the density of defect sites exceeds a certain threshold, the defect sites are connected.
- This model is based on the theory that the probability of formation increases.
- “defect” means that oxygen is deficient in the metal oxide
- “defect site density” also corresponds to the degree of oxygen deficiency. That is, as the oxygen deficiency increases, the density of defect sites also increases.
- the oxygen ion sites of the resistance change layer 104 are approximately assumed as regions (sites) partitioned in a lattice pattern, and the filament 112 formed by the defect sites formed stochastically is obtained by simulation. .
- a site including “0” represents a defect site formed in the resistance change layer 104.
- a blank site represents a site occupied by oxygen ions, which means a high resistance region.
- a cluster of defect sites indicated by arrows an assembly of defect sites connected to each other within one site in the vertical, horizontal, and diagonal directions was applied with a voltage in the vertical direction in the figure.
- a filament 112 formed in the resistance change layer 104 that is, a path through which a current flows is shown.
- the filament 112 that allows current to flow between the lower surface and the upper surface of the variable resistance layer 104 is configured by a cluster of defect sites that connect from the upper end to the lower end of randomly distributed defect sites. .
- the number and shape of the filaments 112 are formed stochastically. The distribution of the number and shape of the filaments 112 causes variations in the resistance value of the resistance change layer 104.
- an interlayer insulating film 102 having a thickness of 200 nm is formed on a substrate 101 made of single crystal silicon by a thermal oxidation method. Then, a Pt thin film having a thickness of 100 nm is formed on the interlayer insulating film 102 as the first electrode 103 by a sputtering method. Note that an adhesion layer of Ti, TiN, or the like may be formed between the first electrode 103 and the interlayer insulating film 102 by a sputtering method. Thereafter, an oxygen-deficient first metal oxide layer 104a is formed on the first electrode 103 by, for example, reactive sputtering using a Ta target.
- the first metal oxide layer 104a is subjected to a modification by oxidation of the outermost surface or a reactive sputtering method using a Ta target.
- a second metal oxide layer 104b having a lower degree of oxygen deficiency than the physical layer 104a is formed.
- the variable resistance layer 104 is configured by a stacked structure of the first metal oxide layer 104a and the second metal oxide layer 104b.
- the thickness of the second metal oxide layer 104b is preferably about 8 nm or less in order to appropriately reduce the initial resistance value, and is preferably about 1 nm or more in order to obtain a stable resistance change.
- the thickness of the second metal oxide layer 104b is 6 nm.
- a Pt thin film having a thickness of 150 nm is formed as the second electrode 105 on the second metal oxide layer 104b by a sputtering method.
- the nonvolatile memory element 100 in which the resistance change layer 104 using the oxygen-deficient Ta oxide is sandwiched between the first electrode 103 and the second electrode 105 can be manufactured.
- ⁇ Resistance value setting> A resistance change was caused by applying an electric pulse signal between the first electrode 103 and the second electrode 105 of the nonvolatile memory element 100.
- a voltage pulse is used as an electrical pulse signal.
- the positive and negative voltages are expressed with reference to the first electrode 103. That is, the voltage when a high voltage is applied to the second electrode 105 is “positive” with respect to the first electrode 103, and the voltage when a low voltage is applied to the second electrode 105 is also “negative”. ".
- the nonvolatile memory element 100 increases in resistance when a positive voltage is applied, and decreases in resistance when a negative voltage is applied.
- the load resistor 202 is connected for the following two reasons. One is that by connecting the load resistor 202, the set resistance value of the nonvolatile memory element 201 is changed, and information on a wide resistance range can be obtained.
- the sample used in this embodiment has a characteristic that the low resistance value of the nonvolatile memory element 201 is equivalent to the load resistance 202, and the high resistance value is about 10 to 100 times the low resistance value. I often take it. Therefore, if the load resistance 202 is reduced, the resistance value of the nonvolatile memory element 201 to be set can be reduced. Conversely, if the load resistance 202 is increased, the resistance value can be increased.
- the second reason is that it is assumed to grasp the fluctuation phenomenon of the resistance value when the nonvolatile memory element 201 is actually used.
- a variable resistance nonvolatile memory element it is not used alone in actual use, but is used in a state where a transistor, a diode, and the like having a certain resistance value are connected.
- the load resistor 202 is connected assuming these external load resistors that occur during actual use.
- the resistance value of the nonvolatile memory element 201 was set to the high resistance state (resistance value RH) and the low resistance state (resistance value RL).
- RH high resistance state
- RL low resistance state
- +2.5 V and ⁇ 2.0 V voltage pulses were alternately applied 100 times, and finally a +2.5 V voltage pulse was applied once.
- a voltage pulse of ⁇ 2.0 V was finally applied once.
- the pulse width here was 100 ns.
- the nonvolatile memory element 201 having the resistance value set as described above was held at room temperature, and a voltage of 50 mV was applied every 20 seconds to measure the resistance value of the nonvolatile memory element 201. Note that the resistance value of the nonvolatile memory element 201 does not change at such a low voltage of about 50 mV.
- FIG. 4 shows a change in the resistance value of the nonvolatile memory element 201 from 0 seconds to 50000 seconds after setting the nonvolatile memory element 201 to the high resistance state with a 6.4 k ⁇ load resistance connected (that is, It is a figure which shows a fluctuation.
- the resistance value of the nonvolatile memory element 201 immediately after setting the nonvolatile memory element 201 to the high resistance state is referred to as a set resistance value.
- the set resistance value was about 170 k ⁇ . Referring to FIG. 4, it can be seen that this resistance value increases and decreases with time and causes a fluctuation phenomenon.
- the minimum value is 150 k ⁇ in about 2000 seconds from the start of measurement, and the maximum value is 250 k ⁇ in about 20000 seconds.
- FIG. 4 shows the fluctuation of the resistance value after setting to the high resistance state, but the present inventor has confirmed a similar fluctuation phenomenon of the resistance value even when the resistance value is set to the low resistance state.
- the horizontal axis indicates the set resistance value of the nonvolatile memory element 201.
- the vertical axis represents the maximum value or the minimum value among the resistance values of the nonvolatile memory element 201 that have fluctuated between 0 seconds and 50000 seconds after the high resistance state is set.
- the data indicated by the black circle mark is the maximum resistance value
- the data indicated by the white circle mark is the minimum resistance value.
- the result of fitting the respective data is also shown.
- the solid line is the result of fitting the maximum resistance value
- the broken line is the result of fitting the minimum resistance value.
- the resistance change phenomenon occurs when a minute filament is formed in the resistance change layer 104, an oxidation-reduction reaction occurs in the minute filament, and the resistance value of the resistance change layer 104 changes. It is done. Therefore, it is considered that the fluctuation phenomenon discovered by the present inventors is also caused by a change in the conduction state in the minute filament due to some influence. Specifically, it is considered that fluctuations may occur due to incomplete bonding or separation of oxygen atoms. In addition, there is a possibility that the electric potential is changed and the resistance state is fluctuated by electrons being captured or released by dangling bonds existing in the minute filament. Therefore, if it is a variable resistance nonvolatile memory element having a structure in which the resistance value increases or decreases in relation to a minute filament, the fluctuation phenomenon inevitably occurs although there is a magnitude of that level. It is guessed.
- the present inventors have newly found the following properties relating to the fluctuation phenomenon.
- the voltage pulse for inducing the fluctuation phenomenon is desirably a voltage value with which the current flowing through the nonvolatile memory element is 1 ⁇ A or more.
- a voltage pulse for inducing the above-described fluctuation phenomenon is expressed as a fluctuation determination voltage pulse.
- the fluctuation phenomenon is induced by the fluctuation determination voltage pulse in the nonvolatile memory element that is likely to fluctuate, and the fluctuation phenomenon is not induced even if the fluctuation determination voltage pulse is applied to the nonvolatile memory element that is less likely to fluctuate.
- FIG. 6 shows an example of how the resistance value of the nonvolatile memory element varies due to the fluctuation determination voltage pulse.
- the left side of FIG. 6 shows a current distribution (horizontal axis) and a normal distribution of current values obtained by applying a fluctuation determination voltage pulse after setting the nonvolatile memory element 100 to a high resistance state and then performing a reading process.
- FIG. 6 shows a current distribution (horizontal axis) and a normal distribution of current values obtained by applying a fluctuation determination voltage pulse after setting the nonvolatile memory element 100 to a low resistance state and then performing a reading process. It is a figure which shows the relationship with (normal expected value; vertical axis
- a high resistance write voltage pulse of +2.5 V and 200 ns is used, and in order to set the nonvolatile memory element 100 to the low resistance state ⁇
- a voltage pulse of 200 ns at +700 mV is used as a fluctuation determination voltage pulse for inducing a fluctuation phenomenon with a low resistance value
- a voltage of 200 ns at -700 mV as a fluctuation determination voltage pulse for inducing a fluctuation phenomenon with a high resistance value. Each pulse was used.
- FIG. 6 also shows a case where a readout process is performed without applying a fluctuation determination voltage pulse (a set of plots labeled “0V” in the figure) as a comparison target.
- a fluctuation determination voltage pulse (a set of plots labeled “0V” in the figure) as a comparison target.
- the current value is increased by applying the +700 mV fluctuation determination voltage pulse (that is, the resistance value of the nonvolatile memory element 100 is increased). (Decrease).
- the current value is decreased by applying the fluctuation determination voltage pulse of ⁇ 700 mV (that is, the resistance value of the nonvolatile memory element 100 is increased). Can be confirmed.
- the resistance value of the nonvolatile memory element can be varied by using the fluctuation determination voltage pulse.
- the set resistance value changes greatly as a result of applying the fluctuation determination voltage pulse so that a data read error occurs, it can be said that the nonvolatile memory element is in a state where it is likely to fluctuate.
- the set resistance value does not change as a result of applying the fluctuation determination voltage pulse, or if the set resistance value changes only within a range where no data read error occurs, the nonvolatile memory element is in a state in which it is difficult to fluctuate. I can say that.
- the fluctuation determination voltage pulse it can be determined whether or not the nonvolatile memory element is in a state in which it is likely to fluctuate.
- FIG. 7A is a flowchart showing a procedure of data write processing of the nonvolatile memory element according to Embodiment 1 of the present invention.
- HR writing high resistance state
- LR writing low resistance state
- the HR writing process is executed (S102).
- a positive writing voltage pulse for example, +2.0 V
- a fluctuation determination voltage pulse is applied between both electrodes (S103).
- the fluctuation determination voltage pulse is a voltage pulse having the same polarity as the voltage pulse for HR writing and having a smaller absolute voltage value than the voltage pulse for HR writing.
- the fluctuation determination voltage pulse in step S103 is, for example, + 0.7V.
- the writing process using the fluctuation determination voltage pulse is referred to as a fluctuation determination writing process.
- a fluctuation determination voltage pulse having a positive polarity (that is, the same polarity as the voltage pulse for HR writing) is used in the fluctuation determination writing process.
- a positive fluctuation determination voltage pulse is applied between both electrodes, electrons are emitted from the filament formed in the resistance change layer 104, and as a result, the conduction path is recovered and the resistance value is lowered.
- the action of lowering the resistance value works by the positive polarity fluctuation determination voltage pulse, the low resistance fluctuation phenomenon is induced in the nonvolatile memory element 100 in the high resistance state.
- a voltage pulse for reading is applied between both electrodes, the value of the current flowing through the resistance change layer 104 is detected at that time, and whether the nonvolatile memory element 100 is in a high resistance state or a low resistance state
- a verify read process is executed to determine whether or not (S104). Then, based on the result of the verify read process, it is determined whether or not the high resistance state set by the HR write process in step S102 is lost, that is, whether or not the nonvolatile memory element 100 is easily fluctuated. (S108).
- step S101 If it is determined in step S101 that the HR writing is not performed, that is, if it is determined that the LR writing is performed (NO in S101), the LR writing process is executed (S105).
- LR writing for example, a negative voltage pulse for writing (for example, ⁇ 2.4 V) is applied between the first electrode 103 and the second electrode 105.
- a fluctuation determination voltage pulse is applied between both electrodes (S106).
- the fluctuation determination voltage pulse is a voltage pulse having the same polarity as the voltage pulse for LR writing and having a smaller absolute voltage value than the voltage pulse for LR writing.
- the fluctuation determination voltage pulse in S106 is, for example, ⁇ 0.7V.
- a fluctuation determination voltage pulse having a negative polarity (that is, the same polarity as the voltage pulse for LR writing) is used in the fluctuation determination writing process.
- a negative fluctuation determination voltage pulse is applied between both electrodes, electrons are injected into the filament formed in the resistance change layer 104. As a result, the conduction path is cut off and the resistance value is increased.
- the fluctuation phenomenon is induced in the nonvolatile memory element 100 in the low resistance state.
- the verify read process similar to the above S104 is executed (S107). Then, based on the result of the verify read process, it is determined whether or not the low resistance state set by the LR writing in step S105 is lost, that is, whether or not the nonvolatile memory element 100 is in a state in which it is likely to fluctuate. (S108).
- S107 when it is determined by the verify read process (S107) that the nonvolatile memory element 100 is not in a low resistance state but in a high resistance state, that is, when it is determined that the nonvolatile memory element 100 is likely to fluctuate (in S108). YES), a rewriting process is performed in which a voltage pulse for LR writing is applied again between both electrodes (S109).
- the nonvolatile memory element 100 can be reset to a desired low resistance state.
- the verify read process S107
- the nonvolatile memory element 100 is maintained in the low resistance state by the verify read process (S107)
- the nonvolatile memory element 100 is not in a state that is likely to fluctuate (NO in S108). The process ends.
- FIG. 7B corresponds to a summary of the procedure in the flowchart of FIG. 7A. That is, a flowchart is shown in which processing for HR writing and processing for LR writing are made common.
- a first voltage pulse (a voltage pulse for writing) for changing the resistance state of the nonvolatile memory element 100 from the first state to the second state between the first electrode 103 and the second electrode 105.
- first application step S120 the writing process (S102 or S105 in FIG. 7A) is performed.
- a second voltage pulse (fluctuation determination) between the first electrode 103 and the second electrode 105 having the same polarity as the first voltage pulse and having a smaller absolute voltage value than the first voltage pulse.
- Voltage pulse is applied (second application step S121). That is, the fluctuation determination writing process (S103 or S106 in FIG. 7A) is performed.
- step S122 it is determined whether or not the resistance state of the nonvolatile memory element 100 is the second state. That is, the verify read process (S104 or S107 in FIG. 7A) and the ease of fluctuation determination (S108 in FIG. 7A) are performed.
- the nonvolatile memory element is interposed between the first electrode 103 and the second electrode 105.
- a third voltage pulse (write voltage pulse) for changing the resistance state of 100 from the first state to the second state is applied (third application step S123). That is, rewrite processing (S109 in FIG. 7A) is performed.
- the process ends.
- the first state corresponds to the low resistance state
- the second state corresponds to the high resistance state
- the first state corresponds to the high resistance state
- the second state corresponds to the low resistance state.
- the third voltage pulse typically has the same voltage value as the first voltage pulse, but in order to ensure more rewriting, the absolute value of the voltage value compared to the first voltage pulse. May be large.
- the second application step S121 and the determination step S122 may be repeated after the third application step S123. That is, the third application step S123, the second application step S121, and the determination step S122 may be repeated until it is determined in the determination step S122 that the resistance state of the nonvolatile memory element 100 is the second state.
- FIG. 8A is a figure for demonstrating the application state of the voltage pulse in HR writing.
- FIG. 8B is a diagram for explaining a voltage pulse application state in LR writing.
- a positive electrode having an absolute value and a voltage value lower than that in the HR write process between the HR write process (S102) and the verify read process (S104).
- the fluctuation determination writing process (S103) for writing the characteristic voltage pulse is executed.
- the rewrite process S109
- the fluctuation determination writing process (S106) for writing the voltage pulse is executed. Then, when it is determined that the nonvolatile memory element 100 is in a state that is likely to fluctuate based on the result of the verify read process, the rewrite process (S109) is executed.
- the fluctuation determination writing is performed after normal writing, and when it is determined that the nonvolatile memory element 100 is in a state in which it is likely to fluctuate, By performing rewriting, the data retention characteristics can be improved.
- FIG. 9 shows an effective voltage (“effective element voltage” on the horizontal axis) applied to the nonvolatile memory element when a positive voltage pulse is applied to the nonvolatile memory element in the high resistance state, and the nonvolatile memory element. It is a figure which shows an example of the relationship with the electric current value (vertical axis) of the electric current which flows through a memory element, and FIG. 10 shows the resistance value (vertical axis
- the voltage value V1 of the fluctuation determination voltage pulse is + 0.6V or more.
- the voltage value V1 of the fluctuation determination voltage pulse is + 1.3V or less. From the above, it is desirable that the voltage value V1 of the fluctuation determination voltage pulse used at the time of HR writing satisfies 0.6V ⁇
- the absolute value of the voltage value of the second voltage pulse is the first electrode when the resistance state of the nonvolatile memory element 100 is the high resistance state.
- the voltage is not less than the minimum voltage (here, 0.6 V) at which current starts to flow through the nonvolatile memory element 100, and the resistance state of the nonvolatile memory element 100 Is a maximum voltage (in this case, 1.3 V) that does not cause dielectric breakdown of the nonvolatile memory element 100 when a voltage is applied between the first electrode 103 and the second electrode 105 in a high resistance state. It is desirable that
- FIG. 11 shows the effective voltage (the “effective element voltage” on the horizontal axis) applied to the nonvolatile memory element and the nonvolatile memory when a negative voltage pulse is applied to the nonvolatile memory element alone in the low resistance state. It is a figure which shows an example of the relationship with the electric current value (vertical axis) of the electric current which flows through a memory element.
- the voltage value V2 of the fluctuation determination voltage pulse is ⁇ 0.05 V or more (in absolute value).
- the voltage value V2 of the fluctuation determination voltage pulse is ⁇ 0.75 V or less (in absolute value). From the above, it is desirable that the voltage value V2 of the fluctuation determination voltage pulse used in the LR writing satisfies 0.05V ⁇
- the absolute value of the voltage value of the second voltage pulse is the first electrode when the resistance state of the nonvolatile memory element 100 is the low resistance state.
- the voltage is not less than the minimum voltage (here, 0.05 V) at which current starts to flow in the nonvolatile memory element 100, and the resistance state of the nonvolatile memory element 100 Is the maximum voltage that does not cause the progress of lowering the resistance of the nonvolatile memory element 100 when a voltage is applied between the first electrode 103 and the second electrode 105 (here, 0.75 V) or less.
- the second embodiment is a one-transistor / 1-nonvolatile memory unit type (so-called 1T1R type) nonvolatile memory device that is configured using the nonvolatile memory element described in the first embodiment.
- FIG. 12 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- the nonvolatile memory device 300 of this embodiment includes a memory cell array 301 including nonvolatile memory elements R311 to R322, an address buffer 302, a control unit 303, a row decoder 304, a word line A driver 305, a column decoder 306, and a bit line / plate line driver 307 are provided.
- the bit line / plate line driver 307 includes a sense circuit (sense amplifier), and can measure a current flowing through the bit line or the plate line.
- the memory cell array 301 includes two word lines W1 and W2 extending in parallel to each other, two bit lines B1 and B2 extending in parallel to each other across the word lines W1 and W2, and the bit lines B1, Four memory cells provided in a matrix corresponding to the intersections of two plate lines P1, P2 provided in one-to-one correspondence with B2, and word lines W1, W2 and bit lines B1, B2.
- MC311, MC312, MC321, and MC322 are provided.
- the memory cells MC311, MC312, MC321, and MC322 have a selection transistor T311 and a nonvolatile memory element R311, a selection transistor T312 and a nonvolatile memory element R312, a selection transistor T321 and a nonvolatile memory element R321, and a selection transistor T322 and a nonvolatile memory, respectively.
- the memory element R322 is constituted.
- the nonvolatile memory elements R311 to R322 correspond to the nonvolatile memory element 100 according to the first embodiment.
- the number or number of each of these components is not limited to the above.
- the number of memory cells included in the memory cell array 301 is not limited to the above four, and may be five or more.
- the plate line is arranged in parallel with the bit line, but the plate line may be arranged in parallel with the word line.
- the plate line is configured to apply a common potential to the connected transistors, but has a source line selection circuit and a driver having the same configuration as the row decoder 304 and the word line driver 305, and the selected source line and A configuration may be adopted in which the non-selected source line is driven with a different voltage (including polarity).
- the configuration of the memory cell array 301 will be further described.
- the memory cell MC311 selection transistor T311 and nonvolatile memory element R3111 is provided between the bit line B1 and the plate line P1, and the source of the selection transistor T311 and the nonvolatile memory cell MC311 are nonvolatile.
- the memory elements R311 are arranged in series to be connected. More specifically, the selection transistor T311 is connected to the bit line B1 and the nonvolatile memory element R311 between the bit line B1 and the nonvolatile memory element R311.
- the nonvolatile memory element R311 is connected to the selection transistor T311 and the plate.
- a selection transistor T311 and a plate line P1 are connected to the line P1.
- the gate of the selection transistor T311 is connected to the word line W1. Since the other memory cells MC312, MC321, and MC322 have the same configuration, description thereof is omitted.
- the address buffer 302 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 304 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 306.
- the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC311 to MC322.
- the row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS
- the column address signal COLUMN is also a signal indicating a column address.
- the address buffer 302, the row decoder 304, the word line driver 305, the column decoder 306, and the bit line / plate line driver 307 are each one memory cell (to be written or read) from the memory cell array 301 ( Alternatively, a selection circuit for selecting a nonvolatile memory element is configured.
- the control unit 303 selects any one of the write mode, the erase mode, and the read mode in accordance with the mode selection signal MODE received from the external circuit, and performs control corresponding to the selected mode.
- the write mode refers to bringing the nonvolatile memory element into a low resistance state
- the erase mode refers to bringing the nonvolatile memory element into a high resistance state
- the read mode refers to Reading data from the nonvolatile memory element (determining the resistance state of the nonvolatile memory element).
- each voltage is applied with reference to the plate line.
- control unit 303 In the write mode, the control unit 303 outputs a control signal CONT instructing “application of write voltage” to the bit line / plate line driver 307 in accordance with the input data Din received from the external circuit. Further, in this write mode, the control unit 303 outputs a control signal CONT instructing “application of first fluctuation determination voltage” to the bit line / plate line driver 307.
- the control unit 303 In the read mode, the control unit 303 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 307. In this read mode, the control unit 303 further receives a signal IREAD output from the bit line / plate line driver 307 and outputs output data Dout indicating a bit value corresponding to the signal IREAD to an external circuit.
- This signal IREAD is a signal indicating the current value of the current flowing through the plate lines P1 and P2 in the read mode.
- control unit 303 In the erase mode, the control unit 303 outputs a control signal CONT instructing “application of erase voltage” to the bit line / plate line driver 307. Further, in this erase mode, the control unit 303 outputs a control signal CONT instructing “application of second fluctuation determination voltage” to the bit line / plate line driver 307.
- control unit 303 performs the same process as in the read mode in order to perform the verify read process.
- the row decoder 304 receives the row address signal ROW output from the address buffer 302, and selects one of the two word lines W1 and W2 according to the row address signal ROW.
- the word line driver 305 applies an activation voltage to the word line selected by the row decoder 304 based on the output signal of the row decoder 304.
- the column decoder 306 receives the column address signal COLUMN output from the address buffer 302, selects one of the two bit lines B1 and B2 according to the column address signal COLUMN, and selects the selected bit line. One of the two plate lines P1 and P2 corresponding to is selected.
- bit line / plate line driver 307 When the bit line / plate line driver 307 receives the control signal CONT instructing “application of write voltage” from the control unit 303, the bit line / plate line driver 307 is selected as the bit line selected by the column decoder 306 based on the output signal of the column decoder 306. A write voltage VWRITE (write voltage pulse) is applied to the plate line.
- the bit line / plate line driver 307 receives the control signal CONT instructing “application of the first fluctuation determination voltage” from the control unit 303, the first fluctuation determination voltage VFLUC1 (between the same bit line and the plate line). First fluctuation determination voltage pulse) is applied.
- the bit line / plate line driver 307 When the bit line / plate line driver 307 receives the control signal CONT instructing “application of read voltage” from the control unit 303, the bit line / plate line driver 307 determines the bit line selected by the column decoder 306 based on the output signal of the column decoder 306. A read voltage VREAD (read voltage pulse) is applied between the selected plate line. Thereafter, the bit line / plate line driver 307 outputs a signal IREAD indicating the current value of the current flowing through the plate line to the control unit 303.
- IREAD read voltage pulse
- bit line / plate line driver 307 when the bit line / plate line driver 307 receives a control signal CONT instructing “application of erase voltage” from the control unit 303, the bit line / plate line driver 307 determines the bit line selected by the column decoder 306 based on the output signal of the column decoder 306. An erase voltage VRESET (write voltage pulse) is applied between the selected plate line.
- the bit line / plate line driver 307 receives the control signal CONT instructing “application of the second fluctuation determination voltage” from the controller 303, the second fluctuation determination voltage VFLUC2 (between the same bit line and the plate line). 2nd fluctuation determination voltage pulse) is applied.
- the voltage values of the write voltage VWRITE and the first fluctuation determination voltage VFLUC1 are set to, for example, -2.4 V and -0.7 V, respectively, and their pulse widths are set to 100 ns.
- the voltage value of the read voltage VREAD is set to + 0.4V, for example.
- the voltage values of the erase voltage VRESET and the second fluctuation determination voltage VFLUC2 are set to, for example, +2.0 V and +0.7 V, respectively, and their pulse widths are set to 100 ns.
- the address signal ADDRESS is a signal indicating the address of the memory cell MC311.
- the control unit 303 executes S105 to S109 described with reference to FIG. 7A in the first embodiment in the write mode. Specifically, the control unit 303 outputs a control signal CONT instructing the “write voltage application” and the “first fluctuation determination voltage” to the bit line / plate line driver 307 in this order. As a result, the “LR write process” (S105) and the “fluctuation determination write process” (S106) are performed on the memory cell MC311.
- control unit 303 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 307, and then is indicated by the signal IREAD received from the bit line / plate line driver 307. It is determined whether or not the current value corresponds to the current value of the current that flows when the nonvolatile memory element R311 is in the low resistance state. In this way, the “verify read process” (S107) is executed. Based on the result of the verify read process, the control unit 303 determines whether or not the low resistance state set by the previous LR write is lost, that is, the nonvolatile memory element R311 of the memory cell MC311 is likely to fluctuate. It is determined whether or not (S108).
- the control unit 303 outputs the control signal CONT instructing “application of write voltage” to the bit line / plate line driver 307 again.
- the “rewrite process” (S109) is executed for the memory cell MC311.
- the control unit 303 ends the process on the memory cell MC311 without performing the “rewrite process”.
- the control unit 303 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 307 in the read mode. Receiving this, the bit line / plate line driver 307 applies a read voltage VREAD (read voltage pulse) between the bit line B1 and the plate line P1, and then indicates a current value of the current flowing through the plate line P1. IREAD is output to the control unit 303.
- READ read voltage pulse
- the control unit 303 determines the output data Dout corresponding to the current value indicated by the signal IREAD received from the bit line / plate line driver 307, and outputs it to the outside.
- the control unit 303 when the current value indicated by IREAD corresponds to the current value of the current that flows when the nonvolatile memory element R311 is in the low resistance state, the control unit 303 outputs the output data indicating “1”. Dout is output.
- the control unit 303 outputs the output data Dout indicating “0”.
- the control unit 303 executes steps S102 to S104, S108, and S109 described with reference to FIG. 7A in the first embodiment in the erase mode. Specifically, the control unit 303 outputs a control signal CONT instructing the “erase voltage application” and the “second fluctuation determination voltage” to the bit line / plate line driver 307 in this order. As a result, the “HR write process” (S102) and the “fluctuation determination write process” (S103) are performed on the memory cell MC311.
- control unit 303 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 307, and then is indicated by the signal IREAD received from the bit line / plate line driver 307. It is determined whether or not the current value corresponds to the current value of the current that flows when the nonvolatile memory element R311 is in the high resistance state. In this way, the “verify read process” (S104) is executed. Based on the result of the verify read process, the control unit 303 determines whether or not the high resistance state set by the previous HR write is lost, that is, the nonvolatile memory element R311 of the memory cell MC311 is likely to fluctuate. It is determined whether or not (S108).
- the control unit 303 outputs the control signal CONT instructing “application of erase voltage” to the bit line / plate line driver 307 again.
- the “rewrite process” (S109) is executed for the memory cell MC311.
- the control unit 303 ends the process on the memory cell MC311 without performing the “rewrite process”.
- the nonvolatile memory device 300 in this embodiment includes (1) the first electrode 103, the second electrode 105, the first electrode 103, and the second electrode as main components.
- Non-volatile memory element R311 and the like having a resistance change layer 104 made of a metal oxide and a functional component between (2) the first electrode 103 and the second electrode 105
- a first voltage pulse (write voltage pulse) for changing the resistance state of the nonvolatile memory element R311 or the like from the first state to the second state is applied, and then the first electrode 103 and A writing unit that applies a second voltage pulse (fluctuation determination voltage pulse) having the same polarity as that of the first voltage pulse and having a smaller absolute value than the first voltage pulse between the second electrodes 105;
- a determination unit that determines whether the resistance state of the nonvolatile memory element R311 or the like is the second state after the voltage pulse of 2 is applied; and (4) the determination unit determines whether the nonvolatile memory element R311 or the like is in the second state
- the resistance state of the nonvolatile memory element R311 or the like is changed from the first state to the second state between the first electrode 103 and the second electrode 105.
- the writing unit, the determination unit, and the rewriting unit are mainly realized by the control unit 303 and the bit line / plate line driver 307.
- the third embodiment is a cross-point type nonvolatile memory device configured using the nonvolatile memory element described in the first embodiment.
- the cross-point type nonvolatile storage device is a storage device in a mode in which an active layer is interposed at an intersection (a three-dimensional intersection) between a word line and a bit line. The configuration and operation of this nonvolatile memory device will be described below.
- FIG. 13 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 3 of the present invention.
- the nonvolatile memory device 400 of this embodiment includes a memory cell array 401 including nonvolatile memory elements R11 to R33, an address buffer 402, a control unit 403, a row decoder 404, a word A line driver 405, a column decoder 406, and a bit line driver 407 are provided.
- the bit line driver 407 includes a sense circuit, and can measure a current flowing through the bit line.
- the memory cell array 401 includes a plurality of word lines W1, W2, and W3 formed so as to extend in parallel with each other, and bit lines formed so as to cross these word lines W1, W2, and W3 and extend in parallel with each other. B1, B1, and B3.
- the word lines W1, W2, and W3 are formed in a first plane parallel to the main surface of the substrate (not shown), and the bit lines B1, B1, and B3 are formed from the first plane. It is formed in a second plane located above or below and substantially parallel to the first plane.
- the word lines W1, W2, and W3 and the bit lines B1, B1, and B3 are three-dimensionally crossed, and a plurality of memory cells MC11, MC12, MC13, MC21, MC22, MC23, and MC31 correspond to the three-dimensional intersection.
- MC32, MC33 (hereinafter referred to as “memory cells MC11, MC12,...”) are provided.
- Each of the memory cells MC11, MC12,... Has a non-volatile memory element R11, R12, R13, R21, R22, R23, R31, R32, R33 connected in series and a current composed of, for example, a bidirectional diode.
- Control elements D11, D12, D13, D21, D22, D23, D31, D32, and D33 are provided.
- These nonvolatile storage elements R11 to R33 are connected to the bit lines B1, B1, and B3, and the current control elements D11 to D33 are connected to the nonvolatile storage elements and the word lines W1, W2, and W3.
- the nonvolatile memory elements R11 to R22 correspond to the nonvolatile memory element 100 according to the first embodiment.
- MIM Metal Insulator Metal
- MSM Metal Semiconductor Metal
- the address buffer 402 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 404 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 406.
- the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC11, MC12,.
- the row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is also a signal indicating a column address.
- the address buffer 402, the row decoder 404, the word line driver 405, the column decoder 406, and the bit line driver 407 are read from the memory cell array 401 by one memory cell (or nonvolatile memory).
- a selection circuit for selecting a storage element for selecting a storage element.
- the control unit 403 selects one of the write mode, the erase mode, and the read mode according to the mode selection signal MODE received from the external circuit, and performs control corresponding to the selected mode.
- each voltage is applied with reference to the bit line.
- control unit 403 sends the write voltage pulse, the first fluctuation determination voltage pulse, the erase voltage pulse, and the second fluctuation determination voltage pulse to the word line according to the input data Din received from the external circuit. Output to the driver 405.
- the control unit 403 In the read mode, the control unit 403 outputs a read voltage pulse to the word line driver 405. In this read mode, the control unit 403 further detects the current value of the current flowing between the bit line B2 and the word line W2, and outputs output data Dout indicating the bit value corresponding to the current value to the external circuit. .
- control unit 303 performs the same process as in the read mode in order to perform the verify read process.
- the row decoder 404 receives the row address signal ROW output from the address buffer 402, and selects any one of the word lines W1, W2, and W3 according to the row address signal ROW.
- the word line driver 405 applies a predetermined voltage to the word line selected by the row decoder 404 based on the output signal of the row decoder 404.
- the column decoder 406 receives the column address signal COLUMN output from the address buffer 402, and selects any one of the bit lines B1, B2, and B3 according to the column address signal COLUMN.
- the bit line driver 407 sets the bit line selected by the column decoder 406 to the ground state based on the output signal of the column decoder 406.
- a multilayer cross-point nonvolatile memory device may be formed by stacking memory cell arrays.
- the positional relationship between the nonvolatile memory element and the current control element may be interchanged. That is, the word line may be connected to the nonvolatile memory element, and the bit line may be connected to the current control element.
- bit line and / or the word line may also serve as an electrode in the nonvolatile memory element.
- the on-resistance of the current control element (diode) constituting the memory cell is higher than the on-resistance of the transistor, the voltage applied to the memory cell in each mode is the memory cell constituted by the transistor. Higher than the case.
- the control unit 403 executes S105 to S109 described with reference to FIG. 7A in the first embodiment. Specifically, when data representing “1” is written to the memory cell MC22, the bit line B2 is grounded by the bit line driver 407, and the word line W2 and the control unit 403 are electrically connected by the word line driver 405. Is done. Then, the control unit 403 applies a write voltage pulse to the word line W2, and further applies a first fluctuation determination voltage pulse to the word line W2. As a result, the “LR write process” (S105) and the “fluctuation determination write process” (S106) are performed on the memory cell MC22.
- control unit 403 outputs a read voltage pulse to the word line W2 via the word line driver 405, and then the current value of the current flowing between the bit line B2 and the word line W2 (in the memory cell MC22). Current value corresponding to the resistance value of the nonvolatile memory element R22). Then, the control unit 403 determines whether or not the current value corresponds to the current value of the current that flows when the nonvolatile memory element R22 is in the low resistance state. In this way, the “verify read process” (S107) is executed.
- the control unit 403 determines whether or not the low resistance state set by the previous LR writing is lost, that is, the nonvolatile memory element R22 of the memory cell MC22 is likely to fluctuate. It is determined whether or not (S108). As a result, when it is determined that the nonvolatile memory element R22 is in a state in which it is likely to fluctuate, the control unit 403 again outputs a write voltage pulse to the word line W2. As a result, the “rewrite process” (S109) is executed for the memory cell MC22. On the other hand, when it is determined that the nonvolatile memory element R22 is not in a state in which it is likely to fluctuate, the control unit 403 ends the process on the memory cell MC22 without performing the “rewrite process”.
- a current having a current value corresponding to the resistance value of the nonvolatile memory element R22 of the memory cell MC22 flows between the bit line B2 and the word line W2.
- the control unit 403 detects the current value of the current, and determines the resistance state of the nonvolatile memory element R22 based on the current value.
- the nonvolatile memory element R22 is in a low resistance state, it can be seen that the data written in the memory cell MC22 is “1”.
- the high resistance state it can be seen that the data written in the memory cell MC22 is “0”.
- the control unit 403 executes S102 to S104, S108, and S109 described with reference to FIG. 7A in the first embodiment. Specifically, when data representing “0” is written in the memory cell MC22, the bit line B2 is grounded by the bit line driver 407, and the word line W2 and the control unit 403 are electrically connected by the word line driver 405. Is done. Then, the control unit 403 applies an erase voltage pulse to the word line W2, and further applies a second fluctuation determination voltage pulse to the word line W2. As a result, the “HR write process” (S102) and the “fluctuation determination write process” (S103) are performed on the memory cell MC22.
- control unit 403 outputs a read voltage pulse to the word line W2 via the word line driver 405, and then the current value of the current flowing between the bit line B2 and the word line W2 (in the memory cell MC22). Current value corresponding to the resistance value of the nonvolatile memory element R22). Then, the control unit 403 determines whether or not the current value corresponds to the current value of the current that flows when the nonvolatile memory element R22 is in the high resistance state. In this way, the “verify read process” (S104) is executed.
- the control unit 403 determines whether or not the high resistance state set by the previous HR writing is lost, that is, the nonvolatile memory element R22 of the memory cell MC22 is likely to fluctuate. It is determined whether or not (S108). As a result, when it is determined that the nonvolatile memory element R22 is in a state in which it is likely to fluctuate, the control unit 403 outputs the erase voltage pulse to the word line W2 again. As a result, the “rewrite process” (S109) is executed for the memory cell MC22. On the other hand, when it is determined that the nonvolatile memory element R22 is not in a state in which it is likely to fluctuate, the control unit 403 ends the process on the memory cell MC22 without performing the “rewrite process”.
- the nonvolatile memory device 400 in this embodiment includes (1) the first electrode 103, the second electrode 105, the first electrode 103, and the second electrode as main components.
- Non-volatile memory element R11 and the like having a resistance change layer 104 made of a metal oxide, and a functional component between (2) the first electrode 103 and the second electrode 105.
- a first voltage pulse (write voltage pulse) for changing the resistance state of the nonvolatile memory element R11 or the like from the first state to the second state is applied to the first electrode 103 and A writing unit for applying a second voltage pulse (fluctuation determination voltage pulse) having the same polarity as the first voltage pulse and having a smaller absolute voltage value than the first voltage pulse between the second electrodes 105; (3) Second A determination unit that determines whether or not the resistance state of the nonvolatile memory element R11 or the like is the second state after the voltage pulse is applied; and (4) the resistance state of the nonvolatile memory element R11 or the like by the determination unit.
- the resistance state of the nonvolatile memory element R11 and the like is changed between the first electrode 103 and the second electrode 105 from the first state to the second state.
- the writing unit, the determination unit, and the rewriting unit are mainly realized by the control unit 403 and the bit line driver 407.
- the fluctuation determination voltage pulse is written in both HR writing and LR writing. However, it may be performed only in either case. In particular, since it has been observed that the fluctuation phenomenon of the resistance value appears more markedly in the high resistance state than in the low resistance state, the fluctuation determination voltage pulse is written only in the case of HR writing. You may do it.
- the example in which the voltage pulse having the same condition as that in the normal write process (S102 or S105) is applied to the rewrite process (S109) has been described.
- the pulse is not limited to this.
- the absolute value of the voltage value of the voltage pulse in the rewriting process may be larger than the voltage pulse in the normal writing process. This ensures the rewriting.
- the configuration of the nonvolatile memory device for example, the rewrite unit
- the nonvolatile memory element data writing method and nonvolatile memory device of the present invention are useful as a nonvolatile memory element data writing method and memory device used in various electronic devices such as personal computers and portable telephones, respectively. .
- Nonvolatile memory element 101
- Substrate 102
- Interlayer insulating film 103
- First electrode 104
- Resistance change layer 104a
- First metal oxide layer 104b
- Second metal oxide layer 105
- Second Electrode 202
- Column decoder 307 Bit line / Plate line driver
- Bit line driver MC11 to MC33
- Memory cell T311 to T322 Select transistor D11 to D33
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Abstract
Description
[不揮発性記憶素子の構成]
図1Aは、本発明の実施の形態1に係る不揮発性記憶素子の構成を示す断面図である。
次に、本実施の形態の不揮発性記憶素子100の製造方法の一例について説明する。なお、以下で説明する、各工程における手法、材料、膜厚、その他の条件等についてはあくまでも例示であり、本実施の形態はこれに限定されない。
以下では、上述のようにして作製された不揮発性記憶素子100の抵抗状態の保持特性について、本発明者等が実験によって新たに見出した知見について詳細に説明する。なお、以下で説明する、電圧値、パルス幅、印加回数、抵抗値等はあくまでも、当該知見を説明する実験例を示すものであり、本実施の形態はこれに限定されない。
不揮発性記憶素子100の第1の電極103及び第2の電極105間に電気的パルス信号を与えることにより抵抗変化を起こさせた。以下では、電気的パルス信号として電圧パルスを用いた場合について説明する。なお、本明細書では、第1の電極103を基準にして電圧の正負を表現する。すなわち、第1の電極103に対して、高い電圧を第2の電極105に印加した場合の電圧は“正”であり、同じく低い電圧を第2の電極105に印加した場合の電圧は“負”である。不揮発性記憶素子100は、正の電圧が与えられた場合に高抵抗化し、負の電圧が与えられた場合に低抵抗化する。
上述したようにして抵抗値を設定した不揮発性記憶素子201を室温に保持し、20秒毎に50mVの電圧を印加して不揮発性記憶素子201の抵抗値を測定した。なお、このような50mV程度の低い電圧では、不揮発性記憶素子201の抵抗値は変化しない。
上述したように、抵抗変化現象は、抵抗変化層104中に微小なフィラメントが形成され、この微小なフィラメント中で酸化還元反応が起こり、抵抗変化層104の抵抗値が変化することによって発生すると考えられる。したがって、今回発明者等が発見した揺らぎ現象も、この微小なフィラメント中の導通状態が何らかの影響で変化することにより発生していると考えられる。具体的には、酸素原子が不完全な結合をしたり、乖離をしたりすることで揺らぎが発生している可能性があると考えられる。また、微小なフィラメント内に存在するダングリングボンドに電子が捕獲されたり、放出されたりすることで、電気的なポテンシャルが変化して抵抗状態が揺らいでいる可能性も考えられる。したがって、微小なフィラメントが関係して抵抗値が増減するような構造を有する抵抗変化型の不揮発性記憶素子であれば、その程度の大小はあるものの、揺らぎ現象は必然的に発生するものであると推測される。
本実施の形態のデータ書き込み方法は、上述の新規の知見に基づいて見出されたものである。以下に、本実施の形態のデータ書き込み方法について説明する。
以下、HR書き込み及びLR書き込みの際に用いられる揺らぎ判定電圧パルスの電圧値の望ましい範囲について説明する。
実施の形態2は、実施の形態1において説明した不揮発性記憶素子を用いて構成される、1トランジスタ/1不揮発性記憶部型(いわゆる1T1R型)の不揮発性記憶装置である。
図12は、本発明の実施の形態2に係る不揮発性記憶装置の構成の一例を示すブロック図である。図12に示すとおり、本実施の形態の不揮発性記憶装置300は、不揮発性記憶素子R311~R322を具備するメモリセルアレイ301と、アドレスバッファ302と、制御部303と、行デコーダ304と、ワード線ドライバ305と、列デコーダ306と、ビット線/プレート線ドライバ307とを備えている。また、ビット線/プレート線ドライバ307はセンス回路(センスアンプ)を備えており、ビット線またはプレート線に流れる電流を測定することができる。
以下、上述しように構成される不揮発性記憶装置300の動作例を、上記の書き込みモード、読み出しモード、及び消去モードの各モードに分けて説明する。
制御部303は、書き込みモードにおいて、実施の形態1において図7Aを参照しながら説明したS105~S109を実行する。具体的に説明すると、制御部303は、ビット線/プレート線ドライバ307に対して、「書き込み電圧印加」及び「第1揺らぎ判定電圧」をそれぞれ指示する制御信号CONTをこの順に出力する。これにより、メモリセルMC311に対して、「LR書き込み処理」(S105)及び「揺らぎ判定書き込み処理」(S106)が行われることになる。
制御部303は、読み出しモードにおいて、「読み出し電圧印加」を指示する制御信号CONTをビット線/プレート線ドライバ307に出力する。これを受けたビット線/プレート線ドライバ307は、ビット線B1とプレート線P1との間に読み出し電圧VREAD(読み出し電圧パルス)を印加し、その後、プレート線P1に流れる電流の電流値を示す信号IREADを制御部303に出力する。
制御部303は、消去モードにおいて、実施の形態1において図7Aを参照しながら説明したステップS102~S104、S108及びS109を実行する。具体的に説明すると、制御部303は、ビット線/プレート線ドライバ307に対して、「消去電圧印加」及び「第2揺らぎ判定電圧」をそれぞれ指示する制御信号CONTをこの順に出力する。これにより、メモリセルMC311に対して、「HR書き込み処理」(S102)及び「揺らぎ判定書き込み処理」(S103)が行われることになる。
実施の形態3は、実施の形態1において説明した不揮発性記憶素子を用いて構成される、クロスポイント型の不揮発性記憶装置である。ここで、クロスポイント型の不揮発性記憶装置とは、ワード線とビット線との交点(立体交差点)にアクティブ層を介在させた態様の記憶装置である。以下、この不揮発性記憶装置の構成及び動作について説明する。
図13は、本発明の実施の形態3に係る不揮発性記憶装置の構成の一例を示すブロック図である。図13に示すように、本実施の形態の不揮発性記憶装置400は、不揮発性記憶素子R11~R33を具備するメモリセルアレイ401と、アドレスバッファ402と、制御部403と、行デコーダ404と、ワード線ドライバ405と、列デコーダ406と、ビット線ドライバ407とを備えている。また、ビット線ドライバ407はセンス回路を具備しており、ビット線に流れる電流を測定することができる。
次に、上述したように構成された不揮発性記憶装置400の動作例を、書き込みモード、消去モード及び呼び出しモードの各モードに分けて説明する。なお、ビット線及びワード線を選択する方法、並びに電圧パルスを印加する方法等については、周知のものが利用可能であるため、詳細な説明を省略する。
制御部403は、書き込みモードにおいて、実施の形態1において図7Aを参照しながら説明したS105~S109を実行する。具体的に説明すると、メモリセルMC22に“1”を表すデータを書き込む場合、ビット線ドライバ407によりビット線B2が接地され、ワード線ドライバ405によりワード線W2と制御部403とが電気的に接続される。そして、制御部403によって、ワード線W2に書き込み電圧パルスが印加され、さらに、ワード線W2に第1揺らぎ判定電圧パルスが印加される。これにより、メモリセルMC22に対して、「LR書き込み処理」(S105)及び「揺らぎ判定書き込み処理」(S106)が行われることになる。
メモリセルMC22に書き込まれているデータを読み出す場合、ビット線ドライバ407によりビット線B2が接地され、ワード線ドライバ405によりワード線W2と制御部403とが電気的に接続される。そして、制御部403により、ワード線W2に読み出し電圧パルスが印加される。
制御部403は、消去モードにおいて、実施の形態1において図7Aを参照しながら説明したS102~S104、S108及びS109を実行する。具体的に説明すると、メモリセルMC22に“0”を表すデータを書き込む場合、ビット線ドライバ407によりビット線B2が接地され、ワード線ドライバ405によりワード線W2と制御部403とが電気的に接続される。そして、制御部403によって、ワード線W2に消去電圧パルスが印加され、さらに、ワード線W2に第2揺らぎ判定電圧パルスが印加される。これにより、メモリセルMC22に対して、「HR書き込み処理」(S102)及び「揺らぎ判定書き込み処理」(S103)が行われることになる。
上記の各実施の形態においては、HR書き込み及びLR書き込みの両方の場合に揺らぎ判定電圧パルスの書き込みを行っているが、いずれか一方の場合のみに行うようにしてもよい。特に、抵抗値の揺らぎ現象は低抵抗状態の場合よりも高抵抗状態の場合の方がより顕著に表れることが観察されていることから、HR書き込みの場合にのみ揺らぎ判定電圧パルスの書き込みを行うようにしてもよい。
101 基板
102 層間絶縁膜
103 第1の電極
104 抵抗変化層
104a 第1の金属酸化物層
104b 第2の金属酸化物層
105 第2の電極
202 負荷抵抗
203、204 端子
300、400 不揮発性記憶装置
301、401 メモリセルアレイ
302、402 アドレスバッファ
303、403 制御部
304、404 行デコーダ
305、405 ワード線ドライバ
306、406 列デコーダ
307 ビット線/プレート線ドライバ
407 ビット線ドライバ
MC11~MC33、MC311~MC322 メモリセル
T311~T322 選択トランジスタ
D11~D33 電流制御素子
Claims (26)
- 第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成される抵抗変化層とを備える不揮発性記憶素子のデータ書き込み方法であって、
前記第1の電極及び前記第2の電極間に、前記不揮発性記憶素子の抵抗状態を第1の状態から第2の状態へ変化させるための第1の電圧パルスを印加する第1の印加ステップと、
前記第1の印加ステップの後で、前記第1の電極及び前記第2の電極間に、前記第1の電圧パルスと同じ極性で、かつ前記第1の電圧パルスよりも電圧値の絶対値が小さい第2の電圧パルスを印加する第2の印加ステップと、
前記第2の印加ステップの後で、前記不揮発性記憶素子の抵抗状態が前記第2の状態であるか否かを判定する判定ステップと、
前記判定ステップで前記不揮発性記憶素子の抵抗状態が前記第2の状態でないと判定された場合、前記第1の電極及び前記第2の電極間に、前記不揮発性記憶素子の抵抗状態を前記第1の状態から前記第2の状態へ変化させるための第3の電圧パルスを印加する第3の印加ステップと
を含む不揮発性記憶素子のデータ書き込み方法。 - 前記第1の状態が低抵抗状態であり、前記第2の状態が前記低抵抗状態よりも前記不揮発性記憶素子の抵抗値が高い高抵抗状態である
請求項1に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第2の電圧パルスの電圧値の絶対値は、前記不揮発性記憶素子の抵抗状態が前記高抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子に電流が流れ始める最小の電圧以上であり、かつ、前記不揮発性記憶素子の抵抗状態が前記高抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子の絶縁破壊を引き起こすことがない最大の電圧以下である
請求項2に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記最小の電圧は、0.6Vであり、
前記最大の電圧は、1.3Vである
請求項3に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第1の状態が高抵抗状態であり、前記第2の状態が前記高抵抗状態よりも前記不揮発性記憶素子の抵抗値が低い低抵抗状態である
請求項1に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第2の電圧パルスの電圧値の絶対値は、前記不揮発性記憶素子の抵抗状態が前記低抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子に電流が流れ始める最小の電圧以上であり、かつ、前記不揮発性記憶素子の抵抗状態が前記低抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子の低抵抗化の進行を引き起こすことがない最大の電圧以下である
請求項5に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記最小の電圧は、0.05Vであり、
前記最大の電圧は、0.75Vである
請求項6に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第3の電圧パルスが、前記第1の電圧パルスと同じ電圧値である
請求項1~7のいずれか1項に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第3の電圧パルスが、前記第1の電圧パルスに比べて電圧値の絶対値が大きい
請求項1~7のいずれか1項に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記金属酸化物がタンタル酸化物である
請求項1~9のいずれか1項に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記不揮発性記憶素子は、前記第1の電極及び前記第2の電極間に印加される電圧パルスの極性に応じて、当該不揮発性記憶素子の抵抗状態が前記第1の状態から前記第2の状態、又は、前記第2の状態から前記第1の状態に遷移するバイポーラ型の記憶素子である
請求項1~10のいずれか1項に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記抵抗変化層は、第1の金属の酸化物を含む第1の金属酸化物層と、第2の金属の酸化物を含む第2の金属酸化物層とを含む積層構造を有し、
前記第1の金属酸化物層の酸素不足度は、前記第2の金属酸化物層の酸素不足度よりも大きい
請求項1~11のいずれか1項に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第2の金属酸化物層は、当該第2の金属酸化物層内に、局所的に高い電流密度の電流を流す電流経路であるフィラメントを有する
請求項12に記載の不揮発性記憶素子のデータ書き込み方法。 - 前記第2の金属酸化物層は、当該第2の金属酸化物層内に、局所的に高い酸素欠陥濃度をもつ領域を有する
請求項12に記載の不揮発性記憶素子のデータ書き込み方法。 - 第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成される抵抗変化層とを備える不揮発性記憶素子と、
前記第1の電極及び前記第2の電極間に、前記不揮発性記憶素子の抵抗状態を第1の状態から第2の状態へ変化させるための第1の電圧パルスを印加し、その後、前記第1の電極及び前記第2の電極間に、前記第1の電圧パルスと同じ極性で、かつ前記第1の電圧パルスよりも電圧値の絶対値が小さい第2の電圧パルスを印加する書き込み部と、
前記第2の電圧パルスが印加された後で、前記不揮発性記憶素子の抵抗状態が前記第2の状態であるか否かを判定する判定部と、
前記判定部により前記不揮発性記憶素子の抵抗状態が前記第2の状態でないと判定された場合、前記第1の電極及び前記第2の電極間に、前記不揮発性記憶素子の抵抗状態を前記第1の状態から前記第2の状態へ変化させるための第3の電圧パルスを印加する再書き込み部と
を備える不揮発性記憶装置。 - 前記第1の状態が低抵抗状態であり、前記第2の状態が前記低抵抗状態よりも前記不揮発性記憶素子の抵抗値が高い高抵抗状態である
請求項15に記載の不揮発性記憶装置。 - 前記第2の電圧パルスの電圧値の絶対値は、前記不揮発性記憶素子の抵抗状態が前記高抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子に電流が流れ始める最小の電圧以上であり、かつ、前記不揮発性記憶素子の抵抗状態が前記高抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子の絶縁破壊を引き起こすことがない最大の電圧以下である
請求項16に記載の不揮発性記憶装置。 - 前記最小の電圧は、0.6Vであり、
前記最大の電圧は、1.3Vである
請求項17に記載の不揮発性記憶装置。 - 前記第1の状態が高抵抗状態であり、前記第2の状態が前記高抵抗状態よりも前記不揮発性記憶素子の抵抗値が低い低抵抗状態である
請求項15に記載の不揮発性記憶装置。 - 前記第2の電圧パルスの電圧値の絶対値は、前記不揮発性記憶素子の抵抗状態が前記低抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子に電流が流れ始める最小の電圧以上であり、かつ、前記不揮発性記憶素子の抵抗状態が前記低抵抗状態である場合に前記第1の電極及び前記第2の電極間に電圧を印加したときに前記不揮発性記憶素子の低抵抗化の進行を引き起こすことがない最大の電圧以下である
請求項19に記載の不揮発性記憶装置。 - 前記最小の電圧は、0.05Vであり、
前記最大の電圧は、0.75Vである
請求項20に記載の不揮発性記憶装置。 - 前記金属酸化物がタンタル酸化物である
請求項15~21のいずれか1項に記載の不揮発性記憶装置。 - 前記不揮発性記憶素子は、前記第1の電極及び前記第2の電極間に印加される電圧パルスの極性に応じて、当該不揮発性記憶素子の抵抗状態が前記第1の状態から前記第2の状態、又は、前記第2の状態から前記第1の状態に遷移するバイポーラ型の記憶素子である
請求項15~22のいずれか1項に記載の不揮発性記憶装置。 - 前記抵抗変化層は、第1の金属の酸化物を含む第1の金属酸化物層と、第2の金属の酸化物を含む第2の金属酸化物層とを含む積層構造を有し、
前記第1の金属酸化物層の酸素不足度は、前記第2の金属酸化物層の酸素不足度よりも大きい
請求項15~23のいずれか1項に記載の不揮発性記憶装置。 - 前記第2の金属酸化物層は、当該第2の金属酸化物層内に、局所的に高い電流密度の電流を流す経路であるフィラメントを有する
請求項24に記載の不揮発性記憶装置。 - 前記第2の金属酸化物層は、当該第2の金属酸化物層内に、局所的に高い酸素欠陥濃度をもつ領域を有する
請求項24に記載の不揮発性記憶装置。
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