WO2013024842A1 - 半導体製造装置及び処理方法 - Google Patents
半導体製造装置及び処理方法 Download PDFInfo
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- WO2013024842A1 WO2013024842A1 PCT/JP2012/070630 JP2012070630W WO2013024842A1 WO 2013024842 A1 WO2013024842 A1 WO 2013024842A1 JP 2012070630 W JP2012070630 W JP 2012070630W WO 2013024842 A1 WO2013024842 A1 WO 2013024842A1
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- pins
- region
- end surface
- substrate
- processed
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000003672 processing method Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 230000007723 transport mechanism Effects 0.000 description 14
- 230000007246 mechanism Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
Definitions
- Various aspects of the present invention relate to a semiconductor manufacturing apparatus and a processing method.
- Patent Document 1 describes a semiconductor manufacturing apparatus.
- the semiconductor manufacturing apparatus described in Patent Document 1 includes a stage and a plurality of pins.
- the stage is provided with a plurality of holes, and a plurality of pins are inserted into the plurality of holes, respectively.
- Some of the plurality of pins are for raising and lowering the substrate to be processed placed on the stage with respect to the upper surface of the stage.
- the other part of the plurality of pins is for raising and lowering the focus ring placed on the stage relative to the upper surface of the stage.
- the semiconductor manufacturing apparatus described above requires a plurality of drive mechanisms for moving the pins up and down according to the number of pins. Therefore, the apparatus becomes complicated according to the number of pins.
- holes corresponding to the number of pins need to be formed in the stage. However, it is desirable that the number of holes formed in the stage is small.
- a semiconductor manufacturing apparatus includes a processing container, a stage, a plurality of pins, and a driving unit.
- the processing container defines a processing space.
- the stage is provided in the processing container.
- the stage includes a placement surface.
- the placement surface has a first area for placing the substrate to be processed and a second area for placing the focus ring.
- the second area is provided so as to surround the first area.
- a plurality of holes are formed in the stage.
- the plurality of holes extend in a direction intersecting the placement surface through the boundary between the first region and the second region.
- the plurality of pins are respectively provided in the plurality of holes.
- Each of the plurality of pins has a first upper end surface and a second upper end surface.
- the second upper end surface is provided above the first upper end surface, and is offset to the first region side with respect to the first upper end surface.
- the drive unit moves the plurality of pins up and down in the direction.
- the substrate to be processed is moved by moving the plurality of pins upward so that only the second upper end surface of the first upper end surface and the second upper end surface protrudes from the stage mounting surface. It can be lifted from the mounting surface. Further, the focus ring can be lifted from the mounting surface by moving the plurality of pins upward so that the first upper end surface protrudes from the mounting surface of the stage. That is, each pin has an end surface that contacts the substrate to be processed and an end surface that contacts the focus ring. Therefore, according to this semiconductor manufacturing apparatus, it is possible to raise and lower the substrate to be processed and the focus ring with a small number of pins.
- the semiconductor manufacturing apparatus may further include a control unit.
- the control unit controls the drive unit so that the second upper end surface of the first upper end surface and the second upper end surface of the plurality of pins protrudes from the placement surface
- the second mode The drive unit may be controlled so that the first upper end surfaces of the plurality of pins protrude from the stage mounting surface.
- the semiconductor manufacturing apparatus may include a control unit that controls the operation of the drive unit described above.
- a processing method is a processing method using the semiconductor manufacturing apparatus described above.
- the processing method includes (a) a step of placing a focus ring on the second region, (b) a step of placing a substrate to be processed on the first region, and (c) a step of placing on the first region.
- the focus ring is placed on the second region by moving a plurality of pins that simultaneously support the substrate to be processed and the focus ring above the placement surface, so that the first region A substrate to be processed may be placed thereon.
- the substrate to be processed and the focus ring may be simultaneously lifted from the placement surface by a plurality of pins, and then the substrate to be processed may be taken out from the processing vessel and the focus ring may be taken out from the processing vessel.
- a semiconductor manufacturing apparatus capable of moving a substrate to be processed and a focus ring up and down, and a processing method using the semiconductor manufacturing apparatus are provided.
- FIG. 1 It is a figure showing roughly the semiconductor manufacturing device concerning one embodiment. It is sectional drawing which expands and shows the stage of the semiconductor manufacturing apparatus shown in FIG. 1, a some pin, and a drive part. It is a flowchart which shows the processing method which concerns on one Embodiment. It is sectional drawing which shows the position of the pin in process S4 of FIG. It is sectional drawing which shows the position of the pin in process S6 of FIG. It is a flowchart which shows the processing method which concerns on another embodiment. It is sectional drawing which shows the position of the pin in process S6 of FIG.
- FIG. 1 is a diagram schematically showing a semiconductor manufacturing apparatus according to an embodiment.
- FIG. 1 shows a cross section of a semiconductor manufacturing apparatus according to an embodiment.
- FIG. 2 is an enlarged cross-sectional view showing the stage, the plurality of pins, and the drive unit of the semiconductor manufacturing apparatus shown in FIG.
- the semiconductor manufacturing apparatus 10 of one embodiment may be a parallel plate type plasma processing apparatus.
- the semiconductor manufacturing apparatus 10 includes a processing container 12.
- the processing container 12 has a substantially cylindrical shape and defines a processing space S as its internal space.
- the semiconductor manufacturing apparatus 10 includes a stage ST in the processing container 12.
- the stage ST includes a table 14 and an electrostatic chuck 50.
- the base 14 has a substantially disc shape and is provided below the processing space S.
- the base 14 is made of aluminum, for example, and constitutes a lower electrode.
- the semiconductor manufacturing apparatus 10 further includes a cylindrical holding part 16 and a cylindrical support part 17.
- the cylindrical holding portion 16 is in contact with the edge of the side surface and the bottom surface of the table 14 and holds the table 14.
- the cylindrical support portion 17 extends in the vertical direction from the bottom portion of the processing container 12 and supports the table 14 via the cylindrical holding portion 16.
- the semiconductor manufacturing apparatus 10 further includes a focus ring 18. As shown in FIG. 2, the focus ring 18 is placed on the upper surface of the peripheral portion of the table 14.
- the focus ring 18 is a member for improving the in-plane uniformity of the processing accuracy of the substrate W to be processed.
- the focus ring 18 is a plate-like member having a substantially ring shape, and can be made of, for example, silicon, quartz, or silicon carbide.
- an exhaust path 20 is formed between the side wall of the processing vessel 12 and the cylindrical support portion 17.
- a baffle plate 22 is attached to the inlet of the exhaust passage 20 or in the middle thereof.
- An exhaust port 24 is provided at the bottom of the exhaust path 20.
- the exhaust port 24 is defined by an exhaust pipe 28 fitted in the bottom of the processing container 12.
- An exhaust device 26 is connected to the exhaust pipe 28.
- the exhaust device 26 has a vacuum pump and can depressurize the processing space S in the processing container 12 to a predetermined degree of vacuum.
- a gate valve 30 that opens and closes the loading / unloading port for the substrate W to be processed is attached to the side wall of the processing container 12.
- a high frequency power source 32 for plasma generation is electrically connected to the table 14 via a matching unit 34.
- the high frequency power supply 32 applies high frequency power of a predetermined high frequency (for example, 13 MHz) to the lower electrode, that is, the table 14.
- the semiconductor manufacturing apparatus 10 further includes a shower head 38 in the processing container 12.
- the shower head 38 is provided above the processing space S.
- the shower head 38 includes an electrode plate 40 and an electrode support 42.
- the electrode plate 40 is a conductive plate having a substantially disk shape and constitutes an upper electrode.
- a high frequency power source 35 for plasma generation is electrically connected to the electrode plate 40 via a matching unit 36.
- the high frequency power source 35 applies high frequency power of a predetermined high frequency (for example, 60 MHz) to the electrode plate 40.
- a high frequency electric field is formed in the space between the table 14 and the electrode plate 40, that is, the processing space S.
- the electrode plate 40 has a plurality of gas vent holes 40h.
- the electrode plate 40 is detachably supported by an electrode support 42.
- a buffer chamber 42 a is provided inside the electrode support 42.
- the semiconductor manufacturing apparatus 10 further includes a gas supply unit 44, and the gas supply unit 44 is connected to the gas introduction port 25 of the buffer chamber 42a via a gas supply conduit 46.
- the gas supply unit 44 supplies a processing gas to the processing space S.
- This processing gas may be, for example, an etching processing gas or a film forming processing gas.
- the electrode support 42 is formed with a plurality of holes each continuous with the plurality of gas vent holes 40h, and the plurality of holes communicate with the buffer chamber 42a. The gas supplied from the gas supply unit 44 is supplied to the processing space S via the buffer chamber 42a and the gas vent hole 40h.
- a magnetic field forming mechanism 48 extending annularly or concentrically is provided on the ceiling of the processing vessel 12.
- the magnetic field forming mechanism 48 functions to facilitate the start of high-frequency discharge (plasma ignition) in the processing space S and maintain stable discharge.
- an electrostatic chuck 50 is provided on the upper surface of the table 14.
- the electrostatic chuck 50 includes an electrode 52 and a pair of insulating films 54a and 54b.
- the electrode 52 is a conductive film and is provided between the insulating film 54a and the insulating film 54b.
- a DC power source 56 is connected to the electrode 52 via a switch SW. When a DC voltage is applied to the electrode 52 from the DC power source 56, a Coulomb force is generated, and the substrate W to be processed is attracted and held on the electrostatic chuck 50 by the Coulomb force.
- the semiconductor manufacturing apparatus 10 further includes a gas supply line 58 and a heat transfer gas supply unit 62.
- the heat transfer gas supply unit 62 is connected to a gas supply line 58.
- the gas supply line 58 extends to the upper surface of the electrostatic chuck 50 and extends annularly on the upper surface.
- the heat transfer gas supply unit 62 supplies a heat transfer gas such as He gas between the upper surface of the electrostatic chuck 50 and the substrate W to be processed.
- the semiconductor manufacturing apparatus 10 further includes a control unit 66.
- the control unit 66 is connected to the exhaust device 26, the switch SW, the high frequency power supply 32, the matching unit 34, the high frequency power source 35, the matching unit 36, the gas supply unit 44, and the heat transfer gas supply unit 62.
- the control unit 66 sends control signals to the exhaust device 26, the switch SW, the high frequency power source 32, the matching unit 34, the high frequency power source 35, the matching unit 36, the gas supply unit 44, and the heat transfer gas supply unit 62, respectively.
- control unit 66 exhaust by the exhaust device 26, opening / closing of the switch SW, power supply from the high frequency power source 32, impedance adjustment of the matching unit 34, power supply from the high frequency power source 35, impedance adjustment of the matching unit 36, The supply of the processing gas by the gas supply unit 44 and the supply of the heat transfer gas by the heat transfer gas supply unit 62 are controlled.
- the processing gas is supplied from the gas supply unit 44 to the processing space S. Further, a high frequency electric field is formed between the electrode plate 40 and the table 14, that is, in the processing space S. As a result, plasma is generated in the processing space S, and the substrate to be processed W is processed by radicals of elements contained in the processing gas.
- the treatment of the substrate to be processed W can be any treatment, and may be, for example, etching of the substrate to be processed W or film formation on the substrate to be processed W, but is limited. It is not a thing.
- the stage ST has a placement surface PF.
- the placement surface PF includes a first region R1 and a second region R2.
- the first region R1 is a region for placing the substrate W to be processed.
- the first region R1 is defined by the upper surface of the electrostatic chuck 50 and is a substantially circular region.
- the second region R2 is a region for placing the focus ring 18, and is provided in an annular shape so as to surround the first region R1.
- the second region R ⁇ b> 2 is defined by the upper surface of the peripheral portion of the table 14.
- the stage ST is provided with a plurality of holes 14h.
- the plurality of holes 14h pass through the boundary between the first region R1 and the second region R2 and extend in a direction (vertical direction) intersecting the placement surface PF of the stage ST.
- the holes 14h are provided at equal intervals in the circumferential direction, and the number of the holes 14h is three or more.
- each pin 70 has a first upper end surface 70a and a second upper end surface 70b.
- each pin 70 includes a first columnar portion 70c and a second columnar portion 70d.
- the first columnar portion 70c is provided below the second columnar portion 70d.
- the diameter of the first columnar portion 70c is larger than the diameter of the second columnar portion 70d.
- the upper end surface of the first columnar portion 70c constitutes the first upper end surface 70a.
- the second columnar portion 70d extends upward from the upper end surface of the first columnar portion 70c.
- the upper end surface of the second columnar portion 70d constitutes the second upper end surface 70b.
- the central axis of the second columnar portion 70d is deviated toward the first region R1 side with respect to the central axis of the first columnar portion 70c. That is, the second upper end surface 70b is deviated toward the first region R1 with respect to the first upper end surface 70a. Thereby, even if each pin 70 moves upward, the upper end surface of the second columnar portion 70d does not come into contact with the focus ring 18.
- a seal such as an O-ring is provided between the second columnar portion 70c of each pin 70 and the surface of the base 14 that defines the corresponding hole 14h, that is, the inner surface that defines the hole 14h.
- a member 72 is provided. The hole 14h is sealed by the seal member 72, and as a result, the airtightness of the processing space S is ensured.
- a plurality of drive units 74 are connected to each of the plurality of pins 70.
- Each driving unit 74 generates a driving force that moves the corresponding pin 70 in the vertical direction, that is, moves up and down.
- An arbitrary drive mechanism that moves the pin 70 in the vertical direction can be employed for the plurality of drive units 74.
- the plurality of drive units 74 may have hydraulic or pneumatic cylinders.
- the control unit 66 described above may be connected to a plurality of drive units 74. That is, the movement of the plurality of pins 72 in the vertical direction may be controlled by a control signal supplied from the control unit 66 to the plurality of driving units 74.
- the control unit 66 in the first mode, is configured such that only the second upper end surface 70b of the first upper end surface 70a and the second upper end surface 70b of each pin 70 is upward from the placement surface PF.
- the drive of the plurality of pins 70 by the plurality of drive units 74 is controlled so as to protrude.
- the second upper end surfaces 70b of the plurality of pins 70 come into contact with the substrate to be processed W, and the substrate to be processed W is moved from the placement surface PF (first region R1) by the plurality of pins 70. Lifted.
- the substrate to be processed W lifted from the mounting surface PF is taken out of the processing container 12 from the gate valve 30 by a transport mechanism such as a robot arm.
- the control unit 66 controls the driving of the plurality of pins 70 by the plurality of driving units 74 so that the first upper end surface 70a of each pin 70 protrudes upward from the placement surface PF.
- the first upper end surfaces 70a of the plurality of pins 70 come into contact with the focus ring, and the focus ring 18 is lifted from the placement surface PF (second region R2) by the plurality of pins 70.
- the focus ring 18 lifted from the placement surface PF is taken out of the processing container 12 from the gate valve 30 by a transport mechanism such as a robot arm.
- each pin 70 has the second upper end surface 70b for lifting the substrate W to be processed upward and the first upper end surface 70a for lifting the focus ring 18 upward.
- FIG. 3 is a flowchart illustrating a processing method according to an embodiment.
- the processing method shown in FIG. 3 can be performed using the semiconductor manufacturing apparatus 10.
- the focus ring 18 can be placed on the second region R2 in step S1.
- the plurality of pins 70 are set in a state of being accommodated in the plurality of holes 14h, that is, in a state in which the second upper end surface 70b is positioned below the placement surface PF.
- the focus ring 18 is guided to a predetermined position in the processing space S, that is, above the second region R2 via the gate valve 30 by a transfer mechanism such as a robot arm.
- the plurality of pins 70 are moved upward so that the first upper end surface 70 a contacts the back surface of the focus ring 18.
- the plurality of pins 70 are moved downward. As a result, the focus ring 18 is placed on the second region R2.
- the substrate W to be processed can be placed on the first region R1.
- the plurality of pins 70 are set in a state of being accommodated in the plurality of holes 14h, that is, in a state in which the second upper end surface 70b is positioned below the placement surface PF.
- the substrate W to be processed is guided to a predetermined position in the processing space S, that is, above the first region R1, via the gate valve 30 by a transfer mechanism such as a robot arm.
- the plurality of pins 70 are moved upward so that the second upper end surface 70b is in contact with the back surface of the substrate W to be processed.
- the transport mechanism is moved to the outside of the processing container 12, the plurality of pins 70 are moved downward. Thereby, the to-be-processed base
- step S3 the substrate to be processed W is processed.
- step S3 arbitrary processing such as plasma etching or film formation is performed in the processing space S.
- FIG. 4 is a cross-sectional view showing the positions of the pins in step S4 of FIG.
- the second upper end surface 70 b is in contact with the back surface of the substrate to be processed W, and the plurality of pins 70 moves the substrate W to be processed from the placement surface PF (first region R ⁇ b> 1). lift.
- the first upper end surface 70a is located below the placement surface PF, that is, below the back surface of the focus ring 18.
- step S5 the substrate to be processed W is taken out of the processing container 12.
- a transport mechanism such as a robot arm is sent into the processing container 12 via the gate valve 30.
- the substrate W to be processed is held by the transport mechanism.
- the substrate W to be processed is taken out of the processing container 12 by the transport mechanism.
- the steps S2 to S5 can be performed one or more times while exchanging the substrate to be processed W.
- FIG. 5 is a cross-sectional view showing the positions of the pins in step S6 of FIG.
- step S ⁇ b> 6 the first upper end surface 70 a is in contact with the back surface of the focus ring 18, and the plurality of pins 70 lift the focus ring 18 from the placement surface PF (second region R ⁇ b> 2).
- the focus ring 18 is taken out of the processing container 12. Specifically, a transport mechanism such as a robot arm is sent into the processing container 12 via the gate valve 30. Next, the focus ring 18 is held by the transport mechanism. Next, after the plurality of pins 70 are moved downward so as not to interfere with the focus ring 18, the focus ring 18 is taken out of the processing container 12 by the transport mechanism. Thereby, the focus ring 18 to be replaced can be taken out from the processing container 12, and then the processing from step S1 can be repeated.
- a transport mechanism such as a robot arm is sent into the processing container 12 via the gate valve 30.
- the focus ring 18 is held by the transport mechanism.
- the focus ring 18 is taken out of the processing container 12 by the transport mechanism. Thereby, the focus ring 18 to be replaced can be taken out from the processing container 12, and then the processing from step S1 can be repeated.
- FIG. 6 is a flowchart showing a processing method according to another embodiment.
- the plurality of pins 70 are set in a state of being accommodated in the plurality of holes 14h, that is, in a state in which the second upper end surface 70b is positioned below the placement surface PF.
- the focus ring 18 is guided to a predetermined position in the processing space S via the gate valve 30 by the transfer mechanism such as a robot arm, that is, above the second region R2.
- the substrate W to be processed is guided to a predetermined position, that is, above the first region R1.
- the plurality of pins 70 are moved upward so that the first upper end surface 70a is in contact with the back surface of the focus ring 18 and the second upper end surface 70b is in contact with the back surface of the substrate W to be processed. Then, the transport mechanism is moved to the outside of the processing container 12. At this time, the target substrate W and the focus ring 18 are simultaneously supported by the plurality of pins 70 above the placement surface PF. Thereafter, the plurality of pins 70 are moved downward. Thereby, first, in step S1, the focus ring 18 is placed on the second region R2. Then, by moving the plurality of pins 70 further downward, the substrate W to be processed is placed on the first region R1 in step S2.
- step S6 is performed subsequent to step S4. That is, in another embodiment, in step S4, the plurality of pins 70 are moved upward, and the substrate to be processed W is lifted from the placement surface PF (first region R1) by the plurality of pins 70. In step S6 subsequent to step S4, the plurality of pins 70 are further moved upward, and the focus ring 18 is lifted from the placement surface PF (second region R2) by the plurality of pins 70.
- FIG. 7 is a cross-sectional view showing the positions of the pins in step S6 of FIG. When step S6 of FIG. 6 is performed, as shown in FIG.
- the second upper end surfaces 70b of the plurality of pins 70 are in contact with the back surface of the substrate W, and the first upper end surfaces 70a of the plurality of pins 70 are It contacts the back surface of the focus ring 18. At this time, the target substrate W and the focus ring 18 are simultaneously supported by the plurality of pins 70 above the placement surface PF.
- step S5 and step S7 are performed simultaneously. That is, a transport mechanism such as a robot arm is sent into the processing container 12 via the gate valve 30, and the substrate W and the focus ring 18 are held by the transport mechanism. Then, after the plurality of pins 70 are moved downward so as not to interfere with the focus ring 18, the substrate W and the focus ring 18 are taken out of the processing container 12 by the transport mechanism. Thus, the throughput can be improved by simultaneously lifting the substrate to be processed W and the focus ring 18 by the plurality of pins 70 and simultaneously taking them out of the processing container 12.
- the semiconductor manufacturing apparatus 10 described above is a parallel plate type plasma processing apparatus
- the above-described aspects of the present invention and the idea of the embodiment can be applied to a plasma processing apparatus having an arbitrary plasma generation source.
- the idea of the above-described aspects and embodiments of the present invention is not limited to the plasma processing apparatus, and the target substrate W is processed by placing the target substrate W and the focus ring on the stage in the processing space. It can be applied to any semiconductor manufacturing apparatus.
- SYMBOLS 10 Semiconductor manufacturing apparatus, 12 ... Processing container, 14 ... Stand, 14h ... Hole, 18 ... Focus ring, 50 ... Electrostatic chuck, 66 ... Control part, 70 ... Pin, 70a ... First upper end surface, 70b ... First 2 upper end surface, 70c ... first columnar portion, 70d ... second columnar portion, 72 ... sealing member, 74 ... driving unit, PF ... mounting surface, R1 ... first region, R2 ... second region , S: processing space, ST: stage, W: substrate to be processed.
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Abstract
Description
Claims (4)
- 処理空間を画成する処理容器と、
前記処理容器内に設けられたステージであって、被処理基体を載置するための第1の領域、及び、フォーカスリングを載置するための第2の領域であり該第1の領域を囲むように設けられた該第2の領域を有する載置面を含み、前記第1の領域と前記第2の領域との境界を通って前記載置面に交差する方向に延びる複数の孔が形成されている、該ステージと、
前記複数の孔内にそれぞれ設けられた複数のピンであって、各々が、第1の上端面、及び、該第1の上端面よりも上方に設けられており、該第1の上端面よりも前記第1の領域の側に偏位した第2の上端面を有する、該複数のピンと、
前記複数のピンを前記方向において上下動させる駆動部と、
を備える半導体製造装置。 - 第1のモードにおいて、前記複数のピンの前記第1の上端面及び前記第2の上端面のうち前記第2の上端面が前記載置面から突き出るよう、前記駆動部を制御し、第2のモードにおいて、前記複数のピンの前記第1の上端面が前記載置面から突き出るよう、前記駆動部を制御する制御部を更に備える、請求項1に記載の半導体製造装置。
- 半導体製造装置を用いた処理方法であって、
前記半導体製造装置は、
処理空間を画成する処理容器と、
前記処理容器内に設けられたステージであって、被処理基体を載置するための第1の領域、及び、フォーカスリングを載置するための第2の領域であり該第1の領域を囲むように設けられた該第2の領域を有する載置面を含み、前記第1の領域と前記第2の領域との境界を通って前記載置面に交差する方向に延びる複数の孔が形成されている、該ステージと、
前記複数の孔内にそれぞれ設けられた複数のピンであって、各々が、第1の上端面、及び、該第1の上端面よりも上方に設けられており、該第1の上端面よりも前記第1の領域の側に偏位した第2の上端面を有する、該複数のピンと、
前記複数のピンを前記方向において上下動させる駆動部と、
を備え、
前記第2の領域上にフォーカスリングを載置する工程と、
前記第1の領域上に被処理基体を載置する工程と、
第1の領域上に被処理基体が載置され、第2の領域上にフォーカスリングが載置された状態において、前記被処理基体を処理する工程と、
前記複数のピンの前記第1の上端面及び前記第2の上端面のうち前記第2の上端面が前記ステージの前記載置面から突き出るよう、該複数のピンを上方に移動させる工程と、
前記複数のピンによって持ち上げられた前記被処理基体を前記処理容器から取り出す工程と、
前記複数のピンの前記第1の上端面が前記載置面から突き出るよう、該複数のピンを上方に移動させる工程と、
前記複数のピンによって持ち上げられた前記フォーカスリングを前記処理容器から取り出す工程と、
を含む処理方法。 - 前記載置面の上方において前記被処理基体及び前記フォーカスリングを同時に支持した前記複数のピンを下方に移動させることにより、前記第2の領域上に前記フォーカスリングが載置され、前記第1の領域上に前記被処理基体が載置され、
前記複数のピンにより前記被処理基体及び前記フォーカスリングを同時に前記載置面から持ち上げた後に、前記被処理基体が前記処理容器から取り出され、前記フォーカスリングが前記処理容器から取り出される、
請求項3に記載の処理方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150364347A1 (en) * | 2014-06-13 | 2015-12-17 | Applied Materials, Inc. | Direct lift process apparatus |
CN111900118A (zh) * | 2020-06-19 | 2020-11-06 | 中国科学院微电子研究所 | 晶圆转移机构、半导体制造设备以及晶圆转移方法 |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016046451A (ja) * | 2014-08-26 | 2016-04-04 | 株式会社アルバック | 基板処理装置及び基板処理方法 |
CN105575863B (zh) * | 2014-11-10 | 2019-02-22 | 中微半导体设备(上海)有限公司 | 等离子体处理装置、基片卸载装置及方法 |
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US10658222B2 (en) | 2015-01-16 | 2020-05-19 | Lam Research Corporation | Moveable edge coupling ring for edge process control during semiconductor wafer processing |
US11605546B2 (en) | 2015-01-16 | 2023-03-14 | Lam Research Corporation | Moveable edge coupling ring for edge process control during semiconductor wafer processing |
US10957561B2 (en) | 2015-07-30 | 2021-03-23 | Lam Research Corporation | Gas delivery system |
US10825659B2 (en) | 2016-01-07 | 2020-11-03 | Lam Research Corporation | Substrate processing chamber including multiple gas injection points and dual injector |
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US10651015B2 (en) | 2016-02-12 | 2020-05-12 | Lam Research Corporation | Variable depth edge ring for etch uniformity control |
US10699878B2 (en) | 2016-02-12 | 2020-06-30 | Lam Research Corporation | Chamber member of a plasma source and pedestal with radially outward positioned lift pins for translation of a substrate c-ring |
US10438833B2 (en) | 2016-02-16 | 2019-10-08 | Lam Research Corporation | Wafer lift ring system for wafer transfer |
US11011353B2 (en) | 2016-03-29 | 2021-05-18 | Lam Research Corporation | Systems and methods for performing edge ring characterization |
US10312121B2 (en) | 2016-03-29 | 2019-06-04 | Lam Research Corporation | Systems and methods for aligning measurement device in substrate processing systems |
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US11011355B2 (en) * | 2017-05-12 | 2021-05-18 | Lam Research Corporation | Temperature-tuned substrate support for substrate processing systems |
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US11075105B2 (en) | 2017-09-21 | 2021-07-27 | Applied Materials, Inc. | In-situ apparatus for semiconductor process module |
US10950483B2 (en) * | 2017-11-28 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Systems and methods for fixed focus ring processing |
US11043400B2 (en) | 2017-12-21 | 2021-06-22 | Applied Materials, Inc. | Movable and removable process kit |
US11121010B2 (en) | 2018-02-15 | 2021-09-14 | Tokyo Electron Limited | Plasma processing apparatus |
JP7018331B2 (ja) * | 2018-02-23 | 2022-02-10 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
US10600623B2 (en) | 2018-05-28 | 2020-03-24 | Applied Materials, Inc. | Process kit with adjustable tuning ring for edge uniformity control |
US11935773B2 (en) | 2018-06-14 | 2024-03-19 | Applied Materials, Inc. | Calibration jig and calibration method |
US11289310B2 (en) | 2018-11-21 | 2022-03-29 | Applied Materials, Inc. | Circuits for edge ring control in shaped DC pulsed plasma process device |
JP7134104B2 (ja) * | 2019-01-09 | 2022-09-09 | 東京エレクトロン株式会社 | プラズマ処理装置およびプラズマ処理装置の載置台 |
KR102370471B1 (ko) * | 2019-02-08 | 2022-03-03 | 주식회사 히타치하이테크 | 플라스마 처리 장치 |
US11101115B2 (en) | 2019-04-19 | 2021-08-24 | Applied Materials, Inc. | Ring removal from processing chamber |
US12009236B2 (en) | 2019-04-22 | 2024-06-11 | Applied Materials, Inc. | Sensors and system for in-situ edge ring erosion monitor |
TWM593655U (zh) * | 2019-05-10 | 2020-04-11 | 美商蘭姆研究公司 | 半導體製程模組的中環 |
WO2020232074A1 (en) | 2019-05-14 | 2020-11-19 | Mattson Technology, Inc. | Plasma processing apparatus having a focus ring adjustment assembly |
JP7345289B2 (ja) * | 2019-06-18 | 2023-09-15 | 東京エレクトロン株式会社 | 基板処理装置、基板処理システム及び基板搬送方法 |
CN112563186A (zh) * | 2019-09-26 | 2021-03-26 | 东京毅力科创株式会社 | 基片支承器和等离子体处理装置 |
KR102301191B1 (ko) * | 2019-10-15 | 2021-09-10 | (주)에스티아이 | 기판처리장치 |
JP7192756B2 (ja) * | 2019-12-19 | 2022-12-20 | 株式会社Sumco | 気相成長装置及び気相成長方法 |
JP7455012B2 (ja) * | 2020-07-07 | 2024-03-25 | 東京エレクトロン株式会社 | プラズマ処理装置およびプラズマ処理装置の載置台 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07305168A (ja) * | 1994-03-18 | 1995-11-21 | Anelva Corp | 基板の機械的脱離機構およびその機構を用いた脱離方法 |
JPH08227934A (ja) * | 1994-10-18 | 1996-09-03 | Applied Materials Inc | 静電チャックを備えたチャンバのためのプラズマガード |
JPH11111822A (ja) * | 1997-10-06 | 1999-04-23 | Toshiba Corp | ウェーハチャック装置 |
JP2007073589A (ja) * | 2005-09-05 | 2007-03-22 | Matsushita Electric Ind Co Ltd | 半導体製造装置および半導体ウエハ処理方法 |
JP2009302482A (ja) * | 2008-06-17 | 2009-12-24 | Tokyo Electron Ltd | 処理装置 |
JP2011054933A (ja) * | 2009-08-07 | 2011-03-17 | Tokyo Electron Ltd | 基板処理装置及び位置決め方法並びにフォーカスリング配置方法 |
JP2011151263A (ja) * | 2010-01-22 | 2011-08-04 | Tokyo Electron Ltd | エッチング方法、エッチング装置及びリング部材 |
JP2011238825A (ja) * | 2010-05-12 | 2011-11-24 | Tokyo Electron Ltd | プラズマ処理装置及び半導体装置の製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5352294A (en) * | 1993-01-28 | 1994-10-04 | White John M | Alignment of a shadow frame and large flat substrates on a support |
US5708556A (en) * | 1995-07-10 | 1998-01-13 | Watkins Johnson Company | Electrostatic chuck assembly |
JP2713276B2 (ja) * | 1995-12-07 | 1998-02-16 | 日本電気株式会社 | 半導体装置の製造装置およびこれを用いた半導体装置の製造方法 |
JP3234576B2 (ja) * | 1998-10-30 | 2001-12-04 | アプライド マテリアルズ インコーポレイテッド | 半導体製造装置におけるウェハ支持装置 |
JP2002134596A (ja) * | 2000-10-25 | 2002-05-10 | Tokyo Electron Ltd | 処理装置 |
US6776849B2 (en) * | 2002-03-15 | 2004-08-17 | Asm America, Inc. | Wafer holder with peripheral lift ring |
TW200415681A (en) * | 2002-10-17 | 2004-08-16 | Matsushita Electric Ind Co Ltd | Plasma processing apparatus |
US7730737B2 (en) * | 2004-12-21 | 2010-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cooling station lifter pins |
JP2006196691A (ja) * | 2005-01-13 | 2006-07-27 | Toshiba Corp | 半導体製造装置及び半導体装置の製造方法 |
US7824146B2 (en) * | 2007-09-07 | 2010-11-02 | Advanced Technology Development Facility | Automated systems and methods for adapting semiconductor fabrication tools to process wafers of different diameters |
JP4858395B2 (ja) * | 2007-10-12 | 2012-01-18 | パナソニック株式会社 | プラズマ処理装置 |
WO2009155117A2 (en) * | 2008-05-30 | 2009-12-23 | Applied Materials, Inc. | Method and apparatus for detecting the substrate temperature in a laser anneal system |
JP2010087473A (ja) * | 2008-07-31 | 2010-04-15 | Canon Anelva Corp | 基板位置合わせ装置及び基板処理装置 |
US8034723B2 (en) * | 2009-12-25 | 2011-10-11 | Tokyo Electron Limited | Film deposition apparatus and film deposition method |
CN103081088B (zh) * | 2010-08-06 | 2016-04-06 | 应用材料公司 | 静电夹盘和使用静电夹盘的方法 |
JP6003011B2 (ja) * | 2011-03-31 | 2016-10-05 | 東京エレクトロン株式会社 | 基板処理装置 |
-
2011
- 2011-08-17 JP JP2011178494A patent/JP5948026B2/ja active Active
-
2012
- 2012-08-13 KR KR1020197024401A patent/KR102077438B1/ko active IP Right Grant
- 2012-08-13 US US14/238,860 patent/US9859146B2/en active Active
- 2012-08-13 WO PCT/JP2012/070630 patent/WO2013024842A1/ja active Application Filing
- 2012-08-13 KR KR1020147003894A patent/KR20140050664A/ko active Application Filing
- 2012-08-16 TW TW101129651A patent/TWI528485B/zh active
-
2017
- 2017-12-21 US US15/850,875 patent/US10699935B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07305168A (ja) * | 1994-03-18 | 1995-11-21 | Anelva Corp | 基板の機械的脱離機構およびその機構を用いた脱離方法 |
JPH08227934A (ja) * | 1994-10-18 | 1996-09-03 | Applied Materials Inc | 静電チャックを備えたチャンバのためのプラズマガード |
JPH11111822A (ja) * | 1997-10-06 | 1999-04-23 | Toshiba Corp | ウェーハチャック装置 |
JP2007073589A (ja) * | 2005-09-05 | 2007-03-22 | Matsushita Electric Ind Co Ltd | 半導体製造装置および半導体ウエハ処理方法 |
JP2009302482A (ja) * | 2008-06-17 | 2009-12-24 | Tokyo Electron Ltd | 処理装置 |
JP2011054933A (ja) * | 2009-08-07 | 2011-03-17 | Tokyo Electron Ltd | 基板処理装置及び位置決め方法並びにフォーカスリング配置方法 |
JP2011151263A (ja) * | 2010-01-22 | 2011-08-04 | Tokyo Electron Ltd | エッチング方法、エッチング装置及びリング部材 |
JP2011238825A (ja) * | 2010-05-12 | 2011-11-24 | Tokyo Electron Ltd | プラズマ処理装置及び半導体装置の製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150364347A1 (en) * | 2014-06-13 | 2015-12-17 | Applied Materials, Inc. | Direct lift process apparatus |
US9978632B2 (en) * | 2014-06-13 | 2018-05-22 | Applied Materials, Inc. | Direct lift process apparatus |
CN111900118A (zh) * | 2020-06-19 | 2020-11-06 | 中国科学院微电子研究所 | 晶圆转移机构、半导体制造设备以及晶圆转移方法 |
CN111900118B (zh) * | 2020-06-19 | 2023-04-07 | 中国科学院微电子研究所 | 晶圆转移机构、半导体制造设备以及晶圆转移方法 |
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