WO2012131898A1 - 炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置 Download PDFInfo
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- WO2012131898A1 WO2012131898A1 PCT/JP2011/057787 JP2011057787W WO2012131898A1 WO 2012131898 A1 WO2012131898 A1 WO 2012131898A1 JP 2011057787 W JP2011057787 W JP 2011057787W WO 2012131898 A1 WO2012131898 A1 WO 2012131898A1
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- insulating film
- gate insulating
- silicon carbide
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- metal oxide
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 70
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 69
- 239000004065 semiconductor Substances 0.000 title claims description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 42
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 25
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 23
- 238000000034 method Methods 0.000 description 20
- 238000005468 ion implantation Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 229960001730 nitrous oxide Drugs 0.000 description 2
- 235000013842 nitrous oxide Nutrition 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a silicon carbide semiconductor device.
- Silicon carbide is a material that can reduce the loss of FET (Field Effect Transistor) because the dielectric breakdown electric field is about 10 times larger than Si, and the drift layer that maintains the breakdown voltage can be made thin and highly concentrated. It is. For this reason, MOSFETs (Metal Oxide Semiconductor FETs) using SiC are attracting attention as next-generation high breakdown voltage / low loss switching devices.
- FET Field Effect Transistor
- reference numeral 1 denotes an n + substrate serving as a drain region
- 2 denotes an n ⁇ drift layer
- 3 denotes a p base region
- 4 denotes a p + contact region
- 5 denotes an n + source region
- 6 denotes a gate insulating film
- 7 denotes a gate.
- An electrode, 8 is an interlayer insulating film for electrically insulating the source / gate
- 9 is a source electrode
- 10 is a drain electrode.
- the quality of the interface between SiC and the gate insulating film is one of the factors that have a great influence on the device performance of this MOSFET.
- silicon dioxide is generally used by a method such as thermal oxidation or chemical vapor deposition (CVD), but there are many interface states at the so-called MOS interface of silicon dioxide / silicon carbide. Since (trap) exists, the channel mobility becomes very low, the on-resistance of the element increases, and there is a problem that the loss during the on operation increases.
- Patent Document 2 reports a method in which an oxide film is formed by a deposition method after direct heat treatment of SiC using dinitrogen monoxide gas (N 2 O) or nitrogen monoxide (NO).
- N 2 O dinitrogen monoxide gas
- NO nitrogen monoxide
- Non-Patent Document 1 reports a method of forming a gate insulating film after performing nitrogen implantation on a SiC substrate.
- Patent Document 3 reports a method of forming 0.3 to 0.9 nm of SiO 2 as a gate insulating film on a SiC substrate and depositing aluminum oxide on the SiC substrate at a temperature of 300 degrees or less and 10 to 100 nm. Yes.
- SiO 2 is formed as a gate insulating film on a SiC substrate, and then a high dielectric film is deposited, and further SiO 2 is deposited thereon. Methods for depositing and improving dielectric breakdown properties have been reported.
- a silicon carbide semiconductor including a silicon carbide substrate, a gate insulating film formed on the silicon carbide substrate, a gate electrode formed on the gate insulating film, and a MOSFET having a source region formed on the silicon carbide substrate
- nitrogen introduced into the channel region of the MOSFET or the interface between the silicon carbide substrate and the gate insulating film, and a metal oxide film having a thickness of 10% or less of the thickness of the gate insulating film in the gate insulating film.
- the threshold voltage (Vth) of the MOSFET can be shifted in the positive direction. That is, it is possible to realize both high mobility and normally-off when combined with a means for improving the mobility by introducing nitrogen into the channel region or the SiC substrate interface of the SiC substrate.
- Vth threshold voltage
- a metal oxide film having a thickness of 10% or less of the thickness of the gate insulating film it is possible to provide a silicon carbide semiconductor device that achieves both high mobility and normally-off and has higher reliability. be able to.
- FIG. 4 is the film thickness dependence of the mobility of the SiC MOSFET according to one embodiment of the present invention.
- FIG. 5 is a relationship between the threshold (Vth) shift amount of the SiC MOSFET according to one embodiment of the present invention and the ratio of the aluminum oxide film thickness to the entire gate insulating film.
- 3 shows the relationship between the gate voltage shift amount after electrical stress of the SiC MOSFET according to one embodiment of the present invention and the ratio of the aluminum oxide film thickness to the entire gate insulating film. It is sectional drawing which showed the outline of SiC MOSFET in connection with Example 2 of this invention.
- FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to Example 1 of the present invention.
- reference numeral 1 denotes an n + substrate serving as a drain region
- 2 denotes an n ⁇ drift layer
- 3 denotes a p base region
- 4 denotes a p + contact region
- 5 denotes an n + source region
- 6 denotes a gate insulating film
- 7 denotes a gate.
- An electrode, 8 is an interlayer insulating film for electrically insulating the source / gate
- 9 is a source electrode
- 10 is a drain electrode.
- reference numerals 1 and 2 may be collectively referred to as a SiC substrate, and nitrogen is introduced into the surface (channel region) of the n ⁇ drift layer 2 or the interface between the gate insulating film and the SiC substrate.
- the gate insulating film 6 is composed of a laminated film in which a first gate insulating film 6a, a metal oxide film 6b, and a second gate insulating film 6c are sequentially formed from the SiC substrate side.
- the second gate insulating film 6c is made of, for example, a silicon oxide film
- the metal oxide film 6b is made of, for example, a metal oxide film such as aluminum oxide.
- the film thickness of the first gate insulating film 6a is 3 nm or more, and the metal oxide film 6b is separated from the surface of the SiC substrate by 3 nm or more.
- the total film thickness of the gate insulating film 6 is not less than 30 nm and not more than 100 nm.
- the thickness ratio of the metal oxide film 6b to the entire gate insulating film 6 is 10% or less.
- a substrate on which an n ⁇ drift layer 2 is laminated on an SiC substrate 1 is prepared.
- the n ⁇ drift layer 2 formed on the SiC substrate 1 is patterned with an ion implantation mask material, and Al is ion-implanted to form the p-type base region 3.
- the ion implantation conditions at this time are a dose of 3 ⁇ 10 13 cm ⁇ 2 .
- the p-type base region 3 is formed with a doping concentration of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 3.0 ⁇ m.
- an ion implantation mask material is patterned on the surfaces of the n ⁇ drift layer 2 and the p-type base region 3, and Al is ion-implanted to form the p + contact region 4.
- the nitrogen to form a n + source region 5 Ion implantation.
- the ion implantation masking agent is patterned, and nitrogen is ion-implanted only into the n ⁇ drift layer 2 (channel region). Thereby, nitrogen is introduced into the channel region.
- the first gate insulating film 6a is formed by thermal oxidation within a process temperature range of about 1000 to 1300 degrees.
- the first gate insulating film 6a is formed using NO gas or N 2 O gas, for example. Thereby, nitrogen is introduced into the interface between the SiC substrate and the gate insulating film.
- the film thickness of the first gate insulating film 6a is 3 nm or more.
- a metal oxide film 6b and a second gate insulating film are sequentially formed.
- the thickness of the metal oxide film 6b is 10% or less of the entire thickness of the gate insulating film 6.
- the entire thickness of the gate insulating film 6 is not less than 30 nm and not more than 100 nm.
- the metal oxide film is, for example, aluminum oxide.
- the gate electrode 7 is formed from polycrystalline silicon. Thereafter, an insulating interlayer 8 is formed on the surface of the gate electrode 7. Then, an etching mask material is patterned on the interlayer insulating film 8, and the interlayer insulating film 8 and the gate insulating film 6 are processed by dry etching to form a contact window in which the p + contact region 4 and the n + source region 5 are exposed. . Finally, after removing the mask material, the drain electrode 10 is formed on the surface of the n + substrate 1. Thereafter, the source electrode 9 is formed in a predetermined contact window where the p + contact region 4 and the n + source region 5 are exposed, whereby the MOSFET shown in FIG. 1 is completed.
- FIG. 3 shows the relationship between the thickness of the first gate insulating film thickness of the silicon carbide semiconductor device according to the first embodiment of the present invention and the mobility of the MOSFET.
- the mobility when the thickness of the first gate insulating film was 5 nm was defined as 100. Since the mobility tends to saturate at 3 nm or more, the first gate insulating film thickness is more preferably 3 nm or more.
- the shift amount of the threshold voltage (Vth) was evaluated by variously changing the ratio of the aluminum oxide film thickness 6b of the silicon carbide semiconductor device according to Example 1 of the present invention to the total film thickness of the gate insulating film 6.
- FIG. 4 shows the result.
- the vertical axis represents the shift amount of the threshold voltage (Vth) to the positive side
- the horizontal axis represents the ratio of the aluminum oxide film thickness 6b to the total film thickness of the gate insulating film 6.
- the amount of shift is 10% of the total thickness of the gate oxide film 6 of the aluminum oxide film thickness 6b. It shows a saturation tendency around%. It can also be seen that the threshold voltage (Vth) shift effect can be obtained even at a very small ratio of 0.5% or more.
- the electrical characteristics were evaluated by variously changing the ratio of the metal oxide film 6b to the total thickness of the gate insulating film 6 of the metal oxide film of the silicon carbide semiconductor device according to Example 1 of the present invention, which exceeded 10%.
- Vth threshold voltage
- the thickness ratio of the metal oxide film 6b is desirably 10% or less from the viewpoint of reliability.
- the amount of change in the stress voltage can be reduced if it is 5% or less. From the above results, the ratio of the metal oxide film 6b to the total film thickness of the gate oxide film 6 is preferably 10% or less, and more preferably 5% or less.
- metal oxide film aluminum oxide is exemplified as the metal oxide film, but the present invention is not limited to this, and any of titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide may be used. Good.
- reference numeral 1 denotes an n + substrate serving as a drain region
- 2 denotes an n ⁇ drift layer
- 3 denotes a p base region
- 4 denotes a p + contact region
- 5 denotes an n + source region
- 6 denotes a gate insulating film
- 7 denotes a gate.
- An electrode, 8 is an interlayer insulating film for electrically insulating the source / gate
- 9 is a source electrode
- 10 is a drain electrode.
- reference numerals 1 and 2 may be collectively referred to as a SiC substrate, and nitrogen is introduced into the surface (channel region) of the n ⁇ drift layer 2 or the interface between the gate insulating film and the SiC substrate.
- a first gate insulating film 6a, a silicon nitride film (SiN film) 6d, a metal oxide film 6b, a silicon nitride film (SiN film) 6e, and a second gate insulating film 6c are sequentially formed from the SiC substrate side.
- the first gate insulating film 6a and the second gate insulating film 6c are made of, for example, a silicon oxide film
- the metal oxide film 6b is made of, for example, a metal oxide film such as aluminum oxide.
- silicon nitride films (6d, 6e) are formed above and below, and each film is in contact with the metal oxide film.
- the film thickness of the first gate insulating film 6a is 3 nm or more, and the metal oxide film 6b is separated from the surface of the SiC substrate by 3 nm or more.
- the total film thickness of the gate insulating film 6 is not less than 30 nm and not more than 100 nm.
- the thickness ratio of the metal oxide film 6b to the entire gate insulating film 6 is 10% or less.
- a substrate in which an n ⁇ drift layer 2 is laminated on a SiC substrate 1 is prepared.
- the n ⁇ drift layer 2 formed on the SiC substrate 1 is patterned with an ion implantation mask material, and Al is ion-implanted to form the p-type base region 3.
- the ion implantation conditions at this time are a dose of 3 ⁇ 10 13 cm ⁇ 2 .
- the p-type base region 3 is formed with a doping concentration of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 3.0 ⁇ m.
- an ion implantation mask material is patterned on the surfaces of the n ⁇ drift layer 2 and the p-type base region 3, and Al is ion-implanted to form the p + contact region 4.
- the nitrogen to form a n + source region 5 Ion implantation.
- the ion implantation masking agent is patterned, and nitrogen is ion-implanted only into the n ⁇ drift layer 2 (channel region). This introduces nitrogen into the channel region.
- the first gate insulating film 6a is formed by thermal oxidation within a process temperature range of about 1000 to 1300 degrees.
- the first gate insulating film 6a is formed using NO gas or N 2 O gas, for example. Thereby, nitrogen is introduced into the interface between the SiC substrate and the gate insulating film.
- the film thickness of the first gate insulating film 6a is 3 nm or more.
- a silicon nitride film (SiN film) 6d, a metal oxide film 6b, a silicon nitride film 6e, and a second gate insulating film 6c are sequentially formed.
- the thickness of the metal oxide film 6b is 10% or less of the entire thickness of the gate insulating film 6.
- the entire thickness of the gate insulating film 6 is not less than 30 nm and not more than 100 nm.
- the metal oxide film is, for example, aluminum oxide.
- the gate electrode 7 is formed from polycrystalline silicon. Thereafter, an insulating interlayer 8 is formed on the surface of the gate electrode 7. Then, an etching mask material is patterned on the interlayer insulating film 8, and the interlayer insulating film 8 and the gate insulating film 6 are processed by dry etching to form a contact window in which the p + contact region 4 and the n + source region 5 are exposed. . Finally, after removing the mask material, the drain electrode 10 is formed on the surface of the n + substrate 1. Thereafter, the source electrode 9 is formed in a predetermined contact window where the p + contact region 4 and the n + source region 5 are exposed, whereby the MOSFET shown in FIG. 6 is completed.
- Example 2 In the silicon carbide semiconductor device of Example 2, an evaluation result equivalent to that of Example 1 is obtained, and the ratio of metal oxide film 6b to the total thickness of gate insulating film 6 of the metal oxide film is 10% or less. Desirably, 5% or less is more desirable.
- the reliability was improved as compared with the structure of Example 1 in which the silicon nitride film was not provided. Specifically, TDDB (Time-Dependent Dielectric Breakdown) life, Vth stability, etc. have been improved. This is presumably because the diffusion of metal atoms in the metal oxide film into the gate insulating film could be suppressed by this silicon nitride film.
- TDDB Time-Dependent Dielectric Breakdown
- metal oxide film aluminum oxide is exemplified as the metal oxide film, but the present invention is not limited to this, and any of titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide may be used. Good.
- n + type SiC substrate 1: n + type SiC substrate, 2: n ⁇ type drift layer, 3: p type base region, 4: p + type contact region, 5: n + type source region, 6: gate insulating film, 7: gate electrode, 8: interlayer insulating film, 9: source electrode, 10: drain electrode
Abstract
Description
Claims (10)
- 炭化珪素基板と、前記炭化珪素基板上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、前記炭化珪素基板に形成されたソース領域を備えたMOSFETを含む炭化珪素半導体装置において、
前記MOSFETのチャネル領域若しくは前記炭化珪素基板と前記ゲート絶縁膜との界面に導入された窒素と、
前記ゲート絶縁膜内に前記ゲート絶縁膜の膜厚の10%以下の膜厚の金属酸化膜を有することを特徴とする炭化珪素半導体装置。 - 請求項1記載の炭化珪素半導体装置において、前記金属酸化膜の膜厚は前記ゲート絶縁膜の膜厚の5%以下であることを特徴とする炭化珪素半導体装置。
- 請求項1記載の炭化珪素半導体装置において、前記金属酸化膜は、前記炭化珪素基板の表面と3nm以上離れていることを特徴とする炭化珪素半導体装置。
- 請求項2記載の炭化珪素半導体装置において、前記金属酸化膜は、前記炭化珪素基板の表面と3nm以上離れていることを特徴とする炭化珪素半導体装置。
- 請求項1記載の炭化珪素半導体装置において、前記ゲート絶縁膜の膜厚は30nm以上100nm以下であることを特徴とする炭化珪素半導体装置。
- 請求項2記載の炭化珪素半導体装置において、前記ゲート絶縁膜の膜厚は30nm以上100nm以下であることを特徴とする炭化珪素半導体装置。
- 請求項1記載の炭化珪素半導体装置において、前記金属酸化膜の上下に窒化珪素膜が形成され、前記窒化珪素膜の夫々は前記金属酸化膜に接していることを特徴とする炭化珪素半導体装置。
- 請求項2記載の炭化珪素半導体装置において、前記金属酸化膜の上下に窒化珪素膜が形成され、前記窒化珪素膜の夫々は前記金属酸化膜に接していることを特徴とする炭化珪素半導体装置。
- 請求項1記載の炭化珪素半導体装置において、前記金属酸化膜は、アルミ酸化物、チタン酸化物、タンタル酸化物、ハフニウム酸化物、ジルコニウム酸化物を含むことを特徴とする炭化珪素半導体装置。
- 請求項2記載の炭化珪素半導体装置において、前記金属酸化膜は、アルミ酸化物、チタン酸化物、タンタル酸化物、ハフニウム酸化物、ジルコニウム酸化物を含むことを特徴とする炭化珪素半導体装置。
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JPWO2012131898A1 (ja) | 2014-07-24 |
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