WO2012113297A1 - 一种用于三维封装的多层混合同步键合结构及方法 - Google Patents

一种用于三维封装的多层混合同步键合结构及方法 Download PDF

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Publication number
WO2012113297A1
WO2012113297A1 PCT/CN2012/071116 CN2012071116W WO2012113297A1 WO 2012113297 A1 WO2012113297 A1 WO 2012113297A1 CN 2012071116 W CN2012071116 W CN 2012071116W WO 2012113297 A1 WO2012113297 A1 WO 2012113297A1
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Prior art keywords
bonded
mixed
layer
bonding
metal
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PCT/CN2012/071116
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English (en)
French (fr)
Inventor
于大全
王惠娟
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中国科学院微电子研究所
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Publication of WO2012113297A1 publication Critical patent/WO2012113297A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • the invention relates to a multi-layer hybrid synchronous bonding structure and method for three-dimensional packaging, and belongs to the technical field of microelectronic packaging. Background technique
  • three-dimensional stacked package technology is a typical representative of these technologies.
  • This structure can directly stack multiple chips or substrates by bonding, in three dimensions.
  • the metal interconnection structure in the direction greatly reduces the interconnection distance and increases the transmission speed, thereby realizing the integration of a system or a certain function on the three-dimensional structure.
  • the bonding technology is indispensable for realizing the ratio of three-dimensional stacked package structure, and it is also the most important technical focus and difficulty.
  • Hybrid bonding generally refers to the use of metallic materials on the upper and lower surfaces of the substrate to be bonded.
  • the dielectric adhesion layer is mixed and bonded at the same time.
  • Commonly used hybrid bonding uses different polymeric materials such as BCB, SU-8, AL-polymer and PI as the dielectric adhesion layer during hybrid bonding.
  • the metal is thermocompression bonded or eutectic alloy, and the adhesive layer is bonded together by hot pressing and curing, thereby improving the bonding force of the bonding.
  • Various low-temperature bonding methods using a special bonding structure to reduce the bonding temperature such as a low-temperature controllable bonding method proposed by Hitachi Co., Ltd. by designing solder balls and the shape of the pads, on the upper layer of bonding
  • the pads are plated into a raised nail-like structure, and blind holes are formed in the bonded lower layer pads, and finally, when the upper and lower layers are bonded, a mechanically bonded structure is formed between the nails and the holes, thereby Can achieve the purpose of low temperature bonding.
  • the Belgian Microelectronics Center also proposes a selective hybrid bonding method, which is mainly used for the hybrid bonding method of simultaneously bonding a plurality of different chips to a substrate, and also utilizes two different materials, namely A hybrid bonding technique of dielectric material and metal material to achieve a synchronized effect.
  • EP 480 194 A also mentions the formation of a cone having a height of about 60 to 80 on the surface of a metal by electrochemical means, and interconnecting a surface or a metal having such a structure to form a stable joint structure; in addition, US6761803B2 is directly After the surface of the silicon substrate is protected by photolithography, the silicon wafer is placed in the ion beam reaction chamber, and a micro-convex structure is formed on the surface of the silicon by suitable conditions, so that the formation and application of the structure can be realized.
  • the invention has the advantages of long bonding time and high bonding temperature for the existing bonding structure and method, which seriously affects production efficiency and product reliability, causes insufficient wafer warpage, and provides a multilayer for three-dimensional packaging. Hybrid synchronous bonding structure and method.
  • a multi-layer hybrid synchronous bonding method for three-dimensional packaging includes:
  • Step 1 The upper substrate to be mixed and bonded and the lower substrate to be mixed and bonded on each of the n wafers or the vertically stacked structures of the chips are on the bonded to be mixed. Forming a through hole on the substrate and the lower substrate to be mixed and bonded, wherein the through hole is filled with metal to form a metal interconnection structure, and a metal pad is formed on a surface of the metal interconnection structure, wherein n > 2;
  • Step 1 forming a hard metal layer on the surface of the upper substrate metal pad to be mixed and bonded; Step 3, forming a hard metal tapered bump array on the surface of the hard metal layer;
  • Step 4 forming a soft metal layer composed of a solder material on a surface of the lower substrate metal pad to be mixed and bonded;
  • Step 5 forming a dielectric adhesion layer on the surface of the upper substrate to be mixed and bonded and the lower substrate non-metal pad to be mixed and bonded;
  • Step 6. Align the upper substrate to be mixed and bonded with the lower substrate to be mixed and bonded; Step 7. On the upper substrate to be mixed and bonded and the lower substrate pair to be mixed and bonded After the quasi-temperature, a pressure of 5 kN to 90 kN is applied in a temperature range lower than the melting point of the solder material and higher than the softening temperature of the dielectric adhesive layer, the pressure depending on the material and the bond of the dielectric adhesive layer.
  • the size of the substrate such as BCB as the adhesion layer for the gossip wafer, requires a pressure of about 10KN to be applied to insert the hard metal tapered bump array on the upper substrate to be mixed and bonded to be mixed.
  • the dielectric adhesion layer on the upper substrate to be mixed and bonded and the dielectric adhesion layer on the lower substrate to be mixed and bonded are also combined. , thereby forming a stable pre-bonding structure; Step 8.
  • the stabilized pre-bonded structure is reflowed at a temperature higher than the melting point of the solder material.
  • the specific reflow conditions depend on the composition of the solder, such as the lead-free solder reflow temperature of SnCu and SnAgCu.
  • the time is 1 minute ⁇ 2 minutes, such as In lead-free solder reflow temperature of 130 ° C ⁇ 180 ° C, the time is 1 minute ⁇ 2 minutes, into the soft metal layer
  • the hard metal tapered bump array forms a metallurgical bonding alloy, and the dielectric adhesion layer on the upper substrate to be mixed and bonded and the dielectric adhesion layer on the lower substrate to be mixed and bonded are also cured together.
  • the bonding method of the present invention can be applied to wafer-to-wafer bonding, chip-to-wafer bonding, and chip-to-chip bonding (Chip-to- Chip ), or pre-bonding a plurality of layers together, bonding the pieces to the wafer, and finally combining the various forms of the multi-layer wafers to achieve three-dimensional Stacking.
  • the present invention can also be improved as follows.
  • the upper substrate to be mixedly bonded in the step 1 / the lower substrate to be mixed and bonded is a silicon substrate, a compound, a ceramic or a glass substrate.
  • the roughness-contour arithmetic mean deviation Ra of the tapered bump array in the step 3 is greater than 0. lum, less than 10
  • the array of tapered bumps is composed of any one of nickel, copper, tungsten and iron, and the hardness thereof is greater than 500 HV.
  • the soft metal layer is composed of any one of Sn In Snln SnAg SnCu and SnAgCu, and the hardness thereof is less than 100HV.
  • step 5 dielectric electroadhesive layer is composed of benzocyclobutene resin BCB or polyimide PI.
  • the n wafers or chips are sequentially aligned Thereafter, a plurality of pre-bondings are combined by ⁇ - 1 heating and pressurization.
  • a pre-bonding is performed by one heating and pressing.
  • the present invention also provides a technical solution to solve the above technical problems as follows: A multilayer hybrid synchronous bonding structure made by the above-described multilayer hybrid synchronous bonding method for three-dimensional packaging.
  • the beneficial effects of the present invention are:
  • the present invention realizes the hybrid stack bonding technique by improving the process and material design, and the core idea is to use a hybrid bonding method, that is, to bond the solder joints with a polymer glue and a temporary mechanical method.
  • this method has many advantages.
  • a bonding process, that is, a high temperature and elegant process is required once, and the invention uses all substrates to be bonded at the same time, which can save time cost, greatly improve the bonding efficiency, improve the yield of the structure, and improve the reliability of the product.
  • the temperature requirement required for bonding can be reduced.
  • the present invention employs a method of hybrid bonding, in addition to forming a bond of a metal compound in the pad region, and forming adhesion in the non-pad region.
  • the bonding between the layers increases the bonding strength and reliability of the bonding.
  • the method of inserting a hard metal surface tapered bump array into the soft metal during the pre-bonding process can form a stable pre-bonding. The structure thus ensures the accuracy requirements of the three-dimensional synchronous bonding of the entire structure.
  • FIG. 1 is a schematic structural view of a surface of a pad after upper and lower bonding according to an embodiment of the present invention
  • FIGS. 2a to 2h are schematic structural views corresponding to a process of completing hybrid bonding between two substrates according to an embodiment of the present invention
  • 3a to 3c are schematic structural views corresponding to a process of three-dimensional multilayer stack bonding according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of another multi-layer hybrid bonding in accordance with an embodiment of the present invention after completing a three-dimensional structure. detailed description
  • FIG. 1 is a schematic structural view of a surface of a pad after upper and lower bonding according to an embodiment of the present invention, taking a silicon-based plate as an example, and forming metal via holes on the silicon-based plate of each layer to form interconnections, and in the upper and lower metal interconnection structures
  • a special bonding structure is formed on the surface pad as shown in FIG. 1. It can be seen from the figure that there is a metal pad 101 on the upper and lower substrates, preferably metal copper, which can form a hard metal on the upper pad as needed.
  • the layer 102 may be a conductive metal with good contact with the pad such as metal chromium, titanium, nickel, etc., and then a tapered bump array 103 formed on the upper pad surface, and a soft metal such as metal tin is formed on the lower pad. 104.
  • FIGS. 2a to 2h are schematic structural views corresponding to a process of completing hybrid bonding between two layers of substrates according to an embodiment of the present invention:
  • Step 1 as shown in FIG. 2a, taking a silicon-based plate as an example, and forming a TSV hole on the upper substrate 201 to be mixed and bonded and the lower substrate 202 to be mixed and bonded to form a metal interconnection structure 203, as a mixed bonded substrate, the TSV holes are generally metallic copper;
  • Step 2 as shown in FIG. 2b, forming a metal pad 204 on the surface of the metal interconnection structure, the metal is generally copper or nickel gold, and the formation method may be electroplating or the like to form a hard metal layer on the surface of the metal pad 204;
  • Step 3 as shown in Figure 2c, forming a hard metal pyramid bump array 205 on the surface of the upper substrate hard metal layer to be bonded;
  • Step 4 as shown in Figure 2d, forming a soft metal 206 of a certain thickness on the surface of the underlying substrate metal pad to be bonded;
  • Step 5 as shown in Figure 2e, the surface of the non-metallic pad of the upper and lower substrates to be bonded is coated with a thickness of the dielectric adhesion layer 207;
  • Step 6 as shown in Figure 2f, aligning the upper and lower substrates to be bonded
  • Step 7 as shown in FIG. 2g, after the upper and lower substrates to be bonded are aligned, pre-bonded together at a low temperature, at which time the tapered bump array 205 on the pad is inserted into the soft metal 206 of the lower pad.
  • the upper and lower dielectric adhesive layers 207 are also combined, so that a stable pre-bonding structure can be formed;
  • Step 8 As shown in Fig. 2h, the upper and lower substrates to be bonded are reflowed at a high temperature to form a metallurgical bonding alloy 208, and the adhesion layer portions are also cured and bonded together.
  • the composition of the metallurgical bonding alloy 208 is an intermetallic compound, the type of which is related to the selection of specific solder materials and hard metal materials.
  • the solder material in the soft metal layer has two possibilities after reflow, that is, complete conversion to an intermetallic compound or a residual solder.
  • FIG. 3a to FIG. 3c are schematic structural diagrams corresponding to the process of the three-dimensional multi-layer stack hybrid bonding according to the embodiment of the present invention.
  • FIG. 3a is a schematic structural diagram of a multi-substrate wafer in a pre-bonded stack, wherein each of the substrate wafers to be bonded, such as the first to-be-mixed bonded substrate 310 and the second to-be-bonded bonded substrate 320.
  • the nth to-be-bonded substrate 3n0 has its structure, as shown in FIG. 3b, and the finally formed structure is shown in FIG. 3c.
  • the substrate is a silicon-based substrate, and may be other three-dimensional structures to be bonded, such as direct chi p-to-chi p, two or more layers of bonding structures may be used, or these structures may be used.
  • Composite use the specific structure is shown in Figure 4, where 41 0 is the substrate to be bonded, 420 is a three-layer bonded structure, and 430 is a two-layer bonded assembly. Structure.

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  • Manufacturing & Machinery (AREA)
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Description

一种用于三维封装的多层混合同步键合结构及方法 技术领域
本发明涉及一种用于三维封装的多层混合同步键合结构及方法，属于微 电子封装技术领域。 背景技术
随着人们对电子产品的要求向小型化、 多功能、 环保型等方向的发展， 人们努力寻求将电子系统越做越小， 集成度越来越高， 功能越做越多， 越来 越强。 由此产生了许多新技术、 新材料和新设计， 例如三维堆叠封装等技术 就是这些技术的典型代表， 该结构可直接将多个棵芯片或者衬底通过键合的 方式堆叠起来， 实现在三维方向上的金属互联结构， 大大减小互联距离， 提 高传输速度， 从而实现一个系统或者某个功能在三维结构上的集成。 而其中 键合技术是实现三维堆叠封装结构比必不可少，也是最关键的技术重点和难 点， 常用的键合方法有直接氧化物键合， 金属键合如铜铜键合， 还有特殊有 机聚合物的键合如 BCB。 同时也有不同材料之间的混合键合， 如聚合物和金 属的混合键合方法等， 通常这些方法都是通过高的温度和高的压力条件下， 一层一层来键合。 所以这些传统的键合方法都存在以下的一些问题：
1)键合的条件对结构本身的影响， 如温度和压力， 会在一定程度上影响 结构本身的可靠性和产率； 2)由于多层的堆叠需要一层一层去键合， 下一次 的键合必然会对上一次造成影响， 如键合精度和结合强度等都有一定的减 小，也就是多次键合比单词键合的精度以及结合的强度都会有一定程度的减 小； 3)另外由于键合过程中存在一个等待升温和降温的时间， 这对于需要量 产的多次键合结构， 势必会影响其整体的键合速度以及产量， 从而大大增加 其成本。
由于这种传统的方法复杂， 存在很多困难， 对产品的成品率和可靠性造 成极大的影响。 各种新的工艺， 材料以及键合方法也逐步被提出和讨论， 例 如采用混合键合来加强键合的结合力， 混合键合一般是指在待键合的衬底上 下表面采用金属材料和介电粘附层同时混合来键合， 常用的混合键合采用不 同的如 BCB, SU-8 , AL-聚合物以及 PI等这几种聚合材料来作为混合键合时 的介电粘附层， 在键合以后， 金属采用热压键合或者共熔合金， 粘附层则通 过热压后固化粘结在一起， 从而提高键合的结合力。 采用特殊的键合结构来 降低键合温度的各种低温键合方法，如日立有限公司提出通过设计焊球以及 焊盘的形状而提出的一种低温可控制的键合方法，在键合上层的焊盘上电镀 成凸起的钉状结构， 而在键合的下层焊盘上开出盲孔， 最后上下两层键合的 时候， 钉与孔之间形成一种机械结合的结构， 从而能达到低温键合的目的。 而比利时的微电子中心也提出一种选择性的混合键合方法， 主要用于将多个 不同的棵片同时与衬底键合的混合键合方法， 也是利用了两种不同的材料， 即介质材料和金属材料的混合键合技术来达到一种同步的效果。
还有一种利用材料的结果与属性进行键合的方法，在上下焊盘上采用两 种不同的金属， 其中上焊盘表面形成微星锥状结构， 直接插入下层的软金属 中来完成机械。如专利 US6204089B1提到，在焊盘的表面形成一种锥形焊球， 以穿透用于做粘合或者绝缘的不导电层，然后再进一步来键合，与电极相连， 构成电学连接； 而 EP480194A也提到， 通过电化学方法在金属的表面形成高 度约 60画~ 80画 的锥形， 并将一表面或者两表面有此结构的金属互联， 以 形成稳固的连接结构；另外 US6761803B2 直接在硅基的表面通过光刻涂覆保 护后， 将硅片置于离子束反应腔， 并通过合适的条件控制在硅的表面形成微 凸起结构， 使这种结构的形成和应用得以实现。 但是以上的这些方法都存在 一定的缺陷和问题， 如难以大规模量产， 而且每个方法都只解决了一个侧面 问题， 还是存在键合时间长， 键合温度高等问题， 这严重影响了生产效率和 产品可靠性， 引起晶圆翘曲等。 发明内容
本发明针对现有键合结构及方法存在的键合时间长， 键合温度高， 严重 影响了生产效率和产品可靠性， 引起晶圆翘曲的不足， 提供一种用于三维封 装的多层混合同步键合结构及方法。
本发明解决上述技术问题的技术方案如下： 一种用于三维封装的多层混 合同步键合方法包括：
步骤 1、 在 n个晶圆或者芯片垂直堆叠的结构中任一个互连界面上均包 括待混合键合的上衬底和待混合键合的下衬底，在所述待混合键合的上衬底 和待混合键合的下衬底上分别形成通孔，所述通孔内填充金属后形成金属互 联结构， 在所述金属互联结构的表面形成金属焊盘， 其中， n > 2 ;
步骤 1、 在所述待混合键合的上衬底金属焊盘的表面形成硬金属层； 步骤 3、 在所述硬金属层的表面形成硬金属锥形凸点阵列；
步骤 4、 在所述待混合键合的下衬底金属焊盘的表面形成由软钎焊材料 构成的软金属层；
步骤 5、 在所述待混合键合的上衬底和待混合键合的下衬底非金属焊盘 的表面形成介电粘附层；
步骤 6、 将所述待混合键合的上衬底和待混合键合的下衬底对准； 步骤 7、 在所述待混合键合的上衬底和待混合键合的下衬底对准后， 在 低于软钎焊材料熔点而高于介电粘附层软化温度的温度范围内，施加 5千牛 顿 ~ 90千牛顿的压力，压力大小取决于介电粘附层的材料以及键合基板的大 小， 如对八吋的晶圆采用 BCB做粘附层， 需要施加约 1 0KN的压力， 使所述 待混合键合的上衬底上的硬金属锥形凸点阵列插入待混合键合的下衬底的 软金属层中， 同时所述待混合键合的上衬底上的介电粘附层和待混合键合的 下衬底上的介电粘附层也结合在一起， 从而形成一个稳固的预键合结构； 步骤 8、 将所述稳固的预键合结构在高于软钎焊材料熔点的温度下进行 回流， 具体的回流条件取决于钎料的成分， 如含 SnCu和 SnAgCu的无铅钎料 回流温度为 210 °C ~ 230 °C , 时间为 1分钟〜 2分钟， 如含 In的无铅钎料回 流温度为 130 °C ~ 180 °C , 时间为 1分钟〜 2分钟， 使插入软金属层中的硬金 属锥形凸点阵列形成冶金结合合金， 同时所述待混合键合的上衬底上的介电 粘附层和待混合键合的下衬底上的介电粘附层也固化结合在一起。 即本发明的键合方法可应用于晶圆到晶圆 （Wafer-to-Wafer ) 的键合， 芯片到晶圆 （ Chip_to_Waf er ) 的键合， 以及芯片到芯片 的键合 ( Chip-to-Chip ), 或者先将多层棵片预键合在一起， 再将棵片与晶圆键合 在一起 最后再将多层晶圆之间来混合键合等多种形式的复合形式来实现三 维堆叠。
在上述技术方案的基础上， 本发明还可以做如下改进。
进一步， 所述步骤 1 中待混合键合的上衬底 /待混合键合的下衬底为硅 基板、 化合物、 陶瓷或者玻璃衬底。
进一步，所述步骤 3中锥形凸点阵列的粗糙度 -轮廓算术平均偏差 Ra大 于 0. lum, 小于 10
进一步， 所述步骤 3中锥形凸点阵列由镍、 铜、 钨和铁中任一种硬金属 构成， 其硬度大于 500HV
进一步， 所述步 4中软金属层由 Sn In Snln SnAg SnCu和 SnAgCu 中任一种软钎焊材料构成， 其硬度小于 100HV
进一步，所述步骤 5中介电粘附层由苯并环丁烯树脂 BCB或者聚酰亚胺 PI构成。
进一步， 所述步骤 7中施加 5千牛顿 ~ 90千牛顿的压力。
进一步， 在所述多层混合同步键合中， 所述 n个晶圆或者芯片依次对准 后， 通过 η-1次加温和加压进行多次预键合结合在一起。
进一步， 在所述多层混合同步键合中， 所述 η个晶圆或者芯片依次对准 后， 通过一次加温和加压进行一次预键合结合在一起。
本发明还提供一种解决上述技术问题的技术方案如下： 一种由上述的用 于三维封装的多层混合同步键合方法制成的多层混合同步键合结构。
本发明的有益效果是： 本发明通过改进工艺与材料设计来实现混合堆叠 键合技术， 核心思想是利用混合键合方法， 即用聚合物胶和临时机械方法结 合焊点。 这种方法与传统的键合方法相比， 有着诸多优点， 首先， 不同于传 统的三维堆叠时采用一层一层的键合， 每多堆叠一层衬底， 或者是棵片， 都 需要进行一次键合过程， 即都需要一次经过高温和高雅的过程， 而本发明采 用所有衬底同时键合， 可节省时间成本， 大大提高了键合的效率， 提高结构 的成品率， 提高产品的可靠性， 另外通过机械结合可减小键合时需要的温度 要求； 第二， 本发明采用混合键合的方法， 除了在焊盘区域形成金属化合物 的键后， 还在非焊盘区域形成粘附层之间的键合， 增加了键合的结合强度和 可靠性； 第三， 在预键合过程中采用硬金属表面锥形凸点阵列插入软金属中 的方法， 可以形成稳固的预键合结构， 从而保证整个结构的三维同步键合的 精度要求。 附图说明
图 1为本发明实施例上下键合后焊盘表面的结构示意图；
图 2a至图 2h为本发明实施例两层衬底之间完成混合键合的工艺过程对 应的结构示意图；
图 3a至图 3c为本发明实施例三维多层堆叠键合的工艺过程对应的结构 示意图；
图 4为本发明实施例其他多层混合键合完成三维结构后的结构示意图。 具体实施方式
以下结合附图对本发明的原理和特征进行描述， 所举实例只用于解释本 发明， 并非用于限定本发明的范围。
图 1为本发明实施例上下键合后焊盘表面的结构示意图，以硅基版为例， 并在每一层的硅基版上形成金属通孔以形成互联， 并在上下金属互联结构的 表面焊盘上形成特殊的键合结构如图 1所示，从图中可以看出在上下衬底上 有一层金属焊盘 101, 优选为金属铜， 可以按需要在上焊盘上形成硬金属层 102, 可为金属铬， 钛， 镍等与焊盘接触良好的导电金属， 然后在上焊盘表 面形成的锥形凸点阵列 103,同时在下焊盘上形成一层软金属，如金属锡 104。
图 2a至图 2h为本发明实施例两层衬底之间完成混合键合的工艺过程对 应的结构示意图：
步骤 1, 如图 2a 所示， 以硅基版为例， 并在待混合键合的上衬底 201 和待混合键合的下衬底 202上形成 TSV孔以形成金属互联结构 203, 作为待 混合键合的衬底， TSV孔一般为金属铜；
步骤 2, 如图 2b所示， 在金属互联结构表面形成金属焊盘 204, 该金属 一般为铜或者镍金， 形成方法可为电镀等， 在金属焊盘 204的表面形成硬金 属层；
步骤 3, 如图 2c, 在待键合的上衬底硬金属层的表面形成一层硬金属锥 形凸点阵列 205;
步骤 4, 如图 2d, 在待键合的下衬底金属焊盘表面形成一定厚度的软金 属 206;
步骤 5, 如图 2e, 在待键合的上下衬底的非金属焊盘表面涂敷形成一定 厚度的介电粘附层 207;
步骤 6, 如图 2f, 将待键合的上下衬底对准； 步骤 7 ,如图 2g ,在待键合的上下衬底对准后，在低温下预键合在一起， 这时焊盘上的锥形凸点阵列 205插入下焊盘的软金属 206中， 同时上下介质 粘附层 207也结合在一起， 这样则可以形成一个稳固的预键合结构；
步骤 8 , 如图 2h, 将待键合的上下衬底的在高温下回流， 使金属部分形 成冶金结合合金 208 , 粘附层部分也固化结合在一起。
冶金结合合金 208的成分为金属间化合物，其类型与具体的软钎焊材料 和硬金属材料的选择相关。依据软金属层和硬金属锥形凸点阵列厚度和回流 温度， 软金属层中的软钎焊材料在回流后存在两种可能， 即完全转变为金属 间化合物或者还有残余钎料。
同时也可采用上述的方法将多层衬底预键合在一起后， 通过一定的温度 和压力来回流， 使焊盘处形成金属化合物键合， 在介质粘附区域也形成好的 结合， 从而实现整个结构的同步键合， 如图 3a至图 3c为本发明实施例三维 多层堆叠混合键合的工艺过程对应的结构示意图。 其中图 3a为在堆叠预键 合的多层衬底晶圆结构示意图， 其中每一个待键合衬底晶圆， 如第一待混合 键合衬底 310、 第二待混合键合衬底 320、 第 n待混合键合衬底 3n0都有其 结构， 如图 3b所示， 最后形成的结构示意图如图 3c所示。
将另外， 该衬底为硅基衬底， 也可为其他待键合的三维结构， 如直接 chi p-to-chi p , 可以用二层以及二层以上的键合结构， 或者将这些结构复合 起来使用， 具体结构示意图如图 4所示， 其中 41 0为待键合的衬底， 420为 一个三层的已经键合堆叠好的结构， 430则为一个两层的已经键合堆叠好的 结构。
以上所述仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明 的精神和原则之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发 明的保护范围之内。

Claims

权利要求书
1. 一种用于三维封装的多层混合同步键合方法， 其特征在于， 所述同 步键合方法包括：
步骤 1、 在 n个晶圆或者芯片垂直堆叠的结构中任一个互连界面上均包 括待混合键合的上衬底和待混合键合的下衬底，在所述待混合键合的上衬底 和待混合键合的下衬底上分别形成通孔，所述通孔内填充金属后形成金属互 联结构，在所述金属互联结构的表面形成金属焊盘金属互联结构金属互联结 构， 其中， n > 2 ;
步骤 1、 在所述待混合键合的上衬底金属焊盘的表面形成硬金属层； 步骤 3、 在所述硬金属层的表面形成硬金属锥形凸点阵列；
步骤 4、 在所述待混合键合的下衬底金属焊盘的表面形成由软钎焊材料 构成的软金属层；
步骤 5、 在所述待混合键合的上衬底和待混合键合的下衬底非金属焊盘 的表面形成介电粘附层；
步骤 6、 将所述待混合键合的上衬底和待混合键合的下衬底对准； 步骤 7、 在所述待混合键合的上衬底和待混合键合的下衬底对准后， 在 低于软钎焊材料熔点而高于介电粘附层软化温度的温度范围内， 施加压力， 使所述待混合键合的上衬底上的硬金属锥形凸点阵列插入待混合键合的下 衬底的软金属层中， 同时所述待混合键合的上衬底上的介电粘附层和待混合 键合的下衬底上的介电粘附层也结合在一起，从而形成一个稳固的预键合结 构；
步骤 8、 将所述稳固的预键合结构在高于软钎焊材料熔点的温度下进行 回流， 使插入软金属层中的硬金属锥形凸点阵列形成冶金结合合金， 同时所 述待混合键合的上衬底上的介电粘附层和待混合键合的下衬底上的介电粘 附层也固化结合在一起。
2. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 1 中待混合键合的上衬底 /待混合键合的下衬底为硅基 板、 化合物、 陶瓷或者玻璃衬底。
3. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 3中锥形凸点阵列的轮廓算术平均偏差大于 0. lum, 小 于 10
4. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 3中锥形凸点阵列由镍、 铜、 钨和铁中任一种硬金属构 成， 其硬度大于 500HV
5. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 4中软金属层由 Sn In Snln SnAg SnCu和 SnAgCu 中任一种软钎焊材料构成， 其硬度小于 100HV
6. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 5中介电粘附层由苯并环丁烯树脂或者聚酰亚胺构成。
7. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于， 所述步骤 7中施加 5千牛顿 ~ 90千牛顿的压力。
8. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于，在所述多层混合同步键合中，所述 n个晶圆或者芯片依次对准后， 通过 n-1次加温和加压进行多次预键合结合在一起。
9. 根据权利要求 1所述的用于三维封装的多层混合同步键合方法， 其 特征在于，在所述多层混合同步键合中，所述 n个晶圆或者芯片依次对准后， 通过一次加温和加压进行一次预键合结合在一起。
10.一种由如权利要求 1至 9任一所述的用于三维封装的多层混合同步 键合方法制成的多层混合同步键合结构。
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