TW423132B - Bumpless flip chip package and method for fabricating - Google Patents

Bumpless flip chip package and method for fabricating Download PDF

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Publication number
TW423132B
TW423132B TW88112937A TW88112937A TW423132B TW 423132 B TW423132 B TW 423132B TW 88112937 A TW88112937 A TW 88112937A TW 88112937 A TW88112937 A TW 88112937A TW 423132 B TW423132 B TW 423132B
Authority
TW
Taiwan
Prior art keywords
layer
connection layer
flip chip
process
integrated circuit
Prior art date
Application number
TW88112937A
Inventor
Tsung-Hsiung Wang
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW88112937A priority Critical patent/TW423132B/en
Application granted granted Critical
Publication of TW423132B publication Critical patent/TW423132B/en

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Abstract

This invention discloses the bumpless flip chip package and method for fabricating. The invention is accomplished by using the connection layer with single-layer or multi-layer structure, which has plural conduction bump-pad stages. The connection layer having the conduction bump-pad stage is thermal resist type and is with low coefficient of thermal expansion. In addition, this connection layer is composed of soft, electric-insulation polymer material that has adhesion characteristic and elastic structure. The top portion and bottom portion of this connection layer are composed of the homogeneous or heterogeneous electrically-insulated polymer material that has adhesion characteristic such that it has substantial adhesion strength for both integrated circuit chip surface and substrate surface. The connection layer is placed in between the integrated circuit chip and substrate so that the connection behavior of electric conduction is obtained by using thermal press process. This connection layer can be designed as the connection layer that has layer-added type with multi layer structure according to the input/output redistribution requirement of the integrated circuit chip and can be combined with flip chip technique to change the peripheral array package into grid point array package so as to expand the application field range. By using the bumpless flip chip package structure and fabrication process of this invention, the fabrication process can be simplified, in which the deposition process of bump on chip, the flux cleaning process and the bottom glue adding process are not required, and the utilization of material such as flux, bottom glue and so on can be eliminated such that the requirements of production cost down and reliability increase can be obtained.
TW88112937A 1999-07-27 1999-07-27 Bumpless flip chip package and method for fabricating TW423132B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88112937A TW423132B (en) 1999-07-27 1999-07-27 Bumpless flip chip package and method for fabricating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88112937A TW423132B (en) 1999-07-27 1999-07-27 Bumpless flip chip package and method for fabricating

Publications (1)

Publication Number Publication Date
TW423132B true TW423132B (en) 2001-02-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW88112937A TW423132B (en) 1999-07-27 1999-07-27 Bumpless flip chip package and method for fabricating

Country Status (1)

Country Link
TW (1) TW423132B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI394240B (en) * 2009-11-02 2013-04-21 Powertech Technology Inc Flip chip package eliminating bump and its interposer
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
TWI394240B (en) * 2009-11-02 2013-04-21 Powertech Technology Inc Flip chip package eliminating bump and its interposer

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