TW423132B - Bumpless flip chip package and method for fabricating - Google Patents

Abstract

This invention discloses the bumpless flip chip package and method for fabricating. The invention is accomplished by using the connection layer with single-layer or multi-layer structure, which has plural conduction bump-pad stages. The connection layer having the conduction bump-pad stage is thermal resist type and is with low coefficient of thermal expansion. In addition, this connection layer is composed of soft, electric-insulation polymer material that has adhesion characteristic and elastic structure. The top portion and bottom portion of this connection layer are composed of the homogeneous or heterogeneous electrically-insulated polymer material that has adhesion characteristic such that it has substantial adhesion strength for both integrated circuit chip surface and substrate surface. The connection layer is placed in between the integrated circuit chip and substrate so that the connection behavior of electric conduction is obtained by using thermal press process. This connection layer can be designed as the connection layer that has layer-added type with multi layer structure according to the input/output redistribution requirement of the integrated circuit chip and can be combined with flip chip technique to change the peripheral array package into grid point array package so as to expand the application field range. By using the bumpless flip chip package structure and fabrication process of this invention, the fabrication process can be simplified, in which the deposition process of bump on chip, the flux cleaning process and the bottom glue adding process are not required, and the utilization of material such as flux, bottom glue and so on can be eliminated such that the requirements of production cost down and reliability increase can be obtained.

Description

V. Description of the invention (1) In the field of invention, the invention relates to a land with a flip-chip structure: it is a connection layer using a green layer having a plurality of conductive bumps to form a bumpless plastic flip-chip structure. Structures and methods are invented. Background As electronics, information, and communications products have increasingly urgent demands for lightness, thinness, short functionality, multifunctionality, and ancient speed, we are emphasizing that we can increase the density of component combinations = connection methods or mounting technologies. Increasingly demanding. The flip chip technology is a combination that everyone can accept. The traditional flip-chip structure method must use integrated circuit dies that already have solder bumps (so 1 der bumps), combined with the flux coating process, the reflow process, and the flux ( (Fiux) cleaning process, as well as dispensing and thermal curing processes, etc. 'directly connect integrated circuit (1C) die to the substrate' to achieve a high reliability of the assembly requirements. The formation of solder bumps can generally use a composite mater ial of t in and 1 ead through a mask, using vaporization, sputtering, or recording. (electrodeposition), etc. to generate solder bumps with corresponding positions. Recently, some people have combined the technology of electrode implantation to produce solder bumps in flip-chip fabrication processes, and they have already achieved good R & D results. In addition, solder bumps are produced by solder paste screening.

V. Invention Description (2) is a widely used technology. However, with the recent demand for miniaturization of the size of component components, the gap or spacing between solder bumps and bumps has a tendency to gradually shrink. At that time, solder paste screen printing technology will Difficulties and low yields that do not meet demand 'and when solder bumps are printed using solder paste screen printing technology, because the solder paste itself is a mixture of flux material and solder alloy particles, when the solder bumps want to reduce the product, The concentration and uniformity of the solder paste composition will become difficult to control. Therefore, it is necessary to use small and uniform solder particles with a suitable particle size, and to mix appropriate flux, but it will increase a lot of manufacturing costs and mixing difficulties. In addition, when the solder is from the paste state to the cured spheroid state (cured state), the diameter will be significantly reduced. So when the distance between the solder bump and the bump is reduced, it can be between The limited space used cannot meet the minimum size requirements for the design and production of the diameter of screen hole for solder paste screen printing. Other technologies that can form solder bumps, such as mastered high-level bare chip reverse buckling welding technology (C4) and thin film electrode implantation technology, are also often used in integrated circuits. A long bump process for circuit wafers. However, for the requirements of fine-pitched front tin bumps, the application of C4 technology will be limited due to the increased difficulty in making the molybdenum mask required for the process. Similarly, the thin film electrode implantation technology also uses an etching process to make the underlying metal layer of the bump (under

C: \ patent \ 880014 ~ lerso. Ptd page 6 Γ w: ... 423132 V. Description of invention (3) --- The technical capability of bum? Metal lurgy (UBM) is the same as that of C4 limit. Figures 丨 A to 1F show the manufacturing process of a conventional solder bump. FIG. 1A is a schematic diagram of a cross-sectional structure of a conventional integrated circuit chip. On the top surface 16 of the silicon wafer 12, there are bond pads 14 for connecting external circuits. The connection pads 14 are usually aluminum metal. A passivating layer 20 is coated on top of the connection pads 14 to protect the conductive lines and metal pads from moisture or oxidation. A window 22 'for connecting the bonding pads is produced by a photolithography process (phot01 ithography process) to scribe out the area of the area where the connecting pads 4 are electrically connected externally. The protective layer 20 is an electrically insulating material, such as oxide, nitride, or organic materiai. On the top surface 24 of the protective layer 20 and the exposed area 18 on the top surface of the connection pad 14, a bump bottom metal layer 26 is evaporated or sputtered to increase the distance between the solder bump 42 and the exposed area 18 of the wafer connection pad. Then the intensity and its reliability 'are shown in FIG. 1B. The bump bottom metal layer 26 is generally composed of an adhesion diffusion barrier layer 30 and a wetting layer 28. The adhesion diffusion barrier layer 30 can be made of titanium (Ti), titanium tungsten (TiW), nickel (Ni) or chromium (Cr); and the wet layer 28 is usually a copper (Cu) metal layer. The next step of the process is to apply a photoresist layer (phot or e s t 1 ay er) 3 4 ′ over the bump bottom metal 26 using a photolithographic process.

C: \ patent \ 880014 ~ lerso. Ptd page 7 423132 V. Description of the invention (4) (Photolithography process), the area 38 of the bottom of the bump is exposed, as shown in Figure lc. Twisting: for pre-made soldering. Use evaporation, sputtering or electroplating technology to implant solder material into the openings of long solder bumps to form the height and diameter of the long solder bumps to the fresh solder bumps. In the range. After removing the photoresist layer, Figure 1E is the next stage of the mushroom inspection process, which is to cover the bumps 4 and 40 ° 2 to protect the underlying metal of the bumps below. ^ Λ 呆 β (wet etching) ^ ^ and re-soldering process to make the bumps 凸

As shown in Figure 1F. Ye Wang 〇View 4Z transmission such as the removal of the upper flip-chip surface, multiple fill bottoms are repeated, and the long-term tin technology described in the conventional flip-chip assembly is linked to oxides and synergistic flux jumps (under fi Is the miscellaneous and long convex underfill the quality of the product? The soldering process needs to be removed for the production of bumps. 11) The quality of the soldering blocks is exactly the same. In addition to the process, the soldering bumps are used in the process and process. Bottom failure and assist, etc., need to include the hard solder flux that needs to be included in the coating agent after the reflow soldering process, which will affect the yield of the integrated circuit crystal engineering process, the drying process after the washing process. Reliability is not high, circuit wafer advancement and substrate advancement to remove solder fusion connection, and process, and so on, the process is redundant or not, the direct cost will be high.

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423132

Factors, and delays in delivery. It ’s expensive and difficult to control because of its nature. In addition, 'flux and primer materials are also the source that can not be reduced in cost-Summary of the Invention Therefore, one object of the present invention is the structure and manufacturing process, which can eliminate processes such as hard coating of flux primer and can reduce the lengthy crystal structure. The process is simpler. ’Provide a new and complicated process of flip-chip mounting, flux cleaning, filling primer, and more complex traditional mounting process, and this process. Yet another object of the present invention is to provide a covering process that does not require the integrated circuit chip to be embossed. Another object of the present invention is to connect the integrated circuit chip to a single-layer or multi-layer structure of a substrate. Layer Another object of the present invention is to provide a structure and a manufacturing process, and the number of this structure, with adhesive properties and elastic junction materials, to form a connection layer with a plurality of structures, this connection layer is placed at ^ for a A flip-chip mounting structure, and a plurality of conductive bump pads are placed between the junctions to achieve the purpose of circuit connection and conduction. ^ A crystal structure for a solderless bump is made of a soft electrical insulating polymer using a heat-resistant type and a low thermal expansion structure. A single-layer or multi-layer integrated circuit chip between a conductive bump pad and a substrate is used.

423132

Hot-pressed with para-position. Process technology to achieve the flip-chip bonding electrical conduction of the purpose of the present invention-θ or multilayer structure of far two: is to provide a single layer of homogeneous or heterogeneous f φ 2 with a plurality of conductive bump pads, the connection layer The top and bottom are high-molecular polymers with adhesive characteristics and substrate surface, and the integrated circuit chip circuit chip connection / strength. This continuous system can be based on the connection layer of the product and "cover two: need to be 'designed as a multi-layer multi-layer structure ^ m ^ 0 overlay technology, to change the surrounding array structure to the grid array structure' to expand the field of application Scope. In the fabrication process of the present invention, a circuit chip can be integrated, and then a substrate and a plurality of connection pads are provided. The connection layer of the structure is connected to the corresponding third plurality of first plural connections and is completed using the connection layer. For thermocompression bonding, in the preferred embodiment, the following operation is used with a surface of the substrate having a 'this substrate'. The third plurality of integrated circuit pads are provided with conductive bump pads and the substrate. The step of forming a bumpless flip-chip is implemented. Between the first piece of the first plurality of connection surfaces and the substrate with the conductive bump pad at a relative position, the second plurality of surfaces connecting the integrated circuit circuit surface and the product Firstly, a solder pad is provided for the connection of the body circuit for electrical continuity. However, there is a second or multiple junction connection layer for connecting the pads on the surface of the wafer, and the purpose of the chip and the substrate. This forms a bumpless flip chip Comprising the step of forming a connection layer structure and package of this configuration process, you can enter - a further step of first providing an electrically insulating material

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10 pages

423132 V. Description of the invention (7) The layer may be a liquid crystal polymer (liquid crystal pololy), polyimide (PI), epoxy (epoxy), and bismaleimide (blSffialeimide , BM〗), the thickness can be between the design requirements, in this electrical insulation material layer by mechanical, electrical destruction or laser drilling to form a third plurality of through holes (thr㈣h holes), and then A copper layer is plated on the side wall of the third plurality of through holes by a traditional plated through, dip coating process, and a solderable metal is filled in the side walls. Materials, once the connection layer of the single-layer or multi-layer structure of the plurality of conductive bump pads is made. 〃 This forms a structure and process of bumpless flip-chip structure, which can further SI: specific redistribution (1 / 〇 ⑽ 心 ―) Function: The peripheral array structure is changed into a grid array structure, and the layer structure can be adjusted according to the needs. In this structure, the output / input reconfiguration of the line layout (Uay0ut) is completed. This forms a bumpless connection layer of a bumpless flip-chip structure. According to the integrated circuit circuit board connection, the top and bottom of the connection layer are coated with homogeneous or 垆 Lei Lin ". Knowing J: Insulation polymer, it has a considerable degree of bonding strength to the surface of the integrated circuit chip and the substrate. The formation of a bump-free disc-on-chip cracking junction includes a reduction atmosphere alignment hot pressing process. The process is to integrate the circuit chip, the connection layer and the

V. Description of the invention (8) After the sandwich structure of the substrate is precisely aligned, it can be placed in a reducing atmosphere of hydrogen / nitrogen (H2 / N2) at a temperature between 150 ° C and 300 ° C as required. 200 Pounds per square 'Psi' pressure 'to achieve flip-chip bonding electrical continuity bonding β By the following illustrations and examples, and the definition of the scope of the special brake application, the above and this Other objects and advantages of the invention are detailed later. Brief Description of the Drawings Figure 1 is a schematic enlarged cross-sectional view of a conventional integrated circuit chip of A, in which a metal connection pad is provided on the top surface of the silicon wafer, which is covered with a protective layer. FIG. 1B is an enlarged cross-sectional view of the structure of the conventional integrated circuit wafer of FIG. 1A covered with the underlying metal layer of the bump, wherein the underlying metal layer of the bump includes two layers, one is an adhesion diffusion barrier layer, and the other is a wetting layer. FIG. 1C is an enlarged cross-sectional view of an opening pattern formed by coating a photoresist on the metal surface of the bottom layer of the bump in FIG. 1B and subjecting it to an exposure and development process by photolithography. Fig. 1D is an enlarged cross-sectional view of the structure of Fig. 1C, in which a mushroom-shaped solder bump protruding from the top surface of the photoresist layer is formed using electroplating technology.

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423132 'V. Description of the invention (9) Fig. 1 E is an enlarged sectional view of the structure of Fig. 1 D, in which a photoresist is completely removed using a remover, and a mushroom-shaped solder bump is exposed. FIG. 1F is an enlarged cross-sectional view of the structure of FIG. 1E, in which 'the mushroom-shaped solder bump is used as a protective cover for money engraving' to protect the underlying metal of the bump from being etched, and the unprotected metal is completely etched away. 'And after the re-soldering process, the mushroom solder bumps are formed into spherical solder bumps. 2A to 2D show a manufacturing process for forming a connection layer according to a first embodiment of the present invention. FIG. 2A is an enlarged cross-sectional view of an electrically insulating material layer having bonding characteristics. FIG. 2B is an enlarged cross-section of the electrical insulating material layer of the present invention of FIG. 2A, and a plurality of through holes are formed thereon. Fig. 2 C is a magnified sectional view of the lightning insulation material layer of the invention according to the present invention. Fig. 2 is a magnified cross-section of the phantom electrical insulating material layer. A copper layer is plated to form an enlarged cross-sectional view of a single or multi-layered connection insulating material layer of the electrical property of the present invention, which is filled with a solderable metal material holder, as shown in FIG. 2D and FIG. 2C. A plurality of conductive convex layers are produced. pad

5. Description of the invention (10) FIG. 3 is an enlarged d-plane view of a connecting layer formed by a second embodiment of the present invention. Electrical insulation materials used Top and bottom surface of the integrated circuit: the surface properties of the sheet, coated with an appropriate adhesive β. According to the third embodiment of the present invention, a 2 section of the connection layer is formed. This connection layer is designed as a multi-layer multi-layer structure, and the circuit layout of the redistribution of I / O in I / O. 5A is a cross-sectional view of the structure according to the first embodiment of the method according to the present invention, in which a integrated circuit wafer, a connection layer, and an atmosphere plate are aligned and laminated together by hot pressing. Soil system: According to the method of the present invention, the structure scraped surface of the 1-jazhao circuit chip and a connection laminate in the hot pressing method is aligned and laminated together. Based on the method of the present invention, the structure of the front surface of the structure before pressing and bonding together is performed by a hot pressing method, which is to ′ -Ji Zhao circuit chip, a connection layer; ^ atmosphere plate ”. The cross-sectional view of the structure of the integrated circuit wafer, connection layer and substrate of the base diagram.

423132 V. Description of the invention (11) FIG. 7A is a diagram illustrating a third embodiment of the method according to the present invention. In a reduction atmosphere 2, a integrated circuit chip, a connection layer, and a substrate are paired together by hot pressing. Sectional view of the structure before bit compression. Fig. 7B is a cross-sectional view of the structure of the integrated circuit wafer, the connection layer and the substrate of Fig. 7A after being aligned and pressed together. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION The present invention discloses a structure of bumpless cladding structure and a method of making such a structure. The invention uses a single-layer or multi-layer electrical insulating connection layer having a plurality of conductive bump pads. This connection layer is placed between the integrated circuit chip and the substrate and is thermocompression bonded, so that the integrated circuit chip is not required. Solder bump process. The present invention further discloses a method for manufacturing the connection layer, and further discloses a method for completing bump-free crystal-on-chip structure by using a single-layer or multi-layer electrical insulating connection layer having a plurality of conductive bump pads. In the step of forming the connection layer, an electrically insulating material layer is first provided, and then a plurality of through holes are formed in the electrically insulating material layer, and then the side walls of the plurality of through holes are conventionally plated with through holes, vapor deposition, or Sputtering and other methods are used to plate an adhesion-promoting copper layer to improve the bonding between the solder material and the electrical insulating material ^, and to fix the solder material in the through hole to prevent the phenomenon of tin flow during the reflow process. . Fill the through hole with solder material to form multiple

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4 2 3 13 2 V. Description of the invention (12) II: The filling of two i :: f materials can be accomplished by techniques such as electricity ore and non-electric ore, = ϊ = :. This connection layer can provide different forms of the bottom surface of the adhesive layer 1 according to the surface properties of the layer. It is suitable for connecting to the integrated body. The connection layer can also be designed as a multilayer multi-layer structure. The redistribution circuit layout can be used as a redistribution structure, which can be applied to the requirement of changing the surrounding array structure to a grid array structure. The method of light ir = is to combine the long bump process, the solder ball connection process, the filling bottom glue process and the line redistribution process into one, and it can be linked and produced without bump bumps. And the formation of the & many traditional processing steps required for flip chip fabrication process. For example, 'solder bump: formation step, flux-up step, removal of soldering material, filling bottom step, and spot hardening step 1. This invention has a non-convex structure and formation method' process Simple and can shorten the process time: the material of the connection layer can be changed as required, the material selectivity is high, and the production cost can be reduced. _ The connecting layer of the present invention may be suitable for a pressing process in a pressure range of 50 psi to 200 psi and a temperature range of 150 to 300 degrees Celsius. The connection layer can be selected from the thickness of 15 / zm to 25 () in m according to the overall assembly requirements. The through hole part of the connection layer can be formed by mechanical, plasma or laser. Page 16 C: \ patent \ 880014 ~ lerso. Ptd 423132 V. Description of the invention (13) Drilling technology to form the hole diameter from 0.3 To 0025 off. The electrical insulating material forming the main J carrier of the connection layer is a heat-resistant, low thermal expansion coefficient, and flexible material with an elastic structure, such as: high-temperature-resistant adhesive polymer, liquid crystal polymer, polyurethane, epoxy Resin / bis-imine imine composition, or polyacetic acid and other materials. Adhesive polymers used on the top and bottom surfaces of the connection layer must withstand an operating temperature of about J 800 ° C and have good dimensional characterization UiinensiQn. Referring now to FIG. 2A, an enlarged sectional view of the electrically insulating material layer 50 of the first embodiment of the connection layer of the present invention. The electrically insulating material layer 50 is formed of a soft material having an elastic structure, such as: high-temperature-resistant adhesive polymer, liquid crystalline polymer, polyimide, epoxy resin / bismaleimide, or multiple lambda Cool materials' This material layer must have heat resistance and high dimensional stability up to approximately 180 ° C. The through hole 52 in the electrically insulating material layer 50 can be formed by mechanical, plasma or laser drilling technology, as shown in FIG. 2B. The diameter of the through hole 52 may be from 0.3 mm to 0.25 mm as needed. After the through-hole 52 is formed: a traditional copper-plated through-hole, vapor deposition, or sputtering method is used on the sidewall 54 to promote a layer of adhesion-promoting copper layer 56 'This adhesion-promoting copper layer 56 can increase the solder material and electrical properties to be implanted later Bonding between insulating material layers 50 and sidewalls 54. This is shown in Figure 2C. In the final step of the process, the 'solder material 58 can be plated into the through hole 52 by electroplating, electroless plating, screen printing or stencil printing, as shown in Fig. 2D.

C: \ patent \ 880014 ~ lerso. Ptd Page 17 4 23132 V. Description of the invention (14) Figure 3 shows the second embodiment of the connection layer of the present invention. Providing a series of main connection layers 60 is similar, but the connection layer The part 64 of 64 must be in the electrically insulating material layer 51. The connection surface 64 in the connecting layer 64 is coated with the adhesive layers 68 and 70. In > i, the battery, the grace material layer 51, is a soft surface molecular polymer having an elastic structure, such as: liquid crystalline polymer, polyurethane, epoxy resin / bismaleimide, or multiple Vinegar and so on. The adhesiveness of the electrically insulating material layer 51 can be completed by the top adhesive bonding layer 68 and the bottom adhesive bonding layer to bond to the integrated circuit chip and the substrate (not shown in the figure). The material can be polyimide, epoxy resin / bismaleimide, or more than 70 esters, etc. According to the specific combination of the integrated circuit chip and the substrate, different adhesive properties can be selected. The material layers used as the load bearing body and the contact layer must have heat resistance characteristics as high as about 18 ° C and good dimensional stability. The through holes in the electrically insulating material layer can be formed by mechanical, electrical or staggered drilling techniques, as shown in circle 3. The diameter of the through hole can be from 0.3 mm to 0.025 mm as required. After the through-holes are formed, a layer of adhesion-promoting copper is applied to the sidewalls by using conventional plated-through holes, evaporation, or sputtering. Combination. This is shown in Figure 3. FIG. 4 illustrates a third embodiment of the connection layer 74 of the present invention. Arrays for the perimeter changes are constructed as grid arrays. In this embodiment, the connection layer is designed as a multi-layer multi-layer structure, in which the redistribution of input / output is completed.

C: \ patent \ 880014 ~ lerscxptd Page 18 4 2313 2 V. Description of the invention (15) ^ Road layout 'The electrical insulating material carrier used therein may not have adhesiveness, and it has a via 82 in the middle, and At the position of the corresponding via hole on the surface of the bottom 80, there are gold ^ as a communication and the top connection metal pad 86 and the bottom connection metal 塾 84. Depending on the surface properties of the integrated electrical sheet and the assembly substrate, apply appropriate bonding materials, such as an electrical insulating material 78 bonded to the surface of the wafer, and an electrical insulating material 88 bonded to the surface of the US board. Both of them have a plurality of conductive bump pads corresponding to their positions. The manufacturing steps are as shown in the manufacturing process of FIG. 2, which include a through-hole side wall 94, a side wall metallization 96, and a solderable metal material 100. The connection layer 74 has an I / O redistribution structure, which can be changed from a peripheral array configuration to an area array configuration change, as shown in FIGS. 7A and 7B. 5A to 7B illustrate three embodiments of a bump-free flip-chip structure having a novel particle shape according to the present invention. 5A and 5B are first structural examples illustrating the flip-chip assembly before and after the hot pressing process using the connection layer 60 and the integrated circuit wafer 110 and the substrate 120 in FIG. 2D. As shown in FIG. 5A, the integrated circuit wafer 11 has a plurality of connection metal pads 112 on the wafer surface 114, a corresponding plurality of connection metal pads 122 on the top surface 124 of the substrate 120, and a bottom surface 128 of the substrate. There are also a plurality of connecting metal pads 126. After the sandwich structure of the integrated circuit chip, the connection layer and the substrate is accurately aligned, it is placed in a hydrogen / nitrogen mixed hydrogen / nitrogen mixture reducing atmosphere at a temperature between 150 ° C and 300 ° C as required, and 50% is applied. ~ 200 psi pressure, hot pressing process to achieve flip-chip bonding electrical conduction bonding, overall flip-chip assembly

C: \ patent \ 880014 ~ lerso. Ptd page 19 4 23132 V. Description of the invention (16) The structure 130 is formed, as shown in Fig. 5B. The thickness of the connection layer 60 is about 15 to 250 μm. The connecting metal pads 112, 122, and 126 may be aluminum alloys, such as Al-Mn, diamond-silver (Al ** Ag), or copper alloys, such as copper-town (Cu-Ni) and copper-shao (Cu-Al), etc. The solderable material used to fill the 60 through-holes in the connection layer can be tin / lead (Sn / Pb), tin / zinc (Sn / Zn) or tin / silver (Sn / Ag) alloys or mixtures. 6A and 6B are second structural examples illustrating the flip-chip assembly using the connection layer 64 and the integrated circuit wafer 110 and the substrate 120 ′ shown in FIG. 3 before and after the hot pressing process. As shown in FIG. 6A, 'integrated circuit wafer ji 〇 has a plurality of connection metal pads 112 on the top surface 124 of the substrate 120 on the wafer surface π 4', and the bottom surface 128 of the substrate 'There are also a plurality of connection metal pads 126, an adhesive 68 on the surface of the connection layer 64 for bonding the wafer, and an adhesive 7Q for bonding the substrate. After the sandwich structure of the integrated circuit wafer 'connection layer and the substrate is accurately aligned, it is placed in a hydrogen / nitrogen mixed hydrogen / nitrogen mixture reducing atmosphere at a temperature between 150 ° C and 300 ° C as required, and 50% is applied. At a pressure of ~ 200 psi, a hot-pressing process is performed to achieve the bonding of the flip-chip bonding electrically conductive. The overall flip-chip structure 140 is formed, as shown in FIG. 6B. The thickness of the connection layer 64 is between about 15 Vni and 250 // II. The connection metal pads 112, 122, and 126 may be aluminum alloy, aluminum-manganese, aluminum-silver, steel alloy, or copper_nickel and steel_aluminum. The solderable material filled in the vias of the connection layer 64 with & may be an alloy or a mixture of tin / lead, tin, zinc, or tin / silver.

423132 V. Description of the invention (17) FIGS. 7A and 7B are illustrations of the third structure implementation of the flip-chip structure before and after the hot pressing process using the connection layer 74, the integrated circuit wafer 110 and the substrate 120 in FIG. 4 example. As shown in FIG. 7A, the integrated circuit wafer 111 has a plurality of connection metal pads 112 on the wafer surface 11 4, the top surface 124 of the substrate 120 has a plurality of corresponding connection metal pads 122, and the bottom surface 128 of the substrate There are also a plurality of connection metal pads 126, an adhesive 78 for bonding wafers on the surface of the connection layer 74, and an adhesive 80 for bonding substrates, having a functional structure of output / input redistribution. Integrate the sandwich structure of the integrated circuit wafer, the connection layer and the substrate, and accurately align it into the reducing atmosphere of an argon / nitrogen mixture at a temperature between i 50 ° C and 300 ° C as required, and apply A pressure of 50 to 200 pounds per square inch is subjected to a hot pressing process to break the bonding of the chip-on-chip electrical connection. The overall chip-on-chip structure 150 is formed, as shown in FIG. 7B. The thickness of the connecting layer 74 is between about 15 and 25 Å. The connection metal pads 112, 122, and 126 may be aluminum alloy, aluminum-manganese, aluminum-silver, copper alloy, or copper-nickel and copper-aluminum. The solderable material used to fill the vias of the connection layer 74 can be tin / lead, tin / zinc, or an alloy or mixture of tin / silver. The bumpless flip-chip structure and method of the present invention are novel and unique, and have practical application in the market. In the embodiments shown in Figs. "73", they have been described in detail. However, the above This is only a preferred embodiment of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, any equivalent changes and modifications made in accordance with the present invention within the scope of the patent should still fall within the scope of the patent of the present invention. .

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Claims (1)

423132 VI. Scope of patent application1. A process method for bumpless flip-chip mounting, including the following steps: Provide an integrated circuit chip, which is equipped with a first plurality of connecting metal plastics * On the surface; a substrate is provided, the substrate has a second plurality of opposing metal potentials on its top surface; a connection layer is provided, which is placed between the integrated circuit wafer and the substrate, and the connection layer has a third A plurality of conductive bump pads' are applied relative to the first and second plurality of connection metal pads; and ~ a sandwich structure that combines the integrated circuit chip, the connection layer, and the substrate is applied under a reducing atmosphere A temperature and a pressure, so that the first plurality of connection metal pads of the integrated circuit wafer and the second plurality of connection metal pads of the substrate are electrically connected, and can pass through the third conductive protrusion of the connection layer And the seat was established. 2. According to the process method of bumpless flip-chip structure described in item 1 of the scope of the patent application, the forming of the connection layer further includes the following steps: providing—an electrically insulating material layer with adhesive properties; A third plurality of openings are formed in the insulating insulating material layer. In the first, the sidewalls of the plurality of openings have a layer of metal that is then promoted; and two solder materials are inserted into the third plurality of openings. . The manufacturing process is achieved by a machine, as described in No. 2 of the scope of application for a bumpless flip-chip structure. The third layer of the connection layer is shaped, electro-polymerized, or laser drilled to achieve the system. Page 22 6. The scope of patent application: The process-method of bumpless flip-chip structure as described in item 2 of the scope of patent application-wherein the bonding metal layer is achieved by a metal plating technology, including plating Through-hole and evaporation or sputtering techniques. According to the process method of bumpless flip-chip structure described in item 2 of the scope of the patent application, wherein the solderable material is achieved by a hole filling technology, including screen printing and stencil printing. 6 * The process for bumpless flip-chip fabrication as described in item 2 of the scope of the patent application-Method 1 'The bearing body of the connection layer is not adhesive. 7. The method for manufacturing bumpless flip-chip structure as described in item 2 of the scope of patent application, further comprising the step of coating an electrically insulating material adhesive on the top and bottom surfaces of the connection layer to increase Adhesion to the integrated circuit wafer and the substrate. The method for manufacturing a bumpless flip-chip structure as described in item 7 of the scope of patent application, wherein the electrically insulating material adhesive is a homogeneous electrically insulating material adhesive. 9. The manufacturing method of bumpless flip-chip structure according to item 2 of the scope of the patent application, wherein the material of the connection layer is an electrically insulating material having an elastic structure with a high temperature and a low thermal expansion coefficient, including a high Molecular polymers, polyurethanes C: \ patent \ 880014 ~ lerso. Ptd page 23 423132 6. Scope of patent application Amine, epoxy resin / bismaleimide and polyvinegar. 1〇_ The process method for bumpless flip-chip fabrication as described in item 2 of the scope of the patent application, wherein the connecting layer has a degree of between about 15βΐίΐ and 25 0 # m. Π. The process method for bumpless flip-chip fabrication as described in item 2 of the scope of the patent application, wherein the material of the connection layer that promotes the metal layer includes copper, nickel, or nickel-chromium alloy ^ 1 2 _ 如The method for manufacturing a bumpless flip-chip structure described in item 2 of the scope of the patent application, wherein the solderable material of the conductive bump pad of the connection layer includes tin / lead, tin / zinc, or tin / silver alloys Or mixture of materials. 13. The process method of bumpless flip-chip structure as described in item 1 of the scope of the patent application, wherein the reducing atmosphere is a reducing atmosphere of a hydrogen / nitrogen mixture of argon / nitrogen, and the temperature is 15 ° C. And 300 degrees Celsius' the applied pressure is 50 to 200 pieces per square hour. 14. A bumpless flip-chip structure, comprising: an integrated circuit wafer 'the integrated circuit wafer is equipped with a first plurality of connection metal pads on its surface; a substrate', the substrate has opposite Second, a plurality of connection metals are integrated on the top surface thereof; and, a connection layer is interposed between the integrated circuit wafer and the substrate, and the connection 4 2 3 13 2 year f ο month name: 3 amendments / more jtw supplementary six, the patent application scope layer has a third plurality of conductive bump pads' with respect to the first and second plurality of connection metal pads; its t In a sandwich structure in which the integrated circuit wafer, the connection layer and the substrate are combined, a temperature and a pressure are applied in a reducing atmosphere, so that the first plurality of connection metal pads of the integrated circuit wafer and the The electrical continuity of the second plurality of connection metal pads of the substrate can be established through the third plurality of conductive bump pads of the connection layer. 15. The bumpless flip-chip structure described in item 14 of the scope of the patent application, wherein the connection layer further includes a plurality of layers and then layers on the top and bottom surfaces thereof to respectively combine the integrated circuit crystals. And the substrate. 16. The bumpless flip-chip structure described in item 14 of the scope of the patent application, wherein the connection layer further includes a layered multilayer structure in which the circuit layout of redistribution of input / output is completed. As a redistribution structure of input / output. Knife " structure, each pass in the material layer σ. 17. The bumpless flip-chip as described in item 14 of the scope of the patent application. The connection layer further includes: a layer of an electrically insulating material having a bonding property, and a third plurality of ports are formed in the electrically insulating layer. ; And, a metal layer which is then promoted is formed on the side wall of the third plurality of openings, and a solderable material is filled in the third plurality of openings; Page 25 6. Scope of patent application 18. The bumpless flip-chip structure described in item 17 of the scope of patent application, wherein the formation of the third plurality of ports of the connection layer is achieved by mechanical, A plasma or laser drill is used to achieve this. 19. The bumpless flip-chip structure as described in item 17 of the scope of the patent application, wherein the bonding metal layer is achieved by a metal plating technology, including a technology of plating through holes and evaporation or sputtering. 20- The bumpless flip-chip structure described in item 17 of the scope of the patent application, wherein the solderable material is achieved by a hole filling technology, including screen printing and stencil printing. 21. According to the bumpless flip-chip structure described in item 17 of the scope of patent application, the supporting body of the connection layer does not have adhesive properties. 2 2. The bumpless flip-chip structure as described in item 17 of the scope of patent application, further comprising the step of applying an electrically insulating material adhesive on the top and bottom surfaces of the connection layer to increase the Adhesion between the integrated circuit wafer and the substrate. 23. The bumpless flip-chip structure according to item 7 of the scope of the patent application, wherein the electrically insulating material adhesive is a homogeneous electrically insulating material adhesive. C: \ patent \ 880014 ^ 1erso. Ptd page 26 4 2 3 13 2 The dead body is revised / corrected / added VI. The scope of patent application 24. No bump as described in item 17 of the scope of patent application Type flip-chip structure, in which the material of the connecting layer is an electrical insulating material with a high-resistance and low thermal expansion coefficient elastic structure, including high molecular polymers, polyimide, epoxy resin / bismaleimide Polyester β 25. The bumpless cladding structure as described in item 17 of the scope of the patent application, wherein the thickness of the connecting layer is between about 15 / zm and 250 μm. 26. The bumpless flip-chip structure described in item 17 of the scope of the patent application, wherein the material of the connection layer followed by the promoting metal layer includes copper, nickel, or a nickel-complex alloy. 27. The bumpless flip-chip structure described in item 17 of the scope of patent application, wherein the solderable material of the conductive bump pad of the connection layer includes tin / lead, tin / zinc, or tin / silver, etc. Alloy or mixture materials. 28. The bumpless flip-chip structure described in item 17 of the scope of the patent application, wherein the reducing atmosphere is a reducing atmosphere of a hydrogen / nitrogen mixture of argon / nitrogen, and the temperature is between 150 ° C and 300 ° C Between degrees, the applied pressure is between 50 and 200 pounds per square inch.