WO2012112937A2 - Procédé et appareil permettant une séparation au niveau tranche - Google Patents

Procédé et appareil permettant une séparation au niveau tranche Download PDF

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Publication number
WO2012112937A2
WO2012112937A2 PCT/US2012/025716 US2012025716W WO2012112937A2 WO 2012112937 A2 WO2012112937 A2 WO 2012112937A2 US 2012025716 W US2012025716 W US 2012025716W WO 2012112937 A2 WO2012112937 A2 WO 2012112937A2
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Prior art keywords
semiconductor substrate
semiconductor
substrate
film
dies
Prior art date
Application number
PCT/US2012/025716
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English (en)
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WO2012112937A3 (fr
Inventor
Klaus Schuegraf
Seshadri Ramaswami
Michael R. Rice
Mohsen S. Salek
Claes H. Bjorkman
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Applied Materials, Inc.
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Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to JP2013554654A priority Critical patent/JP5882364B2/ja
Priority to KR1020137024514A priority patent/KR101579772B1/ko
Priority to CN201280009324.0A priority patent/CN103370780B/zh
Publication of WO2012112937A2 publication Critical patent/WO2012112937A2/fr
Publication of WO2012112937A3 publication Critical patent/WO2012112937A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02076—Cleaning after the substrates have been singulated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Definitions

  • semiconductor integrated circuit die The die are then packaged for use in products.
  • the wafer is mounted on an adhesive tape and is then cut using a saw, for example, along scribe lines or saw streets between active die regions.
  • the singulated die attached to the tape are then available for further packaging steps.
  • the present invention relates generally to semiconductor processing techniques. More particularly, the invention includes a method and apparatus for performing wafer level singulation. Merely by way of example, the invention has been applied to a method of laser singulating and debonding singulated semiconductor dies from a carrier wafer. The method and apparatus is applicable to a variety of semiconductor processing applications including wafer level packaging. [0005] According to an embodiment of the present invention, a method of singulating a plurality of semiconductor dies is provided. The method includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices.
  • the method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate.
  • the method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.
  • a system for singulation of semiconductor dies includes a coating unit operable to form a mask layer on a semiconductor substrate including a plurality of devices, a bonding unit operable to join the semiconductor substrate to a carrier substrate, and a laser processing unit operable to expose a predetermined portion of the mask layer to laser light.
  • the system also includes a development processing unit operable to form a predetermined mask pattern on the semiconductor substrate and a singulation unit operable to form the plurality of
  • Each of the plurality of semiconductor dies is associated with the predetermined mask pattern and includes one or more of the plurality of devices.
  • the system further includes a die separation unit operable to separate the plurality of semiconductor dies from the carrier substrate.
  • an alternative method of singulating a plurality of semiconductor dies includes forming an inert film coupled to a device surface of a semiconductor substrate, removing a portion of the inert film in a peripheral region, and forming an adhesive material coupled to the peripheral region of the device surface of the semiconductor substrate.
  • the method also includes joining the semiconductor substrate to a carrier substrate and forming a plurality of semiconductor dies.
  • the process for forming the plurality of semiconductor dies can include a masking process or be performed using a maskless process, both or either of which can utilize a laser singulation process.
  • the method further includes separating the plurality of semiconductor dies from the carrier substrate.
  • FIGS. 1 A - ID are simplified schematic diagrams illustrating a first process flow according to an embodiment of the present invention
  • FIGS. 2A - 2F are simplified schematic diagrams illustrating a second process flow according to an embodiment of the present invention.
  • FIG. 3 is a plan view of a semiconductor substrate during singulation according to an embodiment of the present invention.
  • FIG. 4 is a simplified flowchart illustrating a method of singulating a plurality of semiconductor dies according to an embodiment of the present invention
  • FIG. 5 is a simplified schematic diagram of a system for singulating a plurality of semiconductor dies according to an embodiment of the present invention.
  • FIG. 6 is a simplified flowchart illustrating a method of singulating a plurality of semiconductor dies according to another embodiment of the present invention.
  • the invention includes a method and apparatus for performing wafer level singulation.
  • the invention has been applied to a method of laser singulating and debonding singulated semiconductor dies from a carrier wafer.
  • the method and apparatus is applicable to a variety of semiconductor processing applications including wafer level packaging.
  • a carrier substrate also referred to as a carrier wafer is provided.
  • a silicon carrier substrate is utilized although other suitable substrates characterized by mechanical rigidity and ability to be processed at appropriate temperatures can be utilized.
  • a semiconductor substrate also referred to as a device wafer, is joined to the carrier substrate.
  • an adhesive is applied to one or more surfaces of the carrier substrate and/or the semiconductor substrate as part of the bonding process.
  • Heat treatment processes can also be performed.
  • a temporary bond is formed during the wafer bonding process.
  • Substrate thinning can be performed using a chemical mechanical polishing (CMP) process or other suitable process to reduce the thickness of the
  • the semiconductor substrate After thinning, the semiconductor substrate is typically attached to a tape and the carrier substrate is removed a wafer debonding process, for example, shearing the substrate, inserting a wedge at the bond region, or the like. Once attached to the tape, the semiconductor substrate can be diced and then dies can be picked for placement during packaging.
  • the use of tape presents several undesirable processing constraints.
  • the use of tape prevents some high temperature processing steps from being performed on the semiconductor substrate.
  • FIGS. 1 A - ID are simplified schematic diagrams illustrating a first process flow according to an embodiment of the present invention.
  • an inert film 110 is formed on a device surface of semiconductor substrate 120.
  • the inert film 1 10 can also be referred to as a mold material.
  • the inert film 110 provides a film compatible with low temperature processing (e.g., less than 300°C, less than 275°C, less than 250°C, or the like) to protect the devices 125a, 125b, and 125c fabricated on the
  • the devices 125a, 125b, and 125c can be a wide variety of semiconductor devices including integrated circuits useful for fabricating processors, memory, and the like.
  • the use of the term "inert" indicates that the film is substantially unreactive with respect to the devices formed on the semiconductor substrate.
  • Embodiments of the present invention utilize inert films that are easy to remove from the semiconductor substrate as described more fully below.
  • a number of inert films are included within the scope of the present invention, including spin on films, spin on carbon films, photoresists, oxide films that are strippable using wet chemistry, solvent soluble films such as an Advanced Patterning Film (APF), which can be deposited by Plasma-Enhanced Chemical Vapor Deposition (PECVD) using an Applied Producer system.
  • APF films e.g., APF, APFe, APFx, or the like
  • PECVD Plasma-Enhanced Chemical Vapor Deposition
  • PECVD Plasma-Enhanced Chemical Vapor Deposition
  • APF films e.g., APF, APFe, APFx, or the like
  • a strippable (i.e., plasma ashable) amorphous carbon hard mask that is suitable for critical patterning steps.
  • Combinations of materials can be utilized to form a composite inert structure having multiple layers of the various materials described herein.
  • an adhesion layer can be applied on top of the inert film 110 or below the inert
  • the compatibility of the inert film 1 10 with low temperature processing makes the embodiments described herein suitable for use with a wide variety of semiconductor substrates including active devices, since, for example, solder bumps present on the semiconductor substrate tend to reflow at temperatures in excess of 250 °C.
  • solder bumps present on the semiconductor substrate tend to reflow at temperatures in excess of 250 °C.
  • the definition of low temperature processing can vary depending on the particular device structures and features.
  • an edge removal process is performed to remove a peripheral portion of the inert film 110, providing peripheral regions 111 of the carrier substrate that are substantially free of the inert film 110.
  • a processing unit including an edge bead removal (EBR) arm can be provided at a corner of the processing unit.
  • the EBR arm rotates around a pivot located at a proximal end of the EBR arm to position a distal end of the EBR arm at a position over an edge of the semiconductor substrate mounted on a spin chuck.
  • An EBR fluid is dispensed through a nozzle located at the distal end of the EBR arm to remove the peripheral portion of the inert film 110.
  • Other suitable techniques for removing a peripheral portion of the inert film 110 are included within the scope of the present invention.
  • an adhesive material 113 is applied to the semiconductor substrate, covering the inert film 110 in the illustrated embodiment.
  • the adhesive material is then planarized to form an annular ring 1 14 at the peripheral portions of the carrier substrate as illustrated in FIG. ID.
  • thinning of both the inert layer 110 and the annular ring 114 can be accomplished during these processing steps.
  • the semiconductor substrate can be bonded to the carrier substrate for further processing, such as thinning.
  • a planar structure is illustrated in FIG. ID, such a planar structure is not required by the present invention.
  • cavities extending toward the device surface can be formed in the inert film and/or the adhesive film.
  • the inert film and/or the adhesive film are applied to the carrier substrate rather than the semiconductor substrate.
  • the carrier substrate rather than the semiconductor substrate.
  • other predetermined portions of the semiconductor substrate are coated with the adhesive material.
  • the adhesive material can be removed at the locations of these partial die or dummy die due to the generally circular wafer shape and generally rectangular die shape.
  • the inert material can be removed at the locations of these partial die or dummy die and adhesive material can be applied at these locations to provide a patchwork of adhesive locations distributed across the surface of the semiconductor substrate.
  • dots of solvent can be applied followed by dots of adhesive.
  • dies that are defective i.e., non-yielding dies
  • the adhesive can be applied to these die.
  • the application of the adhesive to the non-yielding die can prevent these die from being picked at a later stage of processing, simplifying the picking process and providing downstream intelligence.
  • FIGS. 2 A - 2F are simplified schematic diagrams illustrating a second process flow according to an embodiment of the present invention.
  • the second process flow includes a wafer bonding, laser singulation, and die removal process provided by embodiments of the present invention.
  • the semiconductor substrate 120 including the inert layer 110 and the annular ring 114 is positioned adjacent a carrier substrate 100 having a bonding surface 105.
  • the carrier substrate comprises a silicon substrate.
  • the carrier substrate includes a glass material to provide for
  • a wafer bonding process is performed to join the semiconductor substrate to the carrier substrate.
  • the wafer bonding process can utilize one of several wafer bonding techniques. These techniques include low temperature bonding methods such as anodic, eutectic, fusion, covalent, glass frit, and/or other bonding techniques.
  • bonding of the two substrates is performed using a variety of techniques. In a specific embodiment, the bonding occurs using a room temperature covalent bonding process.
  • Each of the bonding surfaces is cleaned and activated, for example, by plasma activation or by wet processing. The activated surfaces are brought in contact with each other to cause a sticking action.
  • vent holes are provided (for example, in a radial direction) passing through the annular ring 114 to provide for outgassing to prevent bubble formation in the bonded structure.
  • the backside 124 of the semiconductor substrate is thinned using one or more processing steps to reduce the thickness of this substrate.
  • processing steps may include CMP, grinding, etch back, any combination of these, and the like.
  • an etch stop layer is integrated into the semiconductor substrate to assist in termination of the thinning process.
  • Plasma ashing and/or other cleaning processes can be performed as part of the thinning process.
  • the structure includes the carrier substrate 100, the inert layer 110 at central portions of the structure, annular adhesive layer 114, and the thinned semiconductor substrate 120 with devices 125a/b/c. Additional protective layers can be incorporated in addition to the illustrated layers are discussed throughout the present specification.
  • Embodiments of the present invention utilize a laser singulation process.
  • a mask layer 130 is formed on a surface of the semiconductor substrate, for example, the surface opposing the device surface.
  • the mask layer 130 can be a single layer or a multi-layer structure including one or more layers operable to protect the surface of the semiconductor substrate, which may have solder balls or other structures formed therein.
  • the laser mask is formed directly on the silicon surface, but this is not required by the present invention and other embodiments utilize a two-step mask layer, for example, a polyimide/oxide combination.
  • thinning of the semiconductor substrate is illustrated as occurring prior to singulation, other embodiments perform thinning after singulation or combinations thereof.
  • a variety of suitable masking materials are utilized according to embodiments of the present invention including polyimide materials, photosensitive polymers, non- photosensitive polymers, photoresist, combinations thereof, or the like.
  • Backside alignment i.e., alignment marks on the device surface of the
  • the etch mask layer e.g., a polyimide and/or a thin protect layer
  • the hard mask is used as described below.
  • mask layer 130 Although a single layer is illustrated for mask layer 130, this is not required by the present invention and multiple layer stacks can be utilized including, for example, a polyimide, an oxide, resist, combinations thereof, or the like. Thus, one or more materials may provide for masking during laser ablation and other materials can provide for masking during etching.
  • laser ablation is utilized in some embodiments, other embodiments utilize a lithography process in conjunction with laser ablation or as a replacement for laser ablation.
  • no mask layer is utilized and a laser ablation process, which can be based on a Cartesian coordinate system, is used to perform the device singulation.
  • a mechanical separation process such as diamond sawing, is used to perform the device singulation.
  • combinations of these techniques can be utilized.
  • multiple techniques including laser ablation without use of a mask, laser patterning of a mask/laser ablation/etching process, or mechanical
  • An etching process is then used to remove portions of the semiconductor substrate underlying the portions of the mask layer removed by laser ablation (i.e., a scribe etch process) as illustrated in FIG. 2E.
  • the etching process can include a variety of material removal processing including dry etching, reactive ion etching, wet etching, or the like.
  • the etching process results in singulation of the semiconductor dies.
  • One benefit provided by the laser singulation process is a very small scribe street.
  • the etch can be supplemented with an additional laser ablation process to ablate a portion of the structures.
  • the etch process may be a multi-step process involving multiple etching steps, laser ablation, combinations thereof, or the like.
  • a liner can be applied to the trenches, for example, using a low temperature oxide film formation process. Metal sputtering and/or plating can then be performed as appropriate to the particular application.
  • the dies can be removed easily as illustrated in FIG. 2F, for example, using a vacuum-assisted pick and place tool in contact with the backside of the semiconductor substrate since the inert film has low adhesion to the device surface of the semiconductor substrate in comparison to the adhesive material.
  • FIG. 2E because adhesive material is only in contact with the semiconductor substrate at the peripheral regions free of devices structures, the adhesive material does not adhere the singulated dies to the carrier substrate.
  • the surface interaction between the device structures and the inert material e.g., van der Waals forces
  • a soft adhesion promoter is deposited on the semiconductor substrate prior to deposition of the inert layer 110 illustrated in FIG. 1 A.
  • a low temperature thermal process is utilized to reduce any residual adhesion associated with the inert layer and to assist in the die removal process.
  • the individual dies can be picked with a pick tool, for example, a vacuum pick tool and residue can be cleaned from the front side of the device wafer (e.g., with an oxygen plasma) using a suitable cleaning technique.
  • a pick tool for example, a vacuum pick tool and residue can be cleaned from the front side of the device wafer (e.g., with an oxygen plasma) using a suitable cleaning technique.
  • the die can be placed on another carrier, placed on tape, flipped onto another pick tool/tape, etc., or the like.
  • a pick tool for example, a vacuum pick tool and residue can be cleaned from the front side of the device wafer (e.g., with an oxygen plasma) using a suitable cleaning technique.
  • the die can be placed on another carrier, placed on tape, flipped onto another pick tool/tape, etc., or the like.
  • a variety of picking tools can be utilized including vacuum tools with an O-ring fixture, shoes with non-circular shapes suitable for the particular dies, or the like.
  • a pixilated e-chuck can be used as a carrier on which the singulated die can be placed after picking, facilitating wafer-level cleaning processes.
  • one of several types of carriers, trays, a row of trays, or the like can be used to receive the individual die. Because the surface forces of the individual die are reduced in comparison to a thinned wafer, curling of the dies is typically not an issue, allowing a high level of flexibility in placement of the dies after the picking process.
  • the picking station is integrated with a die bonding tool.
  • a protection layer can be applied prior to application of the inert film.
  • the devices utilize copper pads with an aluminum layer supporting a silver-tin solder ball, these structures can be damaged in a post-picking plasma ashing cleaning process.
  • a protection film can be formed prior to formation of the inert layer 110 illustrated in FIG. 1 A. After the inert film is cleaned, the protection layer can be removed using suitable cleaning processes appropriate for the protection layer.
  • Exemplary protection layer include materials such as polymers, spun on materials, other films, combinations thereof, or the like.
  • a single layer of the inert film 110 is formed on the semiconductor substrate in the embodiment illustrated in FIG. 1 A, the present invention is not limited to this single layer and multi-layer structures can be utilized as appropriate to the particular application.
  • a compliance layer can be formed so that the solder balls or other structures can be surrounded on one or more sides by the compliance layer.
  • a thermal process can be used with a glass carrier substrate in which light in the visible spectrum (e.g., from a lamp) shines through the carrier wafer in a predetermined pattern to locally heat the inert material and thereby facilitate die removal.
  • FIG. 3 is a plan view of a semiconductor substrate 120 during singulation according to an embodiment of the present invention. As illustrated in FIG.
  • FIG. 4 is a simplified flowchart illustrating a method of singulating a plurality of semiconductor dies according to an embodiment of the present invention.
  • the method 400 includes providing a carrier substrate (410) and joining a semiconductor substrate to the carrier substrate (412).
  • the semiconductor substrate includes a plurality of devices.
  • the carrier substrate comprises a silicon substrate although other substrates, including glass substrates can be utilized.
  • joining the semiconductor substrate to the carrier substrate includes forming a film on the semiconductor substrate, for example an inert film (e.g., an amorphous carbon film) that is substantially unreactive with devices on the semiconductor substrate.
  • the edge portion of the film is removed and an adhesive layer coupled to the semiconductor substrate is formed.
  • the adhesive layer can be formed as an annular layer surrounding the film.
  • the carrier substrate, the film, and the adhesive layer are brought into contact to bond the two substrates together.
  • the film can be a single layer of a single material or be a composite structure including multiple materials including adhesion promoters, protection layers, and the like.
  • a photosensitive material is used as a combination adhesive/inert material.
  • a material that becomes adhesive upon exposure to light can be applied and the peripheral or other portions of the material can be exposed, creating an adhesive ring or pattern in the material.
  • Unexposed material will be characterized by low adhesiveness, providing the function associated with the inert material descried herein.
  • a complementary material is used in which exposure leads to a reduction in the adhesiveness of the material and lack of exposure is associated with adhesiveness.
  • joining the semiconductor substrate to the carrier substrate includes forming an inert film on the semiconductor substrate and removing a portion of the inert film associated with a predetermined pattern associated with one or more of the plurality of devices. As an example, if some testing of the dies has been performed and it is determined that a particular die is not fully functional, the adhesive can be applied adjacent the non-functional die, preventing it from being separated during later processing.
  • the method also includes forming a mask layer on the semiconductor substrate (414), exposing a predetermined portion of the mask layer to light (416), and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate (418).
  • forming the predetermined mask pattern can include developing the predetermined portion of the mask layer and etching the
  • portions of the semiconductor substrate under the open areas of the mask layer can be etched all the way through the semiconductor substrate to reach the film/adhesive layer or the carrier substrate.
  • the method further includes forming the plurality of semiconductor dies (420) and separating the plurality of semiconductor dies from the carrier substrate (422).
  • Each of the plurality of semiconductor dies is associated with the predetermined mask pattern and includes one or more of the plurality of devices.
  • the plurality of semiconductor dies can be cleaned using one of various processes after die separation.
  • the picking of the die from the carrier substrate can be performed one at a time or using an apparatus that can pick multiple die simultaneously (gang separation).
  • the vacuum for the various picking elements can be independently controlled to not pick the die that have been determined to be unusable or for other reasons.
  • the die separation tool can be programmed to pick predetermined die and leave the remaining die attached to the carrier substrate.
  • FIG. 5 is a simplified schematic diagram of a system for singulating a plurality of semiconductor dies according to an embodiment of the present invention.
  • the system 500 includes control devices, for example, an input/output interface 510, a processor 512 (also referred to as a data processor), and a computer readable medium 514 such as memory.
  • the processor 512 and the memory 514 interact with the I/O interface to provide for user control of the various units described herein.
  • the processor 512 represents a central processing unit of any type of architecture, such as a CISC (Complex Instruction Set Computing), RISC (Reduced Instruction Set Computing), VLIW (Very Long Instruction Word), or a hybrid architecture, although any appropriate processor may be used.
  • CISC Complex Instruction Set Computing
  • RISC Reduced Instruction Set Computing
  • VLIW Very Long Instruction Word
  • the processor 512 executes instructions and includes that portion of a computer that controls the operation of the entire computer. Although not depicted in FIG. 5, the processor 512 typically includes a control unit that organizes data and program storage in memory and transfers data and other information between the various parts of the computer. The processor 512 receives input data from the I/O interface 510 and/or a network (not shown) and reads and stores code and data in the computer readable medium 514 and presents data to the I/O interface 510.
  • FIG. 5 Although a single processor is illustrated in FIG. 5, the disclosed embodiment applies equally to computers that may have multiple processors and to computers that may have multiple busses with some or all performing different functions in different ways.
  • the computer readable medium 514 represents one or more mechanisms for storing data.
  • the computer readable medium 514 may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and/or other machine-readable media. In other embodiments, any appropriate type of storage device may be used. Although only one computer readable medium 514 is shown, multiple computer readable media and multiple types of storage devices may be present. Further, although the computer readable medium 514 is illustrated as connected to the processor 512, it may be distributed across other computers, for example on a server.
  • the computer readable medium 514 includes a controller (not shown in FIG. 5) and data items.
  • the controller includes instructions capable of being executed on the processor 512 to carry out the methods described more fully throughout the present specification. In another embodiment, some or all of the functions are carried out via hardware in lieu of a processor-based system.
  • the controller is a web browser, but in other embodiments the controller may be a database system, a file system, an electronic mail system, a media manager, an image manager, or may include any other functions capable of accessing data items.
  • the computer readable medium 514 may also contain additional software and data (not shown), which is not necessary to understand the invention.
  • the system further includes a coating unit 520 operable to form a mask layer on a semiconductor substrate including a plurality of devices and a bonding unit 530 operable to join the semiconductor substrate to a carrier substrate.
  • the coating unit can be used to form the various coating layers described herein.
  • a processing and development unit 540 includes one or more sub-units, including a laser processing unit 542 operable to expose a
  • the singulation unit 546 can include a development unit and an etching unit. Although these sub-units are illustrated as combined in the processing and development unit 540 in the embodiment illustrated in FIG. 5, this is not required by the present invention and these sub-units may be stand alone units.
  • the laser processing unit 542 can include a laser source or be optical coupled to an external laser source, for example, through a fiber optic cable.
  • a die separation unit 550 and a cleaning unit 560 are included in system 500.
  • the die separation unit 550 is operable to separate the plurality of semiconductor dies from the carrier substrate.
  • FIG. 6 is a simplified flowchart illustrating a method of singulating a plurality of semiconductor dies according to another embodiment of the present invention.
  • the method includes providing a semiconductor substrate having a plurality of devices formed thereon and forming an inert material coupled to the device surface of the
  • the inert material may be formed in contact with an adhesion layer formed on the semiconductor substrate.
  • the inert film covers the entire semiconductor substrate, whereas in other embodiments, portions of the semiconductor substrate are free of the inert film.
  • the inert material can be a variety of materials that provide a film that is compatible with low temperature processing and substantially unreactive with respect to the devices formed on the semiconductor substrate.
  • the inert film which can be a multilayer composite structure, can be an APF deposited by PECVD, although the inert films are not limited to this example.
  • the method also includes removing a peripheral portion of the inert film (612), which, in some embodiments, exposes a peripheral portion of the semiconductor substrate.
  • the inert film is completely removed in the peripheral region, whereas in other embodiments, part of the inert film remains coupled to the semiconductor substrate in the peripheral region.
  • an EBR process can be used to remove the peripheral portion of the inert film.
  • the method further includes forming an adhesive material coupled to the device surface of the semiconductor substrate (614).
  • the adhesive material can be applied directly to the exposed semiconductor substrate in the peripheral region, applied to an adhesion promoting layer, or the like.
  • an upper surface of the adhesive material is coplanar with an upper surface of the inert material, providing a high quality wafer bonding surface for subsequent wafer bonding processes.
  • a substrate or wafer bonding process is used to join the semiconductor substrate to a carrier substrate (616).
  • the inert material / adhesion material layer can be bonded to a bonding surface of the carrier substrate, forming a compound semiconductor structure.
  • a portion of the semiconductor substrate is removed using a wafer thinning process such as CMP to reduce the thickness of the semiconductor substrate as appropriate for device operation.
  • a mask layer is formed and processed (e.g., on the surface of the semiconductor substrate opposing the device surface) to form a predetermined mask pattern on the semiconductor substrate, for example, by exposing a predetermined portion of the mask layer to light.
  • the method includes processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate.
  • forming the predetermined mask pattern can include developing the predetermined portion of the mask layer and etching the predetermined portion of the mask layer to expose a surface of the semiconductor substrate.
  • portions of the semiconductor substrate under the open areas of the mask layer can be etched all the way through the semiconductor substrate to reach the film/adhesive layer or the carrier substrate.
  • the method additionally includes forming a plurality of semiconductor dies (618) and separating the plurality of semiconductor dies from the carrier substrate (620).
  • a laser singulation method is utilized to singulate the dies as described above.
  • Each of the plurality of semiconductor dies typically includes one or more of the plurality of devices.
  • the plurality of semiconductor dies can be cleaned using one of various processes after die separation.
  • the picking of the die from the carrier substrate can be performed one at a time or using an apparatus that can pick multiple die simultaneously (gang separation).
  • the vacuum for the various picking elements can be independently controlled to not pick the die that have been determined to be unusable or for other reasons.
  • the die separation tool can be programmed to pick predetermined die and leave the remaining die attached to the carrier substrate.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Laser Beam Processing (AREA)

Abstract

La présente invention se rapporte à un procédé permettant de séparer une pluralité de dés semi-conducteurs. Ledit procédé consiste à utiliser un substrat de support et à unir un substrat semi-conducteur au substrat de support. Le substrat semi-conducteur comprend une pluralité de dispositifs. Le procédé consiste également à former une couche de masque sur le substrat semi-conducteur, à exposer à la lumière une partie prédéterminée de la couche de masque et à traiter la partie prédéterminée de la couche de masque pour former un motif de masque prédéterminé sur le substrat semi-conducteur. En outre, le procédé consiste à former la pluralité de dés semi-conducteurs, chaque dé semi-conducteur de la pluralité de dés semi-conducteurs étant associé au motif de masque prédéterminé et comprenant un ou plusieurs dispositifs de la pluralité de dispositifs et à séparer la pluralité de dés semi-conducteurs du substrat de support.
PCT/US2012/025716 2011-02-18 2012-02-17 Procédé et appareil permettant une séparation au niveau tranche WO2012112937A2 (fr)

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JP2013554654A JP5882364B2 (ja) 2011-02-18 2012-02-17 ウエハレベルのシンギュレーションのための方法
KR1020137024514A KR101579772B1 (ko) 2011-02-18 2012-02-17 웨이퍼 레벨 싱귤레이션 방법 및 시스템
CN201280009324.0A CN103370780B (zh) 2011-02-18 2012-02-17 晶片级分割的方法和系统

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CN103370780A (zh) 2013-10-23
WO2012112937A3 (fr) 2013-02-21
US20130045570A1 (en) 2013-02-21
TWI570795B (zh) 2017-02-11
TW201241907A (en) 2012-10-16
JP5882364B2 (ja) 2016-03-09
JP2014511569A (ja) 2014-05-15
US20140196850A1 (en) 2014-07-17
US9502294B2 (en) 2016-11-22
CN103370780B (zh) 2016-01-20
KR20130130834A (ko) 2013-12-02
KR101579772B1 (ko) 2015-12-23
US8580615B2 (en) 2013-11-12

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