WO2012070171A1 - Dispositif d'imagerie à semiconducteur et son procédé de fabrication - Google Patents

Dispositif d'imagerie à semiconducteur et son procédé de fabrication Download PDF

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WO2012070171A1
WO2012070171A1 PCT/JP2011/004339 JP2011004339W WO2012070171A1 WO 2012070171 A1 WO2012070171 A1 WO 2012070171A1 JP 2011004339 W JP2011004339 W JP 2011004339W WO 2012070171 A1 WO2012070171 A1 WO 2012070171A1
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photoelectric conversion
pixel
imaging device
blocking layer
state imaging
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PCT/JP2011/004339
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English (en)
Japanese (ja)
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光雄 安平
晴久 横山
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

Definitions

  • the present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate.
  • a pixel unit 900 includes a p-type semiconductor substrate 305, an emitter electrode 310, a p-type base layer 315, and an n + -type emitter layer. 320, a base electrode 325, a lower electrode 340, an i-type photoelectric conversion film 341, a transparent electrode 344, an insulating film 347, and a p-type blocking layer 342.
  • adjacent photoelectric conversion films 341 are formed in isolation.
  • a blocking layer 342 is formed on the upper surface of the photoelectric conversion film 341, and side surfaces of the photoelectric conversion film 341 and the blocking layer 342 are covered with an insulating film 347.
  • the signal charge generated in the photoelectric conversion film 341 passes through the lower electrode 340, moves to the base layer 315 through the base electrode 325, and lowers the potential of the base layer 315. At this time, a negative pulse is applied to the transparent electrode 344. Then, after a predetermined accumulation time, the emitter electrode 310 is connected to a signal readout capacitor, and a positive pulse is applied to the transparent electrode 344, whereby the signal charge of the base layer 315 is read out through the emitter layer 320 (not shown). Is read out. Thereafter, the signal charge is output to the outside through an amplifier (not shown). Note that a MOS transistor is used when signal charges are output to the outside.
  • the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the p-type blocking layer to the i-type photoelectric conversion film is an i-type photoelectric conversion film.
  • the interface state is also called a surface state, and is an energy level that captures and emits electrons and holes generated at the interface of different substances. Since the interface state is energetically located between the valence band and the conduction band, the energy between the interface state and the valence band or the conduction band is the energy between the valence band and the conduction band. Smaller and easier to move the charge by heat.
  • the charge read out as signal charge is the charge present in the depletion layer.
  • the depletion layer extends to the region where the interface states exist on the side surfaces of the photoelectric conversion film and the blocking layer, a large number of interface states are included in the depletion layer. Then, the charge in the valence band in the depletion layer is thermally excited from the valence band to the interface state, and then excited from the interface state to the conduction band, and may be read as a signal charge.
  • This readout of signal charges is a phenomenon that occurs even when no light is incident, and is called dark current.
  • the charge trapped in the interface state from the conduction band in the depletion layer may be excited to the conduction band at a timing delayed from the original readout frame and read out as a signal charge.
  • This readout of the signal charge causes a trapping afterimage.
  • the present invention has been made to solve the above problem, and is a depletion layer existing in a range from a junction between an i-type photoelectric conversion film and a blocking layer made of an impurity semiconductor material to an i-type photoelectric conversion film.
  • the present invention provides a solid-state imaging device and a method for manufacturing the same that can prevent the interface state generated on the side surface of the blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material from being spread. Objective.
  • a solid-state imaging device has a plurality of pixels, and is isolated for each pixel on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and the interlayer insulating film.
  • the solid-state imaging device manufacturing method is a method for manufacturing a solid-state imaging device having a plurality of pixels, the step of forming an interlayer insulating film on a semiconductor substrate, and the pixel on the interlayer insulating film.
  • the blocking layer covers part or all of the side surface of the photoelectric conversion film. That is, the side surface of the depletion layer present in the range of the i-type photoelectric conversion film from the junction between the blocking layer and the photoelectric conversion film is covered with the blocking layer. Therefore, the depletion layer does not contact the interface state generated on the side surface of the blocking layer and the translucent upper electrode.
  • the blocking layer covers part or all of the side surface of the photoelectric conversion film, so that the depletion layer and the interface state can be prevented from coming into contact with each other.As a result, the influence of the interface state is reduced, Generation of dark current and trapping afterimage can be suppressed.
  • the depletion layer existing in the range of the i-type photoelectric conversion film from the junction between the i-type photoelectric conversion film and the blocking layer made of the impurity semiconductor material is a blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material. It can be suppressed that the interface state generated on the side surface is expanded to a region where the interface state is generated.
  • the blocking layer covers the upper surface of the photoelectric conversion film, and signal charges generated in the photoelectric conversion film can be retained in the photoelectric conversion film. Therefore, the transfer efficiency of signal charges can be improved.
  • the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the blocking layer formed of the impurity semiconductor material to the i-type photoelectric conversion film is an i-type photoelectric conversion film. It is possible to manufacture a solid-state imaging device that can suppress spreading to a region where an interface state generated on the side surface of the blocking layer formed of the conversion film and the impurity semiconductor material is generated.
  • FIG. 1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a top view for 6 pixels in the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG.
  • FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12.
  • FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 4 of this invention.
  • FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15.
  • FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. It is sectional drawing of the conventional solid-state imaging device.
  • FIG. 1 is a plan view showing six pixels as a partial region in the solid-state imaging device 1 shown in FIG. Each pixel 100 is partitioned by a pixel boundary 43.
  • Each pixel 100 includes a reset gate 10, an amplification transistor 11, a storage diode 15 in an n-type impurity diffusion layer, and a floating diffusion in an n-type impurity diffusion layer. 16, an n-type impurity diffusion layer reset transistor drain 17, a transfer gate 18, contacts 31 to 34, and a metal wiring 45.
  • FIG. 3 is a cross-sectional view of the pixel 100 of the solid-state imaging device 1 shown in FIG. 1, and shows a cross-section A-A ′ of FIG.
  • an STI Shallow Trench Isolation
  • a channel stopper 13 is formed in the semiconductor substrate 5 on which the p-type well is formed.
  • a storage diode 15 is formed in each pixel 100.
  • a reset transistor drain 17 is formed in each pixel 100.
  • a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked.
  • a reset gate 10 and an amplification transistor gate 19 are sequentially stacked.
  • a transfer gate 18 and an amplification transistor gate 19 are sequentially stacked.
  • a connection electrode 23 is formed within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.
  • Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20.
  • wirings 24 and 25 for example, formed of Al or Cu
  • connection electrodes 26 is formed.
  • the interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.
  • the pixel electrode 40 is formed on the interlayer insulating film 22 so as to be isolated for each pixel.
  • photoelectric conversion films 41a having spectral sensitivity with respect to red light and photoelectric conversion films 41b having spectral sensitivity with respect to green light are formed alternately and isolated from each other.
  • the solid-state imaging device 1 also has a photoelectric conversion film having spectral sensitivity to blue light.
  • FIG. 3 which is a cross section taken along line AA ′ in FIG. Not.
  • the photoelectric conversion films of the respective colors are collectively referred to as the photoelectric conversion film 41 without being distinguished.
  • the photoelectric conversion film 41 is formed of an i-type semiconductor material made of an inorganic photoconductive film or the like, and the red, green, and blue spectral sensitivities are adjusted by changing the composition ratio of the same semiconductor material.
  • the spectral sensitivity of the photoelectric conversion film 41 is controlled by changing the ratio of ⁇ -Si 1-x C x : x. It has gained.
  • a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • the part 42 b corresponding to the space between the photoelectric conversion films 41 of the blocking layer 42 enters between the adjacent photoelectric conversion films 41 and covers all the side surfaces of the photoelectric conversion film 41.
  • a gap is provided between the blocking layer 42 and the side surface of the pixel electrode 40 so that the blocking layer 42 and the pixel electrode 40 do not contact each other, and the photoelectric conversion film 41 exists in this gap. .
  • a transparent electrode 44 (formed of, for example, ITO or ZnO) is formed as a translucent upper electrode across a plurality of pixels, and the transparent electrode 44 extends over the entire pixel region 61. ing. Between adjacent photoelectric conversion films 41 is a pixel boundary portion 43. In the pixel boundary portion 43, a transparent electrode 44 is formed so as to cover a portion 42 b of the blocking layer corresponding to the space between the photoelectric conversion films 41.
  • a metal wiring 45 is formed on the transparent electrode 44 in the pixel boundary portion 43.
  • the shape of the metal wiring 45 passes between all adjacent pixels in the pixel region 61, and has a mesh shape when the entire pixel region 61 is viewed in plan. Further, the metal wiring 45 is formed so as to surround the pixel region 61. That is, the metal wiring 45 extends from the central portion of the pixel region 61 toward the periphery of the pixel region 61, and connects the central portion of the pixel region 61 and the periphery of the pixel region 61.
  • the metal wiring 45 is made of a material having a lower electrical resistivity than the material of the transparent electrode 44.
  • the metal wiring 45 is provided in the pixel boundary part 43 which is not a light-receiving part, an aperture ratio does not fall by presence of the metal wiring 45. Further, the maximum allowable width of the metal wiring 45 is the same as the width of the pixel boundary 43. 3.
  • Driving of the solid-state imaging device 1 The incident light is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 44, and the generated charge is attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 44 and the pixel electrode 40, and passes through the connection electrodes 23 and 26 from the pixel electrode 40. Thus, it is temporarily stored in the storage diode 15.
  • the charge is transferred and stored from the storage diode 15 to the floating diffusion 16 by the action of the transfer gate 18.
  • the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside.
  • the reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17. 4). Effect A depletion layer exists in the range of the i-type photoelectric conversion film 41 from the junction between the photoelectric conversion film 41 and the blocking layer 42. In this configuration, the portion 42b corresponding to the space between the adjacent photoelectric conversion films 41 of the blocking layer 42 enters between the photoelectric conversion films 41, and all of the side surfaces of the i-type photoelectric conversion film 41 are p-type blocking. Covered with a layer 42. Therefore, the side surface of the depletion layer is covered with the blocking layer 42, and the depletion layer does not extend to the region where the interface state is generated. Therefore, dark current and trapping afterimages due to interface states can be suppressed.
  • the photoelectric conversion film 41 having a predetermined spectral sensitivity is used for each pixel without using a color filter, there is no light absorption by the color filter, and light loss can be avoided.
  • the metal wiring 45 is formed on the transparent electrode 44, the combined resistance of the transparent electrode 44 and the metal wiring 45 is made smaller than the resistance of the transparent electrode 44 alone. Therefore, the voltage drop at the center of the pixel region 61 that has been increased due to the resistance of the transparent electrode 44 is reduced, and the voltage drop at the center of the pixel region 61 can be suppressed. As a result, it is possible to reduce the degradation of the image quality of the captured image that occurs when the magnitude of the voltage drop differs for each location of the pixel region 61.
  • an STI (Shallow Trench Isolation) 12 that separates transistors and diffusion layer elements is formed on a p-type semiconductor substrate 5.
  • the semiconductor substrate 5 is dry-etched to form a trench having a depth of 200 nm to 400 nm serving as an isolation region.
  • sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 ⁇ 10 13 cm ⁇ 2 to B ion implantation is performed at 3 ⁇ 10 13 cm ⁇ 2 to form the channel stopper 13 of the p + layer.
  • the inside of the formed trench is filled with an insulating film, and planarized by CMP (Chemical Mechanical Polishing), thereby forming the STI 12.
  • CMP Chemical Mechanical Polishing
  • the gate oxide film 14 which becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed, for example, by 5 to 10 nm by thermal oxidation or plasma oxidation.
  • a Poly-Si film for example, 100 nm to 200 nm is deposited by thermal CVD, plasma CVD, or the like, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19, and the reset gate 10 made of the Poly-Si film are formed.
  • P and As are ion-implanted into the p-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 ⁇ 10 14 cm ⁇ 2 to 2 ⁇ 10 15 cm ⁇ 2 , so that the storage diode 15, the floating diffusion 16 and the n-type impurity layers of the reset transistor drain 17 are formed simultaneously.
  • a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film, and the electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is established. Connected.
  • An interlayer insulating film 20 made of a CVD oxide film is formed, for example, to 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique.
  • a W (tungsten) plug is embedded in the opened contact opening to form a connection electrode 23 of the W plug, and electrical connection to the storage diode 15 and the reset transistor drain 17 is formed.
  • a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed.
  • a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.
  • a metal film made of Al, W, Mo (molybdenum) or the like is deposited to 100 nm to 300 nm, and a pixel electrode having a predetermined shape is formed by a general photolithography technique and an etching technique. 40 is formed.
  • the pixel electrode 40 is formed so as to be isolated for each pixel, and the area where the pixel electrode 40 is separated determines the effective aperture ratio of the pixel. For example, if the separation width between the pixels is 1/10 to 2/10 of the pixel size of 1.0 ⁇ m to 1.4 ⁇ m, the aperture ratio is estimated to be about 64% to about 81%.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited to 100 nm to 1 ⁇ m by plasma CVD or sputtering so as to cover the pixel electrode 40 and the interlayer insulating film 22.
  • An i-type photoelectric conversion film 41a is formed.
  • this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x.
  • a predetermined resist pattern 70 is formed on the photoelectric conversion film 41a by a general photolithography technique.
  • the size of each pixel of the photoelectric conversion film 41a is, for example, 0.9 ⁇ m to 1.3 ⁇ m in a pixel size of 1.0 ⁇ m to 1.4 ⁇ m.
  • the photoelectric conversion film 41a is etched by a general etching technique to form a photoelectric conversion film 41a having a predetermined pattern.
  • FIG. 7A by repeating the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 5B to 6B, in each pixel 100, on each corresponding pixel electrode 40, An i-type photoelectric conversion film 41b is formed in isolation for each pixel.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the adjacent photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the pixel boundary part 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
  • an ⁇ -Si film having a predetermined energy gap so as to be a blocking layer of the i-type photoelectric conversion film 41 by plasma CVD or sputtering so as to cover the upper surface and side surfaces of the photoelectric conversion film 41.
  • a p-type blocking layer 42 is formed over a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • a transparent electrode 44 made of ITO or ZnO is formed by several tens to several hundreds nm by sputtering or CVD. Both the portion 42 a and the portion 42 b of the blocking layer 42 are covered with the transparent electrode 44.
  • a metal wiring 45 is deposited on the transparent electrode 44 by sputtering or CVD to a thickness of 100 to 300 nm.
  • a predetermined resist pattern 71 is formed on the metal wiring 45 by a general photolithography technique.
  • the metal wiring 45 is etched by a general etching technique to form a mesh-like metal wiring 45 on the transparent electrode 44. Thereby, the solid-state imaging device shown in FIG. 3 is obtained.
  • FIG. 9 is a cross-sectional view of the pixel 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. For the sake of convenience, the description will be made using three pixels 200 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • each pixel 200 a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an insulating film 46 are formed.
  • the photoelectric conversion films 41a and 41b are formed so as to be isolated for each pixel, and at least two of them have different spectral sensitivity characteristics.
  • a blocking layer 42 is formed across a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • the upper half of the side surface of the photoelectric conversion film 41 is covered with a portion 42 b corresponding to the space between the photoelectric conversion films 41 adjacent to the blocking layer 42.
  • An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • upper half and lower half do not indicate that the upper half is strictly divided into upper and lower halves, but indicate respective portions where the photoelectric conversion film 41 is divided into upper and lower portions. That is, the height from the interlayer insulating film 22 to the lower half of the photoelectric conversion film 41 may be slightly higher or lower than one half of the height of the photoelectric conversion film 41 from the interlayer insulating film 22. If the insulating film 46 is formed to be higher than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be easily embedded.
  • the insulating film 46 is formed to be lower than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be formed deeply, and the photoelectric conversion film The photoelectric conversion efficiency by 41 can be improved.
  • the height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. This is to prevent the pixel electrode 40 and the p-type blocking layer 42 from coming into contact with each other and causing a short circuit.
  • a mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the insulating film 46 is embedded in the lower half between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • the pixel electrode 40 can be formed up to a place where both ends of the pixel contact the pixel boundary portion 43.
  • the pixel electrode 40 can be formed wider than in the first embodiment.
  • the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved. 3. Manufacturing Method With respect to the manufacturing method of the pixel 200 according to the second embodiment of the present invention, the main steps will be described with reference to FIGS. 10 and 11, focusing on differences from the first embodiment of the present invention.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited on the pixel electrode 40 by plasma CVD or sputtering to have a thickness of 100 nm to 1 ⁇ m.
  • a photoelectric conversion film 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x.
  • a predetermined resist pattern 72 is formed on the photoelectric conversion film 41a by a general photolithography technique.
  • the photoelectric conversion film 41a is etched by a general etching technique using the resist pattern 72 as a mask, and the photoelectric conversion film 41a having a predetermined pattern is formed isolated for each pixel. Unlike the one in the first embodiment, this photoelectric conversion film 41 a is formed so that both ends of the photoelectric conversion film 41 a coincide with both ends of the pixel electrode 40.
  • FIG. 11A the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 10A to 10B is repeated, and in each pixel 200, on each corresponding pixel electrode 40, i-type photoelectric conversion films 41a and 41b are formed.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the photoelectric conversion films 41 a and 41 b can be made smaller than the pixel electrode 40. If the pixel electrode 40 is formed larger than the photoelectric conversion films 41a and 41b, the sensitivity can be improved.
  • the insulating film 46 is formed later, even if the pixel electrode 40 is larger than the photoelectric conversion films 41a and 41b, it does not contact the blocking layer 42 and the transparent electrode 44. The effect can also be exhibited against misalignment between the mask pattern when the pixel electrode 40 is formed and the mask pattern when the photoelectric conversion film 41a and the photoelectric conversion film 41b are formed.
  • an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41.
  • the insulating film 46 covers the lower half of the photoelectric conversion film 41.
  • the pixel boundary part 43 is formed by forming each pixel separately.
  • the pixel boundary 43 is 0.1 ⁇ m to 0.14 ⁇ m. .
  • FIG. 12 is a cross-sectional view of the pixel 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention. For the sake of convenience, the description will be made using three pixels 300 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • each pixel 300 a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an n-type blocking layer 47 are formed. .
  • Each of the photoelectric conversion films 41a and 41b has different spectral sensitivity characteristics, and a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels.
  • the photoelectric conversion film 41 is formed on each pixel electrode 40 formed for each pixel, and the adjacent photoelectric conversion films 41a and 41b are isolated. The entire side surface of the photoelectric conversion film 41 is covered with a p-type blocking layer 42.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.
  • the n-type blocking layer 47 is formed so as to go around the side surface of the pixel electrode 40 and cover the entire side surface of the pixel electrode 40. That is, the entire upper surface and side surfaces of the pixel electrode 40 are covered with the n-type blocking layer 47.
  • a mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40, and also on the side surface of the pixel electrode 40.
  • a pixel electrode 40 is formed on the interlayer insulating film 22 for each pixel.
  • FIG. 13B several ⁇ -Si films having a predetermined energy gap are formed on each pixel electrode 40 and the interlayer insulating film 22 so as to become a blocking layer of the i-type photoelectric conversion film by plasma CVD or sputtering.
  • An n-type blocking layer 47 is formed by depositing 10 nm to several 100 nm.
  • the predetermined energy gap is obtained by changing the ratio of ⁇ -Si 1-x C x : x to control the spectral sensitivity.
  • a predetermined resist pattern 73 is formed on the blocking layer 47 by a general photolithography technique.
  • the blocking layer 47 is etched by a general etching technique to form the blocking layer 47 having a predetermined pattern on the pixel electrode 40. At this time, the blocking layer 47 is formed to cover the upper surface and side surfaces of the pixel electrode 40. Thereafter, when the photoelectric conversion film 41 is formed on the pixel electrode 40, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 so as to cover the upper surface of the pixel electrode 40, and further, the pixel The structure is such that it is formed so as to go around the side surface of the electrode 40 and cover the entire side surface of the pixel electrode 40.
  • FIG. 15 is a cross-sectional view of the pixel 400 of the solid-state imaging device 1 according to Embodiment 4 of the present invention. For the sake of convenience, the description will be made using three pixels 400 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • Each pixel 400 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, an insulating film 46, and an n-type blocking layer 47. Is formed.
  • the photoelectric conversion films 41a and 41b are formed in isolation, and at least two of them have different spectral sensitivity characteristics.
  • a p-type blocking layer 42 is formed across a plurality of pixels. Adjacent photoelectric conversion films 41 are isolated.
  • the p-type blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to the space between adjacent photoelectric conversion films 41.
  • the upper half of the side surface of the photoelectric conversion film 41 is covered with a corresponding portion 42b between the adjacent photoelectric conversion films 41 of the p-type blocking layer 42.
  • An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • the height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the insulating film 46 is embedded between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. The pixel electrode 40 can be formed so that both ends thereof are in contact with the pixel boundary portion 43.
  • the pixel electrode 40 can be formed larger than in the first embodiment.
  • the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality of the captured image is improved. 3. Manufacturing Method Next, a manufacturing method of the pixel 400 according to the fourth embodiment of the present invention configured as described above will be described with reference to FIGS. 16 and 17, focusing on differences from the first to third embodiments of the present invention. I will explain.
  • an n-type blocking layer 47 is formed on the pixel electrode 40 and the interlayer insulating film 22, and then a general photolithography technique is formed on the blocking layer 47.
  • a predetermined resist pattern 74 is formed.
  • the blocking layer 47 is etched by a general etching technique using the resist pattern 74 as a mask to form the blocking layer 47 having a predetermined pattern on each pixel electrode 40.
  • the blocking layer 47 has a shape that covers only the upper surface of the pixel electrode 40.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited on the blocking layer 47 by plasma CVD or sputtering to a thickness of 100 nm to 1 ⁇ m to form an i-type photoelectric conversion film.
  • 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x. Thereafter, the manufacturing method of the i-type photoelectric conversion film 41a shown in Embodiment 1 and the like is repeated.
  • the i-type photoelectric conversion films 41a and 41b are formed on the corresponding pixel electrodes 40. Each is formed in isolation.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.
  • the pixel boundary portion 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
  • an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41.
  • the insulating film 46 covers the lower half of the photoelectric conversion film 41. Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate
  • 1. Scanning circuit As the scanning circuit, for example, an arbitrary scanning circuit such as a MOS scanning circuit or a CCD may be used. 2.
  • Metal wiring In the embodiment, the shape of the metal wiring has been a mesh shape that passes through all adjacent pixels, but other wiring shapes such as a stripe shape may be employed.
  • the material of the metal wiring 45 can be selected from W, Mo, Ti, etc.
  • the spectral sensitivity of the photoelectric conversion film 41 is varied in order to vary the spectral sensitivity of each pixel.
  • the present invention is not limited to this.
  • the spectral sensitivities for each pixel can be made different even if the spectral sensitivities of the photoelectric conversion films are all the same. In this way, even if the pixels have different colors, the photoelectric conversion film 41 can be formed in a common manner, and the process can be simplified. 4).
  • the configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.
  • the present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which the degradation of the image quality of a captured image is suppressed.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

L'invention concerne un dispositif d'imagerie à semiconducteur possédant des pixels multiples avec un substrat à semiconducteur, un film isolant intercouche formé sur le substrat à semiconducteur, des électrodes inférieures formées sur le film isolant intercouche comme isolation pour chaque pixel, des électrodes supérieures transmettant la lumière formées à travers de multiples pixels, des films de conversion photoélectrique conçus à partir d'un matériau à semiconducteur pur, placé entre une électrode supérieure et une électrode inférieure et formé comme isolation pour chaque pixel, et une couche bloquante conçue à partir d'un matériau à semiconducteur impur et formé sur le film de conversion photoélectrique à travers les multiples pixels de sorte que le site correspondant entre les films de conversion photoélectrique voisins passe entre ces films de conversion photoélectrique et recouvre une partie ou toute la surface latérale des films de conversion photoélectrique.
PCT/JP2011/004339 2010-11-22 2011-07-29 Dispositif d'imagerie à semiconducteur et son procédé de fabrication WO2012070171A1 (fr)

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JP2010260302A JP2012114160A (ja) 2010-11-22 2010-11-22 固体撮像装置及びその製造方法

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US10453898B2 (en) 2014-12-26 2019-10-22 Sony Semiconductor Solutions Corporation Solid state image sensor pixel electrode below a photoelectronic conversion film

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JP6186205B2 (ja) * 2013-08-15 2017-08-23 ソニーセミコンダクタソリューションズ株式会社 撮像素子および撮像装置
WO2016104177A1 (fr) * 2014-12-26 2016-06-30 ソニー株式会社 Élément de capture d'image à semi-conducteur, son procédé de fabrication, et composant électronique
FR3046297B1 (fr) * 2015-12-23 2018-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif optoelectronique matriciel presentant une electrode superieure transparente
WO2018139110A1 (fr) * 2017-01-24 2018-08-02 ソニーセミコンダクタソリューションズ株式会社 Élément de réception de lumière, procédé de fabrication d'élément de réception de lumière, élément de capture d'image et dispositif électronique
JP6929267B2 (ja) * 2018-12-26 2021-09-01 キヤノン株式会社 撮像装置及び撮像システム
JPWO2020217783A1 (fr) * 2019-04-25 2020-10-29
JP7013425B2 (ja) * 2019-10-02 2022-01-31 キヤノン株式会社 光電変換装置、及び撮像システム
WO2022210149A1 (fr) * 2021-03-30 2022-10-06 パナソニックＩｐマネジメント株式会社 Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs

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