WO2022210149A1 - Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs - Google Patents

Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2022210149A1
WO2022210149A1 PCT/JP2022/013401 JP2022013401W WO2022210149A1 WO 2022210149 A1 WO2022210149 A1 WO 2022210149A1 JP 2022013401 W JP2022013401 W JP 2022013401W WO 2022210149 A1 WO2022210149 A1 WO 2022210149A1
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Prior art keywords
solid
state imaging
imaging device
main surface
semiconductor layer
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PCT/JP2022/013401
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English (en)
Japanese (ja)
Inventor
達也 可部
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パナソニックＩｐマネジメント株式会社
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Publication of WO2022210149A1 publication Critical patent/WO2022210149A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the present disclosure relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device.
  • An avalanche photodiode (hereinafter also referred to as APD) is used as one means for increasing sensitivity.
  • An APD is a photodiode that increases light detection sensitivity by multiplying signal charges generated by photoelectric conversion using avalanche breakdown. By using APD, detection sensitivity can be enhanced even with a small number of photons.
  • Patent Document 1 discloses a sensor chip used for the TOF (Time-of-Flight) method.
  • TOF Time-of-Flight
  • Patent Document 1 by providing an inter-pixel separation section between adjacent SPADs (Single Photon Avalanche Diodes), crosstalk between pixels is prevented and the sensitivity of the sensor chip is improved. .
  • the P-type diffusion layer of the SPAD element is formed on the light incident surface side, and the N-type diffusion layer of the SPAD element is formed on the opposite side of the light incident surface.
  • Metal wiring and contacts for applying a reverse bias voltage to the SPAD element are formed on the opposite side of the light incident surface. That is, the N-type diffusion layer and contacts for applying a reverse bias voltage to the SPAD element are formed on the same side of the semiconductor substrate. Therefore, it is necessary to strongly separate the electric fields of adjacent SPAD elements (N-type semiconductors), and it is necessary to space the SPAD elements apart.
  • An object of the present disclosure is to provide a solid-state imaging device that can be miniaturized.
  • a solid-state imaging device is a solid-state imaging device including at least a first avalanche diode and a second avalanche diode on a semiconductor substrate, A first semiconductor layer of a first conductivity type formed on the first main surface side of the semiconductor substrate and a diode on the side opposite to the first main surface and serving as a light-receiving surface of the semiconductor substrate, respectively.
  • a second semiconductor layer of a second conductivity type that is a conductivity type different from the first conductivity type formed on the second principal surface side; and between the first and second avalanche diodes, the first principal
  • a third semiconductor layer of a second conductivity type is formed on the surface side, and the first semiconductor layer and the third semiconductor layer of the first and second avalanche diodes share a continuous depletion layer edge.
  • the second main surface such that a separation trench that insulates and separates the first and second avalanche diodes has an opening in the second main surface. At least a portion of an insulating film is embedded in the separation trench, covering the opening, and forming the second dielectric film of the first and second avalanche diodes.
  • a first metal layer is formed in contact with the semiconductor layer.
  • the solid-state imaging device can be miniaturized.
  • FIG. 2 is a plan view showing an example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 2 is a cross-sectional view showing an example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • FIG. 4 is a cross-sectional view for explaining the manufacturing process of the solid-state imaging device according to the embodiment;
  • each figure is a schematic diagram and is not necessarily strictly illustrated. Moreover, in each figure, the same code
  • FIG. 1 is a plan view showing an example of the layout structure of a solid-state imaging device according to an embodiment.
  • FIG. 2 is a cross-sectional view showing an example of the layout structure of the solid-state imaging device according to the embodiment.
  • FIG. 1(a) is a plan view showing the layout structure of the separation groove L
  • FIG. 1(b) is a plan view showing the layout structure of the wirings 41 and 43 and the metal films 42 and 44. 2 shows a cross section near the boundary between the light receiving area A1 and the peripheral circuit area A2.
  • 1(a) shows only the arrangement of the separation grooves L
  • FIG. 1(b) shows only the wirings 41 and 43, the metal films 42 and 44, and the pads 12 of the solid-state imaging device 1. .
  • the fixed charge film 31 and the insulating film 32 are arranged in different layers from the wirings 41 and 43, the metal films 42 and 44 and the pads 12.
  • FIG. The fixed charge film 31 and the insulating film 32 correspond to the insulating film
  • the wiring 41 and the metal film 42 correspond to the first metal layer
  • the wiring 43 and the metal film 44 correspond to the second metal layer.
  • the wiring 41 corresponds to a metal wiring
  • the metal film 42 corresponds to a metal film.
  • the solid-state imaging device 1 has a plurality of pixels 10 arranged in an array. Although details will be described later, each pixel 10 includes one APD (avalanche photodiode).
  • APD active photodiode
  • the solid-state imaging device 1 is provided with a light receiving area A1 arranged in the center of the drawing and a peripheral circuit area A2 (non-light receiving area) arranged so as to surround the outer periphery of the light receiving area A1.
  • a plurality of pixels 10 are arranged in an array in the light receiving area A1 to detect incident light. Circuits for operating the pixels 10 arranged in the light receiving area A1 are arranged in the peripheral circuit area A2. Pixels 10 are not arranged in the peripheral circuit region A2, and incident light is not detected.
  • the separation grooves L are formed in a lattice shape, a linear shape, or a honeycomb shape in the light receiving area A1, and are arranged at the boundaries between the pixels 10. As shown in FIG. 1(a), the separation grooves L are formed in a lattice shape, a linear shape, or a honeycomb shape in the light receiving area A1, and are arranged at the boundaries between the pixels 10. As shown in FIG. 1(a), the separation grooves L are formed in a lattice shape, a linear shape, or a honeycomb shape in the light receiving area A1, and are arranged at the boundaries between the pixels 10. As shown in FIG.
  • the wiring 41 and the metal film 42 are formed in a grid pattern in the light receiving area A1, and are arranged at the boundary between the pixels 10 similarly to the fixed charge film 31 and the insulating film 32. be done. Further, the wiring 43 and the metal film 44 are provided in the peripheral circuit region A2 in the vicinity of the wiring 41 and the metal film 44 so as to surround the boundary between the light receiving region A1 and the peripheral circuit region A2.
  • a plurality of pads 12 are arranged along the periphery of the solid-state imaging device 1 in the peripheral circuit area A2. The plurality of pads 12 are connected to an external circuit (not shown) and supply power, operation signals, and the like to each pixel 10 .
  • the solid-state imaging device 1 includes a lens layer 101, a first semiconductor substrate 102, a wiring layer 103, and a second semiconductor substrate 104.
  • the lens layer 101 is arranged on the second main surface S2 side of the first semiconductor substrate 102 .
  • the wiring layer 103 is arranged on the first main surface S ⁇ b>1 side of the first semiconductor substrate 102 and arranged between the first semiconductor substrate 102 and the second semiconductor substrate 104 .
  • the wiring layer 103 includes a wiring layer 103a and a wiring layer 103b.
  • the wiring layer 103a is a wiring layer formed on the side of the first semiconductor substrate 102 in the manufacturing process
  • the wiring layer 103b is a wiring layer formed on the side of the second semiconductor substrate 104 in the manufacturing process. described later).
  • the second main surface S2 of the first semiconductor substrate 102 is the light receiving surface and receives incident light
  • the first main surface S1 is the surface opposite to the second main surface S2.
  • the first semiconductor substrate 102 includes a first semiconductor layer 21 , a second semiconductor layer 22 and a third semiconductor layer 23 .
  • the first semiconductor layer 21 is a first conductivity type semiconductor layer.
  • the second semiconductor layer 22 is a semiconductor layer of a second conductivity type having a different polarity (opposite conductivity type) from the first conductivity type, which is formed so as to cover the top and side portions of the first semiconductor layer 21 in the drawing. .
  • the second semiconductor layer 22 is formed such that the impurity concentration of the second conductivity type decreases from the second main surface S2 side to the first main surface S1 side, and the vicinity of the second main surface S2 (connection portion C1 vicinity) has an impurity (second semiconductor) concentration of 1E18/cm 3 or more.
  • a multiplication region 24 is formed by the first semiconductor layer 21 and the second semiconductor layer 22, and the pixel 10 functions as an APD.
  • the semiconductor layer 22 does not need to be formed of one layer, and a high concentration region may be formed only in a portion in contact with the semiconductor layer 21 (not shown).
  • one APD is configured by the first semiconductor layer 21 and the second semiconductor 22, and the adjacent second semiconductor layers 22 are in contact with each other.
  • the third semiconductor layer 23 is a semiconductor layer of the second conductivity type provided on the first main surface S1 side between adjacent APDs (specifically, the first semiconductor layer 21 and the second semiconductor layer 22). .
  • the third semiconductor layer 23 is also provided on the first main surface S1 side of the boundary between the light receiving region A1 and the peripheral circuit region A2.
  • the third semiconductor layer 23 has a higher impurity (second semiconductor) concentration than the second semiconductor layer 22 .
  • the third semiconductor layer 23 forms a depletion layer together with adjacent first semiconductor layers 21 and forms a potential barrier between adjacent APDs. That is, the third semiconductor layer 23 and the adjacent first semiconductor layer 21 share a continuous depletion layer edge. Adjacent APDs are thereby electrically separated from each other. Note that there may be a plurality of adjacent APDs disclosed in the present invention within a pixel.
  • a separation groove L is formed so as to extend in the vertical direction of the drawing from the second main surface S2 to the vicinity of the upper portion of the drawing of the third semiconductor layer 23 (near the first main surface S1). is formed.
  • the separation groove L is formed by etching from the second main surface S2 side of the first semiconductor substrate 102 in the manufacturing process described later. Therefore, the separation groove L has an opening in the second main surface S2.
  • a fixed charge film 31 and an insulating film 32 are embedded in the separation groove L.
  • the fixed charge film 31 is formed on the inner peripheral surface and the bottom surface of the separation groove L and is formed so as to cover the protective film 33 .
  • the protective film 33 is a member that covers the second main surface S2 side of the second semiconductor layer 22 .
  • a high refractive index material having a negative charge is preferably used.
  • a film or a high dielectric film can be used.
  • an oxide or nitride containing at least one element selected from Hf, Al, Zr, Ta, and Ti can be used.
  • the insulating film 32 is embedded in the separation groove L in which the fixed charge film 31 is formed, and is formed so as to cover the fixed charge film 31 and the protective film 33 .
  • the insulating film 32 is preferably made of a material having a refractive index different from that of the fixed charge film 31.
  • silicon oxide, silicon nitride, silicon oxynitride, and resin can be used.
  • the insulating film 32 can be made of a material that has no positive fixed charges or a small amount of positive fixed charges.
  • the adjacent APDs (second semiconductor layers 22) are electrically isolated from each other. . It is not necessary that the fixed charge film 31 and the insulating film 32 cover the entire inner peripheral surface and the bottom surface of the separation groove L, but only a part of them need be covered. That is, it is sufficient that at least a portion of the fixed charge film 31 and the insulating film 32 is embedded in the separation groove L.
  • a wiring 41 and a metal film 42 are formed above the separation groove L in the drawing (on the side of the second main surface S2).
  • the metal film 42 is formed to cover the opening of the separation groove L, and the wiring 41 is formed to cover the metal film 42 .
  • the metal film 42 is in contact with the upper bases (left and right upper ends in the drawing) of the adjacent second semiconductor layers 22 via the connection portion C1.
  • the wiring 41 is connected to the pad 12 and receives a reverse bias voltage applied to the second semiconductor layer 22 via the pad 12. As shown in FIG. The wiring 41 applies a reverse bias voltage to the second semiconductor layer 22 via the metal film 42 . This eliminates the need to form wiring or the like for applying a reverse bias voltage to the APD on the first main surface S1 side (wiring layer 103 side) of the first semiconductor substrate 102, so that the distance between the pixels 10 can be reduced. can do. Thereby, miniaturization of the solid-state imaging device 1 can be achieved.
  • the wiring 41 is made of metal such as Al
  • the metal film 42 is made of metal such as Ti.
  • the materials of the wiring 41 and the metal film 42 may be Al, W, Ti, TiOx, TiNx, Ta, TaOx, and TaNx, respectively.
  • the wiring 43 and the metal film 44 are formed on the second main surface S2 side of the peripheral circuit region A2.
  • the wiring 43 and the metal film 44 function as a pad 12 to which a signal line 71 for inputting power, operating signals, etc. from an external circuit (not shown) is connected.
  • An external circuit inputs signals, power supply, etc. to the circuits formed in the peripheral circuit area A2 of the first semiconductor substrate 102 and the second semiconductor substrate 104 via the signal line 71, the wiring 43, the metal film 44 and the contact 45. conduct. Some of the signals, voltages, etc. reach the pixels through the circuit.
  • the wiring 43 and the metal film 44 cover the second main surface S2 side of the second semiconductor layer 22 from the right end of the solid-state imaging device 1 to the vicinity of the boundary of the light receiving area A1.
  • the wiring 43 and the metal film 44 With a reflective member or a light shielding member, it is possible to suppress the incident light to the peripheral circuit region A2 from entering the light receiving region A1, thereby increasing the sensitivity of the solid-state imaging device 1. can be made
  • the manufacturing process of the solid-state imaging device 1 can be simplified (details will be described later).
  • a lens 61 is formed on the lens layer 101 to receive incident light.
  • the lens 61 is desirably made of a material with high light transmittance.
  • circuits such as switches, resistors, and transistors for operating the pixels 10 are configured on the second semiconductor substrate 104 .
  • This circuit receives a drive signal from the wiring formed in the wiring layer 103 or from the outside, and performs exposure and resetting of the APD.
  • This circuit also receives an output signal (signal charge) from the APD, executes a predetermined process, and outputs the result of the APD to the outside.
  • the APDs and circuits formed on the first semiconductor substrate 102 and the circuits formed on the second semiconductor substrate 104 may be connected by an alloy such as solder formed on the wiring layer 103 .
  • FIG. 3 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment.
  • the metal film 46 is further buried in the separation groove L as compared with FIG.
  • This metal film 46 is formed of a material such as W, Ti, Al, or the like.
  • the metal film 46 in the separation groove L by forming the metal film 46 in the separation groove L, the incident light obliquely incident on the pixel 10 is reflected by the metal film 46 . As a result, it is possible to suppress photoelectric conversion in pixels other than the pixels on which the incident light is incident, and it is possible to reduce color mixture between adjacent APDs.
  • the rate of photoelectric conversion is proportional to the optical path length. Since incident light is reflected by the metal film 46 to extend the optical path length, electrons or holes generated by photoelectric conversion can be guided to the multiplication region 24, and the sensitivity of the pixel 10 can be increased.
  • FIG. 4 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment.
  • a wiring 41a is formed only in the upper part of the separation groove L in place of the wiring 41, as compared with FIG.
  • the width of the wiring 41a in the horizontal direction of the drawing is narrower than that of the wiring 41, for example, about the same as the width of the opening of the separation groove L.
  • the wiring 41a is formed only in the upper part of the opening of the separation groove L.
  • the metal film 42 is very thin, the light incident on the metal film 42 can pass through the metal film 42 and enter the APD. As a result, the APD can detect the incident light on the metal film 42, so that the sensitivity of the solid-state imaging device can be improved.
  • FIG. 5 is a cross-sectional view showing another example of the layout structure of the solid-state imaging device according to the embodiment. 5, in place of the metal film 42, a metal film 42a is formed to cover the second main surface S2 of the first semiconductor substrate 102, as compared with FIG.
  • the metal film 42a is in contact with the second semiconductor layer 22 at the connection portion C1 located at the left and right upper end portions of the second semiconductor layer 22 in the drawing and the connection portion C2 located at the upper central portion of the second semiconductor layer 22 in the drawing.
  • the metal film 42a is made of the same material as the metal film 42, for example.
  • the metal film 42a is very thin like the metal films 42 and 44, the incident light that has entered the metal film 42a can pass through the metal film 42a and enter the APD. As a result, a reverse bias voltage can be applied from the connection portions C1 and C2 to the second semiconductor layer 22 via the wiring 41a and the metal film 42a, so that the uniformity of the electric field of the second semiconductor layer 22 can be maintained. can.
  • FIG. 6 is a plan view showing another example of the layout structure of the solid-state imaging device according to the embodiment.
  • the metal film 42 and the second semiconductor layer 22 are in contact with each other at the connecting portion C3.
  • the metal film 42 and the second semiconductor layer 22 are in contact with each other in a wider range than in FIG. Specifically, in FIG. 1, the metal film 42 is in contact only with the upper bottom of the second semiconductor layer 22, but in FIG. . Thereby, since the metal film 42 and the second semiconductor layer 22 are in contact with each other over a wide range, the uniformity of the electric field of the second semiconductor layer 22 can be maintained.
  • FIG. 7 to 12 each show a cross section of the solid-state imaging device 1.
  • the solid-state imaging device 1 includes a first semiconductor substrate 102 composed of a second semiconductor layer 22 and a third semiconductor substrate 102 formed on the second main surface S2 side of the first semiconductor substrate 102 . and a semiconductor substrate 105 .
  • the concentration of the second semiconductor increases from the first main surface S1 side to the second main surface S2 side.
  • the third semiconductor substrate 105 is composed of a semiconductor layer having a second semiconductor concentration higher than that of the first semiconductor substrate 102 .
  • a mask pattern (hereinafter referred to as a PR mask) is formed by exposing and developing a photoresist on the first main surface S1 side of the first semiconductor substrate 102, and a predetermined region is formed. , a first semiconductor is implanted to form a first semiconductor layer 21 .
  • the first main surface S1 side of the first semiconductor substrate 102 is again covered with a PR mask, a second semiconductor is implanted into a predetermined region, and a third semiconductor layer 23 is formed. to form At this time, the concentration of the second semiconductor implanted into the first semiconductor substrate 102 is higher than the concentration of the second semiconductor in the first semiconductor substrate 102 . Also, the third semiconductor layer 23 is formed between adjacent first semiconductor layers 21 .
  • a wiring layer 103a is formed on the first main surface S1 side of the first semiconductor substrate 102. Then, as shown in FIG. At this time, wiring and the like connecting between the APD formed on the first semiconductor substrate 102 and various circuits on the second semiconductor substrate 104 are formed on the wiring layer 103a.
  • a substrate on which the third semiconductor substrate 105, the first semiconductor substrate 102 and the wiring layer 103a are formed, and a substrate on which the wiring layer 103b and the second semiconductor substrate 104 are formed are separated. are attached by a method such as hybrid bonding, surface activation, or bonding using resin and solder to form a single substrate.
  • the substrates on which the third semiconductor substrate 105, the first semiconductor substrate 102 and the wiring layer 103a are formed are reversed upside down in the drawing and attached.
  • the third semiconductor substrate 105 is removed. This thins the substrate.
  • a protective film 33 is formed on the second main surface S2 side of the first semiconductor substrate 102.
  • the protective film 33 is formed using, for example, a silicon oxide film, a silicon nitride film, or an organic material such as resin.
  • a PR mask is formed so as to cover the second main surface S2 side of the first semiconductor substrate 102, the first semiconductor substrate 102 is etched, and the first semiconductor substrate is etched.
  • a groove portion L1 is formed in 102 .
  • This groove portion L1 is provided at a location where the contact 45 is formed.
  • the mask PR is removed, and a metal film 45a and an insulating film are formed by sputtering, CVD, ALD, vapor deposition, plating, etc. so as to fill the protective film 33 and the trench L1. (not shown) is formed.
  • the contact 45 is formed by removing the portion of the metal film 45a covering the protective film 33.
  • FIG. 10A the contact 45 is formed by removing the portion of the metal film 45a covering the protective film 33.
  • a PR mask is formed so as to cover the second main surface S2 side of the first semiconductor substrate 102, the first semiconductor substrate 102 is etched, and the first semiconductor substrate is etched.
  • a separation groove L is formed in 102 .
  • the separation groove L is formed to extend in the vertical direction of the drawing from the second main surface S2 side to the vicinity of the upper portion of the third semiconductor layer 23 in the drawing (near the first main surface S1).
  • the PR mask is removed, and a fixed charge film is formed by CVD, sputtering, ALD, or the like so as to cover the sidewalls and bottom surfaces of the separation grooves L and the protective film 33 .
  • 31 is formed.
  • an insulating film 32 is formed so as to cover the separation groove L and the fixed charge film 31 . Adjacent APDs are electrically separated from each other by the fixed charge film 31 and the insulating film 32 formed in the separation groove L. As shown in FIG.
  • a PR mask is formed so as to cover the second main surface S2 side of the first semiconductor substrate 102, and the insulating film 32, the fixed charge film 31 and the protective film 33 are etched. to form grooves L2 and L3.
  • the grooves L2 and L3 are formed above the separation groove L and the groove L1 in the drawing, respectively.
  • the groove portion L2 is formed so that the connection portions C1 at the left and right upper end portions of the second semiconductor layer 22 in the drawing are exposed in the upper portion of the separation groove L in the drawing.
  • the groove portion L3 is formed so that the upper portion of the contact 45 in the drawing is exposed at the upper portion of the drawing in the groove portion L1.
  • the PR mask is removed, and sputtering, CVD, ALD, vapor deposition, plating, etc. are used to cover the sidewalls and bottom surfaces of the trenches L2 and L3 and the insulating film 32.
  • metal films 47 and 48 are formed. Although not shown in FIG. 11B, a thin metal film 48 is formed along the lower portion of the metal film 47 in the drawing.
  • the material of the metal film 47 is the same as that of the wirings 41 and 43, and the material of the metal film 48 is the same as that of the metal films 42 and 44.
  • a PR mask is formed so as to cover the second main surface S2 side of the first semiconductor substrate 102, and a predetermined region is etched.
  • the wiring 41 and the metal film 42 are formed above the separation groove L (the fixed charge film 31 and the insulating film 32), and the wiring 43 and the metal film 44 are formed above the groove L1 (contact 45). be done.
  • an insulating film 51 is formed so as to cover the insulating film 32 and the wirings 41 and 43.
  • a PR mask is formed so as to cover the insulating film 51, and a predetermined region is etched. At this time, etching is performed in the region where the pad 12 is to be formed.
  • the PR mask is removed and a lens 61 is formed by a predetermined method. After that, the solid-state imaging device 1 is formed by wiring, lens sealing, and the like.
  • the solid-state imaging device according to the above embodiment can be applied to a photodetector used for the TOF method or the like.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Dans la présente invention, une rainure de séparation (L) destinée à isoler et à séparer des diodes à avalanche adjacentes est formée entre les diodes à avalanche adjacentes, d'un second côté de surface principale (S2) à un premier côté de surface principale (S1). Dans la rainure de séparation (L), au moins des parties d'un film isolant (32) et d'un film de charge électrique solide (31) sont incorporées. Un film métallique (42) et un fil (41) sont formés de manière à être en contact avec des secondes couches semi-conductrices (22) des diodes à avalanche adjacentes et à recouvrir une ouverture de la rainure de séparation (L).
PCT/JP2022/013401 2021-03-30 2022-03-23 Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs WO2022210149A1 (fr)

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