WO2012070171A1 - Solid-state imaging device and manufacturing method thereof - Google Patents

Solid-state imaging device and manufacturing method thereof Download PDF

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Publication number
WO2012070171A1
WO2012070171A1 PCT/JP2011/004339 JP2011004339W WO2012070171A1 WO 2012070171 A1 WO2012070171 A1 WO 2012070171A1 JP 2011004339 W JP2011004339 W JP 2011004339W WO 2012070171 A1 WO2012070171 A1 WO 2012070171A1
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photoelectric conversion
pixel
imaging device
blocking layer
state imaging
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PCT/JP2011/004339
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French (fr)
Japanese (ja)
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光雄 安平
晴久 横山
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

Definitions

  • the present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate.
  • a pixel unit 900 includes a p-type semiconductor substrate 305, an emitter electrode 310, a p-type base layer 315, and an n + -type emitter layer. 320, a base electrode 325, a lower electrode 340, an i-type photoelectric conversion film 341, a transparent electrode 344, an insulating film 347, and a p-type blocking layer 342.
  • adjacent photoelectric conversion films 341 are formed in isolation.
  • a blocking layer 342 is formed on the upper surface of the photoelectric conversion film 341, and side surfaces of the photoelectric conversion film 341 and the blocking layer 342 are covered with an insulating film 347.
  • the signal charge generated in the photoelectric conversion film 341 passes through the lower electrode 340, moves to the base layer 315 through the base electrode 325, and lowers the potential of the base layer 315. At this time, a negative pulse is applied to the transparent electrode 344. Then, after a predetermined accumulation time, the emitter electrode 310 is connected to a signal readout capacitor, and a positive pulse is applied to the transparent electrode 344, whereby the signal charge of the base layer 315 is read out through the emitter layer 320 (not shown). Is read out. Thereafter, the signal charge is output to the outside through an amplifier (not shown). Note that a MOS transistor is used when signal charges are output to the outside.
  • the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the p-type blocking layer to the i-type photoelectric conversion film is an i-type photoelectric conversion film.
  • the interface state is also called a surface state, and is an energy level that captures and emits electrons and holes generated at the interface of different substances. Since the interface state is energetically located between the valence band and the conduction band, the energy between the interface state and the valence band or the conduction band is the energy between the valence band and the conduction band. Smaller and easier to move the charge by heat.
  • the charge read out as signal charge is the charge present in the depletion layer.
  • the depletion layer extends to the region where the interface states exist on the side surfaces of the photoelectric conversion film and the blocking layer, a large number of interface states are included in the depletion layer. Then, the charge in the valence band in the depletion layer is thermally excited from the valence band to the interface state, and then excited from the interface state to the conduction band, and may be read as a signal charge.
  • This readout of signal charges is a phenomenon that occurs even when no light is incident, and is called dark current.
  • the charge trapped in the interface state from the conduction band in the depletion layer may be excited to the conduction band at a timing delayed from the original readout frame and read out as a signal charge.
  • This readout of the signal charge causes a trapping afterimage.
  • the present invention has been made to solve the above problem, and is a depletion layer existing in a range from a junction between an i-type photoelectric conversion film and a blocking layer made of an impurity semiconductor material to an i-type photoelectric conversion film.
  • the present invention provides a solid-state imaging device and a method for manufacturing the same that can prevent the interface state generated on the side surface of the blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material from being spread. Objective.
  • a solid-state imaging device has a plurality of pixels, and is isolated for each pixel on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and the interlayer insulating film.
  • the solid-state imaging device manufacturing method is a method for manufacturing a solid-state imaging device having a plurality of pixels, the step of forming an interlayer insulating film on a semiconductor substrate, and the pixel on the interlayer insulating film.
  • the blocking layer covers part or all of the side surface of the photoelectric conversion film. That is, the side surface of the depletion layer present in the range of the i-type photoelectric conversion film from the junction between the blocking layer and the photoelectric conversion film is covered with the blocking layer. Therefore, the depletion layer does not contact the interface state generated on the side surface of the blocking layer and the translucent upper electrode.
  • the blocking layer covers part or all of the side surface of the photoelectric conversion film, so that the depletion layer and the interface state can be prevented from coming into contact with each other.As a result, the influence of the interface state is reduced, Generation of dark current and trapping afterimage can be suppressed.
  • the depletion layer existing in the range of the i-type photoelectric conversion film from the junction between the i-type photoelectric conversion film and the blocking layer made of the impurity semiconductor material is a blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material. It can be suppressed that the interface state generated on the side surface is expanded to a region where the interface state is generated.
  • the blocking layer covers the upper surface of the photoelectric conversion film, and signal charges generated in the photoelectric conversion film can be retained in the photoelectric conversion film. Therefore, the transfer efficiency of signal charges can be improved.
  • the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the blocking layer formed of the impurity semiconductor material to the i-type photoelectric conversion film is an i-type photoelectric conversion film. It is possible to manufacture a solid-state imaging device that can suppress spreading to a region where an interface state generated on the side surface of the blocking layer formed of the conversion film and the impurity semiconductor material is generated.
  • FIG. 1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a top view for 6 pixels in the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG.
  • FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12.
  • FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 4 of this invention.
  • FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15.
  • FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. It is sectional drawing of the conventional solid-state imaging device.
  • FIG. 1 is a plan view showing six pixels as a partial region in the solid-state imaging device 1 shown in FIG. Each pixel 100 is partitioned by a pixel boundary 43.
  • Each pixel 100 includes a reset gate 10, an amplification transistor 11, a storage diode 15 in an n-type impurity diffusion layer, and a floating diffusion in an n-type impurity diffusion layer. 16, an n-type impurity diffusion layer reset transistor drain 17, a transfer gate 18, contacts 31 to 34, and a metal wiring 45.
  • FIG. 3 is a cross-sectional view of the pixel 100 of the solid-state imaging device 1 shown in FIG. 1, and shows a cross-section A-A ′ of FIG.
  • an STI Shallow Trench Isolation
  • a channel stopper 13 is formed in the semiconductor substrate 5 on which the p-type well is formed.
  • a storage diode 15 is formed in each pixel 100.
  • a reset transistor drain 17 is formed in each pixel 100.
  • a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked.
  • a reset gate 10 and an amplification transistor gate 19 are sequentially stacked.
  • a transfer gate 18 and an amplification transistor gate 19 are sequentially stacked.
  • a connection electrode 23 is formed within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.
  • Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20.
  • wirings 24 and 25 for example, formed of Al or Cu
  • connection electrodes 26 is formed.
  • the interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.
  • the pixel electrode 40 is formed on the interlayer insulating film 22 so as to be isolated for each pixel.
  • photoelectric conversion films 41a having spectral sensitivity with respect to red light and photoelectric conversion films 41b having spectral sensitivity with respect to green light are formed alternately and isolated from each other.
  • the solid-state imaging device 1 also has a photoelectric conversion film having spectral sensitivity to blue light.
  • FIG. 3 which is a cross section taken along line AA ′ in FIG. Not.
  • the photoelectric conversion films of the respective colors are collectively referred to as the photoelectric conversion film 41 without being distinguished.
  • the photoelectric conversion film 41 is formed of an i-type semiconductor material made of an inorganic photoconductive film or the like, and the red, green, and blue spectral sensitivities are adjusted by changing the composition ratio of the same semiconductor material.
  • the spectral sensitivity of the photoelectric conversion film 41 is controlled by changing the ratio of ⁇ -Si 1-x C x : x. It has gained.
  • a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • the part 42 b corresponding to the space between the photoelectric conversion films 41 of the blocking layer 42 enters between the adjacent photoelectric conversion films 41 and covers all the side surfaces of the photoelectric conversion film 41.
  • a gap is provided between the blocking layer 42 and the side surface of the pixel electrode 40 so that the blocking layer 42 and the pixel electrode 40 do not contact each other, and the photoelectric conversion film 41 exists in this gap. .
  • a transparent electrode 44 (formed of, for example, ITO or ZnO) is formed as a translucent upper electrode across a plurality of pixels, and the transparent electrode 44 extends over the entire pixel region 61. ing. Between adjacent photoelectric conversion films 41 is a pixel boundary portion 43. In the pixel boundary portion 43, a transparent electrode 44 is formed so as to cover a portion 42 b of the blocking layer corresponding to the space between the photoelectric conversion films 41.
  • a metal wiring 45 is formed on the transparent electrode 44 in the pixel boundary portion 43.
  • the shape of the metal wiring 45 passes between all adjacent pixels in the pixel region 61, and has a mesh shape when the entire pixel region 61 is viewed in plan. Further, the metal wiring 45 is formed so as to surround the pixel region 61. That is, the metal wiring 45 extends from the central portion of the pixel region 61 toward the periphery of the pixel region 61, and connects the central portion of the pixel region 61 and the periphery of the pixel region 61.
  • the metal wiring 45 is made of a material having a lower electrical resistivity than the material of the transparent electrode 44.
  • the metal wiring 45 is provided in the pixel boundary part 43 which is not a light-receiving part, an aperture ratio does not fall by presence of the metal wiring 45. Further, the maximum allowable width of the metal wiring 45 is the same as the width of the pixel boundary 43. 3.
  • Driving of the solid-state imaging device 1 The incident light is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 44, and the generated charge is attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 44 and the pixel electrode 40, and passes through the connection electrodes 23 and 26 from the pixel electrode 40. Thus, it is temporarily stored in the storage diode 15.
  • the charge is transferred and stored from the storage diode 15 to the floating diffusion 16 by the action of the transfer gate 18.
  • the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside.
  • the reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17. 4). Effect A depletion layer exists in the range of the i-type photoelectric conversion film 41 from the junction between the photoelectric conversion film 41 and the blocking layer 42. In this configuration, the portion 42b corresponding to the space between the adjacent photoelectric conversion films 41 of the blocking layer 42 enters between the photoelectric conversion films 41, and all of the side surfaces of the i-type photoelectric conversion film 41 are p-type blocking. Covered with a layer 42. Therefore, the side surface of the depletion layer is covered with the blocking layer 42, and the depletion layer does not extend to the region where the interface state is generated. Therefore, dark current and trapping afterimages due to interface states can be suppressed.
  • the photoelectric conversion film 41 having a predetermined spectral sensitivity is used for each pixel without using a color filter, there is no light absorption by the color filter, and light loss can be avoided.
  • the metal wiring 45 is formed on the transparent electrode 44, the combined resistance of the transparent electrode 44 and the metal wiring 45 is made smaller than the resistance of the transparent electrode 44 alone. Therefore, the voltage drop at the center of the pixel region 61 that has been increased due to the resistance of the transparent electrode 44 is reduced, and the voltage drop at the center of the pixel region 61 can be suppressed. As a result, it is possible to reduce the degradation of the image quality of the captured image that occurs when the magnitude of the voltage drop differs for each location of the pixel region 61.
  • an STI (Shallow Trench Isolation) 12 that separates transistors and diffusion layer elements is formed on a p-type semiconductor substrate 5.
  • the semiconductor substrate 5 is dry-etched to form a trench having a depth of 200 nm to 400 nm serving as an isolation region.
  • sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 ⁇ 10 13 cm ⁇ 2 to B ion implantation is performed at 3 ⁇ 10 13 cm ⁇ 2 to form the channel stopper 13 of the p + layer.
  • the inside of the formed trench is filled with an insulating film, and planarized by CMP (Chemical Mechanical Polishing), thereby forming the STI 12.
  • CMP Chemical Mechanical Polishing
  • the gate oxide film 14 which becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed, for example, by 5 to 10 nm by thermal oxidation or plasma oxidation.
  • a Poly-Si film for example, 100 nm to 200 nm is deposited by thermal CVD, plasma CVD, or the like, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19, and the reset gate 10 made of the Poly-Si film are formed.
  • P and As are ion-implanted into the p-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 ⁇ 10 14 cm ⁇ 2 to 2 ⁇ 10 15 cm ⁇ 2 , so that the storage diode 15, the floating diffusion 16 and the n-type impurity layers of the reset transistor drain 17 are formed simultaneously.
  • a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film, and the electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is established. Connected.
  • An interlayer insulating film 20 made of a CVD oxide film is formed, for example, to 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique.
  • a W (tungsten) plug is embedded in the opened contact opening to form a connection electrode 23 of the W plug, and electrical connection to the storage diode 15 and the reset transistor drain 17 is formed.
  • a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed.
  • a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.
  • a metal film made of Al, W, Mo (molybdenum) or the like is deposited to 100 nm to 300 nm, and a pixel electrode having a predetermined shape is formed by a general photolithography technique and an etching technique. 40 is formed.
  • the pixel electrode 40 is formed so as to be isolated for each pixel, and the area where the pixel electrode 40 is separated determines the effective aperture ratio of the pixel. For example, if the separation width between the pixels is 1/10 to 2/10 of the pixel size of 1.0 ⁇ m to 1.4 ⁇ m, the aperture ratio is estimated to be about 64% to about 81%.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited to 100 nm to 1 ⁇ m by plasma CVD or sputtering so as to cover the pixel electrode 40 and the interlayer insulating film 22.
  • An i-type photoelectric conversion film 41a is formed.
  • this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x.
  • a predetermined resist pattern 70 is formed on the photoelectric conversion film 41a by a general photolithography technique.
  • the size of each pixel of the photoelectric conversion film 41a is, for example, 0.9 ⁇ m to 1.3 ⁇ m in a pixel size of 1.0 ⁇ m to 1.4 ⁇ m.
  • the photoelectric conversion film 41a is etched by a general etching technique to form a photoelectric conversion film 41a having a predetermined pattern.
  • FIG. 7A by repeating the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 5B to 6B, in each pixel 100, on each corresponding pixel electrode 40, An i-type photoelectric conversion film 41b is formed in isolation for each pixel.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the adjacent photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the pixel boundary part 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
  • an ⁇ -Si film having a predetermined energy gap so as to be a blocking layer of the i-type photoelectric conversion film 41 by plasma CVD or sputtering so as to cover the upper surface and side surfaces of the photoelectric conversion film 41.
  • a p-type blocking layer 42 is formed over a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • a transparent electrode 44 made of ITO or ZnO is formed by several tens to several hundreds nm by sputtering or CVD. Both the portion 42 a and the portion 42 b of the blocking layer 42 are covered with the transparent electrode 44.
  • a metal wiring 45 is deposited on the transparent electrode 44 by sputtering or CVD to a thickness of 100 to 300 nm.
  • a predetermined resist pattern 71 is formed on the metal wiring 45 by a general photolithography technique.
  • the metal wiring 45 is etched by a general etching technique to form a mesh-like metal wiring 45 on the transparent electrode 44. Thereby, the solid-state imaging device shown in FIG. 3 is obtained.
  • FIG. 9 is a cross-sectional view of the pixel 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. For the sake of convenience, the description will be made using three pixels 200 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • each pixel 200 a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an insulating film 46 are formed.
  • the photoelectric conversion films 41a and 41b are formed so as to be isolated for each pixel, and at least two of them have different spectral sensitivity characteristics.
  • a blocking layer 42 is formed across a plurality of pixels.
  • the blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
  • the upper half of the side surface of the photoelectric conversion film 41 is covered with a portion 42 b corresponding to the space between the photoelectric conversion films 41 adjacent to the blocking layer 42.
  • An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • upper half and lower half do not indicate that the upper half is strictly divided into upper and lower halves, but indicate respective portions where the photoelectric conversion film 41 is divided into upper and lower portions. That is, the height from the interlayer insulating film 22 to the lower half of the photoelectric conversion film 41 may be slightly higher or lower than one half of the height of the photoelectric conversion film 41 from the interlayer insulating film 22. If the insulating film 46 is formed to be higher than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be easily embedded.
  • the insulating film 46 is formed to be lower than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be formed deeply, and the photoelectric conversion film The photoelectric conversion efficiency by 41 can be improved.
  • the height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. This is to prevent the pixel electrode 40 and the p-type blocking layer 42 from coming into contact with each other and causing a short circuit.
  • a mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the insulating film 46 is embedded in the lower half between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • the pixel electrode 40 can be formed up to a place where both ends of the pixel contact the pixel boundary portion 43.
  • the pixel electrode 40 can be formed wider than in the first embodiment.
  • the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved. 3. Manufacturing Method With respect to the manufacturing method of the pixel 200 according to the second embodiment of the present invention, the main steps will be described with reference to FIGS. 10 and 11, focusing on differences from the first embodiment of the present invention.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited on the pixel electrode 40 by plasma CVD or sputtering to have a thickness of 100 nm to 1 ⁇ m.
  • a photoelectric conversion film 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x.
  • a predetermined resist pattern 72 is formed on the photoelectric conversion film 41a by a general photolithography technique.
  • the photoelectric conversion film 41a is etched by a general etching technique using the resist pattern 72 as a mask, and the photoelectric conversion film 41a having a predetermined pattern is formed isolated for each pixel. Unlike the one in the first embodiment, this photoelectric conversion film 41 a is formed so that both ends of the photoelectric conversion film 41 a coincide with both ends of the pixel electrode 40.
  • FIG. 11A the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 10A to 10B is repeated, and in each pixel 200, on each corresponding pixel electrode 40, i-type photoelectric conversion films 41a and 41b are formed.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the photoelectric conversion films 41 a and 41 b can be made smaller than the pixel electrode 40. If the pixel electrode 40 is formed larger than the photoelectric conversion films 41a and 41b, the sensitivity can be improved.
  • the insulating film 46 is formed later, even if the pixel electrode 40 is larger than the photoelectric conversion films 41a and 41b, it does not contact the blocking layer 42 and the transparent electrode 44. The effect can also be exhibited against misalignment between the mask pattern when the pixel electrode 40 is formed and the mask pattern when the photoelectric conversion film 41a and the photoelectric conversion film 41b are formed.
  • an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41.
  • the insulating film 46 covers the lower half of the photoelectric conversion film 41.
  • the pixel boundary part 43 is formed by forming each pixel separately.
  • the pixel boundary 43 is 0.1 ⁇ m to 0.14 ⁇ m. .
  • FIG. 12 is a cross-sectional view of the pixel 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention. For the sake of convenience, the description will be made using three pixels 300 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • each pixel 300 a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an n-type blocking layer 47 are formed. .
  • Each of the photoelectric conversion films 41a and 41b has different spectral sensitivity characteristics, and a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels.
  • the photoelectric conversion film 41 is formed on each pixel electrode 40 formed for each pixel, and the adjacent photoelectric conversion films 41a and 41b are isolated. The entire side surface of the photoelectric conversion film 41 is covered with a p-type blocking layer 42.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.
  • the n-type blocking layer 47 is formed so as to go around the side surface of the pixel electrode 40 and cover the entire side surface of the pixel electrode 40. That is, the entire upper surface and side surfaces of the pixel electrode 40 are covered with the n-type blocking layer 47.
  • a mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40, and also on the side surface of the pixel electrode 40.
  • a pixel electrode 40 is formed on the interlayer insulating film 22 for each pixel.
  • FIG. 13B several ⁇ -Si films having a predetermined energy gap are formed on each pixel electrode 40 and the interlayer insulating film 22 so as to become a blocking layer of the i-type photoelectric conversion film by plasma CVD or sputtering.
  • An n-type blocking layer 47 is formed by depositing 10 nm to several 100 nm.
  • the predetermined energy gap is obtained by changing the ratio of ⁇ -Si 1-x C x : x to control the spectral sensitivity.
  • a predetermined resist pattern 73 is formed on the blocking layer 47 by a general photolithography technique.
  • the blocking layer 47 is etched by a general etching technique to form the blocking layer 47 having a predetermined pattern on the pixel electrode 40. At this time, the blocking layer 47 is formed to cover the upper surface and side surfaces of the pixel electrode 40. Thereafter, when the photoelectric conversion film 41 is formed on the pixel electrode 40, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 so as to cover the upper surface of the pixel electrode 40, and further, the pixel The structure is such that it is formed so as to go around the side surface of the electrode 40 and cover the entire side surface of the pixel electrode 40.
  • FIG. 15 is a cross-sectional view of the pixel 400 of the solid-state imaging device 1 according to Embodiment 4 of the present invention. For the sake of convenience, the description will be made using three pixels 400 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
  • Each pixel 400 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, an insulating film 46, and an n-type blocking layer 47. Is formed.
  • the photoelectric conversion films 41a and 41b are formed in isolation, and at least two of them have different spectral sensitivity characteristics.
  • a p-type blocking layer 42 is formed across a plurality of pixels. Adjacent photoelectric conversion films 41 are isolated.
  • the p-type blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to the space between adjacent photoelectric conversion films 41.
  • the upper half of the side surface of the photoelectric conversion film 41 is covered with a corresponding portion 42b between the adjacent photoelectric conversion films 41 of the p-type blocking layer 42.
  • An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
  • the height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41. 2. Effect In this configuration, the insulating film 46 is embedded between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. The pixel electrode 40 can be formed so that both ends thereof are in contact with the pixel boundary portion 43.
  • the pixel electrode 40 can be formed larger than in the first embodiment.
  • the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality of the captured image is improved. 3. Manufacturing Method Next, a manufacturing method of the pixel 400 according to the fourth embodiment of the present invention configured as described above will be described with reference to FIGS. 16 and 17, focusing on differences from the first to third embodiments of the present invention. I will explain.
  • an n-type blocking layer 47 is formed on the pixel electrode 40 and the interlayer insulating film 22, and then a general photolithography technique is formed on the blocking layer 47.
  • a predetermined resist pattern 74 is formed.
  • the blocking layer 47 is etched by a general etching technique using the resist pattern 74 as a mask to form the blocking layer 47 having a predetermined pattern on each pixel electrode 40.
  • the blocking layer 47 has a shape that covers only the upper surface of the pixel electrode 40.
  • an ⁇ -Si film having a red spectral sensitivity characteristic is deposited on the blocking layer 47 by plasma CVD or sputtering to a thickness of 100 nm to 1 ⁇ m to form an i-type photoelectric conversion film.
  • 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of ⁇ -Si 1-x C x : x. Thereafter, the manufacturing method of the i-type photoelectric conversion film 41a shown in Embodiment 1 and the like is repeated.
  • the i-type photoelectric conversion films 41a and 41b are formed on the corresponding pixel electrodes 40. Each is formed in isolation.
  • the spectral sensitivity is controlled by changing the ratio of ⁇ -Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities.
  • the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.
  • the pixel boundary portion 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
  • an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41.
  • the insulating film 46 covers the lower half of the photoelectric conversion film 41. Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate
  • 1. Scanning circuit As the scanning circuit, for example, an arbitrary scanning circuit such as a MOS scanning circuit or a CCD may be used. 2.
  • Metal wiring In the embodiment, the shape of the metal wiring has been a mesh shape that passes through all adjacent pixels, but other wiring shapes such as a stripe shape may be employed.
  • the material of the metal wiring 45 can be selected from W, Mo, Ti, etc.
  • the spectral sensitivity of the photoelectric conversion film 41 is varied in order to vary the spectral sensitivity of each pixel.
  • the present invention is not limited to this.
  • the spectral sensitivities for each pixel can be made different even if the spectral sensitivities of the photoelectric conversion films are all the same. In this way, even if the pixels have different colors, the photoelectric conversion film 41 can be formed in a common manner, and the process can be simplified. 4).
  • the configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.
  • the present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which the degradation of the image quality of a captured image is suppressed.

Abstract

The disclosed solid-state imaging device having multiple pixels is provided with a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, lower electrodes formed on the interlayer insulating film in isolation for each pixel, light-transmissive upper electrodes formed across multiple pixels, photoelectric conversion films configured from a pure semiconductor material, disposed between an upper electrode and a lower electrode and formed in isolation for each pixel, and a blocking layer configured from an impure semiconductor material and formed on the photoelectric conversion film across multiple pixels such that the site corresponding to between neighboring photoelectric conversion films enters between said photoelectric conversion films and covers part of or all of the lateral surface of the photoelectric conversion films.

Description

固体撮像装置及びその製造方法Solid-state imaging device and manufacturing method thereof
　本発明は、光電変換膜が半導体基板上に積層された積層型の固体撮像装置に関する。 The present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate.
　従来の積層型固体撮像装置として、例えば、図１８に示すように、画素部９００が、ｐ型の半導体基板３０５と、エミッタ電極３１０と、ｐ型のベース層３１５と、ｎ＋型のエミッタ層３２０と、ベース電極３２５と、下側電極３４０と、ｉ型の光電変換膜３４１と、透明電極３４４と、絶縁膜３４７と、ｐ型のブロッキング層３４２とを備えたものがある。そして、この固体撮像装置において、隣接する光電変換膜３４１は、孤立して形成されている。また、光電変換膜３４１の上面には、ブロッキング層３４２が形成されており、光電変換膜３４１及びブロッキング層３４２の側面は絶縁膜３４７で覆われている。 As a conventional stacked solid-state imaging device, for example, as shown in FIG. 18, a pixel unit 900 includes a p-type semiconductor substrate 305, an emitter electrode 310, a p-type base layer 315, and an n + -type emitter layer. 320, a base electrode 325, a lower electrode 340, an i-type photoelectric conversion film 341, a transparent electrode 344, an insulating film 347, and a p-type blocking layer 342. In this solid-state imaging device, adjacent photoelectric conversion films 341 are formed in isolation. In addition, a blocking layer 342 is formed on the upper surface of the photoelectric conversion film 341, and side surfaces of the photoelectric conversion film 341 and the blocking layer 342 are covered with an insulating film 347.
　光電変換膜３４１で生成された信号電荷は、下側電極３４０を通り、ベース電極３２５を介してベース層３１５に移動し、ベース層３１５の電位を低下させる。この際、透明電極３４４には負パルスが印加されている。そして、所定の蓄積時間後に、エミッタ電極３１０を信号読み出し用の容量に接続し、透明電極３４４に正パルスを印加することにより、ベース層３１５の信号電荷がエミッタ層３２０を通して読み出し容量（不図示）に読み出しされる。その後、信号電荷は増幅器（不図示）を介して外部へ出力される。なお、外部への信号電荷の出力の際に、ＭＯＳトランジスタが用いられる。 The signal charge generated in the photoelectric conversion film 341 passes through the lower electrode 340, moves to the base layer 315 through the base electrode 325, and lowers the potential of the base layer 315. At this time, a negative pulse is applied to the transparent electrode 344. Then, after a predetermined accumulation time, the emitter electrode 310 is connected to a signal readout capacitor, and a positive pulse is applied to the transparent electrode 344, whereby the signal charge of the base layer 315 is read out through the emitter layer 320 (not shown). Is read out. Thereafter, the signal charge is output to the outside through an amplifier (not shown). Note that a MOS transistor is used when signal charges are output to the outside.
特開平２－２７５６７０号公報JP-A-2-275670
　しかしながら、上記従来の積層型固体撮像装置では、ｉ型の光電変換膜とｐ型のブロッキング層との接合部からｉ型の光電変換膜の範囲に存在する空乏層が、ｉ型の光電変換膜及びｐ型のブロッキング層の側面に生ずる界面準位が発生している領域まで、広がってしまうという課題がある。これは、空乏層が、絶縁膜と半導体との界面に接していることにより生じる。界面準位は表面準位とも呼ばれ、異なる物質の界面に発生する、電子や正孔を捕獲したり放出したりするエネルギー準位である。界面準位は、エネルギー的に価電子帯と伝導帯との間に位置するため、界面準位と価電子帯または伝導帯との間のエネルギーは、価電子帯と伝導帯との間のエネルギーより小さく、電荷が熱によって移動しやすくなる。 However, in the conventional stacked solid-state imaging device, the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the p-type blocking layer to the i-type photoelectric conversion film is an i-type photoelectric conversion film. And there exists a subject that it will spread to the area | region where the interface state which arises in the side surface of a p-type blocking layer has generate | occur | produced. This occurs because the depletion layer is in contact with the interface between the insulating film and the semiconductor. The interface state is also called a surface state, and is an energy level that captures and emits electrons and holes generated at the interface of different substances. Since the interface state is energetically located between the valence band and the conduction band, the energy between the interface state and the valence band or the conduction band is the energy between the valence band and the conduction band. Smaller and easier to move the charge by heat.
　信号電荷として読み出される電荷は、空乏層に存在する電荷である。また、空乏層が、光電変換膜及びブロッキング層の側面に存在する界面準位の発生している領域に広がると、空乏層内に多数の界面準位が含まれることとなる。すると、空乏層内の価電子帯にあった電荷が、価電子帯から界面準位へ熱励起され、その後、界面準位から伝導帯に励起され、信号電荷として読み出されることがある。この信号電荷の読み出しは、光が入射していなくても起きる現象であり、暗電流と呼ばれる。また、空乏層内の伝導帯から界面準位にトラップされた電荷が、本来の読み出しフレームから遅れたタイミングで伝導帯に励起され、信号電荷として読み出されることがある。この信号電荷の読み出しは、トラップ性残像の原因となる。これら暗電流及び残像により、出力画像の画質が劣化してしまう。 The charge read out as signal charge is the charge present in the depletion layer. In addition, when the depletion layer extends to the region where the interface states exist on the side surfaces of the photoelectric conversion film and the blocking layer, a large number of interface states are included in the depletion layer. Then, the charge in the valence band in the depletion layer is thermally excited from the valence band to the interface state, and then excited from the interface state to the conduction band, and may be read as a signal charge. This readout of signal charges is a phenomenon that occurs even when no light is incident, and is called dark current. In addition, the charge trapped in the interface state from the conduction band in the depletion layer may be excited to the conduction band at a timing delayed from the original readout frame and read out as a signal charge. This readout of the signal charge causes a trapping afterimage. These dark currents and afterimages degrade the image quality of the output image.
　本発明は、上記問題の解決を図るべくなされたものであって、ｉ型の光電変換膜と不純物半導体材料からなるブロッキング層との接合部からｉ型の光電変換膜の範囲に存在する空乏層が、ｉ型の光電変換膜及び不純物半導体材料からなるブロッキング層の側面に生ずる界面準位が発生している領域まで広がってしまうことを抑制できる、固体撮像装置とその製造方法を提供することを目的とする。 The present invention has been made to solve the above problem, and is a depletion layer existing in a range from a junction between an i-type photoelectric conversion film and a blocking layer made of an impurity semiconductor material to an i-type photoelectric conversion film. However, the present invention provides a solid-state imaging device and a method for manufacturing the same that can prevent the interface state generated on the side surface of the blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material from being spread. Objective.
　上記目的を達成するために、本発明に係る固体撮像装置は、複数の画素があり、半導体基板と、半導体基板上に形成された層間絶縁膜と、層間絶縁膜上に、画素毎に孤立して形成された下部電極と、複数の画素に亘って形成された透光性を有する上部電極と、真性半導体材料からなり、画素毎に孤立して形成され、下部電極と上部電極とにそれぞれ挟まれた光電変換膜と、不純物半導体材料からなり、光電変換膜上に、複数の画素に亘って形成され、隣接する光電変換膜の間に相当する部位が当該光電変換膜の間に入り込んで、光電変換膜の側面の一部または全部を覆っているブロッキング層とを有することを特徴とする。 In order to achieve the above object, a solid-state imaging device according to the present invention has a plurality of pixels, and is isolated for each pixel on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and the interlayer insulating film. The lower electrode formed in this manner, the translucent upper electrode formed over a plurality of pixels, and made of an intrinsic semiconductor material, are formed separately for each pixel and sandwiched between the lower electrode and the upper electrode, respectively. Made of an impurity semiconductor material, formed over a plurality of pixels on the photoelectric conversion film, and a portion corresponding to between adjacent photoelectric conversion films enters between the photoelectric conversion films, And a blocking layer covering part or all of the side surface of the photoelectric conversion film.
　また、本発明に係る固体撮像装置の製造方法は、複数の画素がある固体撮像装置の製造方法であって、半導体基板上に、層間絶縁膜を形成する工程と、層間絶縁膜上に、画素毎に孤立して下部電極を形成する工程と、各下部電極の上に、画素毎に孤立して光電変換膜を形成する工程と、光電変換膜上に、複数の画素に亘って形成され、隣接する光電変換膜の間に相当する部位が当該光電変換膜の間に入り込んで、光電変換膜の側面の一部または全部とを覆うよう、不純物半導体材料からなるブロッキング層を形成する工程と、ブロッキング層の上に、複数の画素に亘って、透光性を有する上部電極を形成する工程とを含むことを特徴とする。 The solid-state imaging device manufacturing method according to the present invention is a method for manufacturing a solid-state imaging device having a plurality of pixels, the step of forming an interlayer insulating film on a semiconductor substrate, and the pixel on the interlayer insulating film. A step of forming a lower electrode by being isolated every time, a step of forming a photoelectric conversion film by being isolated for each pixel on each lower electrode, and a plurality of pixels on the photoelectric conversion film, A step of forming a blocking layer made of an impurity semiconductor material so that a portion corresponding to between adjacent photoelectric conversion films enters between the photoelectric conversion films and covers a part or all of the side surfaces of the photoelectric conversion film; Forming a translucent upper electrode over a plurality of pixels on the blocking layer.
　本発明に係る固体撮像装置では、ブロッキング層が光電変換膜の側面の一部または全部を覆っている。すなわち、ブロッキング層と光電変換膜との接合部からｉ型の光電変換膜の範囲に存在する空乏層の側面が、ブロッキング層により覆われている。そのため、空乏層がブロッキング層と透光性を有する上部電極との側面に発生する界面準位に接触しない。 In the solid-state imaging device according to the present invention, the blocking layer covers part or all of the side surface of the photoelectric conversion film. That is, the side surface of the depletion layer present in the range of the i-type photoelectric conversion film from the junction between the blocking layer and the photoelectric conversion film is covered with the blocking layer. Therefore, the depletion layer does not contact the interface state generated on the side surface of the blocking layer and the translucent upper electrode.
　このように、ブロッキング層が光電変換膜の側面の一部または全部を覆っていることで、空乏層と界面準位とが接することを防止でき、その結果、界面準位の影響を低減し、暗電流やトラップ性残像の発生を抑制できる。そして、ｉ型の光電変換膜と不純物半導体材料からなるブロッキング層との接合部からｉ型の光電変換膜の範囲に存在する空乏層が、ｉ型の光電変換膜及び不純物半導体材料からなるブロッキング層の側面に生ずる界面準位が発生している領域まで広がることを抑制することができる。 Thus, the blocking layer covers part or all of the side surface of the photoelectric conversion film, so that the depletion layer and the interface state can be prevented from coming into contact with each other.As a result, the influence of the interface state is reduced, Generation of dark current and trapping afterimage can be suppressed. The depletion layer existing in the range of the i-type photoelectric conversion film from the junction between the i-type photoelectric conversion film and the blocking layer made of the impurity semiconductor material is a blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material. It can be suppressed that the interface state generated on the side surface is expanded to a region where the interface state is generated.
　さらに、本発明に係る固体撮像装置では、ブロッキング層が光電変換膜の上面を覆っており、光電変換膜で発生した信号電荷を、光電変換膜内に留めておくことができる。そのため、信号電荷の移動効率を向上させることができる。 Furthermore, in the solid-state imaging device according to the present invention, the blocking layer covers the upper surface of the photoelectric conversion film, and signal charges generated in the photoelectric conversion film can be retained in the photoelectric conversion film. Therefore, the transfer efficiency of signal charges can be improved.
　また、本発明の製造方法によると、ｉ型の光電変換膜と不純物半導体材料で形成されたブロッキング層との接合部からｉ型の光電変換膜の範囲に存在する空乏層が、ｉ型の光電変換膜及び不純物半導体材料で形成されたブロッキング層の側面に生ずる界面準位が発生している領域まで広がることを抑制できる、固体撮像装置を製造することができる。 According to the manufacturing method of the present invention, the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the blocking layer formed of the impurity semiconductor material to the i-type photoelectric conversion film is an i-type photoelectric conversion film. It is possible to manufacture a solid-state imaging device that can suppress spreading to a region where an interface state generated on the side surface of the blocking layer formed of the conversion film and the impurity semiconductor material is generated.
本発明の実施の形態１に係る固体撮像装置の全体構成を模式的に示すブロック図である。1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. 図１に示した固体撮像装置における６画素分の平面図である。It is a top view for 6 pixels in the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 本発明の実施の形態２に係る固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device concerning Embodiment 2 of this invention. 図９に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図９に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 本発明の実施の形態３に係る固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 3 of this invention. 図１２に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. 図１２に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. 本発明の実施の形態４に係る固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 4 of this invention. 図１５に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. 図１５に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. 従来の固体撮像装置の断面図である。It is sectional drawing of the conventional solid-state imaging device.
[実施の形態１] 
１．固体撮像装置１の全体構成
　実施の形態１に係る固体撮像装置１の全体構成について、図１を用いて説明する。 [Embodiment 1]
1. Overall Configuration of Solid-State Imaging Device 1 The overall configuration of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG.
　図１に示すように、固体撮像装置１では、画素領域６１に、複数の画素１００が、二次元配置、例えばマトリクス状（行列状）で存在している。画素領域６１を囲むように、パルス発生回路６２と、垂直シフトレジスタ６３と、水平シフトレジスタ６４とが形成されている。垂直シフトレジスタ６３及び水平シフトレジスタ６４は、パルス発生回路６２からのタイミングパルスの印加に呼応して、各画素１００に対して、順次、駆動パルスを出力する。
２．画素１００の構成
　図２は、図１に示した固体撮像装置１における一部領域として６画素分を示した平面図である。各画素１００同士は画素境界部４３で区画されており、各画素１００には、リセットゲート１０と、増幅トランジスタ１１と、ｎ型不純物拡散層の蓄積ダイオード１５と、ｎ型不純物拡散層のフローティングディフュージョン１６と、ｎ型不純物拡散層のリセットトランジスタドレイン１７と、転送ゲート１８と、コンタクト３１～３４と、金属配線４５とが備えられている。 As shown in FIG. 1, in the solid-state imaging device 1, a plurality of pixels 100 exist in a two-dimensional arrangement, for example, a matrix (matrix) in the pixel region 61. A pulse generation circuit 62, a vertical shift register 63, and a horizontal shift register 64 are formed so as to surround the pixel region 61. The vertical shift register 63 and the horizontal shift register 64 sequentially output drive pulses to each pixel 100 in response to the application of the timing pulse from the pulse generation circuit 62.
2. Configuration of Pixel 100 FIG. 2 is a plan view showing six pixels as a partial region in the solid-state imaging device 1 shown in FIG. Each pixel 100 is partitioned by a pixel boundary 43. Each pixel 100 includes a reset gate 10, an amplification transistor 11, a storage diode 15 in an n-type impurity diffusion layer, and a floating diffusion in an n-type impurity diffusion layer. 16, an n-type impurity diffusion layer reset transistor drain 17, a transfer gate 18, contacts 31 to 34, and a metal wiring 45.
　図３は、図１に示した固体撮像装置１の画素１００の断面図であり、図２のＡ―Ａ’断面を示している。なお、図面の便宜上、固体撮像装置１の有する画素として３つの画素１００を用いて説明する。図３に示すように、ｐ型ウェルが形成された半導体基板５内には、ＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｒａｔｉｏｎ）１２が形成されている。各画素１００には、チャネルストッパー１３と、蓄積ダイオード１５と、フローティングディフュージョン１６と、リセットトランジスタドレイン１７とが形成されている。 FIG. 3 is a cross-sectional view of the pixel 100 of the solid-state imaging device 1 shown in FIG. 1, and shows a cross-section A-A ′ of FIG. For the sake of convenience, the description will be made using three pixels 100 as the pixels of the solid-state imaging device 1. As shown in FIG. 3, an STI (Shallow Trench Isolation) 12 is formed in the semiconductor substrate 5 on which the p-type well is formed. In each pixel 100, a channel stopper 13, a storage diode 15, a floating diffusion 16, and a reset transistor drain 17 are formed.
　半導体基板５の上には、ゲート酸化膜１４と、層間絶縁膜２０とが順に積層されており、層間絶縁膜２０内には、リセットゲート１０と、転送ゲート１８と、増幅トランジスタゲート１９と、接続電極２３とが形成されている。 On the semiconductor substrate 5, a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked. Within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.
　層間絶縁膜２０の上には、層間絶縁膜２１，２２が順に積層されており、層間絶縁膜２１，２２内には、配線２４，２５（例えば、ＡｌやＣｕで形成される）と接続電極２６とが形成されている。層間絶縁膜２０～２２は、例えば、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いてなる酸化膜によって形成される。 Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20. In the interlayer insulating films 21 and 22, wirings 24 and 25 (for example, formed of Al or Cu) and connection electrodes 26 is formed. The interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.
　層間絶縁膜２２の上には、画素電極４０が、画素毎に孤立して形成されている。各画素電極４０の上には、赤色の光に対し分光感度を有する光電変換膜４１ａと、緑色の光に対し分光感度を有する光電変換膜４１ｂとが、交互かつ互いに孤立して形成されている。なお、青色の光に対し分光感度を有する光電変換膜も固体撮像装置１には備わっているが、ベイヤー配列が採用されているため、図２におけるＡ―Ａ’断面である図３には表れていない。以降、分光感度が関係しない場合には、各色の光電変換膜を区別せずに、光電変換膜４１と総称する。 The pixel electrode 40 is formed on the interlayer insulating film 22 so as to be isolated for each pixel. On each pixel electrode 40, photoelectric conversion films 41a having spectral sensitivity with respect to red light and photoelectric conversion films 41b having spectral sensitivity with respect to green light are formed alternately and isolated from each other. . Note that the solid-state imaging device 1 also has a photoelectric conversion film having spectral sensitivity to blue light. However, since a Bayer array is adopted, it appears in FIG. 3 which is a cross section taken along line AA ′ in FIG. Not. Hereinafter, when the spectral sensitivity is not related, the photoelectric conversion films of the respective colors are collectively referred to as the photoelectric conversion film 41 without being distinguished.
　光電変換膜４１は、無機光導電膜等からなるｉ型の半導体材料により形成されており、赤色、緑色、青色の分光感度は、同一の半導体材料の組成比を変えることで調整している。無機光導電膜としてα―Ｓｉ膜を用いた場合、具体的には、光電変換膜４１の分光感度は、α―Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御することにより得ている。 The photoelectric conversion film 41 is formed of an i-type semiconductor material made of an inorganic photoconductive film or the like, and the red, green, and blue spectral sensitivities are adjusted by changing the composition ratio of the same semiconductor material. When the α-Si film is used as the inorganic photoconductive film, specifically, the spectral sensitivity of the photoelectric conversion film 41 is controlled by changing the ratio of α-Si 1-x C x : x. It has gained.
　光電変換膜４１上に、複数の画素に亘って、ｐ型のブロッキング層４２が形成されている。ブロッキング層４２は、光電変換膜４１の上面に形成されている部位４２ａと、隣接する光電変換膜４１の間に相当する部位４２ｂとからなる。ブロッキング層４２の当該光電変換膜４１の間に相当する部位４２ｂは、隣接する光電変換膜４１の間に入り込み、光電変換膜４１の側面の全部を覆っている。また、ブロッキング層４２と画素電極４０とが接しないように、ブロッキング層４２と画素電極４０の側面との間には隙間が設けられており、この隙間には光電変換膜４１が存在している。 A p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels. The blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41. The part 42 b corresponding to the space between the photoelectric conversion films 41 of the blocking layer 42 enters between the adjacent photoelectric conversion films 41 and covers all the side surfaces of the photoelectric conversion film 41. In addition, a gap is provided between the blocking layer 42 and the side surface of the pixel electrode 40 so that the blocking layer 42 and the pixel electrode 40 do not contact each other, and the photoelectric conversion film 41 exists in this gap. .
　ブロッキング層４２上に、複数の画素に亘って、透光性を有する上部電極として透明電極４４（例えば、ＩＴＯやＺｎＯにより形成される）が形成され、透明電極４４は、画素領域６１全体に拡がっている。隣接する光電変換膜４１の間は、画素境界部４３である。画素境界部４３では、当該光電変換膜４１の間に相当するブロッキング層の部位４２ｂを覆うように、透明電極４４が形成されている。 On the blocking layer 42, a transparent electrode 44 (formed of, for example, ITO or ZnO) is formed as a translucent upper electrode across a plurality of pixels, and the transparent electrode 44 extends over the entire pixel region 61. ing. Between adjacent photoelectric conversion films 41 is a pixel boundary portion 43. In the pixel boundary portion 43, a transparent electrode 44 is formed so as to cover a portion 42 b of the blocking layer corresponding to the space between the photoelectric conversion films 41.
　画素境界部４３における透明電極４４上に、金属配線４５が形成されている。金属配線４５の形状は、画素領域６１におけるすべての隣接する画素の間を通るもので、画素領域６１全体を平面視したとき、メッシュ状をしている。さらに、金属配線４５は、画素領域６１を囲むように形成される。すなわち、金属配線４５は、画素領域６１の中央部から画素領域６１の周囲に向かって伸びており、且つ、画素領域６１の中央部と画素領域６１の周囲とを繋ぐことになる。金属配線４５は、透明電極４４の材料よりも電気抵抗率が小さい材料からなる。なお、金属配線４５は受光部では無い画素境界部４３に設けられているため、金属配線４５の存在により開口率が低下することはない。また、金属配線４５の最大許容幅は、画素境界部４３の幅と同じである。
３．固体撮像装置１の駆動
　入射した光は、光電変換膜４１で電荷に変換される。透明電極４４にはバイアス電圧が印加されており、透明電極４４と画素電極４０との間のバイアス電圧により、発生した電荷は画素電極４０に引き寄せられ、画素電極４０から接続電極２３，２６を通って、蓄積ダイオード１５に一時蓄積される。次に、転送ゲート１８の作用により、当該電荷は、蓄積ダイオード１５から、フローティングディフュージョン１６に転送蓄積される。信号電荷量に応じてフローティングディフュージョン１６の電位が変動し、この変動量が増幅トランジスタゲート１９を介して、増幅トランジスタ１１に伝わり、さらに増幅トランジスタ１１で増幅され、外部に信号として取り出される。 A metal wiring 45 is formed on the transparent electrode 44 in the pixel boundary portion 43. The shape of the metal wiring 45 passes between all adjacent pixels in the pixel region 61, and has a mesh shape when the entire pixel region 61 is viewed in plan. Further, the metal wiring 45 is formed so as to surround the pixel region 61. That is, the metal wiring 45 extends from the central portion of the pixel region 61 toward the periphery of the pixel region 61, and connects the central portion of the pixel region 61 and the periphery of the pixel region 61. The metal wiring 45 is made of a material having a lower electrical resistivity than the material of the transparent electrode 44. In addition, since the metal wiring 45 is provided in the pixel boundary part 43 which is not a light-receiving part, an aperture ratio does not fall by presence of the metal wiring 45. Further, the maximum allowable width of the metal wiring 45 is the same as the width of the pixel boundary 43.
3. Driving of the solid-state imaging device 1 The incident light is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 44, and the generated charge is attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 44 and the pixel electrode 40, and passes through the connection electrodes 23 and 26 from the pixel electrode 40. Thus, it is temporarily stored in the storage diode 15. Next, the charge is transferred and stored from the storage diode 15 to the floating diffusion 16 by the action of the transfer gate 18. The potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside.
　リセットトランジスタドレイン１７は、電源電圧端子Ｖｄｄに電気的に接続されている。そのため、リセットトランジスタドレイン１７の電位は常にＶｄｄである。リセットゲート１０をＯＮにすることにより、フローティングディフュージョン１６の電位は、リセットトランジスタドレイン１７の電位Ｖｄｄにリセットされる。
４．効果
　光電変換膜４１とブロッキング層４２との接合部からｉ型の光電変換膜４１の範囲に、空乏層が存在する。この構成では、ブロッキング層４２の隣接する光電変換膜４１の間に相当する部位４２ｂは、当該光電変換膜４１の間に入り込み、ｉ型の光電変換膜４１の側面の全部が、ｐ型のブロッキング層４２で覆われている。従って、空乏層の側面がブロッキング層４２で覆われており、空乏層が界面準位の発生している領域まで広がることはない。そのため、界面準位に起因した暗電流やトラップ性残像を抑制することができる。 The reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17.
4). Effect A depletion layer exists in the range of the i-type photoelectric conversion film 41 from the junction between the photoelectric conversion film 41 and the blocking layer 42. In this configuration, the portion 42b corresponding to the space between the adjacent photoelectric conversion films 41 of the blocking layer 42 enters between the photoelectric conversion films 41, and all of the side surfaces of the i-type photoelectric conversion film 41 are p-type blocking. Covered with a layer 42. Therefore, the side surface of the depletion layer is covered with the blocking layer 42, and the depletion layer does not extend to the region where the interface state is generated. Therefore, dark current and trapping afterimages due to interface states can be suppressed.
　さらに、カラーフィルターを用いず、各画素に所定の分光感度を有する光電変換膜４１を用いる構成となっているため、カラーフィルターによる光の吸収が無く、光損失を避けることができる。 Furthermore, since the photoelectric conversion film 41 having a predetermined spectral sensitivity is used for each pixel without using a color filter, there is no light absorption by the color filter, and light loss can be avoided.
　また、金属配線４５が透明電極４４上に形成されることで、透明電極４４と金属配線４５とをまとめた合成抵抗が、透明電極４４のみの抵抗よりも小さくなる。よって、透明電極４４の抵抗が原因で大きくなっていた画素領域６１の中央部での電圧降下が小さくなり、画素領域６１の中央部での電圧降下を抑制することができる。これにより、画素領域６１の場所ごとに電圧降下の大きさが異なった場合に起きる、撮像画像の画質の劣化を軽減することができる。 Further, since the metal wiring 45 is formed on the transparent electrode 44, the combined resistance of the transparent electrode 44 and the metal wiring 45 is made smaller than the resistance of the transparent electrode 44 alone. Therefore, the voltage drop at the center of the pixel region 61 that has been increased due to the resistance of the transparent electrode 44 is reduced, and the voltage drop at the center of the pixel region 61 can be suppressed. As a result, it is possible to reduce the degradation of the image quality of the captured image that occurs when the magnitude of the voltage drop differs for each location of the pixel region 61.
　加えて、光電変換膜４１は画素毎に分離されているので、分解能が高く混色や画素間リークが抑制でき、撮像画像の画質の劣化を軽減することができる。
５．固体撮像装置１の製造方法
　本発明の実施の形態１における画素１００の製造方法について、図４～８を用いて、要部となる工程を説明する。 In addition, since the photoelectric conversion film 41 is separated for each pixel, the resolution is high, color mixing and inter-pixel leakage can be suppressed, and deterioration of the image quality of the captured image can be reduced.
5. Manufacturing Method of Solid-State Imaging Device 1 With respect to the manufacturing method of the pixel 100 according to the first embodiment of the present invention, a process that is a main part will be described with reference to FIGS.
　図４（ａ）において、ｐ型の半導体基板５に、トランジスタや拡散層の素子を分離するＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｌａｔｉｏｎ）１２を形成する。具体的には、半導体基板５をドライエッチングすることで、分離領域となる深さ２００ｎｍ～４００ｎｍの溝を形成する。形成した溝とＳｉ基板界面との欠陥領域を低減するため、熱酸化等により、例えば、酸化膜厚１０ｎｍ～２０ｎｍの犠牲酸化を行い、さらに、例えば１０ｋｅＶ～２０ｋｅＶ、１×１０１３ｃｍ－２～３×１０１３ｃｍ－２で、Ｂのイオン注入を行い、ｐ＋層のチャネルストッパー１３を形成する。次に、形成した溝の内を絶縁膜で埋め、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）で平坦化することにより、ＳＴＩ１２を形成する。 In FIG. 4A, an STI (Shallow Trench Isolation) 12 that separates transistors and diffusion layer elements is formed on a p-type semiconductor substrate 5. Specifically, the semiconductor substrate 5 is dry-etched to form a trench having a depth of 200 nm to 400 nm serving as an isolation region. In order to reduce the defect region between the formed trench and the Si substrate interface, for example, sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 × 10 13 cm −2 to B ion implantation is performed at 3 × 10 13 cm −2 to form the channel stopper 13 of the p + layer. Next, the inside of the formed trench is filled with an insulating film, and planarized by CMP (Chemical Mechanical Polishing), thereby forming the STI 12.
　次に、熱酸化、またはプラズマ酸化等により、転送ゲート１８やリセットゲート１０を構成するトランジスタのゲート酸化膜となるゲート酸化膜１４を、例えば、５ｎｍ～１０ｎｍ形成する。 Next, the gate oxide film 14 which becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed, for example, by 5 to 10 nm by thermal oxidation or plasma oxidation.
　次に、図４（ｂ）に示すように、熱ＣＶＤ、またはプラズマＣＶＤ等により、Ｐｏｌｙ－Ｓｉ膜を、例えば、１００ｎｍ～２００ｎｍ堆積し、その後一般的なフォトリソグラフィ技術によって、所定のレジストパターンを形成する。そして、Ｐｏｌｙ－Ｓｉ膜を選択的にエッチングすることにより、Ｐｏｌｙ－Ｓｉ膜からなる転送ゲート１８や増幅トランジスタゲート１９やリセットゲート１０を形成する。 Next, as shown in FIG. 4B, a Poly-Si film, for example, 100 nm to 200 nm is deposited by thermal CVD, plasma CVD, or the like, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19, and the reset gate 10 made of the Poly-Si film are formed.
　次に、ｐ型の半導体基板５にＰやＡｓを、例えば、５０ｋｅＶ～８０ｋｅＶ、１×１０１４ｃｍ－２ ～ ２×１０１５ｃｍ－２で、イオン注入することにより、蓄積ダイオード１５、フローティングディフュージョン１６、及びリセットトランジスタドレイン１７の各ｎ型の不純物層を同時に形成する。 Next, P and As are ion-implanted into the p-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 × 10 14 cm −2 to 2 × 10 15 cm −2 , so that the storage diode 15, the floating diffusion 16 and the n-type impurity layers of the reset transistor drain 17 are formed simultaneously.
　ここで、ゲート酸化膜１４形成後に、フローティングディフュージョン１６上の一部を開口し、Ｐｏｌｙ－Ｓｉ膜で構成される増幅トランジスタゲート１９を形成して、フローティングディフュージョン１６と増幅トランジスタゲート１９との電気的接続をとっている。 Here, after the gate oxide film 14 is formed, a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film, and the electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is established. Connected.
　ＣＶＤ酸化膜よりなる層間絶縁膜２０を、例えば５００ｎｍ～１０００ｎｍ形成する。そして、一般的なフォトリソグラフィ技術とエッチング技術によって、所定の位置にコンタクト３１やコンタクト３２、及びコンタクト３３を形成する。開口されたコンタクト開口部にＷ（タングステン）のプラグを埋め込み、Ｗプラグの接続電極２３を形成し、蓄積ダイオード１５やリセットトランジスタドレイン１７との電気的接続を形成する。例えば２００ｎｍ～３００ｎｍの膜厚のＡｌやＣｕ等よりなる配線２４と、ＣＶＤ酸化膜よりなる層間絶縁膜２１とを形成する。同様の繰り返しで、配線２５、層間絶縁膜２２を形成し、多層配線の形成を終了する。ここで、接続電極２３上にコンタクトを開口し、Ｗプラグを埋め込んで接続電極２６を形成する。 An interlayer insulating film 20 made of a CVD oxide film is formed, for example, to 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique. A W (tungsten) plug is embedded in the opened contact opening to form a connection electrode 23 of the W plug, and electrical connection to the storage diode 15 and the reset transistor drain 17 is formed. For example, a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed. Here, a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.
　図５（ａ）において、層間絶縁膜２２形成後に、ＡｌやＷ、Ｍｏ（モリブデン）等よりなる金属膜を１００ｎｍ～３００ｎｍ堆積し、一般的なフォトリソグラフィ技術とエッチング技術によって所定の形状の画素電極４０を形成する。画素電極４０は画素毎に孤立して形成されており、画素電極４０の分離されている面積が、画素の実効的な開口率を決定している。例えば、１．０ｕｍ～１．４ｕｍの画素サイズにおいて画素間の分離幅が画素サイズの１／１０～２／１０とすれば、開口率は約６４％～約８１％と見積もられる。 In FIG. 5A, after the interlayer insulating film 22 is formed, a metal film made of Al, W, Mo (molybdenum) or the like is deposited to 100 nm to 300 nm, and a pixel electrode having a predetermined shape is formed by a general photolithography technique and an etching technique. 40 is formed. The pixel electrode 40 is formed so as to be isolated for each pixel, and the area where the pixel electrode 40 is separated determines the effective aperture ratio of the pixel. For example, if the separation width between the pixels is 1/10 to 2/10 of the pixel size of 1.0 μm to 1.4 μm, the aperture ratio is estimated to be about 64% to about 81%.
　図５（ｂ）において、画素電極４０形成後に、画素電極４０及び層間絶縁膜２２を覆うように、プラズマＣＶＤやスパッタで、赤色の分光感度特性を有するα―Ｓｉ膜を１００ｎｍ～１ｕｍ堆積し、ｉ型の光電変換膜４１ａを形成する。この分光感度は、具体的には、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御することにより得ている。 In FIG. 5B, after forming the pixel electrode 40, an α-Si film having a red spectral sensitivity characteristic is deposited to 100 nm to 1 μm by plasma CVD or sputtering so as to cover the pixel electrode 40 and the interlayer insulating film 22. An i-type photoelectric conversion film 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si 1-x C x : x.
　図６（ａ）において、光電変換膜４１ａ上に、一般的なフォトリソグラフィ技術によって、所定のレジストパターン７０を形成する。光電変換膜４１ａの一画素毎の寸法は、例えば、１．０ｕｍ～１．４ｕｍの画素サイズにおいて、それぞれ０．９ｕｍ～１．３ｕｍである。 6A, a predetermined resist pattern 70 is formed on the photoelectric conversion film 41a by a general photolithography technique. The size of each pixel of the photoelectric conversion film 41a is, for example, 0.9 μm to 1.3 μm in a pixel size of 1.0 μm to 1.4 μm.
　図６（ｂ）において、レジストパターン７０をマスクに、一般的なエッチング技術によって光電変換膜４１ａをエッチングし、所定のパターンの光電変換膜４１ａを形成する。 6B, using the resist pattern 70 as a mask, the photoelectric conversion film 41a is etched by a general etching technique to form a photoelectric conversion film 41a having a predetermined pattern.
　図７（ａ）において、図５（ｂ）～図６（ｂ）に記載したｉ型の光電変換膜４１ａの製造方法の繰り返しにより、各画素１００において、対応する各画素電極４０の上に、ｉ型の光電変換膜４１ｂが画素毎に孤立して形成される。なお、隣接する光電変換膜４１ａ、４１ｂは異なる分光感度を有するように、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御している。また、各画素における光電変換膜４１が孤立して形成されることにより、画素境界部４３が形成される。 In FIG. 7A, by repeating the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 5B to 6B, in each pixel 100, on each corresponding pixel electrode 40, An i-type photoelectric conversion film 41b is formed in isolation for each pixel. Note that the spectral sensitivity is controlled by changing the ratio of α-Si 1-x C x : x so that the adjacent photoelectric conversion films 41a and 41b have different spectral sensitivities. Moreover, the pixel boundary part 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
　図７（ｂ）において、光電変換膜４１の上面及び側面を覆うように、プラズマＣＶＤやスパッタで、ｉ型の光電変換膜４１のブロッキング層となるよう、所定のエネルギーギャップを有するα―Ｓｉ膜を１０ｎｍ～１００ｎｍ堆積し、ｐ型のブロッキング層４２を複数の画素に亘って形成する。ブロッキング層４２は光電変換膜４１の上面に形成されている部位４２ａと、隣接する光電変換膜４１の間に相当する部位４２ｂとからなる。 In FIG. 7B, an α-Si film having a predetermined energy gap so as to be a blocking layer of the i-type photoelectric conversion film 41 by plasma CVD or sputtering so as to cover the upper surface and side surfaces of the photoelectric conversion film 41. Are deposited to a thickness of 10 to 100 nm, and a p-type blocking layer 42 is formed over a plurality of pixels. The blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41.
　図８（ａ）において、光電変換膜４１上に形成されたブロッキング層４２の上に、スパッタやＣＶＤでＩＴＯやＺｎＯよりなる透明電極４４を、数１０ｎｍ～数１００ｎｍ形成する。ブロッキング層４２の部位４２ａと部位４２ｂとは、どちらも透明電極４４によって覆われている。 8A, on the blocking layer 42 formed on the photoelectric conversion film 41, a transparent electrode 44 made of ITO or ZnO is formed by several tens to several hundreds nm by sputtering or CVD. Both the portion 42 a and the portion 42 b of the blocking layer 42 are covered with the transparent electrode 44.
　図８（ｂ）において、透明電極４４の上に、スパッタやＣＶＤで金属配線４５を１００ｎｍ～３００ｎｍ堆積する。次に、一般的なフォトリソグラフィ技術によって、金属配線４５の上に所定のレジストパターン７１を形成する。レジストパターン７１をマスクに、一般的なエッチング技術によって金属配線４５をエッチングし、透明電極４４上にメッシュ状の金属配線４５を形成する。これにより、図３に記載された固体撮像素子となる。 In FIG. 8B, a metal wiring 45 is deposited on the transparent electrode 44 by sputtering or CVD to a thickness of 100 to 300 nm. Next, a predetermined resist pattern 71 is formed on the metal wiring 45 by a general photolithography technique. Using the resist pattern 71 as a mask, the metal wiring 45 is etched by a general etching technique to form a mesh-like metal wiring 45 on the transparent electrode 44. Thereby, the solid-state imaging device shown in FIG. 3 is obtained.
　この工程以降において、オンチップマイクロレンズが形成されて、固体撮像素子の製造が終了するが、本発明の主眼ではないので、説明は省略する。
[実施の形態２]
１．画素２００の構成
　図９は、本発明の実施の形態２における、固体撮像装置１の画素２００の断面図である。なお、図面の便宜上、固体撮像装置１の有する画素として３つの画素２００を用いて説明する。下記以外の構成は、画素１００と同じなので説明を省略する。 After this step, an on-chip microlens is formed and the manufacture of the solid-state imaging device is completed. However, since it is not the main point of the present invention, the description is omitted.
[Embodiment 2]
1. Configuration of Pixel 200 FIG. 9 is a cross-sectional view of the pixel 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. For the sake of convenience, the description will be made using three pixels 200 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
　各画素２００には、画素電極４０と、ｉ型の光電変換膜４１と、ｐ型のブロッキング層４２と、透明電極４４と、金属配線４５と、絶縁膜４６とが形成されている。 In each pixel 200, a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an insulating film 46 are formed.
　各光電変換膜４１ａ、４１ｂは、画素毎に孤立して形成されており、そのうち少なくとも２つが異なる分光感度特性を有している。光電変換膜４１の上には、ブロッキング層４２が複数の画素に亘って形成されている。ブロッキング層４２は光電変換膜４１の上面に形成されている部位４２ａと、隣接する光電変換膜４１の間に相当する部位４２ｂとからなる。光電変換膜４１の側面の上半分は、ブロッキング層４２の隣接する光電変換膜４１の間に相当する部位４２ｂで覆われている。当該光電変換膜４１の間には、絶縁膜４６が埋め込まれており、その結果、光電変換膜４１の側面の下半分を絶縁膜４６が覆っている。ここで、「上半分」「下半分」というのは、厳密に上下二分の一に分かれていることを示しておらず、光電変換膜４１を上下二つに分けたそれぞれの部分を示す。すなわち、層間絶縁膜２２から光電変換膜４１の下半分までの高さは、層間絶縁膜２２からの光電変換膜４１の高さの二分の一から、多少上下しても構わない。絶縁膜４６を、層間絶縁膜２２からの光電変換膜４１の高さの二分の一より高く形成すれば、ブロッキング層４２、透明電極４４及び金属配線４５を、容易に埋め込むことができる。また、絶縁膜４６を、層間絶縁膜２２からの光電変換膜４１の高さの二分の一より低く形成すれば、ブロッキング層４２、透明電極４４および金属配線４５を深くまで形成でき、光電変換膜４１による光電変換効率を向上できる。 The photoelectric conversion films 41a and 41b are formed so as to be isolated for each pixel, and at least two of them have different spectral sensitivity characteristics. On the photoelectric conversion film 41, a blocking layer 42 is formed across a plurality of pixels. The blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to between the adjacent photoelectric conversion films 41. The upper half of the side surface of the photoelectric conversion film 41 is covered with a portion 42 b corresponding to the space between the photoelectric conversion films 41 adjacent to the blocking layer 42. An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. Here, “upper half” and “lower half” do not indicate that the upper half is strictly divided into upper and lower halves, but indicate respective portions where the photoelectric conversion film 41 is divided into upper and lower portions. That is, the height from the interlayer insulating film 22 to the lower half of the photoelectric conversion film 41 may be slightly higher or lower than one half of the height of the photoelectric conversion film 41 from the interlayer insulating film 22. If the insulating film 46 is formed to be higher than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be easily embedded. Further, if the insulating film 46 is formed to be lower than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be formed deeply, and the photoelectric conversion film The photoelectric conversion efficiency by 41 can be improved.
　層間絶縁膜２２からの絶縁膜４６の高さは、層間絶縁膜２２からの画素電極４０の高さより高く形成されている。これは、画素電極４０とｐ型のブロッキング層４２とが接し、ショートすることを防ぐためである。また、光電変換膜４１の透明電極４４上に、メッシュ状の金属配線４５が形成されている。
２．効果
　この構成では、隣接する光電変換膜４１間の下半分に、絶縁膜４６が埋め込まれており、その結果、光電変換膜４１の側面の下半分を絶縁膜４６が覆うことで、画素電極４０の両端が画素境界部４３に接する箇所まで、画素電極４０を形成することができる。すなわち、実施の形態１よりも、画素電極４０を幅広く形成することができる。画素電極４０が大きくなると、光電変換膜４１で変換された信号電荷を多く拾うことができ、多くの信号電荷の出力につながり、固体撮像装置１の感度が向上する。
３．製造方法
　本発明の実施の形態２における画素２００の製造方法について、本発明の実施の形態１との差異を中心に、要部となる工程を、図１０及び図１１を用いて説明する。 The height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. This is to prevent the pixel electrode 40 and the p-type blocking layer 42 from coming into contact with each other and causing a short circuit. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the insulating film 46 is embedded in the lower half between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. The pixel electrode 40 can be formed up to a place where both ends of the pixel contact the pixel boundary portion 43. That is, the pixel electrode 40 can be formed wider than in the first embodiment. When the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.
3. Manufacturing Method With respect to the manufacturing method of the pixel 200 according to the second embodiment of the present invention, the main steps will be described with reference to FIGS. 10 and 11, focusing on differences from the first embodiment of the present invention.
　図１０（ａ）において、画素電極４０を画素毎に形成した後に、画素電極４０上にプラズマＣＶＤやスパッタで、赤色の分光感度特性を有するα―Ｓｉ膜を１００ｎｍ～１ｕｍ堆積し、ｉ型の光電変換膜４１ａを形成する。この分光感度は、具体的には、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御することにより得ている。光電変換膜４１ａ上に、一般的なフォトリソグラフィ技術によって、所定のレジストパターン７２を形成する。 In FIG. 10A, after the pixel electrode 40 is formed for each pixel, an α-Si film having a red spectral sensitivity characteristic is deposited on the pixel electrode 40 by plasma CVD or sputtering to have a thickness of 100 nm to 1 μm. A photoelectric conversion film 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si 1-x C x : x. A predetermined resist pattern 72 is formed on the photoelectric conversion film 41a by a general photolithography technique.
　図１０（ｂ）において、レジストパターン７２をマスクに、一般的なエッチング技術によって光電変換膜４１ａをエッチングし、所定のパターンの光電変換膜４１ａを画素毎に孤立して形成する。この光電変換膜４１ａは、実施の形態１のものとは異なり、光電変換膜４１ａの両端が、画素電極４０の両端と一致するよう形成される。 In FIG. 10B, the photoelectric conversion film 41a is etched by a general etching technique using the resist pattern 72 as a mask, and the photoelectric conversion film 41a having a predetermined pattern is formed isolated for each pixel. Unlike the one in the first embodiment, this photoelectric conversion film 41 a is formed so that both ends of the photoelectric conversion film 41 a coincide with both ends of the pixel electrode 40.
　図１１（ａ）において、図１０（ａ）～図１０（ｂ）に記載したｉ型の光電変換膜４１ａの製造方法が繰り返され、各画素２００において、対応する各画素電極４０の上に、ｉ型の光電変換膜４１ａ、４１ｂが形成される。なお、各光電変換膜４１ａ、４１ｂは異なる分光感度を有するように、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御している。
また、光電変換膜４１ａ、４１ｂを、画素電極４０よりも小さくすることもできる。画素電極４０を光電変換膜４１ａ、４１ｂより大きく形成すると、感度を向上させることができる。この構成では、後に絶縁膜４６が形成されるため、画素電極４０が光電変換膜４１ａ、４１ｂより大きくても、ブロッキング層４２や透明電極４４と接触しないためである。画素電極４０を形成するときのマスクパターンと光電変換膜４１ａや光電変換膜４１ｂを形成するときのマスクパターンとの合わせズレなどに対しても、効果を発揮できる。 In FIG. 11A, the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 10A to 10B is repeated, and in each pixel 200, on each corresponding pixel electrode 40, i-type photoelectric conversion films 41a and 41b are formed. Note that the spectral sensitivity is controlled by changing the ratio of α-Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities.
In addition, the photoelectric conversion films 41 a and 41 b can be made smaller than the pixel electrode 40. If the pixel electrode 40 is formed larger than the photoelectric conversion films 41a and 41b, the sensitivity can be improved. In this configuration, since the insulating film 46 is formed later, even if the pixel electrode 40 is larger than the photoelectric conversion films 41a and 41b, it does not contact the blocking layer 42 and the transparent electrode 44. The effect can also be exhibited against misalignment between the mask pattern when the pixel electrode 40 is formed and the mask pattern when the photoelectric conversion film 41a and the photoelectric conversion film 41b are formed.
　図１１（ｂ）において、隣接する光電変換膜４１の間を埋め込むようにＣＶＤ酸化膜よりなる絶縁膜４６を形成する。その結果、光電変換膜４１の下半分を、絶縁膜４６が覆うこととなる。また、各画素が分離して形成されることにより、画素境界部４３が形成される。ここで、例えば、１．０ｕｍ～１．４ｕｍの画素サイズにおいて、画素境界部４３の分離幅が画素サイズの１／１０とすれば、画素境界部４３は、０．１ｕｍ～０．１４ｕｍとなる。
この工程以降の工程の製造法は、本発明の実施の形態１と同様に、ブロッキング層４２、透明電極４４、金属配線４５、オンチップマイクロレンズ（不図示）を形成するのみなので、説明を省略する。
[実施の形態３]
１．構成
　図１２は、本発明の実施の形態３における、固体撮像装置１の画素３００の断面図である。なお、図面の便宜上、固体撮像装置１の有する画素として３つの画素３００を用いて説明する。下記以外の構成は、画素１００と同じなので説明を省略する。 In FIG. 11B, an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41. As a result, the insulating film 46 covers the lower half of the photoelectric conversion film 41. Moreover, the pixel boundary part 43 is formed by forming each pixel separately. Here, for example, in the pixel size of 1.0 μm to 1.4 μm, if the separation width of the pixel boundary 43 is 1/10 of the pixel size, the pixel boundary 43 is 0.1 μm to 0.14 μm. .
Since the manufacturing method of the process after this process is only forming the blocking layer 42, the transparent electrode 44, the metal wiring 45, and the on-chip microlens (not shown) similarly to Embodiment 1 of this invention, description is abbreviate | omitted. To do.
[Embodiment 3]
1. Configuration FIG. 12 is a cross-sectional view of the pixel 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention. For the sake of convenience, the description will be made using three pixels 300 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
　各画素３００には、画素電極４０と、ｉ型の光電変換膜４１と、ｐ型のブロッキング層４２と、透明電極４４と、金属配線４５と、ｎ型のブロッキング層４７とが形成されている。 In each pixel 300, a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an n-type blocking layer 47 are formed. .
　各光電変換膜４１ａ、４１ｂは、そのうち少なくとも２つが異なる分光感度特性を有しており、光電変換膜４１の上にはｐ型のブロッキング層４２が複数の画素に亘って形成されている。また、光電変換膜４１は、画素毎に形成された各画素電極４０の上に形成され、隣接する光電変換膜４１ａ、４１ｂは孤立している。光電変換膜４１の側面の全部は、ｐ型のブロッキング層４２で覆われている。 Each of the photoelectric conversion films 41a and 41b has different spectral sensitivity characteristics, and a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels. The photoelectric conversion film 41 is formed on each pixel electrode 40 formed for each pixel, and the adjacent photoelectric conversion films 41a and 41b are isolated. The entire side surface of the photoelectric conversion film 41 is covered with a p-type blocking layer 42.
　さらに、ｎ型ブロッキング層４７は、画素電極４０の上面を覆うように、各画素において光電変換膜４１と画素電極４０との間に介挿されている。ｎ型ブロッキング層４７は、画素電極４０の側面にも回り込み、画素電極４０の側面の全部を覆うよう形成されている。すなわち、画素電極４０の上面及び側面の全部は、ｎ型のブロッキング層４７で覆われている。なお、光電変換膜４１の透明電極４４上には、メッシュ状の金属配線４５が形成されている。
２．効果
　この構成では、ｎ型ブロッキング層４７が、画素電極４０の上面を覆うように、各画素において光電変換膜４１と画素電極４０との間に介挿され、さらに、画素電極４０の側面にも回り込み、画素電極４０の側面の全部を覆うよう形成されている。そのため、光電変換膜４１は、画素電極４０に接していない。よって、光電変換膜４１の光導電膜特性が改善され、暗電流が改善し、撮像画像の画質が向上する。
３．製造方法
　次に、以上のように構成された本発明の実施の形態３における画素３００の製造方法について、本発明の実施の形態１との差異を中心に、図１３及び図１４を用いて説明する。 Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. The n-type blocking layer 47 is formed so as to go around the side surface of the pixel electrode 40 and cover the entire side surface of the pixel electrode 40. That is, the entire upper surface and side surfaces of the pixel electrode 40 are covered with the n-type blocking layer 47. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40, and also on the side surface of the pixel electrode 40. It wraps around and covers the entire side surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality of the captured image is improved.
3. Manufacturing Method Next, a manufacturing method of the pixel 300 according to the third embodiment of the present invention configured as described above will be described with reference to FIGS. 13 and 14, focusing on differences from the first embodiment of the present invention. To do.
　図１３（ａ）において、層間絶縁膜２２の上に、画素毎に画素電極４０を形成する。 In FIG. 13A, a pixel electrode 40 is formed on the interlayer insulating film 22 for each pixel.
　図１３（ｂ）において、各画素電極４０及び層間絶縁膜２２上に、プラズマＣＶＤやスパッタで、ｉ型の光電変換膜のブロッキング層になるよう、所定のエネルギーギャップを有するα―Ｓｉ膜を数１０ｎｍ～数１００ｎｍ堆積し、ｎ型のブロッキング層４７を形成する。所定のエネルギーギャップは、具体的には、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御することにより得ている。 In FIG. 13B, several α-Si films having a predetermined energy gap are formed on each pixel electrode 40 and the interlayer insulating film 22 so as to become a blocking layer of the i-type photoelectric conversion film by plasma CVD or sputtering. An n-type blocking layer 47 is formed by depositing 10 nm to several 100 nm. Specifically, the predetermined energy gap is obtained by changing the ratio of α-Si 1-x C x : x to control the spectral sensitivity.
　図１４（ａ）において、ブロッキング層４７上に、一般的なフォトリソグラフィ技術によって、所定のレジストパターン７３を形成する。 14A, a predetermined resist pattern 73 is formed on the blocking layer 47 by a general photolithography technique.
　図１４（ｂ）において、レジストパターン７３をマスクに、一般的なエッチング技術によってブロッキング層４７をエッチングし、画素電極４０上に所定のパターンのブロッキング層４７を形成する。この時、ブロッキング層４７は、画素電極４０の上面及び側面を覆うように形成される。その後、画素電極４０上に光電変換膜４１を形成すると、ｎ型ブロッキング層４７が、画素電極４０の上面を覆うように光電変換膜４１と画素電極４０との間に介挿され、さらに、画素電極４０の側面にも回り込み、画素電極４０の側面の全部を覆うよう形成される、という構成となる。 14B, using the resist pattern 73 as a mask, the blocking layer 47 is etched by a general etching technique to form the blocking layer 47 having a predetermined pattern on the pixel electrode 40. At this time, the blocking layer 47 is formed to cover the upper surface and side surfaces of the pixel electrode 40. Thereafter, when the photoelectric conversion film 41 is formed on the pixel electrode 40, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 so as to cover the upper surface of the pixel electrode 40, and further, the pixel The structure is such that it is formed so as to go around the side surface of the electrode 40 and cover the entire side surface of the pixel electrode 40.
　この工程以降の工程の製造法は、本発明の実施の形態１と同じなので説明を省略する。
[実施の形態４]
１．構成
　図１５は、本発明の実施の形態４における、固体撮像装置１の画素４００の断面図である。なお、図面の便宜上、固体撮像装置１の有する画素として３つの画素４００を用いて説明する。下記以外の構成は、画素１００と同じなので説明を省略する。 Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate | omitted.
[Embodiment 4]
1. Configuration FIG. 15 is a cross-sectional view of the pixel 400 of the solid-state imaging device 1 according to Embodiment 4 of the present invention. For the sake of convenience, the description will be made using three pixels 400 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.
　各画素４００には、画素電極４０と、ｉ型の光電変換膜４１と、ｐ型のブロッキング層４２と、透明電極４４と、金属配線４５と、絶縁膜４６と、ｎ型のブロッキング層４７とが形成されている。 Each pixel 400 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, an insulating film 46, and an n-type blocking layer 47. Is formed.
　各光電変換膜４１ａ、４１ｂは孤立して形成されており、そのうち少なくとも２つが、異なる分光感度特性を有している。光電変換膜４１の上には、ｐ型のブロッキング層４２が、複数の画素に亘って形成されている。隣接する光電変換膜４１は孤立している。ｐ型のブロッキング層４２は、光電変換膜４１の上面に形成されている部位４２ａと、隣接する光電変換膜４１の間に相当する部位４２ｂとからなる。 The photoelectric conversion films 41a and 41b are formed in isolation, and at least two of them have different spectral sensitivity characteristics. On the photoelectric conversion film 41, a p-type blocking layer 42 is formed across a plurality of pixels. Adjacent photoelectric conversion films 41 are isolated. The p-type blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to the space between adjacent photoelectric conversion films 41.
　光電変換膜４１の側面の上半分が、ｐ型のブロッキング層４２の隣接する光電変換膜４１の間に相当する部位４２ｂで覆われている。当該光電変換膜４１の間には、絶縁膜４６が埋め込まれており、その結果、光電変換膜４１の側面の下半分を絶縁膜４６が覆っている。 The upper half of the side surface of the photoelectric conversion film 41 is covered with a corresponding portion 42b between the adjacent photoelectric conversion films 41 of the p-type blocking layer 42. An insulating film 46 is embedded between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.
　絶縁膜４６の層間絶縁膜２２からの高さは、画素電極４０の層間絶縁膜２２からの高さより高く形成されている。さらに、ｎ型ブロッキング層４７は、画素電極４０の上面を覆うように、各画素において光電変換膜４１と画素電極４０との間に介挿されている。また、光電変換膜４１の透明電極４４上には、メッシュ状の金属配線４５が形成されている。
２．効果
　この構成では、隣接する光電変換膜４１の間には、絶縁膜４６が埋め込まれており、その結果、光電変換膜４１の側面の下半分を絶縁膜４６が覆っているため、画素電極４０の両端が画素境界部４３に接するよう、画素電極４０を形成することができる。すなわち、画素電極４０を実施の形態１よりも大きく形成することができる。画素電極４０が大きくなると、光電変換膜４１で変換された信号電荷を多く拾うことができ、多くの信号電荷の出力につながり、固体撮像装置１の感度が向上する。 The height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the insulating film 46 is embedded between the adjacent photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. The pixel electrode 40 can be formed so that both ends thereof are in contact with the pixel boundary portion 43. That is, the pixel electrode 40 can be formed larger than in the first embodiment. When the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.
　この構成では、ｎ型ブロッキング層４７が、画素電極４０の上面を覆うように、各画素において光電変換膜４１と画素電極４０との間に介挿されている。そのため、光電変換膜４１は画素電極４０に接していない。よって、光電変換膜４１の光導電膜特性が改善され、暗電流が改善し、撮像画像の画質が向上する。
３．製造方法
　次に、以上のように構成された本発明の実施の形態４における画素４００の製造方法について、本発明の実施の形態１から３との差異を中心に、図１６及び図１７を用いて説明する。 In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality of the captured image is improved.
3. Manufacturing Method Next, a manufacturing method of the pixel 400 according to the fourth embodiment of the present invention configured as described above will be described with reference to FIGS. 16 and 17, focusing on differences from the first to third embodiments of the present invention. I will explain.
　図１６（ａ）において、実施例3に示したように、画素電極４０及び層間絶縁膜２２上に、ｎ型のブロッキング層４７を形成した後、ブロッキング層４７上に、一般的なフォトリソグラフィ技術によって所定のレジストパターン７４を形成する。 In FIG. 16A, as shown in the third embodiment, an n-type blocking layer 47 is formed on the pixel electrode 40 and the interlayer insulating film 22, and then a general photolithography technique is formed on the blocking layer 47. Thus, a predetermined resist pattern 74 is formed.
　図１６（ｂ）において、レジストパターン７４をマスクに、一般的なエッチング技術によってブロッキング層４７をエッチングし、各画素電極４０上に所定のパターンのブロッキング層４７を形成する。この時、ブロッキング層４７は画素電極４０の上面のみを覆う形状とする。 In FIG. 16B, the blocking layer 47 is etched by a general etching technique using the resist pattern 74 as a mask to form the blocking layer 47 having a predetermined pattern on each pixel electrode 40. At this time, the blocking layer 47 has a shape that covers only the upper surface of the pixel electrode 40.
　図１７（ａ）において、ブロッキング層４７を形成した後、ブロッキング層４７上にプラズマＣＶＤやスパッタで、赤色の分光感度特性を有するα―Ｓｉ膜を１００ｎｍ～１ｕｍ堆積し、ｉ型の光電変換膜４１ａを形成する。この分光感度は、具体的には、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御することにより得ている。その後、実施の形態１等に示したｉ型の光電変換膜４１ａの製造方法が繰り返され、各画素４００において、対応する各画素電極４０の上に、ｉ型の光電変換膜４１ａ、４１ｂが画素毎に孤立して形成される。なお、各光電変換膜４１ａ、４１ｂは異なる分光感度を有するように、α－Ｓｉ１－ｘＣx：ｘの比率を変えて分光感度を制御している。この工程により、ｎ型ブロッキング層４７が、画素電極４０の上面を覆うように、各画素において光電変換膜４１と画素電極４０との間に介挿されることとなる。 In FIG. 17A, after the blocking layer 47 is formed, an α-Si film having a red spectral sensitivity characteristic is deposited on the blocking layer 47 by plasma CVD or sputtering to a thickness of 100 nm to 1 μm to form an i-type photoelectric conversion film. 41a is formed. Specifically, this spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si 1-x C x : x. Thereafter, the manufacturing method of the i-type photoelectric conversion film 41a shown in Embodiment 1 and the like is repeated. In each pixel 400, the i-type photoelectric conversion films 41a and 41b are formed on the corresponding pixel electrodes 40. Each is formed in isolation. Note that the spectral sensitivity is controlled by changing the ratio of α-Si 1-x C x : x so that the photoelectric conversion films 41a and 41b have different spectral sensitivities. By this step, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.
　また、各画素における光電変換膜４１が孤立して形成されることにより、画素境界部４３が形成される。 Further, the pixel boundary portion 43 is formed by forming the photoelectric conversion film 41 in each pixel in isolation.
　図１７（ｂ）において、隣接する光電変換膜４１の間を埋め込むようにＣＶＤ酸化膜よりなる絶縁膜４６を形成する。その結果、光電変換膜４１の下半分を絶縁膜４６が覆うこととなる。
この工程以降の工程の製造法は、本発明の実施の形態１と同じなので説明を省略する。
［変形例］
１．走査回路
　走査回路として、例えば、ＭＯＳ走査回路、ＣＣＤ等、任意の走査回路を用いても良い。
２．金属配線
　実施の形態では、金属配線の形状をすべての隣接する画素を通るというメッシュ状としてきたが、例えば、ストライプ状等他の配線形状を採っても良い。また、金属配線４５の材料は、銅、アルミニウムなどの他にＷ、Ｍｏ、Ｔｉ等も選択できる。
３．光電変換膜
　実施の形態では、画素毎の分光感度を異ならせるため、光電変換膜４１の分光感度を異ならせているが、本発明ではこれに限らない。例えば、画素毎に分光感度の異なるカラーフィルターを用いれば、光電変換膜の分光感度が全て同じであっても、画素毎の分光感度を異ならせることができる。このようにすれば、異なる色での画素であっても光電変換膜４１を共通のもので形成でき、工程を簡素化できる。
４．その他
　なお、本発明に係る固体撮像装置の構成などは、上記実施の形態に係る固体撮像装置１の構成に限定されるものではなく、本発明の効果を奏する範囲において、種々の変形および応用が可能である。そして、技術的思想を逸脱しない範囲において、上述の各工程で使用したプロセスを他の等価なプロセスに置換することが可能である。また、工程順を入れ替えることも、材料種を変更することも可能である。 In FIG. 17B, an insulating film 46 made of a CVD oxide film is formed so as to embed between adjacent photoelectric conversion films 41. As a result, the insulating film 46 covers the lower half of the photoelectric conversion film 41.
Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate | omitted.
[Modification]
1. Scanning circuit As the scanning circuit, for example, an arbitrary scanning circuit such as a MOS scanning circuit or a CCD may be used.
2. Metal wiring In the embodiment, the shape of the metal wiring has been a mesh shape that passes through all adjacent pixels, but other wiring shapes such as a stripe shape may be employed. The material of the metal wiring 45 can be selected from W, Mo, Ti, etc. in addition to copper, aluminum and the like.
3. Photoelectric Conversion Film In the embodiment, the spectral sensitivity of the photoelectric conversion film 41 is varied in order to vary the spectral sensitivity of each pixel. However, the present invention is not limited to this. For example, if color filters having different spectral sensitivities are used for each pixel, the spectral sensitivities for each pixel can be made different even if the spectral sensitivities of the photoelectric conversion films are all the same. In this way, even if the pixels have different colors, the photoelectric conversion film 41 can be formed in a common manner, and the process can be simplified.
4). Others The configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.
　例えば、画素の配置については、実施の形態で示したマトリクス状（行列状）の配列の他に、画素を４５°回転させ配列するといった構成を取ることができる。 For example, with respect to the arrangement of the pixels, in addition to the matrix (matrix) arrangement shown in the embodiment, a configuration in which the pixels are arranged by being rotated by 45 ° can be employed.
　本発明は、デジタルカメラ等に利用でき、撮像画像の画質の劣化が抑制された固体撮像装置を実現するのに有用である。 The present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which the degradation of the image quality of a captured image is suppressed.
１　固体撮像装置
５　半導体基板
１５　蓄積ダイオード
１６　フローティングディフュージョン
１００，２００，３００，４００　画素
９００　画素部 DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 5 Semiconductor substrate 15 Storage diode 16 Floating diffusion 100,200,300,400 Pixel 900 Pixel part

Claims (12)

  1. 　複数の画素がある固体撮像装置であって、
    　半導体基板と、
    　前記半導体基板上に形成された層間絶縁膜と、
    　前記層間絶縁膜上に、画素毎に孤立して形成された下部電極と、
    　複数の画素に亘って形成された透光性を有する上部電極と、
    　真性半導体材料からなり、画素毎に孤立して形成され、前記下部電極と前記上部電極とにそれぞれ挟まれた光電変換膜と、
    　不純物半導体材料からなり、前記光電変換膜上に、複数の画素に亘って形成され、隣接する前記光電変換膜の間に相当する部位が当該光電変換膜の間に入り込んで、前記光電変換膜の側面の一部または全部を覆っているブロッキング層と
    　を有する
    　ことを特徴とする固体撮像装置。     A solid-state imaging device having a plurality of pixels,
    A semiconductor substrate;
    An interlayer insulating film formed on the semiconductor substrate;
    On the interlayer insulating film, a lower electrode formed isolated for each pixel,
    A translucent upper electrode formed across a plurality of pixels;
    A photoelectric conversion film made of an intrinsic semiconductor material, formed isolated for each pixel, and sandwiched between the lower electrode and the upper electrode,
    It is made of an impurity semiconductor material, and is formed on the photoelectric conversion film over a plurality of pixels, and a portion corresponding to between the adjacent photoelectric conversion films enters between the photoelectric conversion films. And a blocking layer covering a part or all of the side surface.
  2. 　前記ブロッキング層がｐ型半導体材料からなる
    　ことを特徴とする請求項１に記載の固体撮像装置     The solid-state imaging device according to claim 1, wherein the blocking layer is made of a p-type semiconductor material.
  3. 　前記ブロッキング層の隣接する前記光電変換膜の間に相当する部位は、前記光電変換膜の側面の上半分を覆っており、
    　前記光電変換膜の側面の下半分は、絶縁膜が覆っており、
    　前記絶縁膜の前記層間絶縁膜からの高さは、前記下部電極の前記層間絶縁膜からの高さよりも高い
    　ことを特徴とする請求項１または２に記載の固体撮像装置。     The portion corresponding to the area between the photoelectric conversion films adjacent to the blocking layer covers the upper half of the side surface of the photoelectric conversion film,
    The lower half of the side surface of the photoelectric conversion film is covered with an insulating film,
    The solid-state imaging device according to claim 1, wherein a height of the insulating film from the interlayer insulating film is higher than a height of the lower electrode from the interlayer insulating film.
  4. 　不純物半導体材料からなる別のブロッキング層が、前記下部電極の上面を覆うように、各画素において前記光電変換膜と前記下部電極との間に介挿されている
    　ことを特徴とする請求項１から３のいずれかに記載の固体撮像装置。     The another blocking layer made of an impurity semiconductor material is interposed between the photoelectric conversion film and the lower electrode in each pixel so as to cover the upper surface of the lower electrode. The solid-state imaging device according to any one of 3.
  5. 　前記別のブロッキング層が、前記下部電極の側面にも回り込み、前記下部電極の側面の全部を覆うよう、形成されている
    　ことを特徴とする請求項４に記載の固体撮像装置。     The solid-state imaging device according to claim 4, wherein the another blocking layer is formed so as to go around the side surface of the lower electrode and cover the entire side surface of the lower electrode.
  6. 　前記別のブロッキング層はｎ型半導体材料からなる
    　ことを特徴とする請求項４または５に記載の固体撮像装置。     The solid-state imaging device according to claim 4, wherein the another blocking layer is made of an n-type semiconductor material.
  7. 　隣接する画素における光電変換膜では、変換対象となる光の波長域がそれぞれ異なる
    　ことを特徴とする請求項１から６のいずれかに記載の固体撮像装置。     The solid-state imaging device according to any one of claims 1 to 6, wherein the photoelectric conversion films in adjacent pixels have different wavelength ranges of light to be converted.
  8. 　前記上部電極上の少なくとも一部には、隣接する画素の間を通り、前記上部電極の材料よりも電気抵抗率が小さい材料からなる金属配線が積層されている
    　ことを特徴とする請求項１から７のいずれかに記載の固体撮像装置。     The metal wiring made of a material having an electric resistivity lower than that of the material of the upper electrode is laminated on at least a part of the upper electrode, passing between adjacent pixels. The solid-state imaging device according to any one of 7.
  9. 　複数の画素がある固体撮像装置の製造方法であって、
    　半導体基板上に、層間絶縁膜を形成する工程と、
    　前記層間絶縁膜上に、画素毎に孤立して下部電極を形成する工程と、
    　前記各下部電極の上に、画素毎に孤立して光電変換膜を形成する工程と、
    　前記光電変換膜上に、複数の画素に亘って形成され、隣接する前記光電変換膜の間に相当する部位が当該光電変換膜の間に入り込んで、前記光電変換膜の側面の一部または全部とを覆うよう、不純物半導体材料からなるブロッキング層を形成する工程と、
    　前記ブロッキング層の上に、複数の画素に亘って、透光性を有する上部電極を形成する工程と
    　を含む
    　ことを特徴とする固体撮像装置の製造方法。     A method of manufacturing a solid-state imaging device having a plurality of pixels,
    Forming an interlayer insulating film on the semiconductor substrate;
    On the interlayer insulating film, forming a lower electrode isolated for each pixel;
    Forming a photoelectric conversion film isolated on a pixel-by-pixel basis on each lower electrode;
    On the photoelectric conversion film, formed over a plurality of pixels, a portion corresponding to between the adjacent photoelectric conversion films enters between the photoelectric conversion films, part or all of the side surface of the photoelectric conversion film Forming a blocking layer made of an impurity semiconductor material so as to cover
    Forming a translucent upper electrode over a plurality of pixels on the blocking layer. A method for manufacturing a solid-state imaging device, comprising:
  10. 　前記ブロッキング層の隣接する前記光電変換膜の間に相当する部位は、前記光電変換膜の側面の上半分を覆うよう形成され、
    　前記下部電極を形成する工程の後であって、
    　前記ブロッキング層を形成する工程の前に、
    　前記光電変換膜の側面の下半分を覆うよう、絶縁膜を形成する工程
    　を含み、
    　前記絶縁膜の前記層間絶縁膜からの高さは、前記下部電極の前記層間絶縁膜からの高さよりも高い
    　ことを特徴とする請求項９に記載の固体撮像装置の製造方法。     The part corresponding to the gap between the photoelectric conversion films adjacent to the blocking layer is formed so as to cover the upper half of the side surface of the photoelectric conversion film,
    After the step of forming the lower electrode,
    Before the step of forming the blocking layer,
    Forming an insulating film so as to cover the lower half of the side surface of the photoelectric conversion film,
    The method for manufacturing a solid-state imaging device according to claim 9, wherein a height of the insulating film from the interlayer insulating film is higher than a height of the lower electrode from the interlayer insulating film.
  11. 　前記下部電極を形成する工程の後であって、
    　前記光電変換膜を形成する工程の前に、
    　前記下部電極の上面を覆うように、各画素において前記光電変換膜と前記下部電極との間に、不純物半導体材料からなる別のブロッキング層を介挿する工程
    　を含む
    　ことを特徴とする請求項９または１０に記載の固体撮像装置の製造方法。     After the step of forming the lower electrode,
    Before the step of forming the photoelectric conversion film,
    The method further comprises a step of interposing another blocking layer made of an impurity semiconductor material between the photoelectric conversion film and the lower electrode in each pixel so as to cover the upper surface of the lower electrode. Or a method for producing a solid-state imaging device according to 10;
  12. 　前記別のブロッキング層が、前記下部電極の側面にも回り込み、前記下部電極の側面の全部を覆うよう、形成される工程を含む
    　ことを特徴とする請求項１１に記載の固体撮像装置の製造方法。     The method of manufacturing a solid-state imaging device according to claim 11, further comprising a step of forming the another blocking layer so as to go around the side surface of the lower electrode and cover the entire side surface of the lower electrode. .
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