WO2012035702A1 - Solid-stage imaging device and manufacturing method therefor - Google Patents

Solid-stage imaging device and manufacturing method therefor Download PDF

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Publication number
WO2012035702A1
WO2012035702A1 PCT/JP2011/004614 JP2011004614W WO2012035702A1 WO 2012035702 A1 WO2012035702 A1 WO 2012035702A1 JP 2011004614 W JP2011004614 W JP 2011004614W WO 2012035702 A1 WO2012035702 A1 WO 2012035702A1
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Prior art keywords
insulating film
photoelectric conversion
pixel
imaging device
solid
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PCT/JP2011/004614
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French (fr)
Japanese (ja)
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光雄 安平
晴久 横山
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures

Definitions

  • the present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate, and more particularly to a technique for improving the element structure in order to equalize a bias voltage applied to the photoelectric conversion film.
  • This solid-state imaging device has a pixel region in which pixel units 400 are two-dimensionally arranged.
  • Signal charges generated by photoelectric conversion in the photoconductive film 404 are accumulated in the N + type source region 409 via the pixel electrode 405 and the extraction electrode 406.
  • a bias voltage is applied to the transparent electrode 402.
  • a read voltage is applied to the gate electrode 408, whereby signal charges are transferred from the N + -type source region 409 to the N ⁇ -type BCCD channel 410.
  • a transfer pulse is applied to the gate electrode 408, the signal charge is transferred through the N ⁇ -type BCCD channel 410 and taken out as a video signal.
  • a signal output path via a MOS transistor may be used instead of the N ⁇ -type BCCD channel 410.
  • the conventional stacked solid-state imaging device has a problem that the voltage drop is larger in the central area of the pixel area where the distance from the peripheral area of the pixel area is larger than in the peripheral area of the pixel area.
  • a transparent electrode 402 made of a material having a relatively high electrical resistivity, for example, ITO (Indium Tin Oxide) or ZnO, is provided on the photoconductive film 404 in a form extending over the entire pixel region, and is transparent.
  • a voltage is applied when a voltage is applied to the photoconductive film 404 via the electrode 402 from the outermost periphery of the pixel region.
  • the resistance is a value obtained by multiplying the electrical resistivity by the length of the resistance and dividing by the cross-sectional area of the resistance, so that the applied voltage is the distance of the current path from the periphery of the pixel area toward the center of the pixel area. As it increases, it descends gradually. For this reason, the voltage drop is larger in the central area of the pixel area than in the peripheral area of the pixel area.
  • the amount of charge generated in the photoconductive film 404 collects on the pixel electrode 405, and the image quality deteriorates.
  • the difference in voltage drop for each pixel region is large, unevenness in the amount of charge collected on the pixel electrode 405 increases, and the deterioration of image quality becomes remarkable.
  • the present invention has been made to solve the above problem, and an object thereof is to provide a solid-state imaging device capable of suppressing a voltage drop at the center of a pixel region and a method for manufacturing the same.
  • a solid-state imaging device is a solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged, and is formed on a semiconductor substrate and the semiconductor substrate.
  • the wiring is laminated.
  • a metal wiring made of a material having a lower electrical resistivity than the material constituting the upper electrode is laminated on at least a part of the upper electrode in the pixel region.
  • the resistance of the portion where the metal wiring is laminated becomes a combined resistance in a state where the upper electrode and the metal wiring are connected in parallel, and this combined resistance is smaller than the resistance of only the upper electrode. For this reason, the voltage drop is reduced at the locations where the metal wirings are laminated, and the potentials are substantially the same.
  • the difference in voltage drop between the peripheral portion of the pixel region and the central portion of the pixel region is smaller than that in the conventional example, that is, the central portion of the pixel region.
  • the voltage drop at can be suppressed.
  • the metal wiring is stacked on the pixel boundary between adjacent pixels, the incident light to the photoelectric conversion film is not blocked.
  • the manufacturing method of the present invention it is possible to manufacture a solid-state imaging device that can suppress a voltage drop at the center of the pixel region.
  • FIG. 1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a top view for 4 pixels in the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG.
  • FIG. 9 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 8. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 3 of this invention.
  • FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10.
  • FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10. It is a top view which shows typically the metal wiring of the solid-state imaging device shown in FIG. It is sectional drawing of the conventional solid-state imaging device.
  • a plurality of pixel units 100 are arranged in a two-dimensional arrangement, for example, a matrix (matrix), thereby forming a pixel region 61.
  • the pixel region 61 includes a pixel region central portion 65 and a pixel region peripheral portion 66.
  • a pulse generation circuit 62, a vertical shift register 63, and a horizontal shift register 64 are formed so as to surround the pixel region 61.
  • the vertical shift register 63 and the horizontal shift register 64 sequentially output drive pulses to each pixel unit 100 in response to the application of the timing pulse from the pulse generation circuit 62.
  • the pixel unit 100 is partitioned by a pixel boundary 43.
  • the pixel unit 100 includes a reset gate 10, an amplification transistor 11, a charge storage region 15 of an N-type impurity diffusion layer, a floating diffusion 16 of an N-type impurity diffusion layer, and a reset transistor drain 17 of an N-type impurity diffusion layer.
  • a transfer gate 18 and contacts 31 to 34 are provided.
  • FIG. 3 is a cross-sectional view of the pixel portion 100 of the solid-state imaging device 1 shown in FIG.
  • an STI Shallow Trench Isolation
  • the pixel unit 100 includes a channel stopper 13, a charge storage region 15, a floating diffusion 16, and a reset transistor drain 17.
  • a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked.
  • a reset gate 10 and an amplification transistor gate 19 are sequentially stacked.
  • a transfer gate 18 and an amplification transistor gate 19 are sequentially stacked.
  • a connection electrode 23 is formed within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.
  • Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20.
  • wirings 24 and 25 for example, formed of Al or Cu
  • connection electrodes 26 is formed.
  • the interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.
  • the pixel electrode 40 is formed on the interlayer insulating film 22 so as to be partitioned for each pixel.
  • a photoelectric conversion film 41 is formed on the pixel electrode 40 by, for example, an ⁇ -Si film, an inorganic photoconductive film, or the like.
  • the photoelectric conversion film 41 is separated at the pixel boundary 43, and the pixel boundary 43 is formed such that an insulating film 44 is interposed between the separated photoelectric conversion films 41.
  • the photoelectric conversion film 41 extends over the entire pixel region 61, and a transparent electrode 42 (for example, formed of ITO or ZnO) is formed on the photoelectric conversion film 41 and the insulating film 44.
  • a metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43.
  • the metal wiring 45 is made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42. Since the insulating film 44 is provided at the pixel boundary portion 43 and the upper surface of the insulating film 44 is not a light receiving portion, the metal wiring 45 disposed on the insulating film 44 does not reduce the aperture ratio. . Therefore, the maximum width of the metal wiring 45 is the same as that of the insulating film 44. Further, the width of the metal wiring 45 may be reduced as long as the reduction degree of the voltage drop at the pixel region central portion 65 in FIG.
  • the metal wiring 45 has a mesh shape that passes between all adjacent pixels in the pixel region 61. Furthermore, the metal wiring 45 is formed so as to surround the pixel region 61. The metal wiring 45 extends from the pixel region central portion 65 toward the pixel region peripheral portion 66, and the metal wiring 45 is connected to the pixel region. The central portion 65 and the pixel region peripheral portion 66 are connected.
  • the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside. .
  • the reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17. 4). Effect Since the metal wiring 45 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the transparent electrode 42 and the metal wiring 45 are combined. The resistance becomes smaller than the resistance of only the transparent electrode 42. Therefore, in the conventional configuration, the voltage drop at the pixel region central portion 65 that has become large due to the resistance of the transparent electrode 42 is reduced, and the voltage drop at the pixel region central portion 65 can be suppressed.
  • the metal wiring 45 is laminated from the pixel region central portion 65 to the pixel region peripheral portion 66, shading can be reduced. Further, since the metal wiring 45 is disposed between adjacent pixels, that is, on the pixel boundary portion 43, the aperture ratio does not decrease.
  • the photoelectric conversion film 41 is electrically separated for each pixel by the insulating film 44. Therefore, even if the film thickness of the photoelectric conversion film 41 is reduced, good characteristics can be obtained with the spectral sensitivity, the afterimage, and the inter-pixel leakage, which are the original characteristics of the photoelectric conversion film 41. If the photoelectric conversion film 41 is not separated for each pixel, the CR time constant between the pixels is required to be sufficiently larger than the accumulation time ⁇ , and the dark conductivity of the photoelectric conversion film 41 needs to be increased. In order to obtain a large dark conductivity without impairing the photoconductivity, it is necessary to select a material having a large band gap as a material of the photoelectric conversion film 41 and reduce carriers in the dark.
  • the photoelectric conversion film 41 needs to be electrically separated for each pixel by the insulating film 44.
  • an STI 12 for separating transistors and diffusion layer elements is formed on a semiconductor substrate 5.
  • the semiconductor substrate 5 is dry-etched to form, for example, a trench having a depth of 200 nm to 400 nm serving as an isolation region.
  • sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 ⁇ 10 13.
  • B ions are implanted at cm ⁇ 2 to 3 ⁇ 10 13 cm ⁇ 2 to form a channel stopper 13 for the P + layer.
  • the gate oxide film 14 which becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed, for example, by 5 to 10 nm by thermal oxidation or plasma oxidation.
  • a Poly-Si film is deposited by, for example, 100 nm to 200 nm by thermal CVD or plasma oxidation, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19, and the reset gate 10 made of the Poly-Si film are formed.
  • P or As is ion-implanted into the P-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 ⁇ 10 14 cm ⁇ 2 to 2 ⁇ 10 15 cm ⁇ 2 , so that the charge accumulation region 15 or the floating region is floated.
  • the N-type impurity layers of the diffusion 16 and the reset transistor drain 17 are simultaneously formed.
  • a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film, and the electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is established. Connected.
  • An interlayer insulating film 20 made of a CVD oxide film is formed, for example, to 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique. A W (tungsten) plug is embedded in the contact opening, a W plug connection electrode 23 is formed, and electrical connection to the charge storage region 15 and the reset transistor drain 17 is formed. For example, a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed. Here, a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.
  • a pixel electrode 40 having a thickness of 100 nm to 300 nm made of aluminum (Al), tungsten (W), molybdenum (Mo) or the like partitioned for each pixel is formed.
  • Al aluminum
  • W tungsten
  • Mo molybdenum
  • an ⁇ -Si film, an inorganic photoconductive film, or the like having a spectral sensitivity characteristic corresponding to the imaging purpose is deposited on the pixel electrode 40 by plasma CVD, sputtering, and a coating apparatus, and photoelectric conversion is performed.
  • a film 41 is formed.
  • the photoelectric conversion film 41 at the pixel boundary 43 is etched by a general photolithography technique and etching technique to form a groove 48 of the photoelectric conversion film.
  • the groove 48 of the photoelectric conversion film corresponding to the pixel boundary 43 is embedded with an insulating film 44 formed of a CVD oxide film. Further, on the photoelectric conversion film 41 and the insulating film 44, a transparent electrode 42 made of ITO or ZnO and having a film thickness of, for example, several tens nm to several hundreds nm is formed by sputtering or CVD.
  • a metal wiring 45 such as Al, W, or Mo having a thickness of 100 nm to 300 nm is deposited on the pixel portion 100 by sputtering or CVD.
  • the photoelectric conversion film 41 is etched by a general photolithography technique and an etching technique, and a mesh-like metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43.
  • FIG. 8 is a cross-sectional view of the pixel unit 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. Since the configuration other than the following is the same as that of the pixel unit 100, the description thereof is omitted.
  • An insulating film 47 is embedded in the lower part of the groove of the photoelectric conversion film 41.
  • a transparent electrode 42 is formed on the photoelectric conversion film 41 and the insulating film 47.
  • the upper surface of the insulating film 47 is at a position lower than the upper surface of the photoelectric conversion film 41.
  • the transparent electrode 42 is attached to the inner wall of the groove of the photoelectric conversion film 41. In other words, the groove is not completely filled with the transparent electrode 42, and the concave portion surrounded by the surface of the transparent electrode 42 remains in the groove.
  • a metal wiring 145 is embedded in the concave portion of the transparent electrode 42.
  • the portion where the metal wiring 145 is embedded also exists on the transparent electrode 42.
  • the depth of the metal wiring 145 is such that the lowermost surface of the metal wiring 145 is below the upper surface of the photoelectric conversion film 41 and the transparent electrode 42 and the insulating film 47 can be formed below the lowermost surface of the metal wiring 145.
  • the metal wiring 145 is made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42. 2. Effect Since the metal wiring 145 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the pixel region central portion 65 is the same as in the first embodiment. The voltage drop at can be suppressed. Furthermore, since the cross-sectional area of the metal wiring 145 is larger than the cross-sectional area of the metal wiring 45 in the first embodiment, the voltage drop at the pixel region central portion 65 can be further reduced.
  • the metal wiring 145 is embedded in the concave shape portion where the groove of the transparent electrode 42 at the pixel boundary portion 43 is not completely filled. Furthermore, since the lowermost surface of the metal wiring 145 is formed below the upper surface of the photoelectric conversion film 41, the oblique incident light from the adjacent pixel can be shielded, and crosstalk due to the oblique incident light from the adjacent pixel is also caused. Can be suppressed. Further, since the metal wiring 145 is formed so that the transparent electrode 42 and the insulating film 47 exist below the lowermost surface thereof, the transparent electrode 42 can be configured to spread over the entire pixel region 61, and the electrode There is no short circuit. 3. Manufacturing Method A manufacturing method of the pixel unit 200 according to the second embodiment of the present invention will be described with reference to FIG. 9, focusing on differences from the first embodiment of the present invention.
  • an insulating film 47 made of a CVD oxide film is formed in the groove of the photoelectric conversion film 41 separated at the pixel boundary 43.
  • the insulating film 47 is formed thicker than the pixel electrode 40 (for example, 100 nm to 300 nm).
  • a transparent electrode 42 made of ITO or ZnO by sputtering or CVD is formed on the photoelectric conversion film 41 and along the side wall of the photoelectric conversion film 41 in the groove on the insulating film 47 at the pixel boundary 43 by, for example, several tens of nm. It is formed with a film thickness of ⁇ 100 nm.
  • FIG. 9B a metal such as Al, W, or Mo is deposited on the transparent electrode 42 with a film thickness of, for example, 100 nm to 300 nm based on sputtering or CVD.
  • a metal is etched by a general photolithography technique and an etching technique, a metal film is formed in the groove, and a mesh-like metal wiring 145 is formed on the transparent electrode 42 at the pixel boundary 43.
  • FIG. 10 is a cross-sectional view of the pixel unit 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention.
  • the photoelectric conversion film 41 is partitioned for each pixel by a pixel boundary 43.
  • An insulating film 28 is formed on the pixel boundary portion 43.
  • a sidewall pixel electrode 39 made of the same material as the pixel electrode 40 is formed on the sidewall of the insulating film 28, leaving the upper portion of the insulating film 28.
  • the side wall pixel electrode 39 made of the same material as the pixel electrode 40 has a light shielding capability and can shield oblique incident light from the adjacent pixel, so that crosstalk due to the oblique incident light from the adjacent pixel can be suppressed.
  • an insulating film 28 made of an oxide film is deposited, for example, by 100 nm to 1 ⁇ m based on the CVD method, and the pixel boundary is formed by a general photolithography technique and an etching technique.
  • An insulating film 28 having a predetermined shape having a separation width equivalent to that of the portion 43 is formed.
  • a metal wiring made of Al, W, Mo, or the like is provided on the side wall of the insulating film 28 at the pixel boundary 43 and at a place excluding the pixel boundary 43.
  • a metal wiring made of Al, W, Mo, or the like is provided on the side wall of the insulating film 28 at the pixel boundary 43 and at a place excluding the pixel boundary 43.
  • 100 nm to 300 nm is deposited, and pixel electrodes 40 and sidewall pixel electrodes 39 having a predetermined shape are formed by a general photolithography technique and etching technique.
  • the area of the pixel electrode 40 is determined by the width of the insulating film 28 at the pixel boundary 43. If the separation width between pixels is 10% to 20% of the pixel size, the aperture ratio is estimated to be 64% to 81%.
  • the pixel electrode 40 and the sidewall pixel electrode 39 have spectral sensitivity characteristics corresponding to the imaging purpose by plasma CVD, sputtering, and coating apparatus.
  • An ⁇ -Si film, an inorganic photoelectric conversion film, and an organic photoelectric conversion film are deposited to a thickness of, for example, 100 nm to 1 ⁇ m to form the photoelectric conversion film 41.
  • a transparent electrode 42 made of ITO or ZnO is deposited on the photoelectric conversion film 41 and the insulating film 28 at the pixel boundary 43 by sputtering or CVD, for example, several tens nm to several hundreds nm. Form. Further, a metal wiring 45 is formed on the transparent electrode 42 and above the insulating film 28. [Other matters] 1. Shape of Metal Wiring In the embodiment according to the present invention, the shape of the metal wiring 45 is a mesh shape shown in FIG. 13A in which it passes between all adjacent pixel portions 100. In this case, since the cross-sectional area of the metal wiring 45 increases, the voltage drop at the pixel region central portion 65 is effectively suppressed.
  • metal wiring is formed in a stripe shape.
  • the plurality of pixel portions 100 are formed so as to be surrounded by the metal wiring 45.
  • the mesh-like metal wiring 45 is formed only around the pixel portion 100 in the pixel region central portion 65, and at least a part of the other metal wiring 45 is transferred to the pixel region peripheral portion 66. It is formed in a shape that connects. *
  • the metal wiring 45 may have a shape passing between some adjacent pixels, or only in at least a part of the pixel region 61. Even if the metal wiring 45 is formed, the same effect as in FIG. 2.
  • the configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.
  • a configuration in which the pixels are arranged by being rotated by 45 ° can be employed.
  • an array such as a primary color Bayer array or a complementary color checkered array can be selected.
  • the material of the metal wiring 45 can be selected from W, Mo, Ti and the like in addition to copper, aluminum and the like.
  • the present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which deterioration of image quality is suppressed.
  • Solid-state imaging device 5
  • Semiconductor substrate 15
  • Charge storage area 16
  • Pixel electrode 41
  • Photoelectric conversion film 42
  • Transparent electrode 43
  • Insulating film 45
  • Metal wiring 100 Pixel part 200 Pixel part 300 Pixel part 400 Pixel part

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Abstract

A solid-state imaging device that has a pixel region comprising a plurality of pixels arranged two-dimensionally. In said solid-state imaging device, a semiconductor substrate and an interlayer insulation film are layered in sequence, and a photoelectric conversion film sandwiched between a bottom electrode and a light-transmitting top electrode is formed on top of the interlayer insulation film. The top electrode covers the entire top of the photoelectric conversion film, and metal wiring is laminated onto at least part of the top electrode so as to pass between adjacent pixels. Said metal wiring comprises a material that has a lower electrical resistivity than the top electrode.

Description

固体撮像装置及びその製造方法Solid-state imaging device and manufacturing method thereof
　本発明は、光電変換膜が半導体基板上に積層された積層型の固体撮像装置に関し、特に、光電変換膜にかかるバイアス電圧の均一化のために、素子構造の改良を図る技術に関する。 The present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate, and more particularly to a technique for improving the element structure in order to equalize a bias voltage applied to the photoelectric conversion film.
　従来の積層型固体撮像装置として、例えば図１４に示すように、Ｐ型の半導体基板４０１と、Ｎ＋型ソース領域４０９と、ゲート電極４０８と、Ｎ－型ＢＣＣＤチャネル４１０と、透明電極４０２と、分離絶縁膜４０３と、光導電膜４０４と、画素電極４０５と、引き出し電極４０６と、層間絶縁膜４０７とを備えたものがある。この固体撮像装置は、画素部４００が二次元配列された画素領域を有する。 As a conventional stacked solid-state imaging device, for example, as shown in FIG. 14, a P-type semiconductor substrate 401, an N + -type source region 409, a gate electrode 408, an N − -type BCCD channel 410, a transparent electrode 402, In some cases, an insulating film 403, a photoconductive film 404, a pixel electrode 405, an extraction electrode 406, and an interlayer insulating film 407 are provided. This solid-state imaging device has a pixel region in which pixel units 400 are two-dimensionally arranged.
　光導電膜４０４で光電変換により発生した信号電荷は、画素電極４０５、及び引き出し電極４０６を介して、Ｎ＋型ソース領域４０９に蓄積される。透明電極４０２には、バイアス電圧が印加されている。そして、所定の蓄積時間後に、読出し電圧がゲート電極４０８に印加されることにより、Ｎ＋型ソース領域４０９から、Ｎ－型ＢＣＣＤチャネル４１０に信号電荷が転送される。次に、転送パルスがゲート電極４０８に印加されることにより、Ｎ－型ＢＣＣＤチャネル４１０を介して信号電荷が転送され、外部に映像信号として取り出される。なお、目的に応じて、Ｎ－型ＢＣＣＤチャネル４１０の代わりにＭＯＳトランジスタを介した信号出力経路を用いることもできる。 Signal charges generated by photoelectric conversion in the photoconductive film 404 are accumulated in the N + type source region 409 via the pixel electrode 405 and the extraction electrode 406. A bias voltage is applied to the transparent electrode 402. Then, after a predetermined accumulation time, a read voltage is applied to the gate electrode 408, whereby signal charges are transferred from the N + -type source region 409 to the N − -type BCCD channel 410. Next, when a transfer pulse is applied to the gate electrode 408, the signal charge is transferred through the N − -type BCCD channel 410 and taken out as a video signal. Depending on the purpose, a signal output path via a MOS transistor may be used instead of the N − -type BCCD channel 410.
特開昭６１-１４２７６７号公報JP 61-142767 A
　しかしながら、上記従来の積層型固体撮像装置では、画素領域周辺部からの距離が大きい画素領域中央部において、画素領域周辺部よりも電圧降下が大きくなるという課題がある。これは、電気抵抗率が比較的大きい材料、例えばＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）やＺｎＯで構成される透明電極４０２が、画素領域全体に拡がった形で光導電膜４０４上に設けられ、かつ、透明電極４０２を介して光導電膜４０４へ電圧が印加される際の電圧印加が、画素領域の最外周部から行われることにより生ずる。抵抗は、電気抵抗率に抵抗の長さを乗じ、さらに抵抗の断面積で除した値であるので、印加された電圧は、画素領域周辺部から画素領域中央部へ向かうにつれ、電流経路の距離の増加に伴い、徐々に降下する。そのため、画素領域周辺部と比べ、画素領域中央部において、電圧降下が大きくなる。 However, the conventional stacked solid-state imaging device has a problem that the voltage drop is larger in the central area of the pixel area where the distance from the peripheral area of the pixel area is larger than in the peripheral area of the pixel area. This is because a transparent electrode 402 made of a material having a relatively high electrical resistivity, for example, ITO (Indium Tin Oxide) or ZnO, is provided on the photoconductive film 404 in a form extending over the entire pixel region, and is transparent. A voltage is applied when a voltage is applied to the photoconductive film 404 via the electrode 402 from the outermost periphery of the pixel region. The resistance is a value obtained by multiplying the electrical resistivity by the length of the resistance and dividing by the cross-sectional area of the resistance, so that the applied voltage is the distance of the current path from the periphery of the pixel area toward the center of the pixel area. As it increases, it descends gradually. For this reason, the voltage drop is larger in the central area of the pixel area than in the peripheral area of the pixel area.
　画素領域の場所により電圧降下が異なると、光導電膜４０４で発生した電荷が、画素電極４０５へ集まる量にむらができ、画質が劣化してしまう。また、画素領域ごとの電圧降下の差が大きいと、電荷の画素電極４０５へ集まる量のむらが大きくなり、画質の劣化が顕著なものとなってしまう。 If the voltage drop differs depending on the location of the pixel region, the amount of charge generated in the photoconductive film 404 collects on the pixel electrode 405, and the image quality deteriorates. In addition, when the difference in voltage drop for each pixel region is large, unevenness in the amount of charge collected on the pixel electrode 405 increases, and the deterioration of image quality becomes remarkable.
　本発明は、上記問題の解決を図るべくなされたものであって、画素領域中央部での電圧降下を抑制することができる固体撮像装置とその製造方法を提供することを目的とする。 The present invention has been made to solve the above problem, and an object thereof is to provide a solid-state imaging device capable of suppressing a voltage drop at the center of a pixel region and a method for manufacturing the same.
　上記目的を達成するために、本発明に係る固体撮像装置は、複数の画素が二次元配置されてなる画素領域を有する固体撮像装置であって、半導体基板と、前記半導体基板上に形成された層間絶縁膜と、前記層間絶縁膜上に形成された下部電極と、透光性を有する上部電極と、前記下部電極と前記上部電極とに挟まれた光電変換膜とを有し、前記上部電極は画素領域全体における光電変換膜上に拡がっており、前記上部電極における少なくとも一部には、隣接する画素の間を通り、前記上部電極を構成する材料よりも電気抵抗率が小さい材料からなる金属配線が積層されていることを特徴とする。 In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged, and is formed on a semiconductor substrate and the semiconductor substrate. An interlayer insulating film; a lower electrode formed on the interlayer insulating film; a translucent upper electrode; and a photoelectric conversion film sandwiched between the lower electrode and the upper electrode. Is spread over the photoelectric conversion film in the entire pixel region, and at least a part of the upper electrode passes between adjacent pixels and is made of a material having a lower electrical resistivity than the material constituting the upper electrode. The wiring is laminated.
　本発明に係る固体撮像装置では、画素領域における上部電極上の少なくとも一部に、上部電極を構成する材料より電気抵抗率の小さい材料からなる金属配線が積層されている。金属配線が積層されている箇所の抵抗は、上部電極と金属配線とが並列接続された状態で合成抵抗になり、この合成抵抗は上部電極のみの抵抗よりも小さくなる。そのため、金属配線が積層されている箇所では、電圧降下が小さくなり、略同一電位となる。 In the solid-state imaging device according to the present invention, a metal wiring made of a material having a lower electrical resistivity than the material constituting the upper electrode is laminated on at least a part of the upper electrode in the pixel region. The resistance of the portion where the metal wiring is laminated becomes a combined resistance in a state where the upper electrode and the metal wiring are connected in parallel, and this combined resistance is smaller than the resistance of only the upper electrode. For this reason, the voltage drop is reduced at the locations where the metal wirings are laminated, and the potentials are substantially the same.
　また、上部電極上の少なくとも一部に、略同一電位となる部分があるため、画素領域周辺部と画素領域中央部とにおける、電圧降下の差は従来例より小さくなる、すなわち、画素領域中央部における電圧降下を抑制することができる。 In addition, since at least a part of the upper electrode has a portion having substantially the same potential, the difference in voltage drop between the peripheral portion of the pixel region and the central portion of the pixel region is smaller than that in the conventional example, that is, the central portion of the pixel region. The voltage drop at can be suppressed.
　このように、上部電極における少なくとも一部に、金属配線が積層されることで、当該部分での全体としての低抵抗化を図ることができ、画素領域中央部での電圧降下が抑制できる。また、金属配線は隣接する画素間の画素境界部上に積層されているため、光電変換膜への入射光を遮ることがない。 As described above, by laminating the metal wiring on at least a part of the upper electrode, it is possible to reduce the resistance as a whole in the part, and it is possible to suppress the voltage drop in the central part of the pixel region. Further, since the metal wiring is stacked on the pixel boundary between adjacent pixels, the incident light to the photoelectric conversion film is not blocked.
　本発明の製造方法によると、画素領域中央部での電圧降下が抑制できる固体撮像装置を製造することができる。 According to the manufacturing method of the present invention, it is possible to manufacture a solid-state imaging device that can suppress a voltage drop at the center of the pixel region.
本発明の実施の形態１に係る固体撮像装置の全体構成を模式的に示すブロック図である。1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. 図１に示した固体撮像装置における４画素分の平面図である。It is a top view for 4 pixels in the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 図１に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. 本発明の実施の形態２に係る固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device concerning Embodiment 2 of this invention. 図８に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 9 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 8. 本発明の実施の形態３に係る固体撮像装置の画素部の断面図である。It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 3 of this invention. 図１０に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10. 図１０に示した固体撮像装置の画素部の製造工程の一部を模式的に示す工程断面図である。FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10. 図１０に示した固体撮像装置の金属配線を模式的に示す平面図である。It is a top view which shows typically the metal wiring of the solid-state imaging device shown in FIG. 従来の固体撮像装置の断面図である。It is sectional drawing of the conventional solid-state imaging device.
[実施の形態１] 
１．固体撮像装置１の全体構成
　実施の形態１に係る固体撮像装置１の全体構成について、図１を用い説明する。 [Embodiment 1]
1. Overall Configuration of Solid-State Imaging Device 1 The overall configuration of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG.
　図１に示すように、実施の形態１に係る固体撮像装置１では、複数の画素部１００が、二次元配置、例えばマトリクス状（行列状）に配列され、画素領域６１となっている。画素領域６１は、画素領域中央部６５と画素領域周辺部６６とを備える。また、固体撮像装置１には、パルス発生回路６２と、垂直シフトレジスタ６３と、水平シフトレジスタ６４とが、画素領域６１を囲むように形成されている。垂直シフトレジスタ６３および水平シフトレジスタ６４は、パルス発生回路６２からのタイミングパルスの印加に呼応して、各画素部１００に対して、順次、駆動パルスを出力する。
２．画素部１００の構成
　図２は、図１に示した固体撮像装置１における４画素分の平面図である。各画素部１００同士は、画素境界部４３で区画されている。画素部１００には、リセットゲート１０と、増幅トランジスタ１１と、Ｎ型不純物拡散層の電荷蓄積領域１５と、Ｎ型不純物拡散層のフローティングディフュージョン１６と、Ｎ型不純物拡散層のリセットトランジスタドレイン１７と、転送ゲート１８と、コンタクト３１～３４とが備えられている。 As shown in FIG. 1, in the solid-state imaging device 1 according to the first embodiment, a plurality of pixel units 100 are arranged in a two-dimensional arrangement, for example, a matrix (matrix), thereby forming a pixel region 61. The pixel region 61 includes a pixel region central portion 65 and a pixel region peripheral portion 66. In the solid-state imaging device 1, a pulse generation circuit 62, a vertical shift register 63, and a horizontal shift register 64 are formed so as to surround the pixel region 61. The vertical shift register 63 and the horizontal shift register 64 sequentially output drive pulses to each pixel unit 100 in response to the application of the timing pulse from the pulse generation circuit 62.
2. Configuration of Pixel Unit 100 FIG. 2 is a plan view of four pixels in the solid-state imaging device 1 shown in FIG. Each pixel unit 100 is partitioned by a pixel boundary 43. The pixel unit 100 includes a reset gate 10, an amplification transistor 11, a charge storage region 15 of an N-type impurity diffusion layer, a floating diffusion 16 of an N-type impurity diffusion layer, and a reset transistor drain 17 of an N-type impurity diffusion layer. A transfer gate 18 and contacts 31 to 34 are provided.
　図３は、図１に示した固体撮像装置１の画素部１００の断面図であり、図２のＡ―Ａ’断面を示している。図３に示すように、Ｐ型ウェルが形成された半導体基板５内には、ＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｒａｔｉｏｎ）１２が形成されている。画素部１００は、チャネルストッパー１３と、電荷蓄積領域１５と、フローティングディフュージョン１６と、リセットトランジスタドレイン１７とを備えている。 FIG. 3 is a cross-sectional view of the pixel portion 100 of the solid-state imaging device 1 shown in FIG. As shown in FIG. 3, an STI (Shallow Trench Isolation) 12 is formed in the semiconductor substrate 5 on which the P-type well is formed. The pixel unit 100 includes a channel stopper 13, a charge storage region 15, a floating diffusion 16, and a reset transistor drain 17.
　半導体基板５の上には、ゲート酸化膜１４と、層間絶縁膜２０とが順に積層されており、層間絶縁膜２０内には、リセットゲート１０と、転送ゲート１８と、増幅トランジスタゲート１９と、接続電極２３とが形成されている。 On the semiconductor substrate 5, a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked. Within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.
　層間絶縁膜２０の上には、層間絶縁膜２１，２２が順に積層されており、層間絶縁膜２１，２２内には、配線２４，２５（例えば、ＡｌやＣｕで形成される）と接続電極２６とが形成されている。層間絶縁膜２０～２２は、例えば、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いてなる酸化膜によって形成される。 Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20. In the interlayer insulating films 21 and 22, wirings 24 and 25 (for example, formed of Al or Cu) and connection electrodes 26 is formed. The interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.
　層間絶縁膜２２の上には、画素電極４０が、画素毎に区画されるよう形成されている。画素電極４０の上には、光電変換膜４１が、例えば、α―Ｓｉ膜や無機光導電膜等により形成されている。光電変換膜４１は、画素境界部４３において分離されており、画素境界部４３では、分離された光電変換膜４１間に、絶縁膜４４が介挿されるよう形成されている。光電変換膜４１は、画素領域６１全体に拡がり、光電変換膜４１及び絶縁膜４４上には、透明電極４２（例えば、ＩＴＯやＺｎＯにより形成される）が形成されている。画素境界部４３における透明電極４２上に、金属配線４５が形成されている。金属配線４５は、透明電極４２を構成する材料より電気抵抗率の小さい材料からなる。なお、絶縁膜４４は画素境界部４３に設けられており、絶縁膜４４の上面は受光部では無いため、絶縁膜４４の上に配置された金属配線４５が、開口率を低下させることはない。そのため、金属配線４５の最大幅は絶縁膜４４と同じ幅である。また、金属配線４５の幅は、図１における画素領域中央部６５での電圧降下の減少の程度が意味を持つ範囲内であれば、小さくしてもよい。金属配線４５の形状は、画素領域６１におけるすべての隣接する画素の間を通るメッシュ状となっている。さらに、金属配線４５が画素領域６１を囲むように形成される、と言うことは、金属配線４５は画素領域中央部６５から画素領域周辺部６６に向かって伸びており、金属配線４５は画素領域中央部６５と画素領域周辺部６６とを繋ぐことになる。 The pixel electrode 40 is formed on the interlayer insulating film 22 so as to be partitioned for each pixel. A photoelectric conversion film 41 is formed on the pixel electrode 40 by, for example, an α-Si film, an inorganic photoconductive film, or the like. The photoelectric conversion film 41 is separated at the pixel boundary 43, and the pixel boundary 43 is formed such that an insulating film 44 is interposed between the separated photoelectric conversion films 41. The photoelectric conversion film 41 extends over the entire pixel region 61, and a transparent electrode 42 (for example, formed of ITO or ZnO) is formed on the photoelectric conversion film 41 and the insulating film 44. A metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43. The metal wiring 45 is made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42. Since the insulating film 44 is provided at the pixel boundary portion 43 and the upper surface of the insulating film 44 is not a light receiving portion, the metal wiring 45 disposed on the insulating film 44 does not reduce the aperture ratio. . Therefore, the maximum width of the metal wiring 45 is the same as that of the insulating film 44. Further, the width of the metal wiring 45 may be reduced as long as the reduction degree of the voltage drop at the pixel region central portion 65 in FIG. The metal wiring 45 has a mesh shape that passes between all adjacent pixels in the pixel region 61. Furthermore, the metal wiring 45 is formed so as to surround the pixel region 61. The metal wiring 45 extends from the pixel region central portion 65 toward the pixel region peripheral portion 66, and the metal wiring 45 is connected to the pixel region. The central portion 65 and the pixel region peripheral portion 66 are connected.
　透明電極４２及び金属配線４５上には、平坦化膜５０，５２と、カラーフィルター５１と、マイクロレンズ５３とが形成されている。
３．固体撮像装置１の駆動
　カラーフィルター５１を通して入射した光は、光電変換膜４１で電荷に変換される。透明電極４２にはバイアス電圧が印加されており、発生した電荷は、透明電極４２と画素電極４０との間のバイアス電圧により、画素電極４０に引き寄せられて、画素電極４０から接続電極２３，２６を通って、電荷蓄積領域１５に一時蓄積される。次に、電荷は、電荷蓄積領域１５から、転送ゲート１８の作用により、フローティングディフュージョン１６に蓄積される。このとき、信号電荷量に応じてフローティングディフュージョン１６の電位が変動し、この変動量が増幅トランジスタゲート１９を介して、増幅トランジスタ１１に伝わり、さらに増幅トランジスタ１１で増幅され、外部に信号として取り出される。 Flattening films 50 and 52, a color filter 51, and a microlens 53 are formed on the transparent electrode 42 and the metal wiring 45.
3. Driving of Solid-State Imaging Device 1 Light incident through the color filter 51 is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 42, and the generated charges are attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 42 and the pixel electrode 40, and are connected from the pixel electrode 40 to the connection electrodes 23 and 26. And temporarily stored in the charge storage region 15. Next, charge is accumulated in the floating diffusion 16 from the charge accumulation region 15 by the action of the transfer gate 18. At this time, the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside. .
　リセットトランジスタドレイン１７は、電源電圧端子Ｖｄｄに電気的に接続されている。そのため、リセットトランジスタドレイン１７の電位は常にＶｄｄである。リセットゲート１０をＯＮにすることにより、フローティングディフュージョン１６の電位は、リセットトランジスタドレイン１７の電位Ｖｄｄにリセットされる。
４．効果
　画素領域６１における透明電極４２上には、透明電極４２を構成する材料より電気抵抗率の小さい材料からなる金属配線４５が積層されているため、透明電極４２と金属配線４５とをまとめた合成抵抗が、透明電極４２のみの抵抗よりも小さくなる。よって、従来の構成では、透明電極４２の抵抗が原因で大きくなっていた画素領域中央部６５での電圧降下が小さくなり、画素領域中央部６５での電圧降下を抑制することができる。これにより、画素領域６１の場所ごとに電圧降下の大きさが異なった場合に起きる、画質の劣化を軽減することができる。さらに、本実施例では、金属配線４５が画素領域中央部６５から画素領域周辺部６６まで積層されているので、シェーディングも軽減できる。また、金属配線４５は隣接する画素の間、すなわち、画素境界部４３上に配されているため、開口率が低下することもない。 The reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17.
4). Effect Since the metal wiring 45 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the transparent electrode 42 and the metal wiring 45 are combined. The resistance becomes smaller than the resistance of only the transparent electrode 42. Therefore, in the conventional configuration, the voltage drop at the pixel region central portion 65 that has become large due to the resistance of the transparent electrode 42 is reduced, and the voltage drop at the pixel region central portion 65 can be suppressed. Accordingly, it is possible to reduce image quality degradation that occurs when the magnitude of the voltage drop differs depending on the location of the pixel region 61. Further, in this embodiment, since the metal wiring 45 is laminated from the pixel region central portion 65 to the pixel region peripheral portion 66, shading can be reduced. Further, since the metal wiring 45 is disposed between adjacent pixels, that is, on the pixel boundary portion 43, the aperture ratio does not decrease.
　また、光電変換膜４１は、絶縁膜４４により画素毎に電気的に分離されている。そのため、光電変換膜４１の膜厚を薄くしても、光電変換膜４１本来の特性である分光感度、残像、及び画素間リークで良好な特性が得られる。仮に、光電変換膜４１が画素毎に分離されていない場合、画素間のＣＲ時定数が蓄積時間τより十分大きいことが求められ、光電変換膜４１の暗導電率を大きくする必要が生じる。光導電性を損なわず大きな暗導電率を得るには、光電変換膜４１の材料としてバンドギャップの大きいものを選択し、暗時のキャリアを減少させねばならない。しかしながら、バンドギャップを大きくした上で、可視光全域で十分な感度を得るには、さらに光電変換膜４１の膜厚を厚くする必要がある。このような構成をとると、光電変換膜４１のバイアス電圧が増大したり、光導電性残像が増大したりしてしまう。従って、光電変換膜４１は、絶縁膜４４により画素毎に電気的に分離される必要が生じる。 Further, the photoelectric conversion film 41 is electrically separated for each pixel by the insulating film 44. Therefore, even if the film thickness of the photoelectric conversion film 41 is reduced, good characteristics can be obtained with the spectral sensitivity, the afterimage, and the inter-pixel leakage, which are the original characteristics of the photoelectric conversion film 41. If the photoelectric conversion film 41 is not separated for each pixel, the CR time constant between the pixels is required to be sufficiently larger than the accumulation time τ, and the dark conductivity of the photoelectric conversion film 41 needs to be increased. In order to obtain a large dark conductivity without impairing the photoconductivity, it is necessary to select a material having a large band gap as a material of the photoelectric conversion film 41 and reduce carriers in the dark. However, in order to obtain a sufficient sensitivity in the entire visible light range after increasing the band gap, it is necessary to further increase the thickness of the photoelectric conversion film 41. With such a configuration, the bias voltage of the photoelectric conversion film 41 increases or the photoconductive afterimage increases. Therefore, the photoelectric conversion film 41 needs to be electrically separated for each pixel by the insulating film 44.
　なお、絶縁膜４４を遮光材料で形成した場合、隣接画素からの斜め入射光を遮光できるため、隣接画素からの斜め入射光によるクロストークを抑制できる。
５．固体撮像装置１の製造方法
　本発明の実施の形態１における画素部１００の製造方法について、図４～７を用いて、要部となる工程を説明する。 When the insulating film 44 is formed of a light shielding material, oblique incident light from adjacent pixels can be shielded, so that crosstalk due to oblique incident light from adjacent pixels can be suppressed.
5. Manufacturing Method of Solid-State Imaging Device 1 With respect to the manufacturing method of the pixel unit 100 according to the first embodiment of the present invention, processes that are essential parts will be described with reference to FIGS.
　図４の（ａ）において、半導体基板５に、トランジスタや拡散層の素子を分離するＳＴＩ１２を形成する。具体的には、半導体基板５をドライエッチングすることで、例えば分離領域となる深さ２００ｎｍ～４００ｎｍの溝を形成する。次に、形成した溝と半導体基板５との界面の欠陥領域を低減するため、熱酸化等により、例えば酸化膜厚１０ｎｍ～２０ｎｍの犠牲酸化を行い、さらに、例えば１０ｋｅＶ～２０ｋｅＶ、１×１０１３ｃｍ－２ ～ ３×１０１３ｃｍ－２で、Ｂのイオン注入を行い、Ｐ＋層のチャネルストッパー１３を形成する。次に、熱酸化、またはプラズマ酸化等により、転送ゲート１８やリセットゲート１０を構成するトランジスタのゲート酸化膜となるゲート酸化膜１４を、例えば、５ｎｍ～１０ｎｍ形成する。 In FIG. 4A, an STI 12 for separating transistors and diffusion layer elements is formed on a semiconductor substrate 5. Specifically, the semiconductor substrate 5 is dry-etched to form, for example, a trench having a depth of 200 nm to 400 nm serving as an isolation region. Next, in order to reduce the defect region at the interface between the formed trench and the semiconductor substrate 5, for example, sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 × 10 13. B ions are implanted at cm −2 to 3 × 10 13 cm −2 to form a channel stopper 13 for the P + layer. Next, the gate oxide film 14 which becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed, for example, by 5 to 10 nm by thermal oxidation or plasma oxidation.
　次に、図４の（ｂ）に示すように、熱ＣＶＤまたはプラズマ酸化等により、Ｐｏｌｙ－Ｓｉ膜を、例えば、１００ｎｍ～２００ｎｍ堆積し、その後一般的なフォトリソグラフィ技術によって、所定のレジストパターンを形成する。そして、Ｐｏｌｙ－Ｓｉ膜を選択的にエッチングすることにより、Ｐｏｌｙ－Ｓｉ膜からなる転送ゲート１８や増幅トランジスタゲート１９やリセットゲート１０を形成する。 Next, as shown in FIG. 4B, a Poly-Si film is deposited by, for example, 100 nm to 200 nm by thermal CVD or plasma oxidation, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19, and the reset gate 10 made of the Poly-Si film are formed.
　次に、Ｐ型の半導体基板５にＰやＡｓを、例えば、５０ｋｅＶ～８０ｋｅＶ、１×１０１４ｃｍ－２ ～ ２×１０１５ｃｍ－２で、イオン注入することにより、電荷蓄積領域１５やフローティングディフュージョン１６、及びリセットトランジスタドレイン１７の各Ｎ型の不純物層を同時に形成する。 Next, P or As is ion-implanted into the P-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 × 10 14 cm −2 to 2 × 10 15 cm −2 , so that the charge accumulation region 15 or the floating region is floated. The N-type impurity layers of the diffusion 16 and the reset transistor drain 17 are simultaneously formed.
　ここで、ゲート酸化膜１４形成後に、フローティングディフュージョン１６上の一部を開口し、Ｐｏｌｙ－Ｓｉ膜で構成される増幅トランジスタゲート１９を形成して、フローティングディフュージョン１６と増幅トランジスタゲート１９との電気的接続をとっている。 Here, after the gate oxide film 14 is formed, a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film, and the electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is established. Connected.
　ＣＶＤ酸化膜よりなる層間絶縁膜２０を、例えば５００ｎｍ～１０００ｎｍ形成する。そして、一般的なフォトリソグラフィ技術とエッチング技術とによって、所定の位置にコンタクト３１やコンタクト３２、及びコンタクト３３を形成する。コンタクト開口部にＷ（タングステン）のプラグを埋め込み、Ｗプラグの接続電極２３を形成し、電荷蓄積領域１５やリセットトランジスタドレイン１７の電気的接続を形成する。例えば２００ｎｍ～３００ｎｍの膜厚のＡｌやＣｕ等よりなる配線２４と、ＣＶＤ酸化膜よりなる層間絶縁膜２１とを形成する。同様の繰り返しで、配線２５、層間絶縁膜２２を形成し、多層配線の形成を終了する。ここで、接続電極２３上にコンタクトを開口し、Ｗプラグを埋め込んで接続電極２６を形成する。 An interlayer insulating film 20 made of a CVD oxide film is formed, for example, to 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique. A W (tungsten) plug is embedded in the contact opening, a W plug connection electrode 23 is formed, and electrical connection to the charge storage region 15 and the reset transistor drain 17 is formed. For example, a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed. Here, a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.
　図５の（ａ）において、画素毎に区画されたアルミニウム（Ａｌ）やタングステン（Ｗ）、モリブデン（Ｍｏ）などからなる膜厚１００ｎｍ～３００ｎｍの画素電極４０を形成する。画素電極４０形成後に、画素電極４０上にプラズマＣＶＤやスパッタ、及び塗布装置で、撮像目的に応じた分光感度特性を有するα―Ｓｉ膜や無機光導電膜等を１００ｎｍ～１ｕｍ堆積し、光電変換膜４１を形成する。 5A, a pixel electrode 40 having a thickness of 100 nm to 300 nm made of aluminum (Al), tungsten (W), molybdenum (Mo) or the like partitioned for each pixel is formed. After the pixel electrode 40 is formed, an α-Si film, an inorganic photoconductive film, or the like having a spectral sensitivity characteristic corresponding to the imaging purpose is deposited on the pixel electrode 40 by plasma CVD, sputtering, and a coating apparatus, and photoelectric conversion is performed. A film 41 is formed.
　図５の（ｂ）において、一般的なフォトリソグラフィ技術とエッチング技術とにより、画素境界部４３における光電変換膜４１をエッチングし、光電変換膜の溝４８を形成する。 5B, the photoelectric conversion film 41 at the pixel boundary 43 is etched by a general photolithography technique and etching technique to form a groove 48 of the photoelectric conversion film.
　図６の（ａ）において、画素境界部４３にあたる光電変換膜の溝４８を、ＣＶＤ酸化膜によって構成される絶縁膜４４で埋め込む。さらに、光電変換膜４１及び絶縁膜４４上に、スパッタやＣＶＤで、ＩＴＯやＺｎＯによって構成される、例えば、数１０ｎｍ～数１００ｎｍの膜厚の透明電極４２を形成する。 6A, the groove 48 of the photoelectric conversion film corresponding to the pixel boundary 43 is embedded with an insulating film 44 formed of a CVD oxide film. Further, on the photoelectric conversion film 41 and the insulating film 44, a transparent electrode 42 made of ITO or ZnO and having a film thickness of, for example, several tens nm to several hundreds nm is formed by sputtering or CVD.
　図６の（ｂ）において、画素部１００上に、スパッタやＣＶＤで、例えば、膜厚１００ｎｍ～３００ｎｍのＡｌやＷ、Ｍｏ等の金属配線４５を堆積する。次に、一般的なフォトリソグラフィ技術とエッチング技術とにより、光電変換膜４１をエッチングし、画素境界部４３における透明電極４２上に、メッシュ状の金属配線４５を形成する。 6B, a metal wiring 45 such as Al, W, or Mo having a thickness of 100 nm to 300 nm is deposited on the pixel portion 100 by sputtering or CVD. Next, the photoelectric conversion film 41 is etched by a general photolithography technique and an etching technique, and a mesh-like metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43.
　図７において、画素電極４０、光電変換膜４１、透明電極４２からなる光電変換部４６上に、平坦化膜５０，５２、オンチップカラーフィルター５１、及びオンチップマイクロレンズ５３を形成する。
[実施の形態２]
１．画素部２００の構成
　図８は、本発明の実施の形態２における、固体撮像装置１の画素部２００の断面図である。下記以外の構成は、画素部１００と同じなので説明を省略する。 In FIG. 7, planarization films 50 and 52, an on-chip color filter 51, and an on-chip microlens 53 are formed on the photoelectric conversion unit 46 including the pixel electrode 40, the photoelectric conversion film 41, and the transparent electrode 42.
[Embodiment 2]
1. Configuration of Pixel Unit 200 FIG. 8 is a cross-sectional view of the pixel unit 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. Since the configuration other than the following is the same as that of the pixel unit 100, the description thereof is omitted.
　光電変換膜４１の溝内の下部には、絶縁膜４７が埋め込まれている。そして、光電変換膜４１及び絶縁膜４７の上には、透明電極４２が形成されている。絶縁膜４７の上面は、光電変換膜４１の上面より低い位置にある。また、透明電極４２の厚みが、光電変換膜４１における画素間の溝の幅の半分と比べて小さいため、光電変換膜４１の溝の内壁に透明電極４２が被着される。すなわち、透明電極４２により溝が埋まり切らず、溝内に透明電極４２の表面により囲まれてなる凹形状部が残った状態となる。透明電極４２の凹形状部には、金属配線１４５が埋め込まれている。金属配線１４５の埋め込まれた部分も、透明電極４２の上に存在することになる。金属配線１４５の深さは、金属配線１４５の最下面が光電変換膜４１の上面より下にあって、且つ、金属配線１４５の最下面の下に透明電極４２と絶縁膜４７とが形成できる程度でなければならない。金属配線１４５は、透明電極４２を構成する材料より電気抵抗率の小さい材料からなる。
２．効果
　画素領域６１における透明電極４２上には、透明電極４２を構成する材料より電気抵抗率の小さい材料からなる金属配線１４５が積層されているため、実施例１と同様に、画素領域中央部６５での電圧降下を抑制することができる。さらに、金属配線１４５の断面積は、実施の形態１における金属配線４５の断面積よりも大きいため、画素領域中央部６５での電圧降下をより小さくできる。 An insulating film 47 is embedded in the lower part of the groove of the photoelectric conversion film 41. A transparent electrode 42 is formed on the photoelectric conversion film 41 and the insulating film 47. The upper surface of the insulating film 47 is at a position lower than the upper surface of the photoelectric conversion film 41. Further, since the thickness of the transparent electrode 42 is smaller than half the width of the groove between the pixels in the photoelectric conversion film 41, the transparent electrode 42 is attached to the inner wall of the groove of the photoelectric conversion film 41. In other words, the groove is not completely filled with the transparent electrode 42, and the concave portion surrounded by the surface of the transparent electrode 42 remains in the groove. A metal wiring 145 is embedded in the concave portion of the transparent electrode 42. The portion where the metal wiring 145 is embedded also exists on the transparent electrode 42. The depth of the metal wiring 145 is such that the lowermost surface of the metal wiring 145 is below the upper surface of the photoelectric conversion film 41 and the transparent electrode 42 and the insulating film 47 can be formed below the lowermost surface of the metal wiring 145. Must. The metal wiring 145 is made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42.
2. Effect Since the metal wiring 145 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the pixel region central portion 65 is the same as in the first embodiment. The voltage drop at can be suppressed. Furthermore, since the cross-sectional area of the metal wiring 145 is larger than the cross-sectional area of the metal wiring 45 in the first embodiment, the voltage drop at the pixel region central portion 65 can be further reduced.
　また、この構成では、画素境界部４３における透明電極４２の溝が埋まり切らず残った凹形状部に、金属配線１４５が埋め込まれている。さらに、金属配線１４５は、その最下面が光電変換膜４１の上面より下にあるように形成されるため、隣接画素からの斜め入射光を遮光でき、隣接画素からの斜め入射光によるクロストークも抑制できる。また、金属配線１４５は、その最下面の下に、透明電極４２と絶縁膜４７とが存在するよう形成されるため、透明電極４２が画素領域６１全体に拡がる構成を取ることができ、かつ電極がショートすることが無い。
３．製造方法
　本発明の実施の形態２における画素部２００の製造方法について、本発明の実施の形態１との差異を中心に、図９を用いて、要部となる工程を説明する。 Further, in this configuration, the metal wiring 145 is embedded in the concave shape portion where the groove of the transparent electrode 42 at the pixel boundary portion 43 is not completely filled. Furthermore, since the lowermost surface of the metal wiring 145 is formed below the upper surface of the photoelectric conversion film 41, the oblique incident light from the adjacent pixel can be shielded, and crosstalk due to the oblique incident light from the adjacent pixel is also caused. Can be suppressed. Further, since the metal wiring 145 is formed so that the transparent electrode 42 and the insulating film 47 exist below the lowermost surface thereof, the transparent electrode 42 can be configured to spread over the entire pixel region 61, and the electrode There is no short circuit.
3. Manufacturing Method A manufacturing method of the pixel unit 200 according to the second embodiment of the present invention will be described with reference to FIG. 9, focusing on differences from the first embodiment of the present invention.
　図９（ａ）において、画素境界部４３の分離された光電変換膜４１の溝に、ＣＶＤ酸化膜よりなる絶縁膜４７を形成する。ここで、前記絶縁膜４７の膜厚は、画素電極４０の膜厚（例えば、１００ｎｍ～３００ｎｍ）より厚く形成する。次に、光電変換膜４１上、及び画素境界部４３における絶縁膜４７上の溝内の光電変換膜４１側壁に沿って、スパッタやＣＶＤでＩＴＯやＺｎＯからなる透明電極４２を、例えば、数１０ｎｍ～数１００ｎｍの膜厚で形成する。 9A, an insulating film 47 made of a CVD oxide film is formed in the groove of the photoelectric conversion film 41 separated at the pixel boundary 43. Here, the insulating film 47 is formed thicker than the pixel electrode 40 (for example, 100 nm to 300 nm). Next, a transparent electrode 42 made of ITO or ZnO by sputtering or CVD is formed on the photoelectric conversion film 41 and along the side wall of the photoelectric conversion film 41 in the groove on the insulating film 47 at the pixel boundary 43 by, for example, several tens of nm. It is formed with a film thickness of ˜100 nm.
　次に、図９（ｂ）において、透明電極４２上に、スパッタやＣＶＤに基づき、例えば１００ｎｍ～３００ｎｍの膜厚でＡｌやＷ、Ｍｏ等の金属を堆積する。一般的なフォトリソグラフィ技術とエッチング技術とによって金属をエッチングし、溝内に金属膜を形成し、画素境界部４３の透明電極４２上に、メッシュ状の金属配線１４５を形成する。
[実施の形態３]
１．画素部３００の構成
　図１０は、本発明の実施の形態３における、固体撮像装置１の画素部３００の断面図である。 Next, in FIG. 9B, a metal such as Al, W, or Mo is deposited on the transparent electrode 42 with a film thickness of, for example, 100 nm to 300 nm based on sputtering or CVD. A metal is etched by a general photolithography technique and an etching technique, a metal film is formed in the groove, and a mesh-like metal wiring 145 is formed on the transparent electrode 42 at the pixel boundary 43.
[Embodiment 3]
1. Configuration of Pixel Unit 300 FIG. 10 is a cross-sectional view of the pixel unit 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention.
　下記以外の構成は、画素部１００と同じなので説明を省略する。 Since the configuration other than the following is the same as that of the pixel unit 100, description thereof is omitted.
　画素部３００において、光電変換膜４１は、画素境界部４３によって画素毎に区画されている。画素境界部４３の上には、絶縁膜２８が形成されている。絶縁膜２８の側壁には、画素電極４０と同一材料により構成された側壁画素電極３９が、絶縁膜２８の上部を残して形成された構造となっている。 In the pixel unit 300, the photoelectric conversion film 41 is partitioned for each pixel by a pixel boundary 43. An insulating film 28 is formed on the pixel boundary portion 43. A sidewall pixel electrode 39 made of the same material as the pixel electrode 40 is formed on the sidewall of the insulating film 28, leaving the upper portion of the insulating film 28.
　画素電極４０と同一材料により構成された側壁画素電極３９が遮光能力を有し、隣接画素からの斜め入射光を遮光できるため、隣接画素からの斜め入射光によるクロストークを抑制できる。
２．製造方法
　本発明の実施の形態３における、画素部３００の製造方法について、本発明の実施の形態１との差異を中心に、図１１，１２を用いて、要部となる工程を説明する。 The side wall pixel electrode 39 made of the same material as the pixel electrode 40 has a light shielding capability and can shield oblique incident light from the adjacent pixel, so that crosstalk due to the oblique incident light from the adjacent pixel can be suppressed.
2. Manufacturing Method A manufacturing method of the pixel unit 300 according to the third embodiment of the present invention will be described with reference to FIGS. 11 and 12, focusing on differences from the first embodiment of the present invention.
　図１１（ａ）において、層間絶縁膜２２形成後に、ＣＶＤ法に基づき、酸化膜よりなる絶縁膜２８を、例えば、１００ｎｍ～１ｕｍ堆積し、一般的なフォトリソグラフィ技術とエッチング技術とによって、画素境界部４３と同等の分離幅を持つ所定の形状の絶縁膜２８を形成する。 In FIG. 11A, after the interlayer insulating film 22 is formed, an insulating film 28 made of an oxide film is deposited, for example, by 100 nm to 1 μm based on the CVD method, and the pixel boundary is formed by a general photolithography technique and an etching technique. An insulating film 28 having a predetermined shape having a separation width equivalent to that of the portion 43 is formed.
　次に、図１１（ｂ）において、絶縁膜２８を形成後に、ＡｌやＷ、Ｍｏ等からなる金属配線を、画素境界部４３では絶縁膜２８の側壁部に、画素境界部４３を除く箇所では絶縁膜２２上に、１００ｎｍ～３００ｎｍ堆積し、一般的なフォトリソグラフィ技術とエッチング技術とによって、所定の形状の画素電極４０と側壁画素電極３９を形成する。画素電極４０の面積は、画素境界部４３における絶縁膜２８の幅で決まる。画素間の分離幅を画素サイズの１０％～２０％とすれば、開口率は６４％～８１％と見積もられる。 Next, in FIG. 11B, after forming the insulating film 28, a metal wiring made of Al, W, Mo, or the like is provided on the side wall of the insulating film 28 at the pixel boundary 43 and at a place excluding the pixel boundary 43. On the insulating film 22, 100 nm to 300 nm is deposited, and pixel electrodes 40 and sidewall pixel electrodes 39 having a predetermined shape are formed by a general photolithography technique and etching technique. The area of the pixel electrode 40 is determined by the width of the insulating film 28 at the pixel boundary 43. If the separation width between pixels is 10% to 20% of the pixel size, the aperture ratio is estimated to be 64% to 81%.
　図１２（ａ）において、画素電極４０、及び側壁画素電極３９形成後に、画素電極４０及び側壁画素電極３９上に、プラズマＣＶＤやスパッタ、及び塗布装置で、撮像目的に応じた分光感度特性を有するα―Ｓｉ膜や無機光電変換膜、及び有機光電変換膜を、例えば、１００ｎｍ～１ｕｍ堆積し、光電変換膜４１を形成する。 In FIG. 12A, after the pixel electrode 40 and the sidewall pixel electrode 39 are formed, the pixel electrode 40 and the sidewall pixel electrode 39 have spectral sensitivity characteristics corresponding to the imaging purpose by plasma CVD, sputtering, and coating apparatus. An α-Si film, an inorganic photoelectric conversion film, and an organic photoelectric conversion film are deposited to a thickness of, for example, 100 nm to 1 μm to form the photoelectric conversion film 41.
　次に、図１２（ｂ）において、光電変換膜４１、及び画素境界部４３の絶縁膜２８上に、スパッタやＣＶＤでＩＴＯやＺｎＯからなる透明電極４２を、例えば数１０ｎｍ～数１００ｎｍ堆積して形成する。さらに透明電極４２上であって、絶縁膜２８の上方に金属配線４５を形成する。
[その他の事項]
１．金属配線の形状
　本発明に係る実施例では、金属配線４５の形状を、すべての隣接する画素部１００の間を通るという図１３(ａ)で示すメッシュ状としてきた。この場合、金属配線４５の断面積が増えるので、画素領域中央部６５の電圧降下が、効果的に抑制される。 Next, in FIG. 12B, a transparent electrode 42 made of ITO or ZnO is deposited on the photoelectric conversion film 41 and the insulating film 28 at the pixel boundary 43 by sputtering or CVD, for example, several tens nm to several hundreds nm. Form. Further, a metal wiring 45 is formed on the transparent electrode 42 and above the insulating film 28.
[Other matters]
1. Shape of Metal Wiring In the embodiment according to the present invention, the shape of the metal wiring 45 is a mesh shape shown in FIG. 13A in which it passes between all adjacent pixel portions 100. In this case, since the cross-sectional area of the metal wiring 45 increases, the voltage drop at the pixel region central portion 65 is effectively suppressed.
　この他にも、金属配線４５の形状として、以下のパターンが考えられる。 In addition, the following pattern is conceivable as the shape of the metal wiring 45.
　図１３（ｂ）に示すようにストライプ状に金属配線を形成する。 As shown in FIG. 13B, metal wiring is formed in a stripe shape.
　図１３（ｃ）に示すように複数の画素部１００をまとめて金属配線４５で囲むように形成する。 As shown in FIG. 13C, the plurality of pixel portions 100 are formed so as to be surrounded by the metal wiring 45.
　図１３（ｄ）に示すように画素領域中央部６５にある画素部１００の周囲にのみメッシュ状の金属配線４５を形成し、他の金属配線４５の少なくとも一部を、画素領域周辺部６６へ繋ぐような形状に形成する。　 As shown in FIG. 13D, the mesh-like metal wiring 45 is formed only around the pixel portion 100 in the pixel region central portion 65, and at least a part of the other metal wiring 45 is transferred to the pixel region peripheral portion 66. It is formed in a shape that connects. *
　上記、図１３（ｂ）、（ｃ）、（ｄ）のように、金属配線４５は、一部の隣接する画素の間を通る形状をとっても、また、画素領域６１の少なくとも一部にのみ、金属配線４５が形成されても、図１３（ａ）と同様の効果が得られる。
２．その他
　なお、本発明に係る固体撮像装置の構成などは、上記実施の形態に係る固体撮像装置１の構成に限定されるものではなく、本発明の効果を奏する範囲において、種々の変形および応用が可能である。そして、技術的思想を逸脱しない範囲において、上述の各工程で使用したプロセスを他の等価なプロセスに置換することが可能である。また、工程順を入れ替えることも、材料種を変更することも可能である。 As shown in FIGS. 13B, 13 </ b> C, and 13 </ b> D, the metal wiring 45 may have a shape passing between some adjacent pixels, or only in at least a part of the pixel region 61. Even if the metal wiring 45 is formed, the same effect as in FIG.
2. Others The configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.
　例えば、画素の配置については、実施の形態で示したマトリクス状（行列状）の配列の他に、画素を４５°回転させ配列するといった構成を取ることができる。カラーフィルターについては、原色ベイヤー配列や補色市松配列等の配列を選択できる。金属配線４５の材料は、銅、アルミニウムなどの他にＷ、Ｍｏ、Ｔｉ等も選択できる。 For example, with respect to the arrangement of the pixels, in addition to the matrix (matrix) arrangement shown in the embodiment, a configuration in which the pixels are arranged by being rotated by 45 ° can be employed. For the color filter, an array such as a primary color Bayer array or a complementary color checkered array can be selected. The material of the metal wiring 45 can be selected from W, Mo, Ti and the like in addition to copper, aluminum and the like.
　本発明は、デジタルカメラ等に利用でき、画質の劣化が抑制された固体撮像装置を実現するのに有用である。 The present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which deterioration of image quality is suppressed.
１　固体撮像装置
５　半導体基板
１５　電荷蓄積領域
１６　フローティングディフュージョン
４０　画素電極
４１　光電変換膜
４２　透明電極
４４　絶縁膜
４５　金属配線
１００　画素部
２００　画素部
３００　画素部
４００　画素部 DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 5 Semiconductor substrate 15 Charge storage area 16 Floating diffusion 40 Pixel electrode 41 Photoelectric conversion film 42 Transparent electrode 44 Insulating film 45 Metal wiring 100 Pixel part 200 Pixel part 300 Pixel part 400 Pixel part

Claims (9)

  1. 　複数の画素が二次元配置されてなる画素領域を有する固体撮像装置であって、
    　半導体基板と、
    　前記半導体基板上に形成された層間絶縁膜と、
    　前記層間絶縁膜上に形成された下部電極と、
    　透光性を有する上部電極と、
    　前記下部電極と前記上部電極とに挟まれた光電変換膜と
    を有し、
    　前記上部電極は画素領域全体における光電変換膜上に拡がっており、
    　前記上部電極における少なくとも一部には、隣接する画素の間を通り、前記上部電極を構成する材料よりも電気抵抗率が小さい材料からなる金属配線が積層されている
    　ことを特徴とする固体撮像装置。     A solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged,
    A semiconductor substrate;
    An interlayer insulating film formed on the semiconductor substrate;
    A lower electrode formed on the interlayer insulating film;
    A translucent upper electrode;
    A photoelectric conversion film sandwiched between the lower electrode and the upper electrode;
    The upper electrode extends over the photoelectric conversion film in the entire pixel region,
    A solid-state imaging device characterized in that at least a part of the upper electrode is laminated with a metal wiring made of a material that passes between adjacent pixels and has a lower electrical resistivity than the material constituting the upper electrode. .
  2. 　前記光電変換膜と前記下部電極とは画素毎に区画されており、
    　隣接する画素における互いの前記光電変換膜間に、絶縁膜が介挿されている
    　ことを特徴とする請求項１に記載の固体撮像装置。     The photoelectric conversion film and the lower electrode are partitioned for each pixel,
    The solid-state imaging device according to claim 1, wherein an insulating film is interposed between the photoelectric conversion films of adjacent pixels.
  3. 　前記絶縁膜はその上面が、前記光電変換膜の上面より低く位置するよう形成されており、
    　前記光電変換膜の側壁と前記絶縁膜の上面とで溝が構成されており、
    　前記上部電極は、前記溝の内壁に沿って形成されており、
    　前記溝内には前記上部電極の表面により囲まれてなる凹形状部が残っており、
    　前記金属配線は、前記凹形状部に埋め込まれている
    　ことを特徴とする請求項２に記載の固体撮像装置。     The insulating film is formed such that its upper surface is positioned lower than the upper surface of the photoelectric conversion film,
    A groove is formed by the side wall of the photoelectric conversion film and the upper surface of the insulating film,
    The upper electrode is formed along the inner wall of the groove,
    In the groove, there remains a concave portion surrounded by the surface of the upper electrode,
    The solid-state imaging device according to claim 2, wherein the metal wiring is embedded in the concave portion.
  4. 　前記絶縁膜が介挿されているのは、前記隣接する画素間における、前記光電変換膜の間の一部であって、
    　前記絶縁膜と前記光電変換膜の間には、
    　前記下部電極と同一材料により構成され前記下部電極と電気的に接続が図られた側壁画素電極が、前記絶縁膜の側壁上部を残して形成されている
    　ことを特徴とする請求項２に記載の固体撮像装置。     The insulating film is interposed between a part of the photoelectric conversion films between the adjacent pixels,
    Between the insulating film and the photoelectric conversion film,
    The side wall pixel electrode, which is made of the same material as the lower electrode and is electrically connected to the lower electrode, is formed leaving the upper side wall of the insulating film. Solid-state imaging device.
  5. 　前記絶縁膜は、遮光性を有する
    　ことを特徴とする請求項２～４のいずれかに記載の固体撮像装置。     The solid-state imaging device according to claim 2, wherein the insulating film has a light shielding property.
  6. 　前記金属配線は、
    　前記半導体基板表面を平面視したとき、前記上部電極の表面がメッシュ状またはストライプ状に形成されている
    　ことを特徴とする請求項１～５のいずれかに記載の固体撮像装置。     The metal wiring is
    6. The solid-state imaging device according to claim 1, wherein when the surface of the semiconductor substrate is viewed in plan, the surface of the upper electrode is formed in a mesh shape or a stripe shape.
  7. 　複数の画素が二次元配置されてなる画素領域を有する固体撮像装置の製造方法であって、
    　半導体基板上に、層間絶縁膜を形成する工程と、
    　前記層間絶縁膜上に、下部電極を形成する工程と、
    　前記下部電極上に、光電変換膜を形成する工程と、
    　前記光電変換膜上に、透光性を有する上部電極を、画素領域全体に拡がるよう、形成する工程と、
    　前記上部電極上における少なくとも一部には、隣接する画素の間を通り、前記上部電極を構成する材料よりも電気抵抗率が小さい材料からなる金属配線を積層する工程とを含む
    　ことを特徴とする固体撮像装置の製造方法。     A method for manufacturing a solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged,
    Forming an interlayer insulating film on the semiconductor substrate;
    Forming a lower electrode on the interlayer insulating film;
    Forming a photoelectric conversion film on the lower electrode;
    Forming a translucent upper electrode on the photoelectric conversion film so as to spread over the entire pixel region;
    And at least part of the upper electrode includes a step of laminating a metal wiring made of a material having a lower electrical resistivity than a material constituting the upper electrode, passing between adjacent pixels. Manufacturing method of solid-state imaging device.
  8. 　前記下部電極を形成する工程では、前記下部電極を画素毎に区画した状態で形成し、
    　前記光電変換膜を形成する工程では、前記光電変換膜を画素毎に区画した状態で形成するものであって、
    　前記光電変換膜を形成する工程の後であって、
    　前記金属配線を積する工程の前に、
    　隣接する画素の前記光電変換膜間を埋め込むように絶縁膜を形成する工程と、
    　前記絶縁膜の上面が、前記光電変換膜の上面より低い位置に配置されるよう、前記絶縁膜の一部を除去する工程とを含む
    　ことを特徴とする請求項７に記載の固体撮像装置の製造方法。     In the step of forming the lower electrode, the lower electrode is formed in a state partitioned for each pixel,
    In the step of forming the photoelectric conversion film, the photoelectric conversion film is formed in a state partitioned for each pixel,
    After the step of forming the photoelectric conversion film,
    Before the step of stacking the metal wiring,
    Forming an insulating film so as to embed between the photoelectric conversion films of adjacent pixels;
    The solid-state imaging device according to claim 7, further comprising: removing a part of the insulating film so that an upper surface of the insulating film is disposed at a position lower than an upper surface of the photoelectric conversion film. Production method.
  9. 　前記層間絶縁膜を形成する工程の後であって、
    　前記下部電極を形成する工程の前に、
    　隣接する画素の間である画素境界部の前記層間絶縁膜の上に、絶縁膜を立設する工程を含み、
    　前記絶縁膜を立設する工程の後であって、
    　前記光電変換膜を形成する工程の前に、
    　前記下部電極と同一材料により構成され、前記下部電極と電気的に接続が図られた側壁画素電極を、前記絶縁膜の側壁に対し、その上部を除いた部分に被着させる工程を含み、
    　前記金蔵配線を積層する工程では、前記隣接する画素の間の前記絶縁膜上に、前記金属配線を積層する
    　ことを特徴とする請求項７に記載の固体撮像装置の製造方法。     After the step of forming the interlayer insulating film,
    Before the step of forming the lower electrode,
    A step of standing an insulating film on the interlayer insulating film at a pixel boundary portion between adjacent pixels;
    After the step of standing the insulating film,
    Before the step of forming the photoelectric conversion film,
    A step of depositing a side wall pixel electrode made of the same material as the lower electrode and electrically connected to the lower electrode on a side wall of the insulating film except for an upper portion thereof;
    The method for manufacturing a solid-state imaging device according to claim 7, wherein, in the step of stacking the metallized wiring, the metal wiring is stacked on the insulating film between the adjacent pixels.
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