JP2012064822A - Solid-state imaging device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device and a manufacturing method therefor, capable of suppressing a voltage drop at the central portion of a pixel region.SOLUTION: A solid-state imaging device 1 having a pixel region 61 of a plurality of two-dimensionally arrayed pixel portions 100 comprises: a semiconductor substrate 5; interlayer insulating films 20-22 formed on the semiconductor substrate 5; a lower electrode 40 formed on the interlayer insulating films 20-22; a photoelectric conversion film 41 formed on the lower electrode 40; and an upper electrode 42 having light transmissivity, formed on the photoelectric conversion film 41. The upper electrode 42 is expanded over the entire pixel region 61. Further, on at least a portion of the upper electrode 42, there is a lamination of metallic wiring 45 passing between adjacent pixel portions 100 and being formed of a material having smaller electrical resistivity than a material constituting the upper electrode 42.

Description

  The present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate, and more particularly to a technique for improving the element structure in order to equalize a bias voltage applied to the photoelectric conversion film.

As a conventional stacked solid-state imaging device, for example, as shown in FIG. 14, a P-type semiconductor substrate 401, an N ⁺ -type source region 409, a gate electrode 408, an N ⁻ -type BCCD channel 410, and a transparent electrode 402 In some cases, an insulating film 403, a photoconductive film 404, a pixel electrode 405, an extraction electrode 406, and an interlayer insulating film 407 are provided. This solid-state imaging device has a pixel region in which pixel units 400 are two-dimensionally arranged.

Signal charges generated by photoelectric conversion in the photoconductive film 404 are accumulated in the N ⁺ type source region 409 via the pixel electrode 405 and the extraction electrode 406. A bias voltage is applied to the transparent electrode 402. Then, after a predetermined accumulation time, a read voltage is applied to the gate electrode 408, whereby signal charges are transferred from the N ⁺ type source region 409 to the N ⁻ type BCCD channel 410. Next, when a transfer pulse is applied to the gate electrode 408, the signal charge is transferred through the N ^- type BCCD channel 410 and taken out as a video signal. Depending on the purpose, a signal output path via a MOS transistor can be used instead of the N ^- type BCCD channel 410.

JP 61-142767 A

  However, the conventional stacked solid-state imaging device has a problem that the voltage drop is larger in the central area of the pixel area than the peripheral area of the pixel area. This is because a transparent electrode 402 made of a material having a relatively high electrical resistivity, such as ITO (Indium Tin Oxide) or ZnO, is provided on the photoconductive film 404 in a form extending over the entire pixel region, and is transparent. When a voltage is applied to the photoconductive film 404 through the electrode 402, the voltage is applied from the outermost periphery of the pixel region. The resistance is a value obtained by multiplying the electrical resistivity by the length of the resistance and dividing by the cross-sectional area of the resistance, so that the applied voltage is the distance of the current path from the periphery of the pixel area toward the center of the pixel area. As it increases, it descends gradually. For this reason, the voltage drop is larger in the central area of the pixel area than in the peripheral area of the pixel area.

  If the voltage drop differs depending on the location of the pixel region, the amount of charge generated in the photoconductive film 404 collects in the pixel electrode 405, and the image quality deteriorates. In addition, when the difference in voltage drop for each pixel region is large, unevenness in the amount of charge collected on the pixel electrode 405 increases, and the deterioration of image quality becomes remarkable.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a solid-state imaging device capable of suppressing a voltage drop at the center of the pixel region and a manufacturing method thereof.

  In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged, and is formed on a semiconductor substrate and the semiconductor substrate. An interlayer insulating film; a lower electrode formed on the interlayer insulating film; a photoelectric conversion film formed on the lower electrode; and a translucent upper electrode formed on the photoelectric conversion film. And the upper electrode extends over the entire pixel region, and at least a part of the upper electrode is made of a material that passes between adjacent pixels and has a lower electrical resistivity than the material constituting the upper electrode. Metal wiring is laminated.

  In the solid-state imaging device according to the present invention, a metal wiring made of a material having a lower electrical resistivity than the material constituting the upper electrode is laminated on at least a part of the upper electrode in the pixel region. The resistance of the portion where the metal wiring is laminated becomes a combined resistance in a state where the upper electrode and the metal wiring are connected in parallel, and this combined resistance is smaller than the resistance of only the upper electrode. For this reason, the voltage drop is reduced at the locations where the metal wirings are laminated, and the potentials are substantially the same.

  In addition, since at least a part of the upper electrode has a portion having substantially the same potential, the difference in voltage drop between the peripheral portion of the pixel region and the central portion of the pixel region is smaller than that in the conventional example, that is, the central portion of the pixel region. The voltage drop at can be suppressed.

  Thus, by laminating the metal wiring on at least a part of the upper electrode, it is possible to reduce the overall resistance in the part, and it is possible to suppress the voltage drop in the central part of the pixel region. Further, since the metal wiring is stacked on the pixel boundary between adjacent pixels, the incident light to the photoelectric conversion film is not blocked.

  According to the manufacturing method of the present invention, it is possible to manufacture a solid-state imaging device that can suppress a voltage drop at the center of the pixel region.

1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a top view for 4 pixels in the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device concerning Embodiment 2 of this invention. FIG. 9 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 8. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 3 of this invention. FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10. FIG. 11 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 10. It is a top view which shows typically the metal wiring of the solid-state imaging device shown in FIG. 10, and the solid-state imaging device which concerns on a modification. It is sectional drawing of the conventional solid-state imaging device.

[Embodiment 1]
1. Overall Configuration of Solid-State Imaging Device 1 The overall configuration of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG.

As shown in FIG. 1, in the solid-state imaging device 1 according to the first embodiment, a plurality of pixel units 100 are arranged in a two-dimensional arrangement, for example, a matrix (matrix), thereby forming a pixel region 61. The pixel region 61 includes a pixel region central portion 65 and a pixel region peripheral portion 66. In the solid-state imaging device 1, a pulse generation circuit 62, a vertical shift register 63, and a horizontal shift register 64 are formed so as to surround the pixel region 61. The vertical shift register 63 and the horizontal shift register 64 sequentially output drive pulses to each pixel unit 100 in response to the application of the timing pulse from the pulse generation circuit 62.
2. Configuration of Pixel Unit 100 FIG. 2 is a plan view of four pixels in the solid-state imaging device 1 shown in FIG. Each pixel unit 100 is partitioned by a pixel boundary 43. The pixel unit 100 includes a reset gate 10, an amplification transistor 11, a charge storage region 15 of an N-type impurity diffusion layer, a floating diffusion 16 of an N-type impurity diffusion layer, and a reset transistor drain 17 of an N-type impurity diffusion layer. A transfer gate 18 and contacts 31 to 34 are provided.

  FIG. 3 is a cross-sectional view of the pixel unit 100 of the solid-state imaging device 1 shown in FIG. 1, and shows a cross-section A-A ′ of FIG. As shown in FIG. 3, an STI (Shallow Trench Isolation) 12 is formed in the semiconductor substrate 5 on which the P-type well is formed. The pixel unit 100 includes a channel stopper 13, a charge storage region 15, a floating diffusion 16, and a reset transistor drain 17.

  On the semiconductor substrate 5, a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked. Within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.

  Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20. In the interlayer insulating films 21 and 22, wirings 24 and 25 (for example, formed of Al or Cu) and connection electrodes 26 is formed. The interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.

  A pixel electrode 40 is formed on the interlayer insulating film 22 so as to be partitioned for each pixel. A photoelectric conversion film 41 is formed on the pixel electrode 40 by, for example, an α-Si film, an inorganic photoconductive film, or the like. The photoelectric conversion film 41 is separated at the pixel boundary 43, and the pixel boundary 43 is formed such that an insulating film 44 is interposed between the separated photoelectric conversion films 41. A transparent electrode 42 (for example, formed of ITO or ZnO) is formed on the photoelectric conversion film 41 and the insulating film 44, and the photoelectric conversion film 41 extends over the entire pixel region 61. A metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43. Since the insulating film 44 is provided at the pixel boundary portion 43 and the upper surface of the insulating film 44 is not a light receiving portion, the metal wiring 45 disposed on the insulating film 44 does not reduce the aperture ratio. . Therefore, the maximum width of the metal wiring 45 is the same as that of the insulating film 44. Further, the width of the metal wiring 45 may be reduced as long as the degree of reduction of the voltage drop at the pixel region central portion 65 in FIG. The shape of the metal wiring 45 is a mesh shape that passes between all adjacent pixels in the pixel region 61. Furthermore, it is formed so as to surround the pixel region 61, which means that the metal wiring 45 extends from the pixel region central portion 65 toward the pixel region peripheral portion 66, and the metal wiring 45 is connected to the pixel region central portion 65. The pixel area peripheral portion 66 is connected.

Flattening films 50 and 52, a color filter 51, and a microlens 53 are formed on the transparent electrode 42 and the metal wiring 45.
3. Driving of Solid-State Imaging Device 1 Light incident through the color filter 51 is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 42, and the generated charges are attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 42 and the pixel electrode 40, and are connected from the pixel electrode 40 to the connection electrodes 23 and 26. And temporarily stored in the charge storage region 15. Next, charge is accumulated in the floating diffusion 16 from the charge accumulation region 15 by the action of the transfer gate 18. At this time, the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside. .

The reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17.
4). Effect Since the metal wiring 45 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the transparent electrode 42 and the metal wiring 45 are combined. The resistance becomes smaller than the resistance of only the transparent electrode 42. Therefore, in the conventional configuration, the voltage drop at the pixel region central portion 65 that has become large due to the resistance of the transparent electrode 42 is reduced, and the voltage drop at the pixel region central portion 65 can be suppressed. Accordingly, it is possible to reduce image quality degradation that occurs when the magnitude of the voltage drop differs depending on the location of the pixel region 61. Further, in this embodiment, since the metal wiring 45 is laminated from the pixel region central portion 65 to the pixel region peripheral portion 66, shading can be reduced. Further, since the metal wiring 45 is disposed between adjacent pixels, that is, on the pixel boundary portion 43, the aperture ratio does not decrease.

  In addition, the photoelectric conversion film 41 is electrically separated for each pixel by the insulating film 44. Therefore, even if the film thickness of the photoelectric conversion film 41 is reduced, good characteristics can be obtained in terms of spectral sensitivity, afterimage, and inter-pixel leakage, which are inherent characteristics of the photoelectric conversion film 41. If the photoelectric conversion film 41 is not separated for each pixel, the CR time constant between the pixels is required to be sufficiently larger than the accumulation time τ, and the dark conductivity of the photoelectric conversion film 41 needs to be increased. In order to obtain a large dark conductivity without impairing the photoconductivity, it is necessary to select a material having a large band gap as a material of the photoelectric conversion film 41 and reduce carriers in the dark. However, in order to obtain a sufficient sensitivity in the entire visible light range after increasing the band gap, it is necessary to further increase the thickness of the photoelectric conversion film 41. When such a configuration is adopted, an increase in the bias voltage of the photoelectric conversion film 41 and a photoconductive afterimage are deteriorated. Therefore, the photoelectric conversion film 41 needs to be electrically separated for each pixel by the insulating film 44.

When the insulating film 44 is formed of a light shielding material, oblique incident light from adjacent pixels can be shielded, so that crosstalk due to oblique incident light from adjacent pixels can be suppressed.
5. Manufacturing Method of Solid-State Imaging Device 1 With respect to the manufacturing method of the pixel unit 100 according to the first embodiment of the present invention, processes that are essential parts will be described with reference to FIGS.

In FIG. 4A, an STI 12 for separating transistors and diffusion layer elements is formed on a semiconductor substrate 5. Specifically, the semiconductor substrate 5 is dry-etched to form, for example, a trench having a depth of 200 nm to 400 nm serving as an isolation region. Next, in order to reduce the defect region at the interface between the formed trench and the semiconductor substrate 5, sacrificial oxidation of, for example, an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and further, for example, 10 keV to 20 keV, 1 × 10 ¹³ cm. The ion implantation of B is performed at ⁻² to 3 × 10 ¹³ cm ⁻² to form the channel stopper 13 of the P ⁺ layer. In addition, P or As is ion-implanted into the P-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² , so that the charge accumulation region 15 and the floating diffusion are formed. 16 and the N-type impurity layers of the reset transistor drain 17 are formed simultaneously. The gate oxide film 14 that becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed by thermal oxidation, plasma oxidation, or the like, for example, 5 nm to 10 nm.

  Next, as shown in FIG. 4B, a Poly-Si film is deposited by, for example, 100 nm to 200 nm by thermal CVD or plasma oxidation, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19 and the reset gate 10 made of the Poly-Si film are formed.

  Here, after the gate oxide film 14 is formed, a part of the floating diffusion 16 is opened to form an amplifying transistor gate 19 composed of a Poly-Si film, and the floating diffusion 16 and the amplifying transistor gate 19 are electrically connected. Have taken.

  An interlayer insulating film 20 made of a CVD oxide film is formed, for example, 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique. A W (tungsten) plug is buried in the opened contact opening to form a connection electrode 23 of the W plug, and electrical connection to the charge storage region 15 and the reset transistor drain 17 is formed. For example, the wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and the interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed. Here, a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.

  In FIG. 5A, a pixel electrode 40 having a thickness of 100 nm to 300 nm made of aluminum (Al), tungsten (W), molybdenum (Mo) or the like partitioned for each pixel is formed. After the pixel electrode 40 is formed, an α-Si film, an inorganic photoconductive film, or the like having a spectral sensitivity characteristic corresponding to the imaging purpose is deposited on the pixel electrode 40 by plasma CVD, sputtering, or a coating apparatus, and then photoelectrically A conversion film 41 is formed.

  In FIG. 5B, the photoelectric conversion film 41 at the pixel boundary 43 is etched by a general photolithography technique and etching technique to form a groove 48 of the photoelectric conversion film.

  In FIG. 6A, the groove 48 of the photoelectric conversion film corresponding to the pixel boundary portion 43 is filled with an insulating film 44 formed of a CVD oxide film. Further, on the photoelectric conversion film 41 and the insulating film 44, a transparent electrode 42 having a film thickness of, for example, several tens of nm to several hundreds of nm made of ITO or ZnO is formed by sputtering or CVD.

  6B, a metal wiring 45 such as Al, W, or Mo having a thickness of 100 nm to 300 nm is deposited on the pixel portion 100 by sputtering or CVD. Next, the photoelectric conversion film 41 is etched by a general photolithography technique and an etching technique, and a mesh-like metal wiring 45 is formed on the transparent electrode 42 in the pixel boundary portion 43.

In FIG. 7, planarization films 50 and 52, an on-chip color filter 51, and an on-chip microlens 53 are formed on a photoelectric conversion unit 46 including a pixel electrode 40, a photoelectric conversion film 41, and a transparent electrode 42.
[Embodiment 2]
1. Configuration of Pixel Unit 200 FIG. 8 is a cross-sectional view of the pixel unit 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention.

Since the configuration other than the following is the same as that of the pixel unit 100, the description thereof is omitted.
An insulating film 47 is embedded in the lower part of the groove of the photoelectric conversion film 41. A transparent electrode 42 is formed on the photoelectric conversion film 41 and the insulating film 47. The upper surface of the insulating film 47 is lower than the upper surface of the photoelectric conversion film 41. Further, since the thickness of the transparent electrode 42 is smaller than half of the width of the groove between the pixels in the photoelectric conversion film 41, the transparent electrode 42 is attached to the inner wall of the groove of the photoelectric conversion film 41. The concave portion formed by the surface of the transparent electrode 42 remains in the groove without being completely filled. A metal wiring 145 is embedded in the concave portion of the transparent electrode 42. The portion where the metal wiring 145 is embedded also exists on the transparent electrode 42. The depth of the metal wiring 145 is such that the lowermost surface of the metal wiring 145 is below the upper surface of the photoelectric conversion film 41 and the transparent electrode 42 and the insulating film 47 can be formed under the lowermost surface of the metal wiring 145. There must be.
2. Effect Since the metal wiring 145 made of a material having a lower electrical resistivity than the material constituting the transparent electrode 42 is laminated on the transparent electrode 42 in the pixel region 61, the pixel region central portion 65 is the same as in the first embodiment. The voltage drop at can be suppressed. Furthermore, since the cross-sectional area of the metal wiring 145 is larger than the cross-sectional area of the metal wiring 45 in the first embodiment, the voltage drop at the pixel region central portion 65 can be further reduced.

Further, in this configuration, the metal wiring 145 is embedded in the concave shape portion where the groove of the transparent electrode 42 at the pixel boundary portion 43 is not completely filled. Furthermore, since the uppermost surface of the metal wiring 145 is formed below the upper surface of the photoelectric conversion film 41, the oblique incident light from the adjacent pixel can be shielded, and crosstalk due to the oblique incident light from the adjacent pixel is also caused. Can be suppressed. Further, since the metal wiring 145 is formed so that the transparent electrode 42 and the insulating film 47 exist below the lowermost surface thereof, the transparent electrode 42 can be configured to spread over the entire pixel region 61, and the electrode There is no short circuit.
3. Manufacturing Method With respect to the manufacturing method of the pixel portion 200 according to the second embodiment of the present invention, the main steps will be described with reference to FIG. 9, focusing on differences from the first embodiment of the present invention.

  In FIG. 9A, an insulating film 47 made of a CVD oxide film is formed in the groove of the photoelectric conversion film 41 separated at the pixel boundary 43. Here, the insulating film 47 is formed to be thicker than the pixel electrode 40 (for example, 100 nm to 300 nm). Next, on the insulating film 47 below the groove of the photoelectric conversion film 41 at the photoelectric conversion film 41 and the pixel boundary portion 43, the sidewall of the photoelectric conversion film 41 in the groove is made of ITO or ZnO by sputtering or CVD. The transparent electrode 42 is formed with a film thickness of, for example, several tens nm to several hundreds nm.

Next, in FIG. 9B, a metal such as Al, W, or Mo is deposited on the transparent electrode 42 with a film thickness of, for example, 100 nm to 300 nm based on sputtering or CVD. A metal is etched by a general photolithography technique and an etching technique, a metal film is formed in the groove, and a mesh-like metal wiring 45 is formed on the transparent electrode 42 at the pixel boundary 43.
[Embodiment 3]
1. Configuration of Pixel Unit 300 FIG. 10 is a cross-sectional view of the pixel unit 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention.

Since the configuration other than the following is the same as that of the pixel unit 100, the description thereof is omitted.
In the pixel portion 300, the photoelectric conversion film 41 is partitioned for each pixel by the pixel boundary portion 43. An insulating film 28 is formed on the pixel boundary portion 43. A sidewall pixel electrode 39 made of the same material as the pixel electrode 40 is formed on the sidewall of the insulating film 28, leaving the upper portion of the insulating film 28.

When the insulating film 28 is formed of a light shielding material, oblique incident light from adjacent pixels can be shielded, so that crosstalk due to oblique incident light from adjacent pixels can be suppressed.
2. Manufacturing Method A manufacturing method of the pixel unit 300 according to the third embodiment of the present invention will be described with reference to FIGS. 11 and 12, focusing on differences from the first embodiment of the present invention.

  In FIG. 11A, after the interlayer insulating film 22 is formed, an insulating film 28 made of an oxide film is deposited, for example, 100 nm to 1 μm based on the CVD method, and a pixel boundary portion is formed by a general photolithography technique and an etching technique. An insulating film 28 having a predetermined shape having an isolation width equivalent to 43 is formed.

  Next, in FIG. 11B, after forming the insulating film 28, metal wiring made of Al, W, Mo or the like is deposited on the pixel portion and the side wall portion of the insulating film 28 to 100 nm to 300 nm, and general photolithography is performed. The pixel electrode 40 and the sidewall pixel electrode 39 having a predetermined shape are formed by the technique and the etching technique. The area of the pixel electrode 40 is determined by the width of the insulating film 28 at the pixel boundary 43. If the separation width between pixels is 10% to 20% of the pixel size, the aperture ratio is estimated to be 64% to 81%.

  In FIG. 12A, after the pixel electrode 40 and the sidewall pixel electrode 39 are formed, the spectral sensitivity characteristics corresponding to the imaging purpose are obtained on the pixel electrode 40 and the sidewall pixel electrode 39 by plasma CVD, sputtering, and a coating apparatus. The α-Si film, the inorganic photoelectric conversion film, and the organic photoelectric conversion film are deposited to a thickness of, for example, 100 nm to 1 μm to form the photoelectric conversion film 41.

Next, in FIG. 12B, on the photoelectric conversion film 41 and the insulating film 28 at the pixel boundary 43, a transparent electrode 42 made of ITO or ZnO is deposited by sputtering or CVD, for example, by depositing several tens nm to several hundreds nm. To do. Further, a metal wiring 45 is formed on the transparent electrode 42 and above the insulating film 28.
[Other matters]
1. Shape of Metal Wiring In the embodiment according to the present invention, the shape of the metal wiring 45 is a mesh shape shown in FIG. 13A in which it passes between all adjacent pixel portions 100. In this case, since the cross-sectional area of the metal wiring 45 increases, the voltage drop at the pixel region central portion 65 is effectively suppressed. However, when the stripe shape shown in FIG. 13B is selected, there is an advantage that it is easy to form the metal wiring 45 in the manufacturing process. In addition, if the plurality of pixel portions 100 shown in FIG. 13C are collectively enclosed by the metal wiring 45, the material spent on the metal wiring 45 is reduced, so that cost reduction can be expected. A mesh-like metal wiring 45 is formed only around the pixel portion 100 in the pixel region central portion 65 shown in FIG. 13D, and at least a part of the other metal wiring 45 is connected to the pixel region peripheral portion 66. If this shape is adopted, it is possible to reduce the cost while suppressing the voltage drop at the pixel region central portion 65 where the influence of the voltage drop becomes particularly significant. In this way, a shape passing between some adjacent pixels may be taken. The same effect can be obtained even if the metal wiring 45 is formed only in at least a part of the pixel region 61.
2. Others The configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.

  For example, with respect to the arrangement of the pixels, in addition to the matrix (matrix) arrangement shown in the embodiment, a configuration in which the pixels are arranged by being rotated by 45 ° can be employed. For the color filter, an array such as a primary color Bayer array or a complementary color checkered array can be selected. The material of the metal wiring 45 can be selected from W, Mo, Ti and the like in addition to copper, aluminum and the like.

  The present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which deterioration of image quality is suppressed.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 5 Semiconductor substrate 15 Charge storage area 16 Floating diffusion 40 Pixel electrode 41 Photoelectric conversion film 42 Transparent electrode 44 Insulating film 45 Metal wiring 100 Pixel part 200 Pixel part 300 Pixel part 400 Pixel part

Claims (9)

A solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged,
A semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A lower electrode formed on the interlayer insulating film;
A photoelectric conversion film formed on the lower electrode;
A translucent upper electrode formed on the photoelectric conversion film;
Have
The upper electrode extends over the entire pixel area;
A solid-state imaging device characterized in that at least a part of the upper electrode is laminated with a metal wiring made of a material that passes between adjacent pixels and has a lower electrical resistivity than the material constituting the upper electrode. . The photoelectric conversion film and the lower electrode are partitioned for each pixel,
The solid-state imaging device according to claim 1, wherein an insulating film is interposed between the photoelectric conversion films of adjacent pixels. The insulating film is formed such that its upper surface is positioned lower than the upper surface of the photoelectric conversion film,
A groove is formed by the side wall of the photoelectric conversion film and the upper surface of the insulating film,
The upper electrode is formed along the inner wall of the groove,
In the groove, there remains a concave portion surrounded by the surface of the upper electrode,
The solid-state imaging device according to claim 2, wherein the metal wiring is embedded in the concave portion. The insulating film is interposed between a part of the photoelectric conversion films between the adjacent pixels,
Between the insulating film and the photoelectric conversion film,
The side wall pixel electrode, which is made of the same material as the lower electrode and is electrically connected to the lower electrode, is formed leaving the upper side wall of the insulating film. Solid-state imaging device. The solid-state imaging device according to claim 2, wherein the insulating film has a light shielding property. The metal wiring is
The solid-state imaging device according to claim 1, wherein when the surface of the semiconductor substrate is viewed in plan, the surface of the upper electrode is formed in a mesh shape or a stripe shape. A method for manufacturing a solid-state imaging device having a pixel region in which a plurality of pixels are two-dimensionally arranged,
Forming an interlayer insulating film on the semiconductor substrate;
Forming a lower electrode on the interlayer insulating film;
Forming a photoelectric conversion film on the lower electrode;
Forming a translucent upper electrode on the photoelectric conversion film so as to spread over the entire pixel region;
And at least part of the upper electrode includes a step of laminating a metal wiring made of a material having a lower electrical resistivity than a material constituting the upper electrode, passing between adjacent pixels. Manufacturing method of solid-state imaging device. In the step of forming the lower electrode, the lower electrode is formed in a state partitioned for each pixel,
In the step of forming the photoelectric conversion film, the photoelectric conversion film is formed in a state partitioned for each pixel,
After the step of forming the photoelectric conversion film,
Before the step of stacking the metal wiring,
Forming an insulating film so as to embed between the photoelectric conversion films of adjacent pixels;
The solid-state imaging device according to claim 7, further comprising: removing a part of the insulating film so that an upper surface of the insulating film is disposed at a position lower than an upper surface of the photoelectric conversion film. Production method. After the step of forming the interlayer insulating film,
Before the step of forming the lower electrode,
A step of standing an insulating film on the interlayer insulating film at a pixel boundary portion between adjacent pixels;
After the step of standing the insulating film,
Before the step of forming the photoelectric conversion film,
A step of depositing a side wall pixel electrode made of the same material as the lower electrode and electrically connected to the lower electrode on a side wall of the insulating film except for an upper portion thereof;
The method for manufacturing a solid-state imaging device according to claim 7, wherein, in the step of stacking the metallized wiring, the metal wiring is stacked on the insulating film between the adjacent pixels.

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