WO2013077121A1 - Solid state image pick-up device - Google Patents

Solid state image pick-up device Download PDF

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Publication number
WO2013077121A1
WO2013077121A1 PCT/JP2012/077059 JP2012077059W WO2013077121A1 WO 2013077121 A1 WO2013077121 A1 WO 2013077121A1 JP 2012077059 W JP2012077059 W JP 2012077059W WO 2013077121 A1 WO2013077121 A1 WO 2013077121A1
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WO
WIPO (PCT)
Prior art keywords
dummy
wiring
light
solid
state imaging
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PCT/JP2012/077059
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French (fr)
Japanese (ja)
Inventor
正治 米谷
正規 永瀬
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富士フイルム株式会社
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Publication of WO2013077121A1 publication Critical patent/WO2013077121A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Definitions

  • the present invention relates to a solid-state imaging device with less occurrence of crosstalk.
  • Digital cameras, mobile phones, and the like are provided with a backward imaging device for photographing a subject.
  • This solid-state imaging device has an imaging surface in which pixels that receive light and perform photoelectric conversion are arranged in a two-dimensional array.
  • Each pixel includes a photodiode (hereinafter referred to as PD) that performs photoelectric conversion to generate a signal charge, a microlens that collects light on the PD, a read transistor for reading the signal charge generated by the PD, and the like.
  • Peripheral circuit Each PD is formed on the surface layer of the semiconductor substrate.
  • an electrode such as a gate electrode of a reading transistor is provided in the vicinity of each PD.
  • a wiring layer having a plurality of wirings is provided above the semiconductor substrate. Each electrode is connected to the wiring layer by a columnar conductor called a plug.
  • the microlens is provided above the wiring layer, but there is no wiring or electrode between the microlens and the PD. For this reason, light incident perpendicularly to the microlens is incident on the PD without being blocked by the wiring and electrodes. However, when light is incident obliquely on the microlens, this light may be reflected by the wiring or electrode and may enter the PD of the adjacent pixel. This phenomenon is called crosstalk.
  • This crosstalk causes a decrease in contrast and the generation of a ghost image, which degrades the image quality.
  • the solid-state imaging device is for color photography and each pixel is provided with a color filter, if crosstalk occurs, color mixture occurs between the pixels and the color reproducibility of the subject decreases. Become.
  • Patent Document 1 it is proposed to suppress the occurrence of crosstalk by forming a light-shielding wall between two adjacent pixels in one of two orthogonal directions.
  • Patent Document 2 it is proposed to suppress the occurrence of crosstalk by forming a frame-shaped light shielding wall so as to surround the PD.
  • Patent Document 3 proposes that when wiring layers are stacked in multiple layers, the plugs connecting the wiring layers are made light-shielding, and the plugs are arranged so as to surround the PD, thereby suppressing the occurrence of crosstalk. Has been.
  • An object of the present invention is to provide a solid-state imaging device capable of miniaturizing pixels and preventing crosstalk.
  • the solid-state imaging device of the present invention includes a semiconductor substrate, a plurality of microlenses, a plurality of electrodes, a light shielding film, a wiring layer, a plug, and a light shielding body.
  • the semiconductor substrate is provided with a plurality of photoelectric conversion units that convert incident light into electric charges and store them.
  • the plurality of microlenses are provided above the semiconductor substrate and collect light on each photoelectric conversion unit.
  • the plurality of electrodes are provided around each photoelectric conversion unit on the semiconductor substrate.
  • the light shielding film is formed on each electrode.
  • the wiring layer is provided above the plurality of electrodes and has a plurality of wirings for reading signal charges from the respective photoelectric conversion units.
  • the plug electrically connects the electrode and the wiring.
  • the light shielding body includes a plurality of dummy plugs that are not electrically connected to electrodes and arranged in a frame shape surrounding each photoelectric conversion unit together with the plurality of electrodes.
  • each dummy plug is preferably not electrically connected to either or both of the wiring and the semiconductor substrate.
  • the plurality of dummy plugs be arranged at a narrower interval than the wavelength of light incident between adjacent dummy plugs.
  • the gap between adjacent dummy plugs is preferably filled with silicon oxide.
  • a color filter of red, green, or blue is provided between each photoelectric conversion unit and each microlens, and the interval between the dummy plugs is a portion where red light is incident. It is preferably about 400 nm or less, about 300 nm or less at a portion where green light is incident, and about 200 nm or less at a portion where blue light is incident.
  • the dummy plugs are arranged in parallel in a plurality of rows, and one of the two adjacent rows is displaced in the arrangement direction by a distance corresponding to half of the arrangement period with respect to the other row. Preferably it is.
  • each dummy plug is preferably formed between the semiconductor substrate and the wiring layer, the upper end is in contact with the wiring, and the lower end is separated from the surface of the semiconductor substrate.
  • a color filter of any one of red, green, and blue is provided between each photoelectric conversion unit and each microlens, and the lower end of each dummy plug is about 200 nm from the surface of the semiconductor substrate. It is preferable that the distance is ⁇ 400 nm.
  • the wiring layer may have a multilayer structure in which a plurality of wirings are stacked, and the dummy plug may be formed between the stacked layers.
  • an electrically isolated dummy wiring may be provided, and the dummy plug may not be connected to the wiring but connected to the dummy wiring.
  • the dummy plug may be formed above the electrode in addition to the region where the electrode above the semiconductor substrate is not formed.
  • the first distance from the dummy plug formed above the electrode to the electrode is substantially the same as the second distance from the dummy plug formed in the region where the electrode is not formed to the semiconductor substrate. Is preferred.
  • the first and second distances are preferably shorter than the wavelength of incident light.
  • the length of the dummy plug formed above the electrode is preferably substantially the same as the length of the dummy plug formed in the region where the electrode is not formed.
  • a plurality of dummy plugs that are not electrically connected to the electrodes are arranged in a frame shape surrounding each photoelectric conversion unit together with the plurality of electrodes, and a light shielding film is formed on each electrode. Therefore, crosstalk can be prevented after the pixels are miniaturized.
  • FIG. 5 is a partial cross-sectional view showing a VI-VI cross section of FIG. 4.
  • FIG. 5 is a partial cross-sectional view showing a VII-VII cross section of FIG. 4.
  • It is sectional drawing which shows the 1st process of the manufacturing method of a CMOS image sensor. It is sectional drawing which shows the 2nd process of the manufacturing method of a CMOS image sensor.
  • the CMOS image sensor 10 includes a pixel set 15 including a first pixel 11, a second pixel 12, a third pixel 13, and a fourth pixel 14.
  • Each of the pixels 11 to 14 is rectangular and has almost the same size.
  • the second pixel 12 is adjacent to the first pixel 11 in the vertical direction
  • the third pixel 13 is adjacent to the first pixel 11 in the horizontal direction.
  • the fourth pixel 14 is adjacent to the second pixel 12 in the horizontal direction and adjacent to the third pixel 13 in the vertical direction.
  • a plurality of pixel sets 15 are arranged in a square lattice pattern on the imaging surface.
  • the first pixel 11 includes a first photodiode (hereinafter referred to as PD) 11a, a first microlens 11b, and a first color filter 11c.
  • the first PD 11a is a photoelectric conversion unit that converts incident light into electric charge and accumulates it.
  • the first microlens 11b condenses light toward the first PD 11a.
  • the first color filter 11c causes only the green light out of the light collected by the first microlens 11b to enter the first PD 11a.
  • the second pixel 12 to the fourth pixel 14 are configured similarly to the first pixel 11, and the second PD 12a to the fourth PD 14a and the second micro lens 12b to the fourth micro lens 14b, respectively.
  • the second color filter 12c to the fourth color filter 14c are provided.
  • the second color filter 12c causes only the red light out of the light collected by the second microlens 12b to enter the second PD 12a.
  • the third color filter 13c causes only the blue light out of the light collected by the third microlens 13b to enter the third PD 13a.
  • the fourth color filter 14c causes only the green light of the light collected by the fourth microlens 14b to enter the fourth PD 14a.
  • the color filters 11c to 14c have a so-called Bayer array.
  • the pixel set 15 includes first to fourth readout transistors 21 to 24, first to third floating diffusions (hereinafter referred to as FD) 25 to 27, a reset transistor 28, an amplifier transistor 29, and a row selection transistor 30 are provided.
  • the CMOS image sensor 10 includes a vertical signal line 32, a power supply line 33, a first readout line 34, a second readout line 35, a third readout line 36, a fourth readout line 37, and a reset line 38.
  • a row selection line 39 is formed.
  • the vertical signal line 32 and the power supply line 33 extend in the vertical direction.
  • One vertical signal line 32 and one power supply line 33 are provided for each pixel set 15 and are used in common for each pixel set 15 arranged in the vertical direction.
  • the first to fourth readout lines 34 to 37, the reset line 38, and the row selection line 39 extend in the horizontal direction.
  • Each of these lines 34 to 39 is provided for each pixel set 15 and is used in common for each pixel set 15 arranged in the horizontal direction.
  • the vertical signal line 32 is used for reading a signal voltage.
  • the power supply line 33 is used to supply the power supply voltage VDD.
  • the first to fourth read lines 34 to 37 are used to input read signals to the first to fourth read transistors 21 to 24, respectively.
  • the reset line 38 is used for inputting a reset signal to the reset transistor 28.
  • the row selection line 39 is used for inputting a row selection signal to the row selection transistor 30.
  • the anodes of the first to fourth PDs 11a to 14a are grounded, and the cathodes are connected to the sources of the first to fourth readout transistors 21 to 24, respectively.
  • the gates of the first to fourth read transistors 21 to 24 are connected to the first to fourth read lines 34 to 37, respectively.
  • the drain of the first read transistor 21 and the drain of the second read transistor 22 are commonly connected to the first FD 25. Further, the drain of the third read transistor 23 and the drain of the fourth read transistor 24 are commonly connected to the second FD 26.
  • the signal charge accumulated in the first PD 11a is changed to the first value. 1 is read into the FD 25.
  • the signal accumulated in the second PD 12a By inputting a read signal to the gate of the second read transistor 22 via the second read line 35 and turning on the second read transistor 22, the signal accumulated in the second PD 12a. The charge is read out to the first FD 25.
  • the signal charge accumulated in the third PD 13a is changed to the first value. 2 to the FD 26.
  • the signal accumulated in the fourth PD 14a is changed to the first value. 2 to the FD 26.
  • the signal accumulated in the fourth PD 14a is read out to the second FD 26.
  • the first to third FDs 25 to 27 are electrically connected by wiring 40.
  • the first to third FDs 25 to 27 that are electrically connected to each other instantaneously distribute charges according to their respective capacities. Potential.
  • the signal charges read from the first PD 11a and the second PD 12a are accumulated in the first FD 25, and also accumulated in the second FD 26 and the third FD 27. Charges are distributed according to the capacity of the third FDs 25 to 27 and the wiring 40 to have the same potential.
  • the signal charges read from the third PD 13a and the fourth PD 14a are accumulated in the second FD 26 and also accumulated in the first FD 25 and the third FD 27, and the first to third The electric charges are distributed according to the capacitances of the FDs 25 to 27 and the wiring 40 to have the same potential.
  • the reset transistor 28 has a source connected to the third FD 27, a drain connected to the power supply line 33, and a gate connected to the reset line 38.
  • the reset transistor 28 is used when discharging signal charges accumulated in the first to third FDs 25 to 27 and resetting them to a predetermined potential.
  • the potential of the third FD 27 is reset to the potential of the power supply voltage VDD and is electrically connected to the third FD 27.
  • the potentials of the first and second FDs 25 and 26 thus reset are also reset to the potential of the power supply voltage VDD.
  • the drain of the amplifier transistor 29 is connected to the power supply line 33, the source is connected to the drain of the row selection transistor 30, and the gate is connected to the third FD 27.
  • the row selection transistor 30 has a drain connected to the source of the amplifier transistor 29, a source connected to the vertical signal line 32, and a gate connected to the row selection line 39.
  • the amplifier transistor 29 forms a source follower circuit, and outputs a voltage corresponding to the signal charge stored in the first to third FDs 25 to 27 as a signal voltage.
  • the row selection transistor 30 is used to select a row for transferring a signal voltage to the vertical signal line 32.
  • each of the PDs 11a to 14a has a signal charge.
  • start accumulating After a predetermined exposure time has elapsed, a read signal is input only to the first read transistor 21, and the signal charge of the first PD 11 a is transferred to the first FD 25.
  • the first to third FDs 25 to 27 electrically connected to each other instantaneously distribute charges according to their respective capacities, so that they have the same signal potential.
  • a signal voltage corresponding to the signal charge accumulated in the first to third FDs 25 to 27 is generated by the amplifier transistor 29.
  • the transistors 28 to 30 necessary for reading are provided one by one for the pixel set 15, so that the pixel size is smaller than when the transistors 28 to 30 are provided for each pixel. It is small and the pixel can be miniaturized.
  • the CMOS image sensor 10 is formed on a P-type semiconductor substrate 50.
  • the microlenses 11b to 14b and the color filters 11c to 14c are not shown.
  • the first to fourth PDs 11 a to 14 a are configured by an N-type impurity diffusion layer formed in the surface layer of the semiconductor substrate 50 and a PN junction between the impurity diffusion layer and the semiconductor substrate 50.
  • a first FD 25 is provided between the first PD 11a and the second PD 12a.
  • a second FD 26 is provided between the third PD 13a and the fourth PD 14a.
  • the first and second FDs 25 and 26 are formed by N-type impurity diffusion layers formed in the surface layer of the semiconductor substrate 50.
  • the first FD 25 is disposed across the first pixel 11 and the second pixel 12 at approximately the center between the first PD 11a and the second PD 12a.
  • the second FD 26 is disposed across the third pixel 13 and the fourth pixel 14 at approximately the center between the third PD 13a and the fourth PD 14a.
  • first to fourth read gate electrodes 51 to 54 which are gate electrodes of the first to fourth read transistors 21 to 24, are provided.
  • the first read gate electrode 51 is disposed so as to straddle the first PD 11a and the first FD 25.
  • the first read gate electrode 51 is connected to a wiring 55 that is a part of the first read line 34 via a plug 56.
  • the wiring 55 is laminated and formed above the semiconductor substrate 50 so that a part of the wiring 55 overlaps the first read gate electrode 51.
  • the plug 56 is a columnar (square columnar or columnar) conductive connecting member extending in a direction substantially orthogonal to the surface of the semiconductor substrate 50, and is formed of a metal material such as tungsten, for example.
  • the CMOS image sensor 10 has a plurality of plugs in addition to the plug 56. Similarly, a metal material such as tungsten is used for each of these plugs.
  • the first read transistor 21 includes an N-type impurity diffusion layer of the first PD 11a, an N-type impurity diffusion layer of the first FD 25, and a first read gate electrode 51. By inputting a read signal to the first read gate electrode 51, the signal charge accumulated in the first PD 11a is read to the first FD 25.
  • the second read gate electrode 52 is disposed so as to straddle the second PD 12a and the first FD 25.
  • the second read gate electrode 52 is connected to a wiring 57 that is a part of the second read line 35 via a plug 58.
  • the third read gate electrode 53 is disposed so as to straddle the third PD 13a and the second FD 26.
  • the third read gate electrode 53 is connected to a wiring 59 that is a part of the third read line 36 via a plug 60.
  • the fourth read gate electrode 54 is disposed so as to straddle the fourth PD 14 a and the second FD 26.
  • the fourth read gate electrode 54 is connected to a wiring 61 that is a part of the fourth read line 37 via a plug 62. Since these structures are the same as those of the first read gate electrode 51, detailed description thereof is omitted.
  • Each wiring 55, 57, 59, 61 is made of aluminum or copper.
  • each wiring 55, 57, 59, 61 is partially shown for simplification. In practice, these are drawn out to the outside through a plug or wiring (not shown) to constitute the readout lines 34-37.
  • a plug or wiring not shown
  • the description is omitted because they are the same.
  • a third FD 27, a reset drain 64, and a reset gate electrode 65 are provided between the fourth PD 14a and the third PD 13a of the adjacent pixel set 15.
  • An amplifier gate electrode 66, a row selection gate electrode 67, and a row selection source 68 are provided between the second PD 12a and the first PD 11a of the adjacent pixel set 15.
  • the third FD 27 and the reset drain 64 are formed by an N-type impurity diffusion layer formed in the surface layer of the semiconductor substrate 50. In addition, the third FD 27 and the reset drain 64 are disposed across these pixels at the approximate center between the fourth PD 14 a and the third PD 13 a of the adjacent pixel set 15.
  • the third FD 27 is electrically connected to the first FD 25, the second FD 26, and the amplifier gate electrode 66 through the wiring 70.
  • the wiring 70 is H-shaped, and is stacked on the semiconductor substrate 50 so that the four end portions thereof overlap the first FD 25, the second FD 26, the third FD 27, and the amplifier gate electrode 66, respectively. ing.
  • plugs 71 to 73 are provided, respectively.
  • a plug 74 is provided in a region where the amplifier gate electrode 66 and the wiring 70 overlap.
  • the first to third FDs 25 to 27 and the amplifier gate electrode 66 are electrically connected by plugs 71 to 74, respectively.
  • the FDs 25, 26, 27 and the amplifier gate electrode 66 have the same potential, and this potential is applied to the gate of the amplifier transistor 29.
  • the reset drain 64 constituting the drain of the reset transistor 28 is connected to a wiring 75 which is a part of the power supply line 33 through a plug 76.
  • the wiring 75 is stacked above the semiconductor substrate 50 so that part of the wiring 75 overlaps the reset drain 64.
  • the plug 76 electrically connects the stacked wiring 75 and the reset drain 64. As a result, the potential of the reset drain 64 is the power supply voltage VDD.
  • the amplifier gate electrode 66 is also close to the N-type impurity diffusion layer 84 that forms the drain of the amplifier transistor 29.
  • the impurity diffusion layer 84 is connected to a wiring 75 that is a part of the power supply line 33 via a plug 85.
  • the insulating film 100 is formed on the surface of the semiconductor substrate 50.
  • the insulating film 100 is a transparent film formed of silicon oxide or the like, and prevents the gate electrodes 51 to 54 and 65 to 67 from coming into contact with the surface of the semiconductor substrate 50, as well as protecting the surface of the semiconductor substrate 50, The interface state due to image quality degradation is reduced.
  • the gate electrodes 51 to 54 and 65 to 67 are formed of polysilicon or the like on the insulating film 100.
  • a light shielding film 102 is provided on the gate electrodes 51 to 54 and 65 to 67. These light shielding films 102 are made of a light shielding material such as tungsten silicide. Each light shielding film 102 reflects light directed toward the gate electrodes 51 to 54 and 65 to 67, thereby preventing light from entering the gate electrodes 51 to 54 and 65 to 67.
  • a first oxide film 94 is formed on the insulating film 100 so as to cover the gate electrodes 51 to 54 and 65 to 67 and the light shielding film 102.
  • the wiring 55, 57, 59, 61, 70, 75, 81, etc. for reading the signal charges accumulated in the PDs 11a to 14a to the outside are provided. Is provided.
  • wirings 105, 106, 111 to 113, etc. are provided as the first-layer wiring. Among these, the wirings 106 and 111 to 113 are connected to the dummy plug 92.
  • a second oxide film 95 is formed so as to cover each wiring in the first layer.
  • second-layer wirings such as wirings 107 to 110 and 114 to 116 are provided.
  • a third oxide film 96 is formed so as to cover each wiring in the second layer.
  • the color filters 11c to 14c are formed. Similar to the first oxide film 94, the second oxide film 95 and the third oxide film 96 are formed of silicon oxide or the like.
  • the wiring layer 104 includes a first-layer wiring on the first oxide film 94, a second oxide film 95, a second-layer wiring on the second oxide film 95, and a third oxide film. This is a layer structure constituted by the film 96.
  • the first-layer wiring and the second-layer wiring are connected by a plug (not shown).
  • the wiring layer 104 is not limited to two layers, and may be three or more layers.
  • Each dummy plug 92 is arranged in a region other than above the gate electrodes 51 to 54 and 65 to 67. Each dummy plug 92 has an upper end in contact with each wiring of the first layer and a lower end slightly separated from the surface of the semiconductor substrate 50. The distance between the lower end of each dummy plug 92 and the surface of the semiconductor substrate 50 is preferably about 200 nm to 400 nm. As described above, each dummy plug 92 is not electrically connected to the semiconductor substrate 50 and the wiring layer 104.
  • the light shielding body 90 is configured by the gate electrodes 65, 66, and 67 disposed between the pixels and the dummy plug 92 disposed along the gate electrodes 65, 66, and 67, a dedicated light shielding body 90 is provided. There is no need for a region, and miniaturization of each of the pixels 11 to 14 is not hindered.
  • the light shielding film 102 is provided on each of the gate electrodes 51 to 54 and 65 to 67, and the light directed to each of the gate electrodes 51 to 54 and 65 to 67 is reflected by each light shielding film 102, Occurrence of so-called crosstalk in which light passes through the gate electrode and enters an adjacent pixel can be suppressed.
  • a resist mask is formed by well-known photolithography, and doping (ion implantation) is performed on a predetermined region of the semiconductor substrate 50, whereby PDs 11a to 14a made of N-type impurity diffusion layers, FDs 25 to 27, a reset drain 64, a row selection source 68, and the like are formed.
  • an insulating film 100 is formed on the surface of the semiconductor substrate 50.
  • Polysilicon and tungsten silicide are sequentially deposited on the insulating film 100, and gate electrodes 51 to 54 and 65 to 67 made of polysilicon and a light shielding film 102 made of tungsten silicide are formed by photolithography and etching.
  • a first oxide film 94 made of silicon oxide is stacked on the semiconductor substrate 50 so as to cover the gate electrodes 51 to 54 and 65 to 67 and the light shielding film 102.
  • the first oxide film 94 has a thickness corresponding to the height of each wiring in the first layer of the wiring layer 104. Irregularities corresponding to the shapes of the gate electrodes 51 to 54 and 65 to 67 are formed on the surface of the first oxide film 94.
  • the surface of the first oxide film 94 is planarized as shown in FIG.
  • the resist 120 is removed, tungsten 124 is deposited on the first oxide film 94, and tungsten 124 is embedded in each hole 123. Thereafter, as shown in FIG. 13, CMP is performed on the tungsten 124, and the tungsten 124 is ground until the surface of the first oxide film 94 is exposed. As a result, plugs 56, 58, etc. are formed in the first oxide film 94.
  • a resist 126 is applied on the first oxide film 94.
  • the resist 126 is subjected to a photolithography process to form a pattern corresponding to the dummy plug 92.
  • a plurality of holes 127 corresponding to the shape of each dummy plug 92 are formed. In this etching, the etching conditions are adjusted so that each hole 127 does not penetrate the first oxide film 94 and the insulating film 100 and reach the surface of the semiconductor substrate 50.
  • each dummy plug 92 is formed in the first oxide film 94, the upper end is brought into contact with each wiring of the first layer, and the lower end is separated from the surface of the semiconductor substrate 50.
  • the lower end of each dummy plug 92 may be brought into contact with the surface of the semiconductor substrate 50 and the upper end may be separated from the wiring.
  • the upper end and the lower end of the dummy plug 92 may be separated from both the surface of the semiconductor substrate 50 and the wiring.
  • a dummy plug 146 whose vertical length is shorter than that of the dummy plug 92 may be provided in the first oxide film 94 above the gate electrodes 65, 66 and 67.
  • the dummy plug 146 has an upper end connected to the first-layer wiring 105 and a lower end separated from the surface of the gate electrode 67 (the light shield 102).
  • a dummy plug 146 may be provided at a position where there is no wiring.
  • the first distance D1 from the lower end of the dummy plug 146 to the surface of the gate electrode 67 (the light shielding body 102) is substantially the same as the second distance D2 from the lower end of the dummy plug 92 to the surface of the semiconductor substrate 50 (the insulating film 100). They are set the same.
  • the first and second distances D1 and D2 are preferably shorter than the wavelength of the incident light. For example, in the region where blue light is incident, the wavelength in the first oxide film 94 is about 310 nm. For this reason, the first and second distances D1 and D2 are shorter than 310 nm, for example, about 200 nm.
  • the first and second distances D1 and D2 are not necessarily the same and may be different.
  • the vertical length of the dummy plug 92 may be the same as the vertical length of the dummy plug 146.
  • the dummy plugs 92 and 146 can be manufactured in the same manufacturing process. As described above, by shortening the length of the dummy plug 92, the light shielding effect is slightly reduced, but the manufacturing efficiency is improved and the area where the dummy plug can be disposed is widened.
  • CMOS image sensor is exemplified as the solid-state imaging device, but the present invention can also be applied to a solid-state imaging device such as a CCD image sensor.
  • First to fourth color filters 50 Semiconductor substrate 51 to 54, 65 to 67 Gate electrode 55, 57, 59, 61, 70, 75, 81 Wiring 56, 58, 60, 62, 73, 74, 76 , 78, 82 Plug 90 Light shielding body 92 Dummy plug 102 Light shielding film 104 Wiring layer

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Abstract

Provided is a solid state image pick-up device that can refine pixels and prevent crosstalk. A CMOS image sensor (10) is provided with a frame-shaped light-blocking body (90) that surrounds the perimeters of each of first through fourth PDs (11a-14a). The light-blocking body (90) has dummy plugs (92) arranged together with gate electrodes (65, 66, 67). The dummy plugs (92) are not electrically connected to the gate electrodes (65, 66, 67). On the surface of the gate electrodes (51-54, 65-67) a light-blocking film (102) is provided.

Description

固体撮像装置Solid-state imaging device
　本発明は、クロストークの発生が少ない固体撮像装置に関する。 The present invention relates to a solid-state imaging device with less occurrence of crosstalk.
　デジタルカメラや携帯電話等では、被写体を撮影するために、後退撮像装置が設けられている。この固体撮像装置は、光を受光して光電変換を行う画素を二次元アレイ状に並べた撮像面を有する。各画素は、光電変換を行って信号電荷を生成するフォトダイオード（以下ＰＤと称す）と、ＰＤに光を集光するマイクロレンズと、ＰＤにより生成された信号電荷を読み出すための読み出しトランジスタなどの周辺回路とを有する。各ＰＤは、半導体基板の表層に形成されている。この半導体基板の表面上には、各ＰＤに近接して読み出しトランジスタのゲート電極などの電極が設けられている。この半導体基板の上方には、複数の配線を有する配線層が設けられている。各電極は、プラグと呼ばれる柱状の導体によって配線層に接続されている。 Digital cameras, mobile phones, and the like are provided with a backward imaging device for photographing a subject. This solid-state imaging device has an imaging surface in which pixels that receive light and perform photoelectric conversion are arranged in a two-dimensional array. Each pixel includes a photodiode (hereinafter referred to as PD) that performs photoelectric conversion to generate a signal charge, a microlens that collects light on the PD, a read transistor for reading the signal charge generated by the PD, and the like. Peripheral circuit. Each PD is formed on the surface layer of the semiconductor substrate. On the surface of the semiconductor substrate, an electrode such as a gate electrode of a reading transistor is provided in the vicinity of each PD. A wiring layer having a plurality of wirings is provided above the semiconductor substrate. Each electrode is connected to the wiring layer by a columnar conductor called a plug.
　マイクロレンズは、配線層の上方に設けられているが、配線や電極は、マイクロレンズとＰＤとの間には存在しない。このため、マイクロレンズに垂直に入射した光は、配線や電極に遮られずにＰＤに入射する。しかし、マイクロレンズに対して斜めに光が入射すると、この光は、配線や電極によって反射され、隣接する画素のＰＤに入射することがある。この現象は、クロストークと呼ばれている。 The microlens is provided above the wiring layer, but there is no wiring or electrode between the microlens and the PD. For this reason, light incident perpendicularly to the microlens is incident on the PD without being blocked by the wiring and electrodes. However, when light is incident obliquely on the microlens, this light may be reflected by the wiring or electrode and may enter the PD of the adjacent pixel. This phenomenon is called crosstalk.
　このクロストークは、コントラストの低下やゴースト像の発生を招き、画質を低下させてしまう。特に、固体撮像装置がカラー撮影用であり、各画素にカラーフィルタが設けられている場合には、クロストークが生じると、画素間での混色が生じ、被写体の色再現性が低下することになる。 This crosstalk causes a decrease in contrast and the generation of a ghost image, which degrades the image quality. In particular, when the solid-state imaging device is for color photography and each pixel is provided with a color filter, if crosstalk occurs, color mixture occurs between the pixels and the color reproducibility of the subject decreases. Become.
　クロストークを防止する種々の技術が提案されている。特許文献１では、直交する２方向の１つで隣接している２つの画素間に遮光壁を形成することにより、クロストークの発生を抑えることが提案されている。特許文献２では、ＰＤを囲うように枠状の遮光壁を形成することによりクロストークの発生を抑えることが提案されている。特許文献３には、配線層が多層に積層されている場合に、配線層間を連結するプラグを遮光性とし、ＰＤを囲うようにプラグを配列することにより、クロストークの発生を抑えることが提案されている。 Various techniques for preventing crosstalk have been proposed. In Patent Document 1, it is proposed to suppress the occurrence of crosstalk by forming a light-shielding wall between two adjacent pixels in one of two orthogonal directions. In Patent Document 2, it is proposed to suppress the occurrence of crosstalk by forming a frame-shaped light shielding wall so as to surround the PD. Patent Document 3 proposes that when wiring layers are stacked in multiple layers, the plugs connecting the wiring layers are made light-shielding, and the plugs are arranged so as to surround the PD, thereby suppressing the occurrence of crosstalk. Has been.
特開２００４－１０４２０３号公報JP 2004-104203 A 特開２００７－０８０９１８号公報JP 2007-080918 A 特開２００８－１０８９１７号公報JP 2008-108917 A
　しかしながら、画素の高密度化を図るために、画素の微細化すると、ＰＤと、このＰＤに近接して設けられた電極との距離が近くなる。これらの電極は、ポリシリコン等の透光性材料で形成されるため、画素の微細化に伴い、電極を透過した光が隣接する画素のＰＤに入射しやすくなるという新たなクロストークの要因が発生してしまう。各特許文献１～３では、遮光性部材でＰＤを囲うことによってクロストークの抑制が図られているが、電極を透過した光に起因するクロストークを抑制することはできない。 However, if the pixel is miniaturized in order to increase the density of the pixel, the distance between the PD and the electrode provided in the vicinity of the PD becomes shorter. Since these electrodes are formed of a light-transmitting material such as polysilicon, a new cause of crosstalk is that light transmitted through the electrodes is likely to be incident on the PD of an adjacent pixel as the pixel is miniaturized. Will occur. In each of Patent Documents 1 to 3, crosstalk is suppressed by enclosing the PD with a light-shielding member, but crosstalk caused by light transmitted through the electrodes cannot be suppressed.
　また、特許文献１～３では、いずれも画素とは別に、クロストークを抑制するための遮光性部材を設けるための専用の領域が必要であるため、画素の微細化に不利であるという問題がある。 Further, in each of Patent Documents 1 to 3, since a dedicated area for providing a light-shielding member for suppressing crosstalk is required separately from the pixels, there is a problem that it is disadvantageous for pixel miniaturization. is there.
　本発明は、画素の微細化を図るとともに、クロストークを防止することができる固体撮像装置を提供することを目的とする。 An object of the present invention is to provide a solid-state imaging device capable of miniaturizing pixels and preventing crosstalk.
　上記目的を達成するため、本発明の固体撮像装置は、半導体基板と、複数のマイクロレンズと、複数の電極と、遮光膜と、配線層と、プラグと、遮光体とを備えている。半導体基板は、入射した光を電荷に変換して蓄積する複数の光電変換部が配設されている。複数のマイクロレンズは、半導体基板の上方に設けられ、各光電変換部に光を集光する。複数の電極は、半導体基板上で各光電変換部の周囲に設けられている。遮光膜は、各電極上に形成されている。配線層は、複数の電極の上方に設けられ、各光電変換部から信号電荷を読み出すための複数の配線を有する。プラグは、電極と配線とを電気的に接続する。遮光体は、電極と電気的に非接続の複数のダミープラグが、複数の電極とともに各光電変換部を囲う枠状に配置されてなる。 In order to achieve the above object, the solid-state imaging device of the present invention includes a semiconductor substrate, a plurality of microlenses, a plurality of electrodes, a light shielding film, a wiring layer, a plug, and a light shielding body. The semiconductor substrate is provided with a plurality of photoelectric conversion units that convert incident light into electric charges and store them. The plurality of microlenses are provided above the semiconductor substrate and collect light on each photoelectric conversion unit. The plurality of electrodes are provided around each photoelectric conversion unit on the semiconductor substrate. The light shielding film is formed on each electrode. The wiring layer is provided above the plurality of electrodes and has a plurality of wirings for reading signal charges from the respective photoelectric conversion units. The plug electrically connects the electrode and the wiring. The light shielding body includes a plurality of dummy plugs that are not electrically connected to electrodes and arranged in a frame shape surrounding each photoelectric conversion unit together with the plurality of electrodes.
　なお、各ダミープラグは、配線及び半導体基板のいずれか一方または両方と電気的に非接続であることが好ましい。 Note that each dummy plug is preferably not electrically connected to either or both of the wiring and the semiconductor substrate.
　また、複数のダミープラグは、隣り合うダミープラグとの間に入射する光の波長よりも狭い間隔で配置されていることが好ましい。隣り合うダミープラグとの間は、酸化シリコンにより埋められていることが好ましい。 In addition, it is preferable that the plurality of dummy plugs be arranged at a narrower interval than the wavelength of light incident between adjacent dummy plugs. The gap between adjacent dummy plugs is preferably filled with silicon oxide.
　この場合、各光電変換部と各マイクロレンズとの間には、赤色、緑色、青色のいずれかの色のカラーフィルタが設けられており、ダミープラグの間隔は、赤色の光が入射する部分では約４００ｎｍ以下であり、緑色の光が入射する部分では約３００ｎｍ以下であり、青色の光が入射する部分では約２００ｎｍ以下であることが好ましい。 In this case, a color filter of red, green, or blue is provided between each photoelectric conversion unit and each microlens, and the interval between the dummy plugs is a portion where red light is incident. It is preferably about 400 nm or less, about 300 nm or less at a portion where green light is incident, and about 200 nm or less at a portion where blue light is incident.
　また、ダミープラグは、複数列に並列して配置され、隣接する２列のうち一方の列は、他方の列に対して、配列周期の半分に相当する距離だけ、配列方向に位置がずれていることが好ましい。 The dummy plugs are arranged in parallel in a plurality of rows, and one of the two adjacent rows is displaced in the arrangement direction by a distance corresponding to half of the arrangement period with respect to the other row. Preferably it is.
　また、各ダミープラグは、半導体基板と配線層との間に形成され、上端が配線に接触し、下端が半導体基板の表面から離れていることが好ましい。この場合、各光電変換部と各マイクロレンズとの間には、赤色、緑色、青色のいずれかの色のカラーフィルタが設けられており、各ダミープラグの下端は、半導体基板の表面から約２００ｎｍ～４００ｎｍ離れていることが好ましい。 Also, each dummy plug is preferably formed between the semiconductor substrate and the wiring layer, the upper end is in contact with the wiring, and the lower end is separated from the surface of the semiconductor substrate. In this case, a color filter of any one of red, green, and blue is provided between each photoelectric conversion unit and each microlens, and the lower end of each dummy plug is about 200 nm from the surface of the semiconductor substrate. It is preferable that the distance is ˜400 nm.
　また、配線層は、複数の配線が積層された多層構造であり、ダミープラグは、積層された各層の間に形成されていてもよい。 The wiring layer may have a multilayer structure in which a plurality of wirings are stacked, and the dummy plug may be formed between the stacked layers.
　また、電気的に孤立したダミー配線を備え、ダミープラグは、配線には接続されず、ダミー配線に接続されていてもよい。 Also, an electrically isolated dummy wiring may be provided, and the dummy plug may not be connected to the wiring but connected to the dummy wiring.
　また、ダミープラグは、半導体基板の上方の電極が形成されていない領域に加えて、電極の上方にも形成されていてもよい。この場合、電極の上方に形成されたダミープラグから電極までの第１の距離は、電極が形成されていない領域に形成されたダミープラグから半導体基板までの第２の距離とほぼ同一であることが好ましい。この第１及び第２の距離は、入射する光の波長よりも短いことが好ましい。 Further, the dummy plug may be formed above the electrode in addition to the region where the electrode above the semiconductor substrate is not formed. In this case, the first distance from the dummy plug formed above the electrode to the electrode is substantially the same as the second distance from the dummy plug formed in the region where the electrode is not formed to the semiconductor substrate. Is preferred. The first and second distances are preferably shorter than the wavelength of incident light.
　また、電極の上方に形成されたダミープラグの長さは、電極が形成されていない領域に形成されたダミープラグの長さとほぼ同一であることが好ましい。 Also, the length of the dummy plug formed above the electrode is preferably substantially the same as the length of the dummy plug formed in the region where the electrode is not formed.
　本発明によれば、電極と電気的に非接続の複数のダミープラグが、複数の電極とともに各光電変換部を囲う枠状に配置されており、また、各電極上に遮光膜が形成されているので、画素の微細化を図った上で、クロストークを防止することができる。 According to the present invention, a plurality of dummy plugs that are not electrically connected to the electrodes are arranged in a frame shape surrounding each photoelectric conversion unit together with the plurality of electrodes, and a light shielding film is formed on each electrode. Therefore, crosstalk can be prevented after the pixels are miniaturized.
ＣＭＯＳイメージセンサの構成を示す平面図である。It is a top view which shows the structure of a CMOS image sensor. 画素セットの構成を示す回路図である。It is a circuit diagram which shows the structure of a pixel set. 画素セットの構成を示すレイアウト図である。FIG. 6 is a layout diagram illustrating a configuration of a pixel set. 配線を省略した状態の画素セットのレイアウト図である。It is a layout diagram of a pixel set in a state where wiring is omitted. 図４の部分拡大図である。It is the elements on larger scale of FIG. 図４のＶＩ－ＶＩ断面を示す部分断面図である。FIG. 5 is a partial cross-sectional view showing a VI-VI cross section of FIG. 4. 図４のＶＩＩ－ＶＩＩ断面を示す部分断面図である。FIG. 5 is a partial cross-sectional view showing a VII-VII cross section of FIG. 4. ＣＭＯＳイメージセンサの製造方法の第１工程を示す断面図である。It is sectional drawing which shows the 1st process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第２工程を示す断面図である。It is sectional drawing which shows the 2nd process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第３工程を示す断面図である。It is sectional drawing which shows the 3rd process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第４工程を示す断面図である。It is sectional drawing which shows the 4th process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第５工程を示す断面図である。It is sectional drawing which shows the 5th process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第６工程を示す断面図である。It is sectional drawing which shows the 6th process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第７工程を示す断面図である。It is sectional drawing which shows the 7th process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第８工程を示す断面図である。It is sectional drawing which shows the 8th process of the manufacturing method of a CMOS image sensor. ＣＭＯＳイメージセンサの製造方法の第９工程を示す断面図である。It is sectional drawing which shows the 9th process of the manufacturing method of a CMOS image sensor. ダミープラグを３列に配置した遮光体を示すレイアウト図である。It is a layout figure which shows the light shielding body which has arrange | positioned the dummy plug in 3 rows. 第１及び第２の酸化膜中にダミープラグを形成した例を示す断面図である。It is sectional drawing which shows the example which formed the dummy plug in the 1st and 2nd oxide film. 配線が設けられていない領域にダミープラグを形成した例を示す断面図である。It is sectional drawing which shows the example which formed the dummy plug in the area | region where wiring is not provided. ダミープラグをダミー配線に接続した例を示す断面図である。It is sectional drawing which shows the example which connected the dummy plug to the dummy wiring. ゲート電極の上方の第２の酸化膜中にダミープラグを形成した例を示す断面図である。It is sectional drawing which shows the example which formed the dummy plug in the 2nd oxide film above a gate electrode. ゲート電極の上方の第１及び第２の酸化膜中にダミープラグを形成した例を示す断面図である。It is sectional drawing which shows the example which formed the dummy plug in the 1st and 2nd oxide film above a gate electrode. 第１の酸化膜中の各ダミープラグを同一構成とした例を示す断面図である。It is sectional drawing which shows the example which made each dummy plug in a 1st oxide film the same structure.
　図１において、ＣＭＯＳイメージセンサ１０は、第１の画素１１、第２の画素１２、第３の画素１３、第４の画素１４からなる画素セット１５を有する。各画素１１～１４は、矩形状であり、それぞれほぼ同一の大きさである。第２の画素１２は、第１の画素１１の垂直方向に隣接しており、第３の画素１３は、第１の画素１１の水平方向に隣接している。第４の画素１４は、第２の画素１２の水平方向に隣接するとともに、第３の画素１３の垂直方向に隣接している。画素セット１５は、撮像面上に正方格子状に複数並べられている。 1, the CMOS image sensor 10 includes a pixel set 15 including a first pixel 11, a second pixel 12, a third pixel 13, and a fourth pixel 14. Each of the pixels 11 to 14 is rectangular and has almost the same size. The second pixel 12 is adjacent to the first pixel 11 in the vertical direction, and the third pixel 13 is adjacent to the first pixel 11 in the horizontal direction. The fourth pixel 14 is adjacent to the second pixel 12 in the horizontal direction and adjacent to the third pixel 13 in the vertical direction. A plurality of pixel sets 15 are arranged in a square lattice pattern on the imaging surface.
　第１の画素１１は、第１のフォトダイオード（以下ＰＤと称す）１１ａと、第１のマイクロレンズ１１ｂと、第１のカラーフィルタ１１ｃとを有している。第１のＰＤ１１ａは、入射した光を電荷に変換して蓄積する光電変換部である。第１のマイクロレンズ１１ｂは、第１のＰＤ１１ａに向けて光を集光する。第１のカラーフィルタ１１ｃは、第１のマイクロレンズ１１ｂが集光した光のうち緑色の光のみを第１のＰＤ１１ａに入射させる。 The first pixel 11 includes a first photodiode (hereinafter referred to as PD) 11a, a first microlens 11b, and a first color filter 11c. The first PD 11a is a photoelectric conversion unit that converts incident light into electric charge and accumulates it. The first microlens 11b condenses light toward the first PD 11a. The first color filter 11c causes only the green light out of the light collected by the first microlens 11b to enter the first PD 11a.
　第２の画素１２～第４の画素１４は、第１の画素１１と同様に構成されており、それぞれ第２のＰＤ１２ａ～第４のＰＤ１４ａ、第２のマイクロレンズ１２ｂ～第４のマイクロレンズ１４ｂ、第２のカラーフィルタ１２ｃ～第４のカラーフィルタ１４ｃを有している。第２のカラーフィルタ１２ｃは、第２のマイクロレンズ１２ｂが集光した光のうち赤色の光のみを第２のＰＤ１２ａに入射させる。第３のカラーフィルタ１３ｃは、第３のマイクロレンズ１３ｂが集光した光のうち青色の光のみを第３のＰＤ１３ａに入射させる。第４のカラーフィルタ１４ｃは、第４のマイクロレンズ１４ｂが集光した光のうち緑色の光のみを第４のＰＤ１４ａに入射させる。このように、カラーフィルタ１１ｃ～１４ｃは、いわゆるベイヤ配列である。 The second pixel 12 to the fourth pixel 14 are configured similarly to the first pixel 11, and the second PD 12a to the fourth PD 14a and the second micro lens 12b to the fourth micro lens 14b, respectively. The second color filter 12c to the fourth color filter 14c are provided. The second color filter 12c causes only the red light out of the light collected by the second microlens 12b to enter the second PD 12a. The third color filter 13c causes only the blue light out of the light collected by the third microlens 13b to enter the third PD 13a. The fourth color filter 14c causes only the green light of the light collected by the fourth microlens 14b to enter the fourth PD 14a. As described above, the color filters 11c to 14c have a so-called Bayer array.
　図２において、画素セット１５は、第１～第４のＰＤ１１ａ～１４ａの他に、第１～第４の読み出しトランジスタ２１～２４、第１～第３のフローティングディフュージョン（以下ＦＤと称す）２５～２７、リセットトランジスタ２８、アンプトランジスタ２９、及び行選択トランジスタ３０を備えている。 In FIG. 2, in addition to the first to fourth PDs 11a to 14a, the pixel set 15 includes first to fourth readout transistors 21 to 24, first to third floating diffusions (hereinafter referred to as FD) 25 to 27, a reset transistor 28, an amplifier transistor 29, and a row selection transistor 30 are provided.
　また、ＣＭＯＳイメージセンサ１０には、垂直信号線３２、電源供給線３３、第１の読み出し線３４、第２の読み出し線３５、第３の読み出し線３６、第４の読み出し線３７、リセット線３８、行選択線３９が形成されている。 Further, the CMOS image sensor 10 includes a vertical signal line 32, a power supply line 33, a first readout line 34, a second readout line 35, a third readout line 36, a fourth readout line 37, and a reset line 38. A row selection line 39 is formed.
　垂直信号線３２及び電源供給線３３は、垂直方向に延在している。垂直信号線３２と電源供給線３３とは、画素セット１５に対して１本ずつ配設され、垂直方向に並ぶ各画素セット１５に共通に用いられる。 The vertical signal line 32 and the power supply line 33 extend in the vertical direction. One vertical signal line 32 and one power supply line 33 are provided for each pixel set 15 and are used in common for each pixel set 15 arranged in the vertical direction.
　第１～第４の読み出し線３４～３７、リセット線３８、及び行選択線３９は、水平方向に延在している。これらの各線３４～３９は、画素セット１５に対して１本ずつ配設され、水平方向に並ぶ各画素セット１５に共通に用いられる。 The first to fourth readout lines 34 to 37, the reset line 38, and the row selection line 39 extend in the horizontal direction. Each of these lines 34 to 39 is provided for each pixel set 15 and is used in common for each pixel set 15 arranged in the horizontal direction.
　垂直信号線３２は、信号電圧の読み出しに用いられる。電源供給線３３は、電源電圧ＶＤＤの供給に用いられる。第１～第４の読み出し線３４～３７は、それぞれ第１～第４の読み出しトランジスタ２１～２４への読み出し信号を入力に用いられる。リセット線３８は、リセットトランジスタ２８へのリセット信号の入力に用いられる。行選択線３９は、行選択トランジスタ３０への行選択信号の入力に用いられる。 The vertical signal line 32 is used for reading a signal voltage. The power supply line 33 is used to supply the power supply voltage VDD. The first to fourth read lines 34 to 37 are used to input read signals to the first to fourth read transistors 21 to 24, respectively. The reset line 38 is used for inputting a reset signal to the reset transistor 28. The row selection line 39 is used for inputting a row selection signal to the row selection transistor 30.
　第１～第４のＰＤ１１ａ～１４ａは、アノードが接地され、カソードが第１～第４の読み出しトランジスタ２１～２４のソースにそれぞれ接続されている。第１～第４の読み出しトランジスタ２１～２４は、ゲートが第１～第４の読み出し線３４～３７にそれぞれ接続されている。第１の読み出しトランジスタ２１のドレインと、第２の読み出しトランジスタ２２のドレインとは、共通に第１のＦＤ２５に接続されている。また、第３の読み出しトランジスタ２３のドレインと、第４の読み出しトランジスタ２４のドレインとは、共通に第２のＦＤ２６に接続されている。 The anodes of the first to fourth PDs 11a to 14a are grounded, and the cathodes are connected to the sources of the first to fourth readout transistors 21 to 24, respectively. The gates of the first to fourth read transistors 21 to 24 are connected to the first to fourth read lines 34 to 37, respectively. The drain of the first read transistor 21 and the drain of the second read transistor 22 are commonly connected to the first FD 25. Further, the drain of the third read transistor 23 and the drain of the fourth read transistor 24 are commonly connected to the second FD 26.
　第１の読み出し線３４を介して第１の読み出しトランジスタ２１のゲートに読み出し信号を入力し、第１の読み出しトランジスタ２１をオン状態にすることで、第１のＰＤ１１ａに蓄積された信号電荷が第１のＦＤ２５に読み出される。同様に、第２の読み出し線３５を介して第２の読み出しトランジスタ２２のゲートに読み出し信号を入力し、第２の読み出しトランジスタ２２をオン状態にすることで、第２のＰＤ１２ａに蓄積された信号電荷が第１のＦＤ２５に読み出される。 By inputting a read signal to the gate of the first read transistor 21 via the first read line 34 and turning on the first read transistor 21, the signal charge accumulated in the first PD 11a is changed to the first value. 1 is read into the FD 25. Similarly, by inputting a read signal to the gate of the second read transistor 22 via the second read line 35 and turning on the second read transistor 22, the signal accumulated in the second PD 12a. The charge is read out to the first FD 25.
　第３の読み出し線３６を介して第３の読み出しトランジスタ２３のゲートに読み出し信号を入力し、第３の読み出しトランジスタ２３をオン状態にすることで、第３のＰＤ１３ａに蓄積された信号電荷が第２のＦＤ２６に読み出される。同様に、第４の読み出し線３７を介して第４の読み出しトランジスタ２４のゲートに読み出し信号を入力し、第４の読み出しトランジスタ２４をオン状態にすることで、第４のＰＤ１４ａに蓄積された信号電荷が第２のＦＤ２６に読み出される。 By inputting a read signal to the gate of the third read transistor 23 via the third read line 36 and turning on the third read transistor 23, the signal charge accumulated in the third PD 13a is changed to the first value. 2 to the FD 26. Similarly, by inputting a read signal to the gate of the fourth read transistor 24 via the fourth read line 37 and turning on the fourth read transistor 24, the signal accumulated in the fourth PD 14a. The charge is read out to the second FD 26.
　第１～第３のＦＤ２５～２７は、配線４０によって電気的に接続されている。第１及び第２のＦＤ２５、２６に信号電荷が転送されると、互いに電気的に接続された第１～第３のＦＤ２５～２７は、それぞれの容量に応じて瞬時に電荷が分配され、同一の電位となる。 The first to third FDs 25 to 27 are electrically connected by wiring 40. When signal charges are transferred to the first and second FDs 25 and 26, the first to third FDs 25 to 27 that are electrically connected to each other instantaneously distribute charges according to their respective capacities. Potential.
　具体的には、第１のＰＤ１１ａ及び第２のＰＤ１２ａから読み出された信号電荷は、第１のＦＤ２５に蓄積されるとともに、第２のＦＤ２６及び第３のＦＤ２７にも蓄積され、第１～第３のＦＤ２５～２７及び配線４０の容量に応じて電荷が分配されて、同一の電位となる。同様に、第３のＰＤ１３ａ及び第４のＰＤ１４ａから読み出された信号電荷は、第２のＦＤ２６に蓄積されるとともに、第１のＦＤ２５及び第３のＦＤ２７にも蓄積され、第１～第３のＦＤ２５～２７及び配線４０の容量に応じて電荷が分配されて、同一の電位となる。 Specifically, the signal charges read from the first PD 11a and the second PD 12a are accumulated in the first FD 25, and also accumulated in the second FD 26 and the third FD 27. Charges are distributed according to the capacity of the third FDs 25 to 27 and the wiring 40 to have the same potential. Similarly, the signal charges read from the third PD 13a and the fourth PD 14a are accumulated in the second FD 26 and also accumulated in the first FD 25 and the third FD 27, and the first to third The electric charges are distributed according to the capacitances of the FDs 25 to 27 and the wiring 40 to have the same potential.
　リセットトランジスタ２８は、ソースが第３のＦＤ２７に接続され、ドレインが電源供給線３３に接続され、ゲートがリセット線３８に接続されている。リセットトランジスタ２８は、第１～第３のＦＤ２５～２７に蓄積された信号電荷を排出し、所定の電位にリセットする際に用いられる。リセットトランジスタ２８のゲートにリセット信号を入力し、リセットトランジスタ２８をオン状態にすることで、第３のＦＤ２７の電位が電源電圧ＶＤＤの電位にリセットされるとともに、第３のＦＤ２７と電気的に接続された第１及び第２のＦＤ２５、２６の電位も電源電圧ＶＤＤの電位にリセットされる。 The reset transistor 28 has a source connected to the third FD 27, a drain connected to the power supply line 33, and a gate connected to the reset line 38. The reset transistor 28 is used when discharging signal charges accumulated in the first to third FDs 25 to 27 and resetting them to a predetermined potential. By inputting a reset signal to the gate of the reset transistor 28 and turning on the reset transistor 28, the potential of the third FD 27 is reset to the potential of the power supply voltage VDD and is electrically connected to the third FD 27. The potentials of the first and second FDs 25 and 26 thus reset are also reset to the potential of the power supply voltage VDD.
　アンプトランジスタ２９は、ドレインが電源供給線３３に接続され、ソースが行選択トランジスタ３０のドレインに接続され、ゲートが第３のＦＤ２７に接続されている。行選択トランジスタ３０は、ドレインがアンプトランジスタ２９のソースに接続されるとともに、ソースが垂直信号線３２に接続され、ゲートが行選択線３９に接続されている。アンプトランジスタ２９は、ソースフォロワ回路を構成しており、第１～第３のＦＤ２５～２７に蓄積された信号電荷に応じた電圧を、信号電圧として出力する。行選択トランジスタ３０は、垂直信号線３２に信号電圧を転送する行の選択に用いられる。 The drain of the amplifier transistor 29 is connected to the power supply line 33, the source is connected to the drain of the row selection transistor 30, and the gate is connected to the third FD 27. The row selection transistor 30 has a drain connected to the source of the amplifier transistor 29, a source connected to the vertical signal line 32, and a gate connected to the row selection line 39. The amplifier transistor 29 forms a source follower circuit, and outputs a voltage corresponding to the signal charge stored in the first to third FDs 25 to 27 as a signal voltage. The row selection transistor 30 is used to select a row for transferring a signal voltage to the vertical signal line 32.
　行選択トランジスタ３０のゲートに行選択信号を入力し、行選択トランジスタ３０をオン状態にすると、アンプトランジスタ２９のゲートに接続された同電位の第１～第３のＦＤ２５～２７に蓄積された信号電荷に応じた電圧が、信号電圧として垂直信号線３２に現れる。垂直信号線３２に転送された信号電圧は、周知のように、ＣＤＳ回路などによってノイズが抑圧された後、水平信号線に転送され、出力アンプを介して外部に出力される。 When a row selection signal is input to the gate of the row selection transistor 30 and the row selection transistor 30 is turned on, signals accumulated in the first to third FDs 25 to 27 of the same potential connected to the gate of the amplifier transistor 29 A voltage corresponding to the charge appears on the vertical signal line 32 as a signal voltage. As is well known, the signal voltage transferred to the vertical signal line 32 is transferred to the horizontal signal line after noise is suppressed by a CDS circuit or the like, and is output to the outside via an output amplifier.
　以上のように構成されたＣＭＯＳイメージセンサ１０は、リセットトランジスタ２８がオン状態とされ、第１～第３のＦＤ２５～２７が電源電圧ＶＤＤの電位にリセットされてから、各ＰＤ１１ａ～１４ａが信号電荷の蓄積を開始する。所定の露光時間が経過した後、第１の読み出しトランジスタ２１のみに読み出し信号が入力され、第１のＰＤ１１ａの信号電荷が第１のＦＤ２５に転送される。このとき、互いに電気的に接続された第１～第３のＦＤ２５～２７は、それぞれの容量に応じて瞬時に電荷が分配され、同一の信号電位となる。この第１～第３のＦＤ２５～２７に蓄積された信号電荷に応じた信号電圧が、アンプトランジスタ２９により生成される。そして、行選択トランジスタ３０に行選択信号が入力されると、アンプトランジスタ２９により生成された信号電圧が垂直信号線３２に読み出される。このように、トランジスタ２１～２４を順次にオンしながら、行選択トランジスタ３０をオンすることで、第１～第４のＰＤ１１ａ～１４ａの信号電荷に応じた信号電圧がそれぞれ読み出される。 In the CMOS image sensor 10 configured as described above, after the reset transistor 28 is turned on and the first to third FDs 25 to 27 are reset to the potential of the power supply voltage VDD, each of the PDs 11a to 14a has a signal charge. Start accumulating. After a predetermined exposure time has elapsed, a read signal is input only to the first read transistor 21, and the signal charge of the first PD 11 a is transferred to the first FD 25. At this time, the first to third FDs 25 to 27 electrically connected to each other instantaneously distribute charges according to their respective capacities, so that they have the same signal potential. A signal voltage corresponding to the signal charge accumulated in the first to third FDs 25 to 27 is generated by the amplifier transistor 29. When a row selection signal is input to the row selection transistor 30, the signal voltage generated by the amplifier transistor 29 is read out to the vertical signal line 32. In this manner, by turning on the row selection transistor 30 while sequentially turning on the transistors 21 to 24, signal voltages corresponding to the signal charges of the first to fourth PDs 11a to 14a are read out.
　本実施形態のＣＭＯＳイメージセンサ１０は、読み出しに必要なトランジスタ２８～３０が、画素セット１５に対して１つずつ設けられるため、画素毎にトランジスタ２８～３０を設ける場合に比べて、画素サイズが小さく、画素の微細化を図ることができる。 In the CMOS image sensor 10 of the present embodiment, the transistors 28 to 30 necessary for reading are provided one by one for the pixel set 15, so that the pixel size is smaller than when the transistors 28 to 30 are provided for each pixel. It is small and the pixel can be miniaturized.
　図３において、ＣＭＯＳイメージセンサ１０は、Ｐ型の半導体基板５０に形成されている。マイクロレンズ１１ｂ～１４ｂやカラーフィルタ１１ｃ～１４ｃは図示を省略している。第１～第４のＰＤ１１ａ～１４ａは、半導体基板５０の表層に形成されたＮ型の不純物拡散層と、この不純物拡散層と半導体基板５０とのＰＮ接合によって構成されている。 In FIG. 3, the CMOS image sensor 10 is formed on a P-type semiconductor substrate 50. The microlenses 11b to 14b and the color filters 11c to 14c are not shown. The first to fourth PDs 11 a to 14 a are configured by an N-type impurity diffusion layer formed in the surface layer of the semiconductor substrate 50 and a PN junction between the impurity diffusion layer and the semiconductor substrate 50.
　第１のＰＤ１１ａと第２のＰＤ１２ａとの間には、第１のＦＤ２５が設けられている。また、第３のＰＤ１３ａと第４のＰＤ１４ａとの間には、第２のＦＤ２６が設けられている。第１及び第２のＦＤ２５、２６は、半導体基板５０の表層に形成されたＮ型の不純物拡散層によって形成されている。第１のＦＤ２５は、第１のＰＤ１１ａと第２のＰＤ１２ａとの間のほぼ中央に、第１の画素１１と第２の画素１２とに跨って配置されている。同様に、第２のＦＤ２６は、第３のＰＤ１３ａと第４のＰＤ１４ａとの間のほぼ中央に、第３の画素１３と第４の画素１４とに跨って配置されている。 A first FD 25 is provided between the first PD 11a and the second PD 12a. A second FD 26 is provided between the third PD 13a and the fourth PD 14a. The first and second FDs 25 and 26 are formed by N-type impurity diffusion layers formed in the surface layer of the semiconductor substrate 50. The first FD 25 is disposed across the first pixel 11 and the second pixel 12 at approximately the center between the first PD 11a and the second PD 12a. Similarly, the second FD 26 is disposed across the third pixel 13 and the fourth pixel 14 at approximately the center between the third PD 13a and the fourth PD 14a.
　半導体基板５０の表面上には、第１～第４の読み出しトランジスタ２１～２４のゲート電極である第１～第４の読み出しゲート電極５１～５４が設けられている。第１の読み出しゲート電極５１は、第１のＰＤ１１ａと第１のＦＤ２５とに跨るように配置されている。第１の読み出しゲート電極５１は、第１の読み出し線３４の一部である配線５５とプラグ５６を介して接続されている。 On the surface of the semiconductor substrate 50, first to fourth read gate electrodes 51 to 54, which are gate electrodes of the first to fourth read transistors 21 to 24, are provided. The first read gate electrode 51 is disposed so as to straddle the first PD 11a and the first FD 25. The first read gate electrode 51 is connected to a wiring 55 that is a part of the first read line 34 via a plug 56.
　配線５５は、その一部が第１の読み出しゲート電極５１上に重なるように、半導体基板５０の上方に積層形成されている。プラグ５６は、半導体基板５０の表面とほぼ直交する方向に延びる柱状（四角柱状または円柱状）の導電性連結部材であり、例えば、タングステンなどの金属材料により形成されている。なお、ＣＭＯＳイメージセンサ１０は、このプラグ５６の他にも複数のプラグを有する。それらの各プラグにも、同様にタングステンなどの金属材料が用いられる。 The wiring 55 is laminated and formed above the semiconductor substrate 50 so that a part of the wiring 55 overlaps the first read gate electrode 51. The plug 56 is a columnar (square columnar or columnar) conductive connecting member extending in a direction substantially orthogonal to the surface of the semiconductor substrate 50, and is formed of a metal material such as tungsten, for example. The CMOS image sensor 10 has a plurality of plugs in addition to the plug 56. Similarly, a metal material such as tungsten is used for each of these plugs.
　第１の読み出しトランジスタ２１は、第１のＰＤ１１ａのＮ型の不純物拡散層と、第１のＦＤ２５のＮ型の不純物拡散層と、第１の読み出しゲート電極５１とによって構成されている。第１の読み出しゲート電極５１に読み出し信号を入力することで、第１のＰＤ１１ａに蓄積された信号電荷が第１のＦＤ２５に読み出される。 The first read transistor 21 includes an N-type impurity diffusion layer of the first PD 11a, an N-type impurity diffusion layer of the first FD 25, and a first read gate electrode 51. By inputting a read signal to the first read gate electrode 51, the signal charge accumulated in the first PD 11a is read to the first FD 25.
　第２の読み出しゲート電極５２は、第２のＰＤ１２ａと第１のＦＤ２５とに跨るように配置されている。第２の読み出しゲート電極５２は、第２の読み出し線３５の一部である配線５７とプラグ５８を介して接続されている。同様に、第３の読み出しゲート電極５３は、第３のＰＤ１３ａと第２のＦＤ２６とに跨るように配置されている。第３の読み出しゲート電極５３は、第３の読み出し線３６の一部である配線５９とプラグ６０を介して接続されている。同様に、第４の読み出しゲート電極５４は、第４のＰＤ１４ａと第２のＦＤ２６とに跨るように配置されている。第４の読み出しゲート電極５４は、第４の読み出し線３７の一部である配線６１とプラグ６２を介して接続されている。これらの構成は、第１の読み出しゲート電極５１と同様であるので、詳しい説明は省略する。 The second read gate electrode 52 is disposed so as to straddle the second PD 12a and the first FD 25. The second read gate electrode 52 is connected to a wiring 57 that is a part of the second read line 35 via a plug 58. Similarly, the third read gate electrode 53 is disposed so as to straddle the third PD 13a and the second FD 26. The third read gate electrode 53 is connected to a wiring 59 that is a part of the third read line 36 via a plug 60. Similarly, the fourth read gate electrode 54 is disposed so as to straddle the fourth PD 14 a and the second FD 26. The fourth read gate electrode 54 is connected to a wiring 61 that is a part of the fourth read line 37 via a plug 62. Since these structures are the same as those of the first read gate electrode 51, detailed description thereof is omitted.
　各配線５５、５７、５９、６１は、アルミニウムや銅で形成されている。図３では、簡略化のため、各配線５５、５７、５９、６１を部分的に示している。これらは、実際には、不図示のプラグや配線などを介して外部まで引き出され、各読み出し線３４～３７を構成している。また、配線については、他にも省略している部分があるが、同様であるので説明は省略する。 Each wiring 55, 57, 59, 61 is made of aluminum or copper. In FIG. 3, each wiring 55, 57, 59, 61 is partially shown for simplification. In practice, these are drawn out to the outside through a plug or wiring (not shown) to constitute the readout lines 34-37. In addition, although there are other parts of the wiring that are omitted, the description is omitted because they are the same.
　第４のＰＤ１４ａと、隣の画素セット１５の第３のＰＤ１３ａとの間には、第３のＦＤ２７と、リセットドレイン６４と、リセットゲート電極６５とが設けられている。また、第２のＰＤ１２ａと、隣の画素セット１５の第１のＰＤ１１ａとの間には、アンプゲート電極６６と、行選択ゲート電極６７と、行選択ソース６８とが設けられている。 A third FD 27, a reset drain 64, and a reset gate electrode 65 are provided between the fourth PD 14a and the third PD 13a of the adjacent pixel set 15. An amplifier gate electrode 66, a row selection gate electrode 67, and a row selection source 68 are provided between the second PD 12a and the first PD 11a of the adjacent pixel set 15.
　第３のＦＤ２７とリセットドレイン６４とは、半導体基板５０の表層に形成されたＮ型の不純物拡散層によって形成されている。また、第３のＦＤ２７とリセットドレイン６４とは、第４のＰＤ１４ａと隣の画素セット１５の第３のＰＤ１３ａとの間のほぼ中央に、これらの画素に跨って配置されている。 The third FD 27 and the reset drain 64 are formed by an N-type impurity diffusion layer formed in the surface layer of the semiconductor substrate 50. In addition, the third FD 27 and the reset drain 64 are disposed across these pixels at the approximate center between the fourth PD 14 a and the third PD 13 a of the adjacent pixel set 15.
　第３のＦＤ２７は、配線７０を介して、第１のＦＤ２５、第２のＦＤ２６、及びアンプゲート電極６６と電気的に接続されている。配線７０は、Ｈ字状であり、４つの端部がそれぞれ第１のＦＤ２５、第２のＦＤ２６、第３のＦＤ２７、アンプゲート電極６６上に重なるように、半導体基板５０の上方に積層形成されている。 The third FD 27 is electrically connected to the first FD 25, the second FD 26, and the amplifier gate electrode 66 through the wiring 70. The wiring 70 is H-shaped, and is stacked on the semiconductor substrate 50 so that the four end portions thereof overlap the first FD 25, the second FD 26, the third FD 27, and the amplifier gate electrode 66, respectively. ing.
　第１～第３のＦＤ２５～２７と配線７０が重なった領域には、それぞれプラグ７１～７３が設けられている。同様に、アンプゲート電極６６と配線７０が重なった領域には、プラグ７４が設けられている。 In areas where the first to third FDs 25 to 27 and the wiring 70 overlap, plugs 71 to 73 are provided, respectively. Similarly, a plug 74 is provided in a region where the amplifier gate electrode 66 and the wiring 70 overlap.
　プラグ７１～７４により、第１～第３のＦＤ２５～２７とアンプゲート電極６６とが、それぞれ電気的に接続されている。ＦＤ２５、２６、２７とアンプゲート電極６６は、同一の電位であり、この電位がアンプトランジスタ２９のゲートに印加される。 The first to third FDs 25 to 27 and the amplifier gate electrode 66 are electrically connected by plugs 71 to 74, respectively. The FDs 25, 26, 27 and the amplifier gate electrode 66 have the same potential, and this potential is applied to the gate of the amplifier transistor 29.
　リセットトランジスタ２８のドレインを構成するリセットドレイン６４は、電源供給線３３の一部である配線７５とプラグ７６を介して接続されている。配線７５は、その一部がリセットドレイン６４上に重なるように、半導体基板５０の上方に積層形成されている。プラグ７６は、積層形成された配線７５とリセットドレイン６４とを電気的に接続している。これにより、リセットドレイン６４の電位が電源電圧ＶＤＤとなっている。 The reset drain 64 constituting the drain of the reset transistor 28 is connected to a wiring 75 which is a part of the power supply line 33 through a plug 76. The wiring 75 is stacked above the semiconductor substrate 50 so that part of the wiring 75 overlaps the reset drain 64. The plug 76 electrically connects the stacked wiring 75 and the reset drain 64. As a result, the potential of the reset drain 64 is the power supply voltage VDD.
　リセットゲート電極６５は、第３のＦＤ２７とリセットドレイン６４とに跨るように配置されている。リセットゲート電極６５は、リセット線３８の一部である配線７７とプラグ７８を介して接続されている。配線７７は、その一部がリセットゲート電極６５上に重なるように、半導体基板５０の上方に積層形成されている。配線７７とリセットゲート電極６５とは、プラグ７８により電気的に接続されている。 The reset gate electrode 65 is disposed so as to straddle the third FD 27 and the reset drain 64. The reset gate electrode 65 is connected to a wiring 77 that is a part of the reset line 38 via a plug 78. The wiring 77 is stacked above the semiconductor substrate 50 so that a part of the wiring 77 overlaps the reset gate electrode 65. The wiring 77 and the reset gate electrode 65 are electrically connected by a plug 78.
　リセットトランジスタ２８は、第３のＦＤ２７Ｎ型の不純物拡散層と、リセットドレイン６４とのＮ型の不純物拡散層と、リセットゲート電極６５とによって構成されている。リセットゲート電極６５にリセット信号を入力することで、ＦＤ２５、２６、２７の電位が、リセットドレイン６４に印加された電源電圧ＶＤＤにリセットされる。 The reset transistor 28 includes a third FD27N-type impurity diffusion layer, an N-type impurity diffusion layer with a reset drain 64, and a reset gate electrode 65. By inputting a reset signal to the reset gate electrode 65, the potentials of the FDs 25, 26, and 27 are reset to the power supply voltage VDD applied to the reset drain 64.
　アンプゲート電極６６と行選択ゲート電極６７と行選択ソース６８とは、第２のＰＤ１２ａと隣の画素セット１５の第１のＰＤ１１ａとの間のほぼ中央に、これらの画素に跨って配置されている。行選択トランジスタ３０のソースを構成する行選択ソース６８は、半導体基板５０の表層に形成されたＮ型の不純物拡散層によって構成されている。行選択ソース６８は、プラグ８０を介して垂直信号線３２と接続されている。 The amplifier gate electrode 66, the row selection gate electrode 67, and the row selection source 68 are disposed across these pixels at the approximate center between the second PD 12 a and the first PD 11 a of the adjacent pixel set 15. Yes. The row selection source 68 constituting the source of the row selection transistor 30 is configured by an N-type impurity diffusion layer formed on the surface layer of the semiconductor substrate 50. The row selection source 68 is connected to the vertical signal line 32 via the plug 80.
　行選択ゲート電極６７は、行選択ソース６８に接するように形成されている。行選択ゲート電極６７は、行選択線３９の一部である配線８１とプラグ８２を介して接続されている。アンプゲート電極６６と行選択ゲート電極６７との間には、アンプトランジスタ２９のソース、及び行選択トランジスタ３０のドレインを形成するＮ型の不純物拡散層８３が配置されている。アンプゲート電極６６と行選択ゲート電極６７とは、不純物拡散層８３に近接している。 The row selection gate electrode 67 is formed in contact with the row selection source 68. The row selection gate electrode 67 is connected to a wiring 81 that is a part of the row selection line 39 via a plug 82. An N-type impurity diffusion layer 83 that forms the source of the amplifier transistor 29 and the drain of the row selection transistor 30 is disposed between the amplifier gate electrode 66 and the row selection gate electrode 67. The amplifier gate electrode 66 and the row selection gate electrode 67 are close to the impurity diffusion layer 83.
　また、アンプゲート電極６６は、アンプトランジスタ２９のドレインを形成するＮ型の不純物拡散層８４にも近接している。この不純物拡散層８４は、電源供給線３３の一部である配線７５とプラグ８５を介して接続されている。行選択ゲート電極６７に行選択信号を入力することで、行選択トランジスタ３０がオン状態となり、アンプゲート電極６６の電位に応じた信号電圧が垂直信号線３２に印加される。 The amplifier gate electrode 66 is also close to the N-type impurity diffusion layer 84 that forms the drain of the amplifier transistor 29. The impurity diffusion layer 84 is connected to a wiring 75 that is a part of the power supply line 33 via a plug 85. By inputting a row selection signal to the row selection gate electrode 67, the row selection transistor 30 is turned on, and a signal voltage corresponding to the potential of the amplifier gate electrode 66 is applied to the vertical signal line 32.
　図４において、ＣＭＯＳイメージセンサ１０は、クロストークを抑えるための遮光体９０を有している。なお、配線は省略している。遮光体９０は、複数のダミープラグ９２と、ゲート電極６５、６６、６７により構成されている。ダミープラグ９２は、所定の間隔で並べられており、ゲート電極６５、６６、６７とにより、各ＰＤ１１ａ～１４ａの周囲を囲んでいる。ダミープラグ９２は、ゲート電極６５、６６、６７の上方には設けられていない。 4, the CMOS image sensor 10 includes a light shielding body 90 for suppressing crosstalk. Note that wiring is omitted. The light shielding body 90 includes a plurality of dummy plugs 92 and gate electrodes 65, 66 and 67. The dummy plugs 92 are arranged at a predetermined interval, and surround the PDs 11a to 14a by the gate electrodes 65, 66, and 67. The dummy plug 92 is not provided above the gate electrodes 65, 66 and 67.
　各ダミープラグ９２は、半導体基板５０の表面とほぼ直交する方向に延びた柱状（四角柱状または円柱状）であり、上記各プラグと同じ金属材料（例えばタングステン）で形成されている。各ダミープラグ９２は、半導体基板５０とは電気的に接続されていない。 Each dummy plug 92 has a columnar shape (a square columnar shape or a columnar shape) extending in a direction substantially orthogonal to the surface of the semiconductor substrate 50, and is formed of the same metal material (for example, tungsten) as each of the plugs. Each dummy plug 92 is not electrically connected to the semiconductor substrate 50.
　ダミープラグ９２の水平方向及び垂直方向への間隔ＰＬ（図５参照）は、ダミープラグ９２間に入射する入射光の波長（絶対値）よりも狭く設定されている。この入射光の波長は、入射光が通過する材料の屈折率に依存する。各ダミープラグ９２の間には、約１．４５の屈折率を有する酸化シリコン（ＳｉＯ２）からなる第１の酸化膜９４（図６及び図７参照）が形成されている。入射光は、第１の酸化膜９４を通過して各ＰＤ１１ａ～１４ａに入射する。 The distance PL between the dummy plugs 92 in the horizontal direction and the vertical direction (see FIG. 5) is set to be narrower than the wavelength (absolute value) of incident light incident between the dummy plugs 92. The wavelength of this incident light depends on the refractive index of the material through which the incident light passes. A first oxide film 94 (see FIGS. 6 and 7) made of silicon oxide (SiO 2 ) having a refractive index of about 1.45 is formed between the dummy plugs 92. Incident light passes through the first oxide film 94 and enters each PD 11a to 14a.
　第１のカラーフィルタ１１ｃ及び第４のカラーフィルタ１４ｃにより分光される緑色の透過光は、分光直後の波長が約５４０ｎｍであり、酸化シリコン中では波長が約３７０ｎｍとなる。第２のカラーフィルタ１２ｃにより分光される赤色の透過光は、分光直後の波長が約６５０ｎｍであり、酸化シリコン中では波長が約４５０ｎｍとなる。第３のカラーフィルタ１３ｃにより分光される青色の透過光は、分光直後の波長が約４５０ｎｍであり、酸化シリコン中では波長が約３１０ｎｍとなる。 The green transmitted light dispersed by the first color filter 11c and the fourth color filter 14c has a wavelength immediately after the spectrum of about 540 nm, and the wavelength in silicon oxide is about 370 nm. The red transmitted light that is split by the second color filter 12c has a wavelength of about 650 nm immediately after the splitting, and a wavelength of about 450 nm in silicon oxide. The blue transmitted light spectrally separated by the third color filter 13c has a wavelength of about 450 nm immediately after the spectral and has a wavelength of about 310 nm in silicon oxide.
　ダミープラグ９２は、検出波長の異なる２つの画素の間に設けられているため、波長の異なる２種の光が入射する。このため、ダミープラグ９２の間隔ＰＬは、ダミープラグ９２の間に入射するいずれの光の波長よりも狭く設定する必要がある。例えば、緑色の光が入射する第１のＰＤ１１ａと、赤色の光が入射する第２のＰＤ１２ａとを仕切る部分では、ダミープラグ９２の間には、一方から緑色の光が入射し、他方から赤色の光が入射する。このため、ダミープラグ９２の間隔ＰＬを、緑色の光の酸化シリコン中での波長（約３７０ｎｍ）と、赤色の光の酸化シリコン中での波長（約４５０ｎｍ）のいずれよりも狭く、例えば、約３００ｎｍとする。 Since the dummy plug 92 is provided between two pixels having different detection wavelengths, two types of light having different wavelengths are incident thereon. For this reason, the interval PL between the dummy plugs 92 needs to be set narrower than the wavelength of any light incident between the dummy plugs 92. For example, in a portion that partitions the first PD 11a into which green light is incident and the second PD 12a into which red light is incident, green light is incident from one side between the dummy plugs 92 and red from the other. Light enters. Therefore, the distance PL between the dummy plugs 92 is narrower than both the wavelength of green light in silicon oxide (about 370 nm) and the wavelength of red light in silicon oxide (about 450 nm). Set to 300 nm.
　同様に、緑色の光が入射する第１のＰＤ１１ａと、青色の光が入射する第３のＰＤ１３ａとを仕切る部分では、ダミープラグ９２の間隔ＰＬを約２００ｎｍとする。第２のＰＤ１２ａと第４のＰＤ１４ａとを仕切る部分、第３のＰＤ１３ａと第４のＰＤ１４ａとを仕切る部分についても同様である。このように、ダミープラグ９２の間隔ＰＬを、そこに入射するいずれの光の波長よりも狭くすることにより、ダミープラグ９２の隙間からの光の漏れが防止される。 Similarly, the interval PL between the dummy plugs 92 is set to about 200 nm in a portion that partitions the first PD 11a into which green light is incident and the third PD 13a into which blue light is incident. The same applies to the part that partitions the second PD 12a and the fourth PD 14a and the part that partitions the third PD 13a and the fourth PD 14a. In this way, by making the interval PL of the dummy plugs 92 smaller than the wavelength of any light incident thereon, light leakage from the gap between the dummy plugs 92 is prevented.
　また、遮光体９０を構成する複数のダミープラグ９２は、水平方向及び垂直方向に沿って、２列並行に隣接して配置されている。この２列のうち、一方の列と他方の列とでは、ダミープラグ９２の配列周期の半分に相当する距離だけ、ダミープラグ９２の位置がずれている。このように、一方の列のダミープラグ９２の隙間を塞ぐように、他方の列のダミープラグ９２が配置されていることにより、ダミープラグ９２の隙間からの光の漏れが、確実に防止される。 Further, the plurality of dummy plugs 92 constituting the light shielding body 90 are arranged adjacent to each other in two rows along the horizontal direction and the vertical direction. Of these two columns, the positions of the dummy plugs 92 are shifted by a distance corresponding to half the arrangement period of the dummy plugs 92 in one column and the other column. In this way, by disposing the dummy plugs 92 in the other row so as to close the gaps in the dummy plugs 92 in one row, light leakage from the gaps in the dummy plugs 92 is reliably prevented. .
　また、ダミープラグ９２は、図５に示すように、行選択ソース６８と垂直信号線３２とが重なる領域（すなわち、不純物拡散層と配線とが重なる領域）にも設けられている。 Further, as shown in FIG. 5, the dummy plug 92 is also provided in a region where the row selection source 68 and the vertical signal line 32 overlap (that is, a region where the impurity diffusion layer and the wiring overlap).
　行選択ソース６８と垂直信号線３２とを接続するプラグ８０は、ダミープラグ９２が配列された線上に配置されている。このように、プラグ８０は、各ダミープラグ９２とともに、遮光体９０の一部を構成している。 The plug 80 that connects the row selection source 68 and the vertical signal line 32 is disposed on the line on which the dummy plugs 92 are arranged. Thus, the plug 80 constitutes a part of the light shield 90 together with each dummy plug 92.
　図６及び図７において、半導体基板５０の表面上には、絶縁膜１００が形成されている。絶縁膜１００は、酸化シリコンなどで形成された透明な膜であり、ゲート電極５１～５４、６５～６７が半導体基板５０の表面に接触することを防ぐとともに、半導体基板５０の表面の保護や、画質劣化に起因する界面準位の低減を行っている。 6 and 7, the insulating film 100 is formed on the surface of the semiconductor substrate 50. The insulating film 100 is a transparent film formed of silicon oxide or the like, and prevents the gate electrodes 51 to 54 and 65 to 67 from coming into contact with the surface of the semiconductor substrate 50, as well as protecting the surface of the semiconductor substrate 50, The interface state due to image quality degradation is reduced.
　ゲート電極５１～５４、６５～６７は、絶縁膜１００の上に、ポリシリコンなどで形成されている。また、ゲート電極５１～５４、６５～６７の上には、遮光膜１０２が設けられている。これらの遮光膜１０２は、タングステンシリサイドなどの遮光性を有する材料で形成されている。各遮光膜１０２は、各ゲート電極５１～５４、６５～６７に向かう光を反射することにより、各ゲート電極５１～５４、６５～６７への光の入射を防ぐ。 The gate electrodes 51 to 54 and 65 to 67 are formed of polysilicon or the like on the insulating film 100. A light shielding film 102 is provided on the gate electrodes 51 to 54 and 65 to 67. These light shielding films 102 are made of a light shielding material such as tungsten silicide. Each light shielding film 102 reflects light directed toward the gate electrodes 51 to 54 and 65 to 67, thereby preventing light from entering the gate electrodes 51 to 54 and 65 to 67.
　絶縁膜１００の上には、ゲート電極５１～５４、６５～６７、及び遮光膜１０２を覆うように第１の酸化膜９４が形成されている。この第１の酸化膜９４の上には、一層目の配線として、各ＰＤ１１ａ～１４ａが蓄積した信号電荷を外部に読み出すための上記配線５５、５７、５９、６１、７０、７５、８１などが設けられている。これらの配線以外に、一層目の配線として、配線１０５、１０６、１１１～１１３などが設けられている。このうち、配線１０６、１１１～１１３はダミープラグ９２に接続されている。 A first oxide film 94 is formed on the insulating film 100 so as to cover the gate electrodes 51 to 54 and 65 to 67 and the light shielding film 102. On the first oxide film 94, as the first layer wiring, the wiring 55, 57, 59, 61, 70, 75, 81, etc. for reading the signal charges accumulated in the PDs 11a to 14a to the outside are provided. Is provided. In addition to these wirings, wirings 105, 106, 111 to 113, etc. are provided as the first-layer wiring. Among these, the wirings 106 and 111 to 113 are connected to the dummy plug 92.
　第１の酸化膜９４の上には、一層目の各配線を覆うように第２の酸化膜９５が形成されている。この第２の酸化膜９５の上には、配線１０７～１１０、１１４～１１６などの二層目の配線が設けられている。そして、二層目の各配線を覆うように第３の酸化膜９６が形成されている。この第３の酸化膜９６の上に、各カラーフィルタ１１ｃ～１４ｃが形成されている。第２の酸化膜９５及び第３の酸化膜９６は、第１の酸化膜９４と同様に、酸化シリコンなどで形成されている。 On the first oxide film 94, a second oxide film 95 is formed so as to cover each wiring in the first layer. On the second oxide film 95, second-layer wirings such as wirings 107 to 110 and 114 to 116 are provided. A third oxide film 96 is formed so as to cover each wiring in the second layer. On the third oxide film 96, the color filters 11c to 14c are formed. Similar to the first oxide film 94, the second oxide film 95 and the third oxide film 96 are formed of silicon oxide or the like.
　これらの各配線は、各ＰＤ１１ａ～１４ａと各カラーフィルタ１１ｃ～１４ｃとの間に位置しないように、ＰＤ１１ａ～１４ａ間の境界領域に配置されている。また、配線層１０４は、第１の酸化膜９４の上の一層目の配線と、第２の酸化膜９５と、第２の酸化膜９５の上の二層目の配線と、第３の酸化膜９６とにより構成された層構造である。一層目の配線と二層目の配線とは、不図示のプラグにより接続されている。なお、配線層１０４は、２層に限られず、３層以上であってもよい。 These wirings are arranged in a boundary region between the PDs 11a to 14a so as not to be positioned between the PDs 11a to 14a and the color filters 11c to 14c. The wiring layer 104 includes a first-layer wiring on the first oxide film 94, a second oxide film 95, a second-layer wiring on the second oxide film 95, and a third oxide film. This is a layer structure constituted by the film 96. The first-layer wiring and the second-layer wiring are connected by a plug (not shown). The wiring layer 104 is not limited to two layers, and may be three or more layers.
　各ダミープラグ９２は、ゲート電極５１～５４、６５～６７の上方以外の領域に配置されている。各ダミープラグ９２は、上端が一層目の各配線に接触し、下端が半導体基板５０の表面から僅かに離れている。各ダミープラグ９２の下端と半導体基板５０の表面との間の距離は、約２００ｎｍ～４００ｎｍであることが好ましい。このように、各ダミープラグ９２は、半導体基板５０と配線層１０４との電気的接続は行なっていない。 Each dummy plug 92 is arranged in a region other than above the gate electrodes 51 to 54 and 65 to 67. Each dummy plug 92 has an upper end in contact with each wiring of the first layer and a lower end slightly separated from the surface of the semiconductor substrate 50. The distance between the lower end of each dummy plug 92 and the surface of the semiconductor substrate 50 is preferably about 200 nm to 400 nm. As described above, each dummy plug 92 is not electrically connected to the semiconductor substrate 50 and the wiring layer 104.
　遮光体９０を設けることにより、マイクロレンズ１１ｂ～１４ｂに対して斜めに入射し、隣接する画素のＰＤに向かう光が遮られるので、隣接する画素に光が入射する、いわゆるクロストークの発生が防止される。 By providing the light shielding body 90, light incident on the microlenses 11b to 14b obliquely and light directed to the PD of the adjacent pixel is blocked, so that the occurrence of so-called crosstalk in which light enters the adjacent pixel is prevented. Is done.
　また、遮光体９０は、画素間に配置された各ゲート電極６５、６６、６７と、これに沿って配置されたダミープラグ９２とにより構成されているため、遮光体９０を設けるための専用の領域を必要とせず、各画素１１～１４の微細化の妨げになることもない。 Further, since the light shielding body 90 is configured by the gate electrodes 65, 66, and 67 disposed between the pixels and the dummy plug 92 disposed along the gate electrodes 65, 66, and 67, a dedicated light shielding body 90 is provided. There is no need for a region, and miniaturization of each of the pixels 11 to 14 is not hindered.
　さらに、各ゲート電極５１～５４、６５～６７の上に遮光膜１０２を設け、各ゲート電極５１～５４、６５～６７に向かう光を各遮光膜１０２で反射させているので、従来のようなゲート電極を光が透過して隣接する画素に入射する、いわゆるクロストークの発生が抑えられる。 Further, since the light shielding film 102 is provided on each of the gate electrodes 51 to 54 and 65 to 67, and the light directed to each of the gate electrodes 51 to 54 and 65 to 67 is reflected by each light shielding film 102, Occurrence of so-called crosstalk in which light passes through the gate electrode and enters an adjacent pixel can be suppressed.
　次に、ＣＭＯＳイメージセンサ１０の製造方法を説明する。まず、図８に示すように、周知のフォトリソグラフィによりレジストマスクを形成し、半導体基板５０の所定の領域にドーピング（イオン注入）を行うことにより、Ｎ型の不純物拡散層からなるＰＤ１１ａ～１４ａ、ＦＤ２５～２７、リセットドレイン６４、行選択ソース６８などを形成する。 Next, a method for manufacturing the CMOS image sensor 10 will be described. First, as shown in FIG. 8, a resist mask is formed by well-known photolithography, and doping (ion implantation) is performed on a predetermined region of the semiconductor substrate 50, whereby PDs 11a to 14a made of N-type impurity diffusion layers, FDs 25 to 27, a reset drain 64, a row selection source 68, and the like are formed.
　この後、半導体基板５０の表面上に絶縁膜１００を形成する。この絶縁膜１００の上にポリシリコン及びタングステンシリサイドを順に堆積させ、フォトリソグラフィとエッチングにより、ポリシリコンからなるゲート電極５１～５４、６５～６７と、タングステンシリサイドからなる遮光膜１０２を形成する。 Thereafter, an insulating film 100 is formed on the surface of the semiconductor substrate 50. Polysilicon and tungsten silicide are sequentially deposited on the insulating film 100, and gate electrodes 51 to 54 and 65 to 67 made of polysilicon and a light shielding film 102 made of tungsten silicide are formed by photolithography and etching.
　ゲート電極５１～５４、６５～６７及び遮光膜１０２を覆うように、半導体基板５０上に、酸化シリコンからなる第１の酸化膜９４を積層する。この第１の酸化膜９４は、図９に示すように、配線層１０４の一層目の各配線の高さに応じた膜厚とする。第１の酸化膜９４の表面には、ゲート電極５１～５４、６５～６７の形状に応じた凹凸が生じている。第１の酸化膜９４の表面に周知のＣＭＰ処理を施すことにより、図１０に示すように、第１の酸化膜９４の表面を平坦化する。 A first oxide film 94 made of silicon oxide is stacked on the semiconductor substrate 50 so as to cover the gate electrodes 51 to 54 and 65 to 67 and the light shielding film 102. As shown in FIG. 9, the first oxide film 94 has a thickness corresponding to the height of each wiring in the first layer of the wiring layer 104. Irregularities corresponding to the shapes of the gate electrodes 51 to 54 and 65 to 67 are formed on the surface of the first oxide film 94. By performing a well-known CMP process on the surface of the first oxide film 94, the surface of the first oxide film 94 is planarized as shown in FIG.
　図１１に示すように、第１の酸化膜９４の上にレジスト１２０が塗布されている。このレジスト１２０にフォトリソグラフを施し、各プラグに対応したパターンを形成する。ここで、レジスト１２０にパターン形成するプラグは、ゲート電極と配線とを接続するプラグ５６、５８、６０、６２、７４、７８、８２や、不純物拡散層と配線とを接続するプラグ７１～７３、７６、８０、８５である。そして、このレジスト１２０をマスクとして第１の酸化膜９４をエッチングすることにより、各プラグの形状に応じた複数の穴１２３を形成する。 As shown in FIG. 11, a resist 120 is applied on the first oxide film 94. The resist 120 is subjected to photolithography to form a pattern corresponding to each plug. Here, plugs for pattern formation on the resist 120 are plugs 56, 58, 60, 62, 74, 78, 82 for connecting the gate electrode and the wiring, plugs 71 to 73 for connecting the impurity diffusion layer and the wiring, 76, 80, 85. Then, by etching the first oxide film 94 using the resist 120 as a mask, a plurality of holes 123 corresponding to the shape of each plug are formed.
　図１２に示すように、レジスト１２０を除去し、第１の酸化膜９４の上にタングステン１２４を堆積させ、各穴１２３にタングステン１２４を埋め込む。この後、図１３に示すように、タングステン１２４に対してＣＭＰ処理を施し、第１の酸化膜９４の表面が露呈されるまでタングステン１２４を研削する。これにより、第１の酸化膜９４にプラグ５６、５８等が形成される。 As shown in FIG. 12, the resist 120 is removed, tungsten 124 is deposited on the first oxide film 94, and tungsten 124 is embedded in each hole 123. Thereafter, as shown in FIG. 13, CMP is performed on the tungsten 124, and the tungsten 124 is ground until the surface of the first oxide film 94 is exposed. As a result, plugs 56, 58, etc. are formed in the first oxide film 94.
　図１４に示すように、第１の酸化膜９４の上にレジスト１２６を塗布する。このレジスト１２６に対してフォトリソグラフ処理を施し、ダミープラグ９２に対応したパターンを形成する。そして、このレジスト１２６をマスクとして第１の酸化膜９４をエッチングすることにより、各ダミープラグ９２の形状に応じた複数の穴１２７を形成する。このエッチング時には、各穴１２７が第１の酸化膜９４及び絶縁膜１００を貫通して半導体基板５０の表面に達することのないようにエッチング条件を調整する。 As shown in FIG. 14, a resist 126 is applied on the first oxide film 94. The resist 126 is subjected to a photolithography process to form a pattern corresponding to the dummy plug 92. Then, by etching the first oxide film 94 using the resist 126 as a mask, a plurality of holes 127 corresponding to the shape of each dummy plug 92 are formed. In this etching, the etching conditions are adjusted so that each hole 127 does not penetrate the first oxide film 94 and the insulating film 100 and reach the surface of the semiconductor substrate 50.
　図１５に示すように、レジスト１２６を除去し、第１の酸化膜９４の上にタングステン１２８を堆積させ、各穴１２７にタングステンを埋め込む。この後、図１６に示すように、タングステン１２８に対してＣＭＰ処理を施し、第１の酸化膜９４の表面が露呈されるまでタングステン１２８を研削する。これにより、ダミープラグ９２が形成される。 As shown in FIG. 15, the resist 126 is removed, tungsten 128 is deposited on the first oxide film 94, and tungsten is embedded in each hole 127. Thereafter, as shown in FIG. 16, CMP processing is performed on the tungsten 128, and the tungsten 128 is ground until the surface of the first oxide film 94 is exposed. Thereby, the dummy plug 92 is formed.
　この後、第１の酸化膜９４の上に、一層目の配線、第２の酸化膜９５、二層目の配線、第３の酸化膜９６を順に設けることにより、前述の配線層１０４を形成する。そして、配線層１０４の上に各カラーフィルタ１１ａ～１４ａを形成し、この上に各マイクロレンズ１１ｂ～１４ｂを形成する。以上により、ＣＭＯＳイメージセンサ１０が完成する。 Thereafter, the first wiring layer, the second oxide film 95, the second wiring layer, and the third oxide film 96 are sequentially provided on the first oxide film 94, thereby forming the wiring layer 104 described above. To do. Then, the color filters 11a to 14a are formed on the wiring layer 104, and the micro lenses 11b to 14b are formed thereon. As described above, the CMOS image sensor 10 is completed.
　なお、上記実施形態では、ダミープラグ９２を２列並行に配置した遮光体９０を用いているが、図１７に示すように、ダミープラグ９２を３列並行に配置した遮光体１４０を用いてもよい。これにより、ダミープラグ９２の隙間からの光の漏れをより確実に防ぐことができる。さらに、ダミープラグ９２を４列以上並行に配置してもよい。また、ダミープラグ９２を並行に配置する列数を、光の漏れ具合などを考慮し、場所に応じて変えてもよい。 In the above embodiment, the light shielding body 90 in which the dummy plugs 92 are arranged in two rows in parallel is used. However, as shown in FIG. 17, the light shielding body 140 in which the dummy plugs 92 are arranged in three rows in parallel may be used. Good. As a result, light leakage from the gap between the dummy plugs 92 can be prevented more reliably. Furthermore, four or more dummy plugs 92 may be arranged in parallel. Further, the number of columns in which the dummy plugs 92 are arranged in parallel may be changed depending on the location in consideration of light leakage and the like.
　また、上記実施形態では、第１の酸化膜９４中に各ダミープラグ９２を形成し、上端を一層目の各配線に接触させ、下端を半導体基板５０の表面から離しているが、これとは反対に、各ダミープラグ９２の下端を半導体基板５０の表面に接触させ、上端を配線から離してもよい。さらに、ダミープラグ９２の上端及び下端を、半導体基板５０の表面と配線との両方から離してもよい。 Further, in the above embodiment, each dummy plug 92 is formed in the first oxide film 94, the upper end is brought into contact with each wiring of the first layer, and the lower end is separated from the surface of the semiconductor substrate 50. On the contrary, the lower end of each dummy plug 92 may be brought into contact with the surface of the semiconductor substrate 50 and the upper end may be separated from the wiring. Furthermore, the upper end and the lower end of the dummy plug 92 may be separated from both the surface of the semiconductor substrate 50 and the wiring.
　また、第１の酸化膜９４中だけでなく、それより上層の第２の酸化膜９５中や第２の酸化膜９５中にダミープラグを設けてもよい。図１８に示す例では、ダミープラグ９２に加えて、第２の酸化膜９５中にダミープラグ１４２を設けている。ダミープラグ１４２は、下端が一層目の配線１０６に接続され、上端は二層目の配線１０９から離れている。また、図１９に示すように、各ダミープラグ９２、１４２を設ける位置に、一層目の配線１０６がなくてもよい。 In addition, a dummy plug may be provided not only in the first oxide film 94 but also in the second oxide film 95 or the second oxide film 95 above it. In the example shown in FIG. 18, a dummy plug 142 is provided in the second oxide film 95 in addition to the dummy plug 92. The dummy plug 142 has a lower end connected to the first-layer wiring 106 and an upper end separated from the second-layer wiring 109. Further, as shown in FIG. 19, the first-layer wiring 106 may not be provided at the position where the dummy plugs 92 and 142 are provided.
　また、一層目の配線１０６がない位置に各ダミープラグ９２、１４２を形成する場合には、図２０に示すように、これらに対応する位置に、信号の読み出しなどに関係しないダミー配線１４４を設けてもよい。ダミー配線１４４は、アルミニウムや銅で形成されており、電気的に孤立している。このように、配線がない位置にダミープラグを設けることや、ダミー配線を設けることは、二層目の配線１０９より上層にも適用可能である。 Further, when the dummy plugs 92 and 142 are formed at a position where the first-layer wiring 106 is not present, dummy wirings 144 that are not related to signal reading or the like are provided at corresponding positions as shown in FIG. May be. The dummy wiring 144 is made of aluminum or copper and is electrically isolated. Thus, providing a dummy plug at a position where there is no wiring or providing a dummy wiring can also be applied to a layer above the second-layer wiring 109.
　また、上記実施形態では、各ゲート電極６５、６６、６７の上方にはダミープラグ９２を設けていないが、図２１に示すように、ゲート電極６５、６６、６７の上方の第２の酸化膜９５中にダミープラグ１４２を設けてもよい。さらに、ゲート電極６５、６６、６７の上方の第３の酸化膜９６中にダミープラグを設けてもよい。なお、配線がない位置にこれらのダミープラグを設けてもよい。 In the above embodiment, the dummy plug 92 is not provided above the gate electrodes 65, 66, and 67. However, as shown in FIG. 21, the second oxide film above the gate electrodes 65, 66, and 67 is provided. A dummy plug 142 may be provided in 95. Furthermore, a dummy plug may be provided in the third oxide film 96 above the gate electrodes 65, 66 and 67. These dummy plugs may be provided at a position where there is no wiring.
　さらに、図２２に示すように、ダミープラグ９２より上下方向の長さが短いダミープラグ１４６を、ゲート電極６５、６６、６７の上方の第１の酸化膜９４中に設けてもよい。このダミープラグ１４６は、上端が一層目の配線１０５に接続され、下端がゲート電極６７の表面（遮光体１０２）から離れている。なお、配線がない位置にダミープラグ１４６を設けてもよい。 Furthermore, as shown in FIG. 22, a dummy plug 146 whose vertical length is shorter than that of the dummy plug 92 may be provided in the first oxide film 94 above the gate electrodes 65, 66 and 67. The dummy plug 146 has an upper end connected to the first-layer wiring 105 and a lower end separated from the surface of the gate electrode 67 (the light shield 102). A dummy plug 146 may be provided at a position where there is no wiring.
　ダミープラグ１４６の下端からゲート電極６７の表面（遮光体１０２）までの第１の距離Ｄ１は、ダミープラグ９２の下端から半導体基板５０の表面（絶縁膜１００）までの第２の距離Ｄ２とほぼ同一に設定されている。第１及び第２の距離Ｄ１、Ｄ２は、入射光の波長より短いことが好ましい。例えば、青色の光が入射する領域では、第１の酸化膜９４中における波長が約３１０ｎｍである。このため、第１及び第２の距離Ｄ１、Ｄ２を３１０ｎｍより短く、例えば、約２００ｎｍとする。 The first distance D1 from the lower end of the dummy plug 146 to the surface of the gate electrode 67 (the light shielding body 102) is substantially the same as the second distance D2 from the lower end of the dummy plug 92 to the surface of the semiconductor substrate 50 (the insulating film 100). They are set the same. The first and second distances D1 and D2 are preferably shorter than the wavelength of the incident light. For example, in the region where blue light is incident, the wavelength in the first oxide film 94 is about 310 nm. For this reason, the first and second distances D1 and D2 are shorter than 310 nm, for example, about 200 nm.
　第１及び第２の距離Ｄ１、Ｄ２は、必ずしも同一である必要がなく、異なっていてもよい。例えば、図２３に示すように、ダミープラグ９２の上下方向の長さを、ダミープラグ１４６の上下方向の長さと同一としてもよい。これにより、ダミープラグ９２、１４６を同一の製造工程で製造することができる。このように、ダミープラグ９２の長さを短くすることで、光の遮蔽効果がやや低下するが、製造が効率化され、ダミープラグを配置可能な領域が広がる。 The first and second distances D1 and D2 are not necessarily the same and may be different. For example, as shown in FIG. 23, the vertical length of the dummy plug 92 may be the same as the vertical length of the dummy plug 146. Thereby, the dummy plugs 92 and 146 can be manufactured in the same manufacturing process. As described above, by shortening the length of the dummy plug 92, the light shielding effect is slightly reduced, but the manufacturing efficiency is improved and the area where the dummy plug can be disposed is widened.
　また、上記実施形態では、ゲート電極と各ダミープラグとで各ＰＤを囲んでいるが、各ダミープラグとともに各ＰＤを囲うための電極は、ゲート電極以外の他の用途の電極でもよい。 Further, in the above embodiment, each PD is surrounded by the gate electrode and each dummy plug, but the electrode for surrounding each PD together with each dummy plug may be an electrode for other purposes other than the gate electrode.
　また、上記各実施形態では、固体撮像装置としてＣＭＯＳイメージセンサを例示しているが、本発明は、ＣＣＤイメージセンサ等の固体撮像装置にも適用可能である。 In each of the above embodiments, a CMOS image sensor is exemplified as the solid-state imaging device, but the present invention can also be applied to a solid-state imaging device such as a CCD image sensor.
　１０　ＣＭＯＳイメージセンサ
　１１～１４　第１～第４の画素
　１１ａ～１４ａ　第１～第４のＰＤ
　１１ｃ～１４ｃ　第１～第４のカラーフィルタ
　５０　半導体基板
　５１～５４、６５～６７　ゲート電極
　５５、５７、５９、６１、７０、７５、８１　配線
　５６、５８、６０、６２、７３、７４、７６、７８、８２　プラグ
　９０　遮光体
　９２　ダミープラグ
　１０２　遮光膜
　１０４　配線層 10 CMOS image sensor 11 to 14 1st to 4th pixel 11a to 14a 1st to 4th PD
11c to 14c First to fourth color filters 50 Semiconductor substrate 51 to 54, 65 to 67 Gate electrode 55, 57, 59, 61, 70, 75, 81 Wiring 56, 58, 60, 62, 73, 74, 76 , 78, 82 Plug 90 Light shielding body 92 Dummy plug 102 Light shielding film 104 Wiring layer

Claims (14)

  1. 　入射した光を電荷に変換して蓄積する複数の光電変換部が配設された半導体基板と、
    　前記半導体基板の上方に設けられ、前記各光電変換部に光を集光する複数のマイクロレンズと、
    　前記半導体基板上で前記各光電変換部の周囲に設けられた複数の電極と、
    　前記各電極上に形成された遮光膜と、
    　前記複数の電極の上方に設けられ、前記各光電変換部から信号電荷を読み出すための複数の配線を有する配線層と、
    　前記電極と前記配線とを電気的に接続するプラグと、
    　前記電極と電気的に非接続の複数のダミープラグが、前記複数の電極とともに前記各光電変換部を囲う枠状に配置されてなる遮光体と、
    　を備えることを特徴とする固体撮像装置。     A semiconductor substrate provided with a plurality of photoelectric conversion units that convert incident light into electric charges and store them;
    A plurality of microlenses provided above the semiconductor substrate and condensing light on the photoelectric conversion units;
    A plurality of electrodes provided around each photoelectric conversion unit on the semiconductor substrate;
    A light-shielding film formed on each of the electrodes;
    A wiring layer provided above the plurality of electrodes and having a plurality of wirings for reading signal charges from the photoelectric conversion units;
    A plug for electrically connecting the electrode and the wiring;
    A plurality of dummy plugs that are not electrically connected to the electrodes, together with the plurality of electrodes, arranged in a frame shape surrounding each photoelectric conversion unit;
    A solid-state imaging device comprising:
  2. 　前記各ダミープラグは、前記配線及び前記半導体基板のいずれか一方または両方と電気的に非接続であることを特徴とする請求の範囲第１項に記載の固体撮像装置。 The solid-state imaging device according to claim 1, wherein each of the dummy plugs is not electrically connected to either or both of the wiring and the semiconductor substrate.
  3. 　前記複数のダミープラグは、隣り合う前記ダミープラグとの間に入射する光の波長よりも狭い間隔で配置されていることを特徴とする請求の範囲第２項に記載の固体撮像装置。 3. The solid-state imaging device according to claim 2, wherein the plurality of dummy plugs are arranged at a narrower interval than the wavelength of light incident between the adjacent dummy plugs.
  4. 　隣り合う前記ダミープラグとの間は、酸化シリコンにより埋められていることを特徴とする請求の範囲第３項に記載の固体撮像装置。 The solid-state imaging device according to claim 3, wherein a gap between the adjacent dummy plugs is filled with silicon oxide.
  5. 　前記各光電変換部と前記各マイクロレンズとの間には、赤色、緑色、青色のいずれかの色のカラーフィルタが設けられており、
    　前記ダミープラグの間隔は、赤色の光が入射する部分では約４００ｎｍ以下であり、緑色の光が入射する部分では約３００ｎｍ以下であり、青色の光が入射する部分では約２００ｎｍ以下であることを特徴とする請求の範囲第４項に記載の固体撮像装置。     Between each photoelectric conversion unit and each microlens, a color filter of any one of red, green, and blue is provided,
    The interval between the dummy plugs is about 400 nm or less in the portion where the red light is incident, about 300 nm or less in the portion where the green light is incident, and about 200 nm or less in the portion where the blue light is incident. The solid-state imaging device according to claim 4, wherein
  6. 　前記ダミープラグは、複数列に並列して配置され、隣接する２列のうち一方の列は、他方の列に対して、配列周期の半分に相当する距離だけ、配列方向に位置がずれていることを特徴とする請求の範囲第２項に記載の固体撮像装置。 The dummy plugs are arranged in parallel in a plurality of columns, and one of two adjacent columns is displaced in the arrangement direction by a distance corresponding to half of the arrangement period with respect to the other column. The solid-state imaging device according to claim 2, wherein:
  7. 　前記各ダミープラグは、前記半導体基板と前記配線層との間に形成され、上端が前記配線に接触し、下端が前記半導体基板の表面から離れていることを特徴とする請求の範囲第２項に記載の固体撮像装置。 The each dummy plug is formed between the semiconductor substrate and the wiring layer, the upper end is in contact with the wiring, and the lower end is separated from the surface of the semiconductor substrate. The solid-state imaging device described in 1.
  8. 　前記各光電変換部と前記各マイクロレンズとの間には、赤色、緑色、青色のいずれかの色のカラーフィルタが設けられており、
    　前記各ダミープラグの下端は、前記半導体基板の表面から約２００ｎｍ～４００ｎｍ離れていることを特徴とする請求の範囲第６項に記載の固体撮像装置。     Between each photoelectric conversion unit and each microlens, a color filter of any one of red, green, and blue is provided,
    The solid-state imaging device according to claim 6, wherein the lower end of each dummy plug is separated from the surface of the semiconductor substrate by about 200 nm to 400 nm.
  9. 　前記配線層は、複数の配線が積層された多層構造であり、前記ダミープラグは、前記積層された各層の間に形成されていることを特徴とする請求の範囲第２項に記載の固体撮像装置。 The solid-state imaging according to claim 2, wherein the wiring layer has a multilayer structure in which a plurality of wirings are stacked, and the dummy plug is formed between the stacked layers. apparatus.
  10. 　電気的に孤立したダミー配線を備え、
    　前記ダミープラグは、前記配線には接続されず、前記ダミー配線に接続されていることを特徴とする請求の範囲第２項に記載の固体撮像装置。     With electrically isolated dummy wiring,
    The solid-state imaging device according to claim 2, wherein the dummy plug is not connected to the wiring, but is connected to the dummy wiring.
  11. 　前記ダミープラグは、前記半導体基板の上方の前記電極が形成されていない領域に加えて、前記電極の上方にも形成されていることを特徴とする請求の範囲第２項に記載の固体撮像装置。 3. The solid-state imaging device according to claim 2, wherein the dummy plug is formed above the electrode in addition to a region where the electrode is not formed above the semiconductor substrate. .
  12. 　前記電極の上方に形成された前記ダミープラグから前記電極までの第１の距離は、前記電極が形成されていない領域に形成された前記ダミープラグから前記半導体基板までの第２の距離とほぼ同一であることを特徴とする請求の範囲第１１項に記載の固体撮像装置。 A first distance from the dummy plug formed above the electrode to the electrode is substantially the same as a second distance from the dummy plug formed in a region where the electrode is not formed to the semiconductor substrate. The solid-state imaging device according to claim 11, wherein:
  13. 　前記第１及び第２の距離は、入射する光の波長よりも短いことを特徴とする請求の範囲第１２項に記載の固体撮像装置。 13. The solid-state imaging device according to claim 12, wherein the first and second distances are shorter than a wavelength of incident light.
  14. 　前記電極の上方に形成された前記ダミープラグの長さは、前記電極が形成されていない領域に形成された前記ダミープラグの長さとほぼ同一であることを特徴とする請求の範囲第１１項に記載の固体撮像装置。 12. The length of the dummy plug formed above the electrode is substantially the same as the length of the dummy plug formed in a region where the electrode is not formed. The solid-state imaging device described.
PCT/JP2012/077059 2011-11-24 2012-10-19 Solid state image pick-up device WO2013077121A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004104203A (en) * 2002-09-05 2004-04-02 Toshiba Corp Solid state imaging device
JP2005311208A (en) * 2004-04-23 2005-11-04 Sharp Corp Solid-state imaging element, manufacturing method therefor, and electronic information apparatus
JP2007081401A (en) * 2005-09-12 2007-03-29 Magnachip Semiconductor Ltd Image sensor reduced in light interference
JP2009290000A (en) * 2008-05-29 2009-12-10 Toshiba Corp Solid-state imaging apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004104203A (en) * 2002-09-05 2004-04-02 Toshiba Corp Solid state imaging device
JP2005311208A (en) * 2004-04-23 2005-11-04 Sharp Corp Solid-state imaging element, manufacturing method therefor, and electronic information apparatus
JP2007081401A (en) * 2005-09-12 2007-03-29 Magnachip Semiconductor Ltd Image sensor reduced in light interference
JP2009290000A (en) * 2008-05-29 2009-12-10 Toshiba Corp Solid-state imaging apparatus

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