JP2023129260A - image sensor - Google Patents

Abstract

To provide an image sensor that can materialize clear image quality.SOLUTION: An image sensor is provided. The image sensor includes: a substrate including a first surface and a second surface opposite each other; a pixel separation portion that penetrates the substrate, separates the substrate into a plurality of pixels, and has a planar grid shape, wherein the pixels constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently a natural number of 2 or more; a light-shielding grid disposed on the first surface and overlapping the pixel separation portion; and a light adjuster overlapping the pixel separating portion at the center of each of the first to third pixel groups and disposed on the first surface, wherein the light-shielding grid has a first width in a first direction, and the light adjuster has a second width in the first direction that is larger than the first width.SELECTED DRAWING: Figure 4A

Description

The present invention relates to an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. A CMOS image sensor is abbreviated as CIS (CMOS image sensor). CIS includes a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). A photodiode serves to convert incident light into an electrical signal.

US Patent No. 10,014,338B2

An object of the present invention is to provide an image sensor that can provide clear image quality.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the description below.

To achieve the above object, an image sensor according to an embodiment of the present invention includes a substrate including a first surface and a second surface opposite to each other, and a plurality of pixels that penetrate through the substrate, are separated into a plurality of pixels, and are arranged in a planar grid. a pixel separation unit having a shape, the pixels forming first to third pixel groups arranged in n columns and m rows, where n and m are each independently a natural number of 2 or more; a light-shielding grid disposed on the first surface and overlaid with the pixel separation section; and a light-shielding grid overlaid with the pixel separation section at the center of each of the first to third pixel groups and placed on the first surface. a light conditioner disposed, the light blocking grid having a first width in a first direction, and the light conditioner having a second width in the first direction that is larger than the first width.

An image sensor according to an embodiment of the present invention includes a substrate including a first surface and a second surface opposite to each other, and a pixel separation section that penetrates the substrate, separates the pixels into a plurality of pixels, and has a planar grid shape. The pixels constitute first to third pixel groups arranged in n columns and m rows, n and m are each independently a natural number of 2 or more, and the pixel separation part is formed of a polysilicon pattern. a pixel isolation section including an insulating film surrounding the pixel isolation section; a transfer gate disposed on the second surface; a floating diffusion region adjacent to the second surface and disposed beside the transfer gate; a light blocking grid disposed on one surface and overlapping with the pixel separation section; and a light control grid disposed on the first surface and overlapping with the pixel separation section at the center of each of the first to third pixel groups. a color filter disposed between the light adjuster and the light shielding grid; a color filter disposed on the color filter, the light shielding grid, and the light adjuster, and a color filter disposed on the first to third pixel groups, respectively; a corresponding microlens, the light blocking grid has a first width in a first direction, the light modulator has a second width in the first direction that is greater than the first width, and the light modulator has a second width in the first direction that is larger than the first width; The upper end of the vessel is located at a distance of 1/3 to 2/3 of the radius of curvature of the microlens from the upper end of the microlens.

An image sensor according to another embodiment of the present invention includes a substrate including a first surface and a second surface opposite to each other, and a pixel separation structure that penetrates the substrate and is separated into a plurality of pixels and has a grid shape in a plane. a pixel separation unit, wherein the pixels constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently a natural number of 2 or more; a light shielding grid disposed on a first surface and overlapping with the pixel separation section; and a light shielding grid disposed on the first surface and overlapping with the pixel separation section at the center of each of the first to third pixel groups. a conditioner, the light-blocking grid having a first width in a first direction, the light conditioner having a second width in the first direction that is greater than the first width, and the light-blocking grid having a second width in the first direction; The light modulator has a first light-shielding pattern and a first low refraction pattern stacked together, and the light adjuster has a second light-shielding pattern and a second low-refraction pattern stacked in order, and the first light-shielding pattern and the second light-shielding pattern The patterns include the same metal, and the first low refraction pattern and the second low refraction pattern include the same dielectric material.

The image sensor according to the present invention includes a light regulator capable of adjusting the path of light to prevent light from entering the polysilicon pattern included in the pixel separation part located at the center of the pixel group. can. Therefore, it is possible to improve quantum efficiency and realize clear image quality with an image sensor. It can also provide excellent autofocus functionality.

FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention. FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the invention. FIG. 1 is a plan view of an image sensor according to an embodiment of the present invention. FIG. 2 is a top view of one pixel group of an image sensor according to an embodiment of the invention. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 4A shows the path of light in the image sensor of FIG. 4A. 4B are cross-sectional views sequentially illustrating a manufacturing process of an image sensor having the cross section of FIG. 4A. FIG. 4B are cross-sectional views sequentially illustrating a manufacturing process of an image sensor having the cross section of FIG. 4A. FIG. 1 shows a partial plan view of an image sensor according to an embodiment of the invention. FIG. 1 shows a partial plan view of an image sensor according to an embodiment of the invention. FIG. 1 shows a partial plan view of an image sensor according to an embodiment of the invention. FIG. 1 shows a partial plan view of an image sensor according to an embodiment of the invention. FIG. 1 shows a top view of an image sensor according to an embodiment of the invention. 1 shows a top view of an image sensor according to an embodiment of the invention. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A, according to an embodiment of the present invention. FIG. 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of FIG. 3 taken along line A-A' according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in order to more specifically explain the present invention, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

Referring to FIG. 1, the image sensor includes an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, and a timing generator ( timing generator) 1005, correlated double sampler (CDS) 1006, analog to digital converter (ADC) 1007, and input/output buffer (I/O buffer) 10 08.

The active pixel sensor array 1001 includes a plurality of unit pixels arranged in two dimensions, and can convert optical signals into electrical signals. The active pixel sensor array 1001 can be driven by a plurality of drive signals from the row driver 1003, such as a pixel selection signal, a reset signal, and a charge transfer signal. The converted electrical signal can also be provided to a correlated dual sampler 1006.

The row driver 1003 may provide the active pixel sensor array 1001 with a number of driving signals for driving a number of unit pixels according to the results decoded by the row decoder 1002. When unit pixels are arranged in a matrix, a driving signal can be provided for each row.

Timing generator 1005 can provide timing and control signals to row decoder 1002 and column decoder 1004.

A correlated double sampler (CDS) 1006 can receive and sample and hold electrical signals generated by the active pixel sensor array 1001. The correlated double sampler 1006 can double sample a specific noise level and a signal level of an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

An analog-to-digital converter (ADC) 1007 can convert the analog signal corresponding to the differential level output from the correlated double sampler 1006 into a digital signal and output the digital signal.

The input/output buffer 1008 can latch the digital signal and sequentially output the latched digital signal to a video signal processing unit (not shown) according to the decoding result of the column decoder 1004.

FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, the sensor array 1001 includes a plurality of pixels PX, and the pixels PX may be arranged in a matrix shape. Each pixel PX may include a transfer transistor TX and logic transistors RX, SX, and DX. The logic transistors may include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. Transfer transistor TX can include a transfer gate TG. Each pixel PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

The photoelectric conversion element PD can generate and accumulate photoelectric charges in proportion to the amount of light incident from the outside. The photoelectric conversion element PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, and combinations thereof. The transfer transistor TX can transfer the charge generated by the photoelectric conversion element PD to the floating diffusion region FD. Charges generated by the photoelectric conversion element PD can be transferred and cumulatively stored in the floating diffusion region FD. The source follower transistor DX can be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

The reset transistor RX can periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode may be connected to the power supply voltage VDD. When the reset transistor RX is turned on, a power voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD can be discharged and the floating diffusion region FD can be reset.

The source follower transistor DX may function as a source follower buffer amplifier. The source follower transistor DX can amplify the potential change in the floating diffusion region FD and output it to the output line Vout.

The selection transistor SX can select pixels PX to be read out row by row. When the selection transistor SX is turned on, a power supply voltage VDD may be applied to the drain electrode of the source follower transistor DX.

FIG. 3A is a top view of an image sensor according to an embodiment of the invention. FIG. 3B is a top view of one pixel group of an image sensor according to an embodiment of the invention. FIG. 4A is a cross-sectional view of FIG. 3A taken along line A-A' according to an embodiment of the present invention. FIG. 4B shows the path of light in the image sensor of FIG. 4A.

Referring to FIGS. 3A, 3B, and 4A, an image sensor 500 according to the present example may include a semiconductor substrate 1. Referring to FIGS. Semiconductor substrate 1 may be a silicon single crystal wafer or a silicon epitaxial layer. The semiconductor substrate 1 may be doped with a first conductivity type impurity. The first conductivity type may be P type, and the impurity may be boron. The semiconductor substrate 1 may include a first surface 1a and a second surface 1b facing each other.

A shallow isolation section 2 may be arranged adjacent to the first surface 1a of the semiconductor substrate 1. The shallow isolation portion 2 can define an active region for a transistor disposed on the first surface 1a. The shallow isolation portion 2 may be formed using a shallow trench isolation (STI) process. The shallow isolation region 2 may have a single film structure or a multilayer structure of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

A pixel isolation section DTI is disposed on the semiconductor substrate 1 to isolate the pixels PX from each other. The pixel isolation portion DTI may be disposed within the deep trench 7. The deep trench 7 may be formed from the first surface 1a toward the second surface 1b. The deep trench 7 may be formed penetrating the shallow isolation portion 2 and the semiconductor substrate 1 . The width of the deep trench 7 can become narrower from the first surface 1a to the second surface 1b. The pixel separation unit DTI may include an inter-group pixel separation unit DTI-1 and an intra-group pixel separation unit DTI-2.

The pixel isolation part DTI may include a polysilicon pattern 51 doped with impurities, a side insulating layer 55 surrounding the sidewalls of the polysilicon pattern 51, and a buried insulating pattern 4. Since the polysilicon pattern 51 has approximately the same coefficient of thermal expansion as the semiconductor substrate 1 made of single crystal silicon, it is possible to reduce the physical stress caused by the difference in the coefficient of thermal expansion of the materials. Additionally, the polysilicon pattern 51 may serve as a common bias line. A negative voltage may be applied to the polysilicon pattern 51. Dark current characteristics can be improved by trapping holes that may exist on the surface of the deep trench 7. The side insulating layer 55 and the buried insulating pattern 4 may each independently have a single layer structure or a multi-layer structure of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The transfer transistor TX described with reference to FIG. 2 can be arranged on the first surface 1a of each pixel PX. Furthermore, at least one of the logic transistors RX, SX, and DX may be arranged in each pixel PX. Logic transistors RX, SX, and DX can be shared with adjacent pixels PX. The transfer transistor TX may include a transfer gate TG, a gate insulating film GO, and a floating diffusion region FD disposed next to the transfer gate TG.

The transfer gate TG may have a vertical type shape in which a portion thereof is inserted into the substrate 1. Alternatively, the transfer gate TG may have a planar type shape. The gate insulating film GO may include, for example, at least one of silicon oxide, silicon nitride, and a high-k film. A high-k film can include an insulating material having a dielectric constant higher than that of silicon oxide. Transfer gate TG can include a conductive film. The floating diffusion region FD may be doped with impurities of a second conductivity type opposite to the first conductivity type. Although the floating diffusion regions FD are illustrated as being disposed in each pixel PX in FIG. 4A, the floating diffusion regions FD may be shared between adjacent pixels PX. In this case, the floating diffusion region FD may be located between adjacent pixels PX or at the center of the pixel groups GP1 to GP3.

A ground region GR may be disposed in the substrate 1 adjacent to the first surface 1a of each pixel PX. The ground region GR may be doped with the first conductivity type impurity doped into the substrate 1, and may be doped at a higher concentration than the impurity doped into the substrate 1.

A photoelectric conversion unit PD can be arranged within the substrate 1 in each pixel PX. The photoelectric conversion portion PD may be a region doped with impurities of a second conductivity type opposite to the first conductivity type. For example, the photoelectric conversion unit PD may be doped with N-type arsenic or phosphorus. The photoelectric conversion portion PD can form a PN junction with the surrounding semiconductor substrate 1 to form a photodiode.

The first surface 1a of the semiconductor substrate 1 may be covered with an interlayer insulating film IL. The interlayer insulating layer IL may include a single layer or a multilayer structure of at least one of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a porous insulating layer. Multilayer wiring 5 can be arranged within the interlayer insulating film IL.

The pixels PX may be two-dimensionally arranged along the first direction X and the second direction Y, as shown in FIG. 3A. One pixel group GP1 to GP3 can be configured by four pixels PX that are adjacent to each other and arranged in a 2x2 array consisting of two columns and two rows. The pixel groups GP1 to GP3 may be covered with corresponding color filters CF1 to CF3 and microlenses ML, respectively. That is, the first pixel group GP1 including four pixels PX arranged in two columns and two rows may be covered with one first color filter CF1 and one microlens ML. A second pixel group GP2 including four pixels PX arranged in two columns and two rows may be covered with one second color filter CF2 and one microlens ML. A third pixel group GP3 including four pixels PX arranged in two columns and two rows may be covered with one third color filter CF3 and one microlens ML. Lower portions of the microlenses ML may be connected to each other. Each of the color filters CF1-CF3 can have one color among green, red, and blue. For example, the first color filter CF1 may be red, the second color filter CF2 may be blue, and the third color filter CF3 may be green.

The image sensor 500 can perform an autofocus function by sensing light entering through one microlens ML arranged on one pixel group GP1 to GP3 using four pixels PX. Furthermore, since the four pixels PX constituting one pixel group GP1 to GP3 are separated by the pixel separation unit DTI, it is possible to prevent a blooming phenomenon between adjacent pixels PX. Therefore, it is possible to perform an excellent autofocus function and realize clear image quality. Image sensor 500 may be an autofocus image sensor. In this example, four pixels PX arranged in a 2×2 array constitute one pixel group GP1 to GP3, but the present invention is not limited thereto. That is, the pixels PX in the nxm array can form one pixel group GP1 to GP3, where n and m can each independently be a natural number of 2 or more.

A fixed charge layer 15 may be interposed between the color filters CF1 to CF3 and the second surface 1b. The fixed charge film 15 can be in contact with the second surface 1b. Fixed charge film 15 can have negative fixed charges. The fixed charge film 15 is a metal oxide containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanoids. (metal oxide) or metal fluoride (metal fluoride). For example, the fixed charge layer 15 may be a hafnium oxide layer or an aluminum oxide layer. At this time, hole accumulation may occur around the fixed charge layer 15. Therefore, the generation of dark current and white spots can be effectively reduced.

Although not shown, an anti-reflection film, a planarization film, etc. may be additionally disposed between the color filters CF1 to CF3 and the fixed charge film 15. Anti-reflection film 46 can include, for example, silicon oxide or silicon nitride. The planarization film can include silicon oxide.

A light shielding grid WG may be disposed on the fixed charge film 15. The light shielding grid WG may be overlapped with the pixel separation part DTI located between the pixel groups GP1 to GP3. A light modulator LS may be disposed on the fixed charge layer 15 at the center of each of the pixel groups GP1 to GP3, and overlapped with the pixel isolation part DTI. The light adjuster LS may be separated from the light shielding grid WG.

The light modulator LS can be overlapped with the center of the microlens ML disposed thereon. For example, the center of the light modulator LS can be overlapped with the center of the microlens ML disposed thereon. The light conditioner LS may be covered with a corresponding one of the color filters CF1 to CF3. The light blocking grid WG may be covered with adjacent color filters CF1 to CF3.

The light shielding grid WG may include a first light shielding pattern 17a and a first low refractive pattern 25a stacked in this order. The light conditioner LS may include a second light shielding pattern 17b and a second low refraction pattern 25b that are stacked in this order. The first light blocking pattern 17a and the second light blocking pattern 17b may have the same thickness and include the same metal. For example, the first light blocking pattern 17a and the second light blocking pattern 17b may include titanium or tungsten. The first low refraction pattern 25a and the second low refraction pattern 25b may include the same dielectric material. The first low refractive pattern 25a and the second low refractive pattern 25b may have a refractive index lower than the refractive index of the color filters CF1 to CF3. Preferably, the first low refractive pattern 25a and the second low refractive pattern 25b have a refractive index of 1.3 or less. Therefore, the incident lights L1 and L2 that are incident as shown in FIG. 4B are refracted by the light adjuster LS and then incident on the photoelectric conversion unit PD of the corresponding pixel PX.

As shown in FIG. 4A, the light blocking grid WG may have a first width WT1. The light conditioner LS may have a second width WT2 that is wider than the first width WT1. For example, the second width WT2 may be two to four times the first width WT1. The light adjuster LS may have a cross shape in plan view as shown in FIGS. 3A and 3B. The second width WT2 of the light adjuster LS may be wider than the width of the pixel separation part DTI. The light conditioner LS can completely cover the pixel isolation part DTI located at the center of each of the pixel groups GP1 to GP3. The light modulator LS can have a (right) rectangular cross section.

As shown in FIG. 4A, the upper surface of the light shielding grid WG may have a first level LV1. The top surface of the light conditioner LS may have a second level LV2. In this example, the second level LV2 may be the same as the first level LV1. The upper surface of the light conditioner LS may be located at or near the focal length of the microlens ML. Preferably, the distance DS2 from the upper end of the microlens ML to the upper surface of the light adjuster LS may be between 1/3 and 2/3 of the radius of curvature DS1 of the microlens ML. Therefore, as shown in FIG. 4B, the lights L1 and L2 that are incident through the microlens ML are scattered by the light adjuster LS and are incident on the photoelectric conversion unit PD. Therefore, it is possible to prevent the lights L1 and L2 from entering the polysilicon pattern 51 located within the pixel isolation section DTI below the light adjuster LS. Since polysilicon has the property of absorbing light, when light is incident on the polysilicon pattern 51, optical loss occurs, and therefore quantum efficiency (incident photon signal electron conversion efficiency) may decrease. In the present invention, the quantum efficiency can be improved by the light regulator LS. Therefore, the amount of light in the image sensor increases, the light sensitivity is improved, and clear image quality can be realized. It can also provide excellent autofocus functionality.

5A and 5B are cross-sectional views sequentially illustrating a manufacturing process of an image sensor having the cross section of FIG. 4A.

Referring to FIG. 5A, a substrate 1 having a first surface 1a and a second surface 1b opposite to each other is prepared. A shallow element isolation section 2 and a pixel isolation section DTI are formed on the substrate 1 through a normal process to define the pixel PX. The pixel isolation part DTI may be formed to include a polysilicon pattern 51 doped with impurities, a side insulating layer 55 surrounding the sidewalls of the polysilicon pattern 51, and a buried insulating pattern 4. The side insulating film 55 may be formed to cover the bottom of the deep trench 7. The side insulating film 55 may be formed to be separated from the second surface 1b. A photoelectric conversion unit PD is formed in the substrate 1 in each pixel PX. A transfer gate TG, a gate insulating film GO, a floating diffusion region FD arranged next to the transfer gate TG, and a ground region GR are formed on the first surface 1a. Multilayer wiring 5 and interlayer insulating film IL are formed on first surface 1a. Turn the substrate 1 over so that the second surface 1b is on top.

Referring to FIG. 5B, a back grinding process is performed on the second surface 1b of the substrate 1 to remove a portion of the substrate 1 and a portion of the side insulating film 55, thereby forming a polysilicon pattern of the pixel isolation portion DTI. 51 is exposed. A fixed charge film 15 is formed on the second surface 1b of the substrate 1. After sequentially stacking a light shielding film and a low refractive film on the fixed charge film 15, the low refractive film and the light shielding film are sequentially etched to form a light shielding grid WG and a light adjuster LS, and the fixed charge film 15 expose. The light shielding grid WG may include a first light shielding pattern 17a and a first low refractive pattern 25a stacked in this order. The light conditioner LS may include a second light shielding pattern 17b and a second low refraction pattern 25b that are stacked in this order. The light conditioner LS may be formed to overlap the pixel separation unit DTI at the center of each of the pixel groups GP1 to GP3. The light adjuster LS may be formed to have a cross shape in plan view, as shown in FIG. 3A.

In the present invention, when forming the light shielding grid WG, the light adjuster LS can be formed at the same time. Therefore, a separate process for forming the light adjuster LS is not required, so the process can be simplified.

Next, referring to FIGS. 3A and 4A, color filters CF1 to CF3 are formed on fixed charge film 15. One of the color filters CF1 to CF3 is formed to cover a corresponding one of the pixel groups GP1 to GP3. The color filters CF1 to CF3 can cover the light shielding grid WG and the light adjuster LS. Microlenses ML are formed on each of color filters CF1 to CF3.

6A-6D illustrate partial top views of image sensors according to embodiments of the present invention.

Referring to FIG. 6A, the light adjuster LS according to the present example may have a circular shape in plan. The light adjuster LS may be separated from the light shielding grid WG, and the pixel isolation part DTI may be exposed between them.

Alternatively, referring to FIG. 6B, the light adjuster LS may have a cross shape in plan. The light conditioner LS may be connected to the light shielding grid WG through a grid protrusion WGP. The grid protruding portion WGP is overlapped with the pixel separation portion DTI. In this case, the pixel isolation portion DTI is not exposed between the light adjuster LS and the light shielding grid WG. The light conditioner LS, the grid protrusion WGP, and the light shielding grid WG may be integrated, and there may be no boundary area between them.

Alternatively, referring to FIG. 6C, the light adjuster LS may have a cross shape in plan view. The light regulator LS may have an empty space CV inside. The free space CV can be overlapped with the center of one pixel group GP1 to GP3. The light adjuster LS may be separated from the light shielding grid WG, and the pixel isolation part DTI may be exposed between them.

Alternatively, referring to FIG. 6D, the light modulator LS may have a rectangular, pyramidal, or rhombic shape in plan view. The light adjuster LS may be separated from the light shielding grid WG, and the pixel isolation part DTI may be exposed between them.

7A and 7B show top views of image sensors according to embodiments of the present invention.

Referring to FIG. 7A, the image sensor 501 according to the present example may include light modulators LS1 to LS4 of various shapes. Each of the light regulators LS1 to LS4 is separated from the light shielding grid WG. For example, the cross-shaped first light adjuster LS1 disclosed in FIG. 3B may be disposed at the center of the first pixel group GP1 located at the top and first from the left in FIG. 7A. The circular second light adjuster LS2 disclosed in FIG. 6A may be disposed at the center of the third pixel group GP3 located at the top and second from the left in FIG. 7A. At the center of the first pixel group GP1 located third from the left at the top in FIG. 7A, the third light adjuster LS3 having a diagonal shape as shown in FIG. 6D may be disposed. At the center of the third pixel group GP3 located fourth from the left at the top in FIG. 7A, a cross-shaped fourth light regulator LS4 having an internal empty space CV disclosed in FIG. 6C may be disposed. can. The positions of the light modulators LS1-LS4 can vary from column to column or from row to row.

Referring to FIG. 7B, the light conditioner LS of the image sensor 502 according to the present example may be connected to the light shielding grid WG through the grid protrusion WGP. The image sensor 502 of FIG. 7B has a shape in which a plurality of pixel groups GP1 to GP3 as shown in FIG. 6B are provided and arranged in two dimensions.

8A to 8E are cross-sectional views of FIG. 3A taken along line A-A' according to an embodiment of the present invention.

Referring to FIG. 8A, in the image sensor 503 according to the present example, the upper surface of the light blocking grid WG may have a first level LV1. The top surface of the light conditioner LS may have a second level LV2. In this example, the second level LV2 may be different from the first level LV1. The second level LV2 may be higher than the first level LV1. Other configurations may be the same as described with reference to FIG. 4A.

Referring to FIG. 8B, in the image sensor 504 according to the present example, the light conditioner LS may have an inclined sidewall. The light modulator LS can have a triangular cross section. The other configuration may be the same as that described with reference to FIG. 8A.

Referring to FIG. 8C, in the image sensor 505 according to the present example, the light adjuster LS may have an empty space CV. The empty space CV can also be referred to as an air gap region. The empty space CV may expose the upper surface of the second light blocking pattern 17b. The second low refraction pattern 25b can limit the top and side surfaces of the empty space CV. Other configurations may be the same as described with reference to FIG. 4A. FIG. 8C may correspond to the cross section of FIG. 6C.

Referring to FIG. 8D, in the image sensor 506 according to the present example, the light adjuster LS, the light shielding grid WG, and the fixed charge film 15 may be conformally covered with a gas permeable film GSPL. The gas permeable film GSPL may be formed of at least one material selected from the group including silicon dioxide (SiO ₂ ), silicon oxide hydrogen carbide (SiOCH), and silicon nitride carbide (SiCN). The gas permeable membrane GSPL may have a thickness of 0.001 to 5 nm. At this time, the first and second low refractive patterns 25a and 25b forming the light shielding grid WG and the light adjuster LS, respectively, may be air gap regions. In the image sensor 506 of FIG. 8D, the first and second low refractive patterns 25a and 25b are formed of a material that can be decomposed by heat or light (for example, ultraviolet light) in the step of FIG. After the gas permeable film GSPL is conformally formed on the low refractive patterns 25a and 25b, heat or light can be applied to the first and second low refractive patterns 25a and 25b. Accordingly, the first and second low refractive patterns 25a and 25b are decomposed into gases having a small molecular weight, and the gases can escape through the gas permeable film GSPL. Therefore, the first and second low refractive index patterns 25a and 25b can be transformed into air gap regions.

Referring to FIG. 8E, in the image sensor 507 according to the present example, the pixel isolation part DTI may be disposed in the deep trench 7. The deep trench 7 may be formed from the second surface 1b toward the first surface 1a. The width of the deep trench 7 can become narrower from the second surface 1b to the first surface 1a. The pixel isolation portion DTI may include a fixed charge layer 9 conformally covering the sidewall of the deep trench 7 and a buried insulating layer 11 filling the deep trench 7 . Fixed charge film 9 can have negative fixed charges. Fixed charge film 9 is a metal oxide containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanoids. (metal oxide) or metal fluoride. For example, the fixed charge film 9 may be a hafnium oxide film or an aluminum oxide film. At this time, hole accumulation may occur around the fixed charge layer 9. Therefore, the generation of dark current and white spots can be effectively reduced. Alternatively, the buried insulating film 11 may be an insulating film with good step coverage characteristics, such as a silicon oxide film. Although not shown, the deep trench 7 can have a lattice shape in plan view. The fixed charge film 9 may be extended onto the second surface 1b and may be in contact with the second surface 1b. The buried insulating layer 11 may also extend onto the second surface 1b.

A device isolation region 3 interposed between a pixel isolation portion DTI and a shallow device isolation portion 2 may be disposed within the semiconductor substrate 1 . The device isolation region 3 may be doped with a first conductivity type impurity. The concentration of the first conductivity type impurity doped into the device isolation region 3 may be higher than the concentration of the first conductivity type impurity doped into the semiconductor substrate 1.

An auxiliary insulating layer 16 may be disposed on the buried insulating layer 11 . The auxiliary insulating layer 16 may include an anti-reflection layer and/or a planarization layer. The auxiliary insulating layer 16 may include a silicon nitride layer and/or an organic insulating layer. Other configurations may be the same as described with reference to FIG. 4A.

FIG. 9 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

Referring to FIG. 9, the image sensor 508 according to the present example may have a structure in which a first sub-chip CH1 and a second sub-chip CH2 are bonded. The first sub-chip CH1 preferably has an image sensing function. The second subchip CH2 may preferably include circuitry for driving the first subchip CH1 or for storing electrical signals generated in the first subchip CH1.

The second subchip CH2 includes a second substrate 100, a plurality of transistors TR disposed on the second substrate 100, a second interlayer insulating film 110 covering the second substrate 100, and a second wiring disposed within the second interlayer insulating film 110. 112. The second interlayer insulating layer 110 may have a single layer structure or a multilayer structure of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous insulating layer. The first subchip CH1 and the second subchip CH2 are bonded. Therefore, the first interlayer insulating film IL and the second interlayer insulating film 110 can be in contact with each other.

The first subchip CH1 includes a first substrate 1 including a pad area PAD, a connection area CNR, an optical black area OB, and a pixel array area APS. The pixel array area APS can include a plurality of pixels PX. A pixel isolation section DTI is disposed on the first substrate 1 in the pixel array region APS to isolate the pixels PX. A shallow isolation portion 2 may be disposed on the first substrate 1 adjacent to the first surface 1a. The pixel isolation section DTI can penetrate the shallow element isolation section 2. A photoelectric conversion unit PD may be disposed within the first substrate 1 in each pixel PX. A transfer gate TG may be disposed on the first surface 1a of the first substrate 1 in each pixel PX. A floating diffusion region FD may be disposed within the first substrate 1 on one side of the transfer gate TG. The first surface 1a may be covered with a first interlayer insulating layer IL. The wiring 5 and the contact CT1 can be arranged in the first interlayer insulating film IL.

It may be assumed that no light enters the substrate 1 in the optical black region OB. The pixel separation part DTI extends to the optical black area OB and can separate the first black pixel PXO1 and the second black pixel PXO2. A photoelectric conversion unit PD may be disposed within the first substrate 1 in the first black pixel PXO1. In the second black pixel PXO2, there is no photoelectric conversion unit PD within the first substrate 1. A transfer gate TG and a floating diffusion region FD may be disposed in the first black pixel PXO1 and the second black pixel PXO2. The first black pixel PXO1 may sense the amount of charge that can be generated from the photoelectric conversion unit PD from which light is blocked, and may provide a first reference amount of charge. The first reference charge amount may serve as a relative reference value when calculating the charge amount generated from the unit pixel UP. The second black pixel PXO2 may sense the amount of charge that can be generated without the photoelectric conversion unit PD, and may provide a second reference amount of charge. The second reference charge amount can be used as information for removing process noise.

The first fixed charge film 24, the second fixed charge film 42, the first protection film 44, and the second protection film 56 are also extended onto the second surface 1b on the optical black area OB, the connection area CNR, and the pad area PAD. can be done.

In the connection region CNR, the connection contact BCA may penetrate through the first passivation layer 44, the second fixed charge layer 42, and a portion of the first substrate 1 to contact the polysilicon pattern 51p of the pixel isolation portion DTI. The coupling contact BCA may be located within the first trench 46 . The connection contact BCA includes a first diffusion prevention pattern 17d that conformally covers the inner wall and bottom surface of the first trench 46, a first metal pattern 52 on the first diffusion prevention pattern 17d, and a second metal pattern that fills the first trench 46. 54.

A portion of the first anti-diffusion pattern 17d may be extended onto the first protective layer 44 on the optical black area OB to provide a first optical black pattern 17c. A portion of the first metal pattern 52 may be extended onto the first optical black pattern 17c on the optical black area OB to provide a second optical black pattern 52a. The second optical black pattern 52a and the connection contact BCA may be covered with a second protective layer 56. A third optical black pattern CFB may be located on the protective layer 56 between the optical black area OB and the connection area CNR.

A first via V1 may be disposed next to the connection contact BCA in the connection region CNR. The first via V1 may also be referred to as a back bias stack via. The first via V1 penetrates through a portion of the first protective film 44, the second fixed charge film 42, the first fixed charge film 24, the first substrate 1, the first interlayer insulating film IL, and the second interlayer insulating film 110. can be in contact with a part of the first wiring 5 and a part of the second wiring 112 at the same time.

The first via V1 may be disposed within the first via hole H1. The first via V1 may include a first diffusion prevention pattern 17d and a first via pattern 52b on the first diffusion prevention pattern 17d. The first via pattern 52b may be connected to the first metal pattern 52. The connection contact BCA may be connected to a portion of the first wiring 5 and a portion of the second wiring 112 through the first via V1.

The first diffusion prevention pattern 17d and the first via pattern 52b may each conformally cover an inner wall of the first via hole H1. The first diffusion prevention pattern 17d and the first via pattern 52b cannot completely fill the first via hole H1. The first low refractive index residual film 50b can fill the first via hole H1. A color filter residual film CFR may be disposed on the first low refractive residual film 50b.

An external connection pad 62 and a second via V2 may be arranged to be connected to each other in the pad region PAD. The external connection pad 62 may penetrate through the first protective layer 44 , the second fixed charge layer 42 , the first fixed charge layer 24 , and a portion of the first substrate 1 . The external connection pad 62 may be disposed within the fourth trench 60. The external connection pad 62 may include a third anti-diffusion pattern 17e and a first pad pattern 52c that sequentially cover the inner wall and bottom of the fourth trench 60 conformally, and a second pad pattern 54a that fills the fourth trench 60.

The second via V2 penetrates through the first protective film 44, the second fixed charge film 42, the first fixed charge film 24, the first substrate 1, the first interlayer insulating film IL, and a part of the second interlayer insulating film 110. It can be in contact with a part of the second wiring 112. The external connection pad 62 may be connected to a portion of the second wiring 112 through a second via V2. The second via V2 may be disposed within the second via hole H2. The second via V2 may include a fourth anti-diffusion pattern 17f and a second via pattern 52d that sequentially and conformally cover an inner wall and a bottom surface of the second via hole H2. The fourth diffusion prevention pattern 17f and the second via pattern 52d cannot completely fill the second via hole H2. The second low refractive index residual film 50c can fill the second via hole H2. A color filter residual layer CFR may be disposed on the second low refractive index residual layer 50c.

The first and second light blocking patterns 17a and 17b, the first anti-diffusion pattern 17d, the first optical black pattern 17c, and the anti-diffusion patterns 17d to 17f may have the same thickness and the same material (for example, titanium). . The first metal pattern 52, the second optical black pattern 52a, the first via pattern 52b, the first pad pattern 52c, and the second via pattern 52d may have the same thickness and the same material (e.g., tungsten). . The second metal pattern 54 and the second pad pattern 54a may be made of the same material (eg, aluminum).

The first and second low refractive index patterns 25a and 25b, the first low refractive index residual layer 50b, and the second low refractive index layer 50c may include the same material. The color filter residual film CFR may include the same color and material as one of the color filters CF1 and CF2.

The first light shielding pattern 17a and the first low refraction pattern 25a can constitute a light shielding grid WG. The second light shielding pattern 17b and the second low refraction pattern 25b may constitute a light adjuster LS.

The second protective layer 56 extends to the pad region PAD and may have an opening that exposes the second pad pattern 54a. A microlens array layer MLL including a plurality of microlenses ML may be extended to an optical black area OB, a connection area CNR, and a pad area PAD. The microlens array layer MLL may have an opening 35 exposing the second pad pattern 54a in the pad region PAD. Other structures may be the same/similar to those described with reference to FIGS. 3A and 4A.

FIG. 10 is a cross-sectional view of FIG. 3A taken along line A-A' according to an embodiment of the present invention.

Referring to FIG. 10, a through electrode 57 may be disposed within the semiconductor substrate 1 in the image sensor 509 according to the present example. The through electrode 57 may be insulated from the polysilicon pattern 51 of the deep isolation region. The through electrode 57 is surrounded by a first via insulating film 59. A via-embedded insulating pattern 4a is arranged between the through electrode 57 and the interlayer insulating film IL. The through electrode 57, the first via insulating film 59, and the via-embedded insulating pattern 4a can be arranged in the through electrode hole 7h arranged in the semiconductor substrate 1. A transfer gate electrode TG may be disposed on the first surface 1a of the semiconductor substrate 1. A first floating diffusion region FD1 may be disposed within the semiconductor substrate 1 adjacent to the transfer gate electrode TG. A second floating diffusion region FD2 may be disposed within the semiconductor substrate 1 and separated from the first floating diffusion region FD1 by a shallow isolation portion 2. A first photoelectric conversion unit PD1 may be disposed within the semiconductor substrate 1 in the unit pixel area UP. The first photoelectric conversion portion PD1 may be a region doped with a second conductivity type impurity.

A fixed charge layer 15 may be disposed on the second surface 1b of the semiconductor substrate 1. Color filters CF1 and CF2 may be disposed on the fixed charge film 15. A light shielding grid WG may be disposed on the fixed charge film 15 between the color filters CF1 and CF2. A light modulator LS may be disposed on the fixed charge film 15 at the center of the pixel groups GP1 to GP3.

A first insulating layer 30 may be disposed on the color filters CF1 and CF2. The first insulating layer 30 may be a silicon oxide layer or a silicon nitride layer. A pixel electrode 32 may be disposed on the first insulating film 30 for each pixel PX. A second insulating layer 144 may be interposed between the pixel electrodes 32. The second insulating layer 144 may be a silicon oxide layer or a silicon nitride layer. A second photoelectric conversion unit PD2 may be disposed on the pixel electrode 32. A common electrode 34 may be disposed on the second photoelectric conversion unit PD2. A passivation layer 36 may be disposed on the common electrode 34. A microlens ML may be disposed on the passivation film 36.

The pixel electrode 32 and the common electrode 34 may include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), and/or an organic transparent conductive material. The second photoelectric conversion unit PD2 may be an organic photoelectric conversion layer. The second photoelectric conversion unit PD2 may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type organic semiconductor material and the n-type organic semiconductor material may form a pn junction. Alternatively, the second photoelectric conversion unit PD2 may include quantum dots or chalcogenide.

The pixel electrode 32 may be electrically connected to the through electrode 57 by a via plug 140. The via plug 140 may include polysilicon doped with impurities, a metal nitride film such as titanium nitride, a metal material such as tungsten, titanium, copper, or a transparent conductive material such as ITO. The via plug 140 can penetrate the light shielding grid WG and the fixed charge film 15 and come into contact with the through electrode 57. A sidewall of the via plug 140 is covered with a second via insulating film 142. The through electrode 57 may be electrically connected to the second floating diffusion region FD2 through the contact CT1 and the wiring 5. Other configurations may be the same/similar to those described with reference to FIGS. 3A and 4A.

Although the embodiments of the present invention have been described above with reference to the attached drawings, it will be understood by those with ordinary knowledge in the technical field to which the present invention pertains that the present invention does not require any change in its technical idea or essential features. It can be understood that other specific forms can be implemented. Therefore, it must be understood that the embodiments described above are illustrative in all respects and are not restrictive. The embodiments of FIGS. 3A-10 can be combined with each other.

1 Semiconductor substrate 2 Shallow element isolation region 7 Deep trench 15 Fixed charge film 46 Anti-reflection film 500 Image sensor CF1 to CF3 Color filter DTI Pixel isolation region FD Floating diffusion region GO Gate insulating film GP1 to GP3 Pixel group GR Ground region IL Interlayer insulation Film LS Light modulator ML Microlens PD Photoelectric conversion unit PX Pixel TG Transfer gate WG Light shielding grid

Claims (10)

a substrate including a first surface and a second surface opposite to each other;
A pixel separation section that penetrates the substrate and separates into a plurality of pixels and has a grid shape in a plan view, the pixels forming first to third pixel groups arranged in n columns and m rows, respectively. a pixel separation unit, where n and m are each independently a natural number of 2 or more;
a light shielding grid disposed on the first surface and overlapping with the pixel separation section;
a light adjuster overlapping the pixel separating section at the center of each of the first to third pixel groups and disposed on the first surface;
The light blocking grid has a first width in a first direction,
The light modulator may have a second width in the first direction that is larger than the first width. a color filter located between the light blocking grid and the light regulator;
further comprising microlenses disposed on the color filter, the light blocking grid, and the light adjuster and corresponding to the first to third pixel groups, respectively;
The image sensor according to claim 1, wherein the upper end of the light adjuster is located at a distance of 1/3 to 2/3 of the radius of curvature of the microlens from the upper end of the microlens. The image sensor according to claim 1, wherein the light adjuster has a shape of a cross, a square, or a circle in plan view. The image sensor according to claim 1, wherein the light modulator has a triangular or square cross section. The image sensor according to claim 1, wherein the light modulator has a cavity inside. The light-shielding grid has a first light-shielding pattern and a first low refraction pattern stacked in order,
The light modulator has a second light shielding pattern and a second low refraction pattern stacked in order,
The first light-shielding pattern and the second light-shielding pattern include the same metal,
The image sensor of claim 1, wherein the first low refraction pattern and the second low refraction pattern include the same dielectric material. The image sensor according to claim 1, wherein a top end of the light modulator is higher than a top end of the light blocking grid. further comprising a gas permeable membrane covering the light regulator,
The image sensor of claim 1, wherein the light modulator includes an air gap region. a substrate including a first surface and a second surface opposite to each other;
A pixel separation section that penetrates the substrate and separates into a plurality of pixels and has a grid shape in a plan view, the pixels forming first to third pixel groups arranged in n columns and m rows, respectively. where n and m are each independently a natural number of 2 or more, and the pixel isolation section includes a polysilicon pattern and an insulating film surrounding the polysilicon pattern;
a transfer gate disposed on the second surface;
a floating diffusion region adjacent to the second surface and disposed beside the transfer gate;
a light shielding grid disposed on the first surface and overlapping with the pixel separation section;
a light adjuster overlapping the pixel separating section at the center of each of the first to third pixel groups and disposed on the first surface;
a color filter disposed between the light regulator and the light blocking grid;
microlenses disposed on the color filter, the light blocking grid, and the light adjuster and corresponding to the first to third pixel groups, respectively;
The light blocking grid has a first width in a first direction,
The light modulator has a second width in the first direction that is larger than the first width,
In the image sensor, the upper end of the light adjuster is located at a distance of 1/3 to 2/3 of the radius of curvature of the microlens from the upper end of the microlens. a substrate including a first surface and a second surface opposite to each other;
A pixel separation section that penetrates the substrate and separates into a plurality of pixels and has a grid shape in a plan view, the pixels forming first to third pixel groups arranged in n columns and m rows, respectively. a pixel separation unit, where n and m are each independently a natural number of 2 or more;
a light shielding grid disposed on the first surface and overlapping with the pixel separation section;
a light adjuster overlapping the pixel separating section at the center of each of the first to third pixel groups and disposed on the first surface;
The light blocking grid has a first width in a first direction,
The light modulator has a second width in the first direction that is larger than the first width,
The light-shielding grid has a first light-shielding pattern and a first low refraction pattern stacked in order,
The light modulator has a second light shielding pattern and a second low refraction pattern stacked in order,
The first light-shielding pattern and the second light-shielding pattern include the same metal,
The first low refraction pattern and the second low refraction pattern may include the same dielectric material.

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