CN112117287A

CN112117287A - Image sensor with a plurality of pixels

Info

Publication number: CN112117287A
Application number: CN202010227364.9A
Authority: CN
Inventors: 金弘基; 金东铉; 金珉宽; 金旻更; 蒋玟澔; 赵寅成
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-06-21
Filing date: 2020-03-27
Publication date: 2020-12-22

Abstract

An image sensor is provided. The image sensor includes a substrate, a mesh structure, and a color filter. The substrate includes a pixel separation structure defining pixel regions and a sub-pixel region for each pixel region. The mesh structure is disposed on the substrate and includes first barrier portions disposed between the sub-pixel regions and second barrier portions disposed between adjacent pixel regions. The mesh structure defines openings corresponding to the sub-pixel regions, respectively. The color filter is disposed in the opening defined by the lattice structure. Each color filter has a flat top surface parallel to its bottom surface.

Description

Image sensor with a plurality of pixels

This application claims priority from korean patent application No. 10-2019-0074388 filed on the korean intellectual property office at 21.6.2019 and from us patent application No. 16/775,937 filed on the us patent and trademark office at 29.1.2020, both of which are hereby incorporated by reference in their entireties.

Technical Field

The present disclosure relates to an image sensor and a method of manufacturing the same, and more particularly, to an image sensor having improved electrical and optical characteristics and a method of manufacturing the same.

Background

The image sensor converts the photon image into an electrical signal. Recent advances in the computer and communications industries have caused a strong demand for high-performance image sensors in various consumer electronic devices, such as digital cameras, mobile phones, camcorders, Personal Communication Systems (PCS), game controllers, security cameras, and medical miniature cameras.

Disclosure of Invention

An aspect provides an image sensor having improved electrical and optical characteristics.

Aspects are not limited to the above-mentioned and other aspects not mentioned above will be clearly understood by those skilled in the art from the following description.

According to an aspect of some example embodiments, there is provided an image sensor including: a substrate including a pixel separation structure defining a plurality of pixel regions and a plurality of sub-pixel regions for each of the plurality of pixel regions; a mesh structure disposed on the substrate and including first barrier portions disposed between the sub-pixel regions and second barrier portions disposed between adjacent pixel regions, the mesh structure defining a plurality of openings corresponding to the plurality of sub-pixel regions, respectively; and a plurality of color filters disposed in the openings defined by the mesh structure, each color filter having a flat top surface, the flat top surface of each color filter being parallel to a bottom surface thereof.

According to another aspect of some example embodiments, there is provided an image sensor including: a substrate having a first surface and a second surface opposite to the first surface, the substrate including a pixel isolation structure defining a plurality of pixel regions; a device isolation layer disposed adjacent to the first surface of the substrate on each of the plurality of pixel regions, the device isolation layer defining an active region in the plurality of pixel regions; a plurality of interlayer dielectric layers stacked on the first surface of the substrate and including contact plugs and connection lines; a fixed charge layer disposed on the second surface of the substrate; a flat dielectric layer disposed on the fixed charge layer; a mesh structure disposed on the flat dielectric layer to overlap the pixel separating structure in a plan view, the mesh structure including barrier portions disposed between adjacent pixel regions, the mesh structure defining a plurality of openings corresponding to the plurality of pixel regions, respectively; a plurality of color filters disposed in the openings defined by the mesh structure; a sacrificial planarizing layer located between adjacent ones of the plurality of color filters, the sacrificial planarizing layer having a top surface coplanar with an uppermost surface of each color filter; and a microlens array disposed on the plurality of color filters.

According to another aspect of some example embodiments, there is provided a method of manufacturing an image sensor, the method including: providing a substrate having a plurality of pixel regions and a plurality of sub-pixel regions for each pixel region; forming a mesh structure on the substrate, the mesh structure including first barrier portions disposed between the sub-pixel regions and second barrier portions disposed between adjacent pixel regions; forming initial color filters on the pixel regions, the initial color filters filling spaces defined by the mesh structures, wherein, in each pixel region, the corresponding initial color filters cover first barrier portions of the mesh structures in the pixel region; forming a sacrificial planarizing layer to cover a top surface of the initial color filter; and performing a planarization process on the sacrificial planarization layer to form a color filter on the pixel region, the color filter having a flat top surface parallel to a bottom surface thereof after the planarization process.

Drawings

FIG. 1 illustrates a simplified plan view showing an image sensor according to some example embodiments;

fig. 2A and 2B illustrate circuit diagrams showing an active pixel sensor array of an image sensor according to some example embodiments;

FIG. 3 illustrates a simplified plan view of an active pixel sensor array showing an image sensor according to some example embodiments;

FIG. 4A illustrates a plan view showing an image sensor according to some example embodiments;

FIG. 4B illustrates a cross-sectional view taken along line I-I' of FIG. 4A showing an image sensor according to some example embodiments;

fig. 5A to 5C illustrate enlarged views showing a section a of fig. 4B;

FIG. 6 illustrates a cross-sectional view taken along line I-I' of FIG. 4A showing an image sensor according to some example embodiments;

fig. 7A and 7B illustrate enlarged views showing a section B of fig. 6;

FIG. 8 illustrates a cross-sectional view taken along line I-I' of FIG. 4A showing an image sensor according to some example embodiments;

fig. 9A and 9B show enlarged views showing a section C of fig. 8;

FIG. 10A illustrates a cross-sectional view taken along line I-I' of FIG. 4A showing an image sensor according to some example embodiments;

fig. 10B shows an enlarged view showing a section D of fig. 10A;

FIG. 11 illustrates a cross-sectional view showing an image sensor according to some example embodiments;

FIG. 12A illustrates a plan view showing an image sensor according to some example embodiments;

FIG. 12B illustrates a cross-sectional view taken along line II-II' of FIG. 12A showing an image sensor according to some example embodiments;

FIG. 13 illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments;

FIG. 14 shows a block diagram showing an image sensor according to some example embodiments;

FIG. 15 illustrates a cross-sectional view showing an image sensor according to some example embodiments;

fig. 16A to 16H illustrate cross-sectional views taken along line I-I' of fig. 4A showing a method of manufacturing an image sensor according to some example embodiments; and

fig. 17A to 17D illustrate cross-sectional views taken along line I-I' of fig. 4A showing a method of manufacturing an image sensor according to some example embodiments.

Detailed Description

An image sensor and a method of manufacturing the same according to some example embodiments will be discussed with reference to the accompanying drawings.

Fig. 1 illustrates a simplified plan view showing an image sensor according to some example embodiments.

Referring to fig. 1, the image sensor may include a pixel array region R1 and a pad (pad, which may also be referred to as a "pad") region R2.

A plurality of unit pixels P may be two-dimensionally arranged in the row direction and the column direction on the pixel array region R1. Each unit pixel P of the pixel array region R1 may output an electrical signal converted from incident light. The pixel array region R1 may include a center region (see CR of fig. 11) and an edge region (see ER of fig. 11) surrounding the center region CR. For example, the edge regions ER may be disposed on the top side, bottom side, left side, and right side of the central region CR when viewed in a plane. The pad region R2 may include a plurality of conductive pads CP for inputting and outputting control signals and photoelectric conversion signals. To easily connect with an external device, the pad region R2 may surround the pixel array region R1 when viewed in a plane.

Fig. 2A and 2B illustrate circuit diagrams showing an active pixel sensor array of an image sensor according to some example embodiments.

Referring to fig. 2A, the active pixel sensor array may include a plurality of unit pixels P, each of which may include first and second photoelectric conversion elements PD1 and PD2, first and second transfer transistors TX1 and TX2, and logic transistors RX, SX, and AX. The logic transistors RX, SX, and AX may include a reset transistor RX, a selection transistor SX, and an amplifier transistor AX. A gate electrode of the first transfer transistor TX1, a gate electrode of the second transfer transistor TX2, a gate electrode of the reset transistor RX, and a gate electrode of the selection transistor SX may be connected to the driving signal lines TG1, TG2, RG, and SG, respectively, correspondingly.

The first transfer transistor TX1 may include a first transfer gate electrode connected to the driving signal line TG 1. The first transfer transistor TX1 may be connected to the first photoelectric conversion element PD 1. The second transfer transistor TX2 may include a second transfer gate electrode connected to the driving signal line TG 2. The second transfer transistor TX2 may be connected to the second photoelectric conversion element PD 2. The first transfer transistor TX1 and the second transfer transistor TX2 may share the charge detection node FD (i.e., a floating diffusion region).

The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can generate and accumulate photocharges in proportion to the amount of externally incident light thereon. The first and second transfer gate electrodes may transfer the charges accumulated in the first and second photoelectric conversion elements PD1 and PD2 to the charge detection node FD (i.e., floating diffusion region). The first transfer gate electrode and the second transfer gate electrode may receive complementary signals. For example, charges may be transferred from one of the first and second photoelectric conversion elements PD1 and PD2 to the charge detection node FD. At a later time, charge may be transferred from the other of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the charge detection node FD.

The charge detection node FD may receive and accumulate charges generated from the first and second photoelectric conversion elements PD1 and PD 2. The amplifier transistor AX can be controlled by the amount of photo-charges accumulated in the charge detection node FD.

The reset transistor RX may periodically reset the charges accumulated in the charge detection node FD. For example, the reset transistor RX may have a drain electrode connected to the charge detection node FD and a source voltage V_DDThe source electrode of (1). When the reset transistor RX is turned on, the charge detection node FD may receive a power supply voltage V connected to a source electrode of the reset transistor RX_DD. Accordingly, when the reset transistor RX is turned on, the charges accumulated in the charge detection node FD may be depleted, and thus the charge detection node FD may be reset.

The amplifier transistor AX can amplify a change in potential at the charge detection node FD, and can output an amplified signal or a pixel signal to the output line V through the selection transistor SX_OUT. The amplifier transistor AX may be a source follower buffer amplifier configured to generate a source-drain current proportional to the amount of photocharge applied to the gate electrode. The amplifier transistor AX may have a gate electrode connected to the charge detection node FD, connected to the power supply voltage V_DDAnd a source electrode connected to the drain electrode of the select transistor SX.

The selection transistor SX may select the unit pixels P of each row to be read out. A power supply voltage V connected to the drain electrode of the amplifier transistor AX when the selection transistor SX is turned on_DDMay be transferred to the drain electrode of the select transistor SX.

Referring to fig. 2B, the active pixel sensor array may include a plurality of unit pixels P, and each of the unit pixels P may include four photoelectric conversion elements PD1, PD2, PD3, and PD4 and four transfer transistors TX1, TX2, TX3, and TX 4. The four transfer transistors TX1, TX2, TX3, and TX4 may share the charge detection node FD and the logic transistors RX, SX, and AX. In the example embodiment shown in fig. 2B, charges may be transferred from one of the four photoelectric conversion elements PD1, PD2, PD3, and PD4 to the charge detection node FD according to signals applied to the four transfer transistors TX1, TX2, TX3, and TX 4.

Fig. 3 illustrates a simplified plan view of an active pixel sensor array showing an image sensor according to some example embodiments.

Referring to fig. 3, the active pixel sensor array may include a plurality of pixel regions P1, P2, and P3 arranged in a matrix shape along a first direction D1 and a second direction D2. The plurality of pixel regions P1, P2, and P3 may include a first pixel region P1, a second pixel region P2, and a third pixel region P3, and each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 may receive light having a wavelength band different from that of light incident on the other of the first pixel region P1, the second pixel region P2, and the third pixel region P3.

In some example embodiments, the number of the first pixel regions P1 may be twice as large as the number of the second pixel regions P2 or the number of the third pixel regions P3. The first pixel region P1 may be disposed in a diagonal direction, and the second pixel region P2 and the third pixel region P3 may be disposed in a diagonal direction. As shown in fig. 3, each of the first pixel regions P1 may be disposed between the second pixel regions P2 in the first direction D1 (or in the second direction D2) and between the third pixel regions P3 in the second direction D2 (or in the first direction D1).

Each of the first, second, and third pixel regions P1, P2, and P3 may include a plurality of sub-pixel regions PG1/PG2, PB, or PR. For example, each of the first, second, and third pixel regions P1, P2, and P3 may include a plurality of sub-pixel regions PG1/PG2, PB, or PR arranged in a 2 × 2 quaternary matrix shape. In particular, in some example embodiments, each of the first pixel regions P1 may include a plurality of first sub-pixel regions PG1 or PG2, and each of the second pixel regions P2 may include a plurality of second sub-pixel regions PR. Each of the third pixel regions P3 may include a plurality of third sub-pixel regions PB.

The first sub-pixel region PG1/PG2 may receive light having a first wavelength band, and the second sub-pixel region PR may receive light having a second wavelength band, which is longer than the first wavelength band. The third subpixel region PB may receive light having a third wavelength band, which is shorter than the first wavelength band. For example, green light may be incident on the first sub-pixel region PG1/PG2, red light may be incident on the second sub-pixel region PR, and blue light may be incident on the third sub-pixel region PB.

In some example embodiments, each of the first, second, and third sub-pixel regions PG1/PG2, PR, and PB may include a photoelectric conversion element and a transfer transistor as discussed above with reference to fig. 2A or 2B. For example, each of the first, second, and third sub-pixel regions PG1/PG2, PR, and PB may include the unit pixel discussed with reference to fig. 2A or 2B.

Fig. 4A illustrates a plan view showing an image sensor according to some example embodiments. Fig. 4B illustrates a cross-sectional view taken along line I-I' of fig. 4A showing an image sensor according to some example embodiments. Fig. 5A to 5C show enlarged views showing the section a of fig. 4B.

Referring to fig. 4A and 4B, an image sensor according to some example embodiments may include a semiconductor substrate 100. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other. The photoelectric conversion region 110 may be disposed on the semiconductor substrate 100. The readout circuit layer may be disposed on the first surface 100a (or front surface) of the semiconductor substrate 100, and the light transmission layer may be disposed on the second surface 100b (or rear surface) of the semiconductor substrate 100.

The semiconductor substrate 100 may be a first conductive type (e.g., p-type) bulk silicon substrate on which an epitaxial layer having a first conductive type is formed. Alternatively, the semiconductor substrate 100 may be a p-type epitaxial layer remaining after a bulk silicon substrate is removed in a manufacturing process for an image sensor. Alternatively, the semiconductor substrate 100 may be a bulk semiconductor substrate including a first conductive type well.

As discussed above by referring to fig. 3, the semiconductor substrate 100 may include the first, second, and third pixel regions P1, P2, and P3 arranged in a quad matrix, and each of the first, second, and third pixel regions P1, P2, and P3 may receive light having a wavelength band different from that of light incident on the other of the first, second, and third pixel regions P1, P2, and P3.

As discussed above, the first, second, and third pixel regions P1, P2, and P3 may include a plurality of corresponding sub-pixel regions PG1/PG2, PR, and PB, respectively. Each of the first pixel regions P1 may include a plurality of first sub-pixel regions PG1 or PG2, and each of the second pixel regions P2 may include a plurality of second sub-pixel regions PR. Each of the third pixel regions P3 may include a plurality of third sub-pixel regions PB. The respective sub-pixel regions PG1/PG2, PR, and PB of the first, second, and third pixel regions P1, P2, and P3 may have the same size and may be defined by the pixel separating structure 103. For example, as shown in fig. 4A and 4B, at least two first sub-pixel regions PG1 may be disposed between adjacent second sub-pixel regions PR.

The pixel separating structure 103 may vertically extend from the first surface 100a to the second surface 100b of the semiconductor substrate 100. The pixel separating structure 103 may penetrate the semiconductor substrate 100. In this case, the pixel separation structure 103 may have a vertical thickness substantially the same as that of the semiconductor substrate 100. Alternatively, in some example embodiments, the pixel separation structure 103 may vertically extend from the first surface 100a of the semiconductor substrate 100 toward but not to the second surface 100 b.

In some example embodiments, as shown in fig. 4B, the pixel separation structure 103 may have a first width adjacent to the first surface 100a of the semiconductor substrate 100 and a second width adjacent to the second surface 100B of the semiconductor substrate 100 that is less than the first width. The pixel separating structure 103 may have a width gradually decreasing from the first surface 100a to the second surface 100b of the semiconductor substrate 100. Alternatively, in some example embodiments, the pixel separation structure 103 may have a uniform width and may penetrate the semiconductor substrate 100.

When viewed in plan, as shown in fig. 4A, the pixel separation structure 103 may surround each of the first, second, and third sub-pixel regions PG1/PG2, PR, and PB. For example, the pixel separation structure 103 may include first portions 103a extending parallel to each other in the first direction D1 and spaced apart from each other in the second direction D2, and further include second portions 103b extending parallel to each other in the second direction D2 while crossing the first portions 103a and spaced apart from each other in the first direction D1.

In some example embodiments, each of the first, second, and third sub-pixel regions PG1/PG2, PR, and PB may have a width corresponding to a space between adjacent first portions 103a and/or a space between adjacent second portions 103 b. The first portion 103a of the pixel separation structure 103 may have a pitch, for example, in the range of about 50 μm to about 100 μm. For example, the first portion 103a of the pixel separation structure 103 may have a pitch of about 70 μm.

The pixel separation structure 103 may be formed of a dielectric material having a refractive index smaller than that of the semiconductor substrate 100, and may include a single dielectric layer or a plurality of dielectric layers. For example, the semiconductor substrate 100 may be silicon. For example, the pixel separation structure 103 may be formed of a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof. The pixel separating structure 103 may prevent crosstalk between adjacent sub-pixel regions among the first, second, and third sub-pixel regions PG1/PG2, PR, and PB.

The photoelectric conversion regions 110 may be disposed on the first, second, and third sub-pixel regions PG1/PG2, PR, and PB, respectively. The photoelectric conversion region 110 may be formed by implanting the semiconductor substrate 100 with impurities having a second conductivity type opposite to that of the semiconductor substrate 100. The photodiode may be formed at a junction between the semiconductor substrate 100 having the first conductive type and the photoelectric conversion region 110 having the second conductive type. The photoelectric conversion region 110 may generate a photo-charge proportional to the amplitude of incident light.

In some example embodiments, each photoelectric conversion region 110 may have a difference in impurity concentration between a portion adjacent to the first surface 100a and a portion adjacent to the second surface 100b, so that a potential slope may be provided between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, each photoelectric conversion region 110 may include a plurality of vertically stacked impurity portions.

The device isolation layer 101 may be disposed adjacent to the first surface 100a of the semiconductor substrate 100 on each of the first, second, and third sub-pixel regions PG1/PG2, PR, and PB. The device isolation layer 101 may define an active region of the semiconductor substrate 100.

The readout circuitry may be disposed on the first surface 100a of the semiconductor substrate 100. The readout circuit may include the MOS transistors discussed with reference to fig. 2A and 2B. On each of the sub-pixel regions PG1/PG2, PR, and PB, the transfer gate electrode TG may be disposed on the first surface 100a of the semiconductor substrate 100, and the readout circuit discussed with reference to fig. 2A and 2B may also be disposed on the first surface 100a of the semiconductor substrate 100.

The transfer gate electrode TG may be disposed on a central portion of each of the sub-pixel regions PG1/PG2, PR, and PB when viewed in a plane. A portion of the transfer gate electrode TG may be disposed within the semiconductor substrate 100, and a gate dielectric layer may be interposed between the transfer gate electrode TG and the semiconductor substrate 100. The floating diffusion area FD may be disposed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting the semiconductor substrate 100 with an impurity of a conductivity type opposite to that of the semiconductor substrate 100. For example, the floating diffusion region FD may be an n-type impurity region.

The interlayer

dielectric layers

211, 213, and 215 may be stacked on the first surface 100a of the semiconductor substrate 100, and the interlayer

dielectric layers

211, 213, and 215 may cover the transfer gate electrode TG and the MOS transistor constituting the readout circuit. The interlayer

dielectric layers

211, 213, and 215 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. A connection line CL may be disposed on each of the interlayer

dielectric layers

211, 213, and 215, and the connection line CL may be electrically connected to the readout circuit through a contact plug CT.

The fixed charge layer 300 may be disposed on the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 may prevent the photoelectric conversion region 110 from receiving charges (e.g., electrons or holes) generated from defects existing on the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 may include a single layer or a plurality of layers. For example, the fixed charge layer 300 may include a metal oxide or a metal fluoride including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanoid (Ln). For example, the fixed charge layer 300 may include one or more of an aluminum oxide layer and a hafnium oxide layer. The fixed charge layer 300 may have a thickness in the range of about 1nm to about 50 nm.

A planar dielectric layer 310 may be disposed on the fixed charge layer 300. The planar dielectric layer 310 may include a first planar layer 311, a second planar layer 313, and a third planar layer 315 (see fig. 5A) which are sequentially stacked. The first, second, and third planarization layers 311, 313, and 315 may include a transparent dielectric material. The first, second, and third planarization layers 311, 313, and 315 may have refractive indices different from each other. The first, second, and third planarization layers 311, 313, and 315 may be combined with each other to have an appropriate thickness, which results in a high refractive index. For example, the first planarization layer 311 may be thicker than the fixed charge layer 300. The second planarization layer 313 may be thicker than the first planarization layer 311. The third flat layer 315 may be thinner than the second flat layer 313.

The first and third

flat layers

311 and 315 may have the same refractive index, and the second flat layer 313 may have a refractive index different from the refractive index of the first and third

flat layers

311 and 315. For example, the first and third planarization layers 311 and 315 may include metal oxide, and the second planarization layer 313 may include silicon oxide.

The mesh structure 320 may be disposed on the planar dielectric layer 310. Similar to the pixel separation structure 103, the mesh structure 320 may have a mesh shape when viewed in a plane. The grid structure 320 may overlap the pixel separation structure 103 when viewed in a plane. For example, the mesh structure 320 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2 while crossing the first portion. The mesh structure 320 may be disposed between the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR, and PB. As shown in fig. 4B, the mesh structure 320 may have a width substantially the same as the minimum width of the pixel separation structure 103, or may have a width smaller than the minimum width of the pixel separation structure 103.

The mesh structure 320 may refract light obliquely incident through the microlenses 353, and then may cause the refracted light to enter the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR, and PB. The mesh structure 320 may have an aspect ratio in the range of about 2:1 to about 5: 1. The lattice structure 320 may have a lattice structure of about

To about

A height within the range of (1). The mesh structure 320 may have a width in the range of about 50nm to about 150 nm.

The mesh structure 320 may include a light blocking pattern 322 and a low refractive index pattern 324 sequentially stacked on the flat dielectric layer 310. The light blocking pattern 322 may be disposed between the low refractive index pattern 324 and the flat dielectric layer 310. The light blocking pattern 322 may include a metal material, such as titanium, tantalum, or tungsten.

Low refractive index pattern 324 may include a material having a refractive index smaller than that of

color filters

345a and 345 b. Low refractive index pattern 324 may include an organic material, and may have a refractive index in a range of about 1.1 to about 1.3. For example, the lattice structure 320 may be a polymer layer including silica nanoparticles. Since the low refractive index patterns 324 have a low refractive index, it may be possible to increase the amount of light incident on the photoelectric conversion region 110 and reduce crosstalk between the sub-pixel regions PG1/PG2, PR, and PB. In this configuration, each photoelectric conversion region 110 can improve light reception efficiency and improve a signal-to-noise ratio (SNR).

The protective layer 330 may be disposed on the planar dielectric layer 310 to cover the planar dielectric layer 310 and the surface of the mesh structure 320 on the planar dielectric layer 310 with a substantially uniform thickness. For example, the overcoat layer 330 may extend from a space between sidewalls of any one of the

color filters

345a and 345b and sidewalls of the mesh structure 320 toward a space between the planar dielectric layer 310 and a bottom surface of any one of the

color filters

345a and 345 b.

The protective layer 330 may be a layer including, for example, oxygenA single layer or multiple layers of one or more of aluminum oxide and silicon oxycarbide. In some example embodiments, the protective layer 330 may have a thickness of about

To about

A thickness within the range of (1). The overcoat layer 330 may protect the

color filters

345a and 345b and may serve to absorb moisture. In some example embodiments, the protective layer 330 may be formed to have a thickness of about

To about

And thus does not have an influence on the paths of light incident on the sub-pixel regions PG1/PG2, PR, and PB.

In some example embodiments, the mesh structure 320 may have openings O, each of which is defined by a pair of first portions of the mesh structure 320 extending in the first direction D1 and a pair of second portions of the mesh structure 320 extending in the second direction D2, and the openings O may overlap the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR, and PB.

Color filters

345a and 345b may be disposed in the openings defined by the mesh structure 320. For example, the first color filter 345a may be disposed on the corresponding first sub-pixel region PG1/PG2 of the first pixel region P1, and the second color filter 345b may be disposed on the corresponding second sub-pixel region PR of the second pixel region P2. Likewise, a third color filter (not shown in fig. 4B) may be disposed on the corresponding third sub-pixel region PB of the third pixel region (see P3 of fig. 3). The first, second, and

third color filters

345a, 345b, and 345b may include green, red, and blue color filters, respectively. Alternatively, the first, second, and

third color filters

345a, 345b, and 345b may include magenta, yellow, and cyan color filters, respectively. Although three types of color filters are provided as mentioned above, in some example embodiments, four types of color filters may be provided.

In some example embodiments, as shown in fig. 4B, at least two first color filters 345a may be disposed between adjacent second color filters 345B. The mesh structure 320 may include a first barrier portion FS1 disposed between sub-pixel regions PG1/PG2, PR, and PB of the pixel regions P1, P2, and P3, and may further include a second barrier portion FS2 disposed between different pixel regions P1, P2, and P3. For example, the first barrier section FS1 of the lattice structure 320 may be disposed between the

color filters

345a or 345b whose colors are the same as each other, and the second barrier section FS2 of the lattice structure 320 may be disposed between the

color filters

345a and 345b whose colors are different from each other.

Each of the

color filters

345a and 345b may have a first sidewall S1 adjacent to the first barrier portion FS1 of the mesh structure 320 and a second sidewall S2 adjacent to the second barrier portion FS2 of the mesh structure 320. The first sidewall S1 may have a height H1 that is substantially the same as the height H2 of the second sidewall S2. For example, the difference between the first height H1 of the first sidewall S1 and the second height H2 of the second sidewall S2 may be about

To about

Within the range of (1). Each of the

color filters

345a and 345b may have a substantially flat top surface, and the top surfaces of the

color filters

345a and 345b may be parallel to the bottom surfaces of the

color filters

345a and 345 b.

Referring to fig. 4B and 5A, the overcoat layer 330 may cover the top surface of the mesh structure 320, and the top surfaces of the color filters 345A and 345B may be substantially coplanar with the top surface of the overcoat layer 330 on the top surface of the mesh structure 320. For example, the top surface of the mesh structure 320 may be positioned at substantially the same level as the top surface of the protective layer 330. Referring to fig. 5B, the top surfaces of the color filters 345a and 345B may be positioned at a level lower than the level of the top surface of the mesh structure 320. Referring to fig. 5C, the protection pattern 331 may directly cover the sidewalls of the mesh structure 320 and the bottom surfaces of the

color filters

345a and 345 b. That is, unlike the protection pattern 330, in some example embodiments, the protection pattern 331 may not be disposed along the top surface of the mesh structure 320. The top surface of the protection pattern 331 may be positioned at substantially the same level as the top surface of the mesh structure 320, and the top surfaces of the

color filters

345a and 345b may be positioned at a level lower than the level of the top surface of the mesh structure 320.

Referring back to fig. 4A and 4B, the microlens array 350 may be disposed on a color filter array including a first color filter 345a, a second color filter 345B, and a third color filter. The microlens array 350 may include a flat portion 351 adjacent to the

color filters

345a and 345b, and may further include microlenses 353 corresponding to the sub-pixel regions PG1/PG2, PR, and PB on the flat portion 351.

Since the first, second, and

third color filters

345a, 345b, and 345 have substantially flat top surfaces, the flat portion 351 may have a substantially uniform thickness on the top surfaces of the first, second, and

third color filters

345a, 345b, and 351. For example, the flat portion 351 may have substantially the same thickness on the first and second sidewalls S1 and S2 of each of the

color filters

345a and 345 b. The microlenses 353 may be disposed on the sub-pixel regions PG1/PG2, PR, and PB, respectively, and may each have an upwardly convex shape. In some example embodiments, since the flat portion 351 has a reduced thickness distribution with respect to the microlens array 350, light collection efficiency may be able to be improved by the microlenses 353.

The passivation layer 360 may conformally cover the top surface of the microlens array 350. The passivation layer 360 may be formed of, for example, an inorganic oxide.

In the following description, the same features as those of the image sensor discussed above may be omitted in some cases for the simplicity of description.

Fig. 6 illustrates a cross-sectional view taken along line I-I' of fig. 4A showing an image sensor according to some example embodiments. Fig. 7A and 7B show enlarged views showing a section B of fig. 6.

Referring to fig. 6, 7A, and 7B, each of color filters 345a and 345B may have a substantially flat top surface, as discussed above. Further, as shown in fig. 6, the top surfaces of the

color filters

345a and 345b may be positioned at a higher level than the level of the top surface of the mesh structure 320. The mesh structure 320 may have a height smaller than the thickness of the

color filters

345a and 345 b. The thickness of each of the

color filters

345a and 345b located on the planar dielectric layer 310 may be different from the thickness of each of the

color filters

345a and 345b located on the mesh structure 320.

The first color filter 345a may be disposed on the first pixel region P1 and on the plurality of first sub-pixel regions PG 1. The first color filter 345a may be connected or continuous on the first barrier portions FS1 of the mesh structure 320, the first barrier portions FS1 being disposed between the first sub-pixel regions PG 1. For example, on each of the first sub-pixel regions PG1, the first color filter 345a may cover a top surface of the first barrier portion FS1 of the mesh structure 320 (see, e.g., the middle mesh structure 320 in fig. 6). Even if each of the

color filters

345a and 345b covers the first barrier portion FS1 of the mesh structure 320, a height difference between the first sidewall S1 adjacent to the first barrier portion FS1 of the mesh structure 320 and the second sidewall S2 adjacent to the second barrier portion FS2 of the mesh structure 320 may be about

To about

The range of (1).

Referring to fig. 7A, the mesh structure 320 may include a light shielding pattern 322 and a low refractive index pattern 324 that are sequentially stacked. Low refractive index pattern 324 may have a refractive index of about

To about

Within (e.g., at about)

To about

Within) of the container.

Color filters

345a and 345b may have a range of about

To about

A thickness within the range of (1). Referring to fig. 7B, in some exemplary embodiments, the mesh structure 320 may include a metal material and have a thickness of about

To about

A height within the range of (1).

Fig. 8 illustrates a cross-sectional view taken along line I-I' of fig. 4A showing an image sensor according to some example embodiments. Fig. 9A and 9B show enlarged views showing a section C of fig. 8.

Referring to fig. 8, each of the

color filters

345a and 345b may have different thicknesses at portions adjacent to the first and second barrier portions FS1 and FS2 of the mesh structure 320, respectively. In other words, as shown in fig. 8, the thickness t1 of each of the

color filters

345a and 345b adjacent to the first barrier portion FS1 may be greater than the thickness t2 of each of the

color filters

345a and 345b adjacent to the second barrier portion FS 2. The sacrificial planarizing layer 355 may partially remain between the adjacent first and

second color filters

345a and 345 b. The sacrificial planarizing layer 355 may have a top surface substantially coplanar with the uppermost surfaces of the first and

second color filters

345a and 345 b.

Referring to fig. 9A, in some example embodiments, each of the

color filters

345a and 345b may have a minimum thickness and a maximum thickness each greater than the height of the mesh structure 320. Each of the color filters 345a and 345bMay have a maximum thickness at a portion adjacent to the first fence portion FS1 of the mesh structure 320a and a minimum thickness at a portion adjacent to the second fence portion FS2 of the mesh structure 320 b. The difference between the maximum thickness and the minimum thickness of each of the

color filters

345a and 345b may be about

To about

Within the range of (1).

Referring to fig. 9B, in some example embodiments, each of the color filters 345a and 345B may have an uppermost surface at substantially the same level as the level of the top surface of the overcoat layer 330 covering the top surfaces of the mesh structures 320a and 320B. In this configuration, the minimum thickness of each of the

color filters

345a and 345b may be less than the height of the

mesh structures

320a and 320 b.

Fig. 10A illustrates a cross-sectional view taken along line I-I' of fig. 4A showing an image sensor according to some example embodiments. Fig. 10B shows an enlarged view showing a section D of fig. 10A.

Referring to fig. 10A and 10B, a planar dielectric layer 310 may be disposed on the second surface 100B of the semiconductor substrate 100, and the mesh structure 320 may have a lower portion located within the planar dielectric layer 310. For example, a lower portion of the mesh structure 320 may penetrate the planar dielectric layer 310.

The fixed charge layer 300 may be disposed between the flat dielectric layer 310 and the second surface 100b of the semiconductor substrate 100, and the mesh structure 320 may have a bottom surface in contact with the fixed charge layer 300. Optionally, in some example embodiments, a bottom surface of the mesh structure 320 may be in contact with the pixel separation structure 103. The planar dielectric layer 310 may include a first planar layer 311 and a second planar layer 313, which are sequentially stacked. The first and second planarization layers 311 and 313 may have different refractive indices and different thicknesses.

The mesh structure 320 may include a material having a refractive index smaller than that of the semiconductor substrate 100. The semiconductor substrate 100 may be, for example, silicon. For example, the mesh structure 320 may be formed of a low refractive index material having a refractive index of about 1.3 or less. For example, the lattice structure 320 may be a polymer layer including silica nanoparticles.

Fig. 11 illustrates a cross-sectional view showing an image sensor according to some example embodiments.

Referring to fig. 11, as discussed above with reference to fig. 1, the semiconductor substrate 100 may include a pixel array region R1 and a pad region R2 around the pixel array region R1, and the pixel array region R1 may include a center region CR and an edge region ER surrounding the center region CR and adjacent to the pad region R2.

The

color filters

345a and 345b may have substantially flat top surfaces on the center region CR and the edge region ER. As shown in fig. 11, the

color filters

345a and 345b may have a relatively small thickness on the edge region ER and a relatively large thickness on the central region CR. For example, on the central region CR, the top surfaces of the

color filters

345a and 345b may be positioned at substantially the same level as the top surface of the overcoat layer 330, and on the edge region ER, the top surfaces of the

color filters

345a and 345b may be positioned at a lower level than the level of the top surface of the mesh structure 320.

On the pad region R2, a through plug TPLG may be provided to penetrate the semiconductor substrate 100, and a sidewall dielectric layer SS may surround the sidewall of the through plug TPLG. On the pad region R2, the connection line CL may be disposed on the first surface 100a of the semiconductor substrate 100, and the conductive pad CP may be disposed on the second surface 100b of the semiconductor substrate 100. The connection line CL of the pad region R2 may be connected to the connection line CL of the pixel array region R1. The through plug TPLG may electrically connect the connection line CL to the conductive pad CP.

Fig. 12A illustrates a plan view showing an image sensor according to some example embodiments. Fig. 12B illustrates a cross-sectional view taken along line II-II' of fig. 12A showing an image sensor according to some example embodiments.

Referring to fig. 12A and 12B, each of the first, second, and third pixel regions P1, P2, and P3 discussed above with reference to fig. 3 may include corresponding sub-pixel regions among the sub-pixel regions PG1/PG2, PR, and PB, which are arranged in a 3 × 3 matrix shape. For example, at least three first sub-pixel regions PG1/PG2 may be disposed between adjacent second sub-pixel regions PR.

The mesh structure 320 may include a first barrier portion FS1 disposed between the sub-pixel regions PG1/PG2, PR, and PB, and may further include a second barrier portion FS2 disposed between the pixel regions P1, P2, and P3. In this configuration, at least two first fence portions FS1 may be disposed between the second fence portions FS2 spaced apart from each other.

As discussed above, the

color filters

345a and 345b may fill the openings defined by the grid structure 320, and each of the

color filters

345a and 345b may have a substantially planar surface.

Fig. 13 illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments.

Referring to fig. 13, each unit pixel P may include a photoelectric conversion element PD1, an organic photoelectric conversion element OPD, first and second transfer transistors TX1 and TX2, and readout transistors RX, SX, and AX. As discussed with reference to fig. 2A, the readout transistors may include a reset transistor RX, an amplifier transistor AX, and a selection transistor SX.

The first transfer transistor TX1 may be connected to the photoelectric conversion element PD1, and the second transfer transistor TX2 may be connected to the organic photoelectric conversion element OPD. The first transfer transistor TX1 and the second transfer transistor TX2 may share the charge detection node FD (i.e., a floating diffusion region).

The photoelectric conversion element PD1 and the organic photoelectric conversion element OPD can generate and accumulate photocharges proportional to the amount of externally incident light. In certain example embodiments, the photoelectric conversion element PD1 may be one of a photodiode, a phototransistor, a grating, a Pinned Photodiode (PPD), and combinations thereof. The organic photoelectric conversion element OPD may include an organic photoelectric conversion layer. The organic photoelectric conversion layer may generate a photo charge (electron-hole pair) proportional to incident light having a specific wavelength band. The difference in the voltages applied to the opposite ends of the organic photoelectric conversion element OPD may cause the charge detection node FD to store the photo-charges generated from the organic photoelectric conversion layer.

The first transfer transistor TX1 and the second transfer transistor TX2 may transfer the charges accumulated in the photoelectric conversion element PD1 and the organic photoelectric conversion element OPD to the charge detection node FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by a charge transfer signal supplied through the first charge transfer line TG1 and the second charge transfer line TG2, and charges may be transferred from any one of the photoelectric conversion element PD1 and the organic photoelectric conversion element OPD to the charge detection node FD according to the charge transfer signal applied to the first transfer transistor TX1 and the second transfer transistor TX 2. In particular, when the voltage V is_PIXWhen a charge transfer signal is applied to one of the terminals of the organic photoelectric conversion element OPD and a charge transfer signal is applied to the second transfer transistor TX2, the generated electrons or holes may be transferred to the charge detection node FD and accumulated in the charge detection node FD.

Fig. 14 illustrates a block diagram showing an image sensor according to some example embodiments.

Referring to fig. 14, the image sensor may include a plurality of unit pixels P two-dimensionally arranged in a first direction D1 and a second direction D2 crossing the first direction D1. Each unit pixel P of the image sensor may have a structure in which at least two photoelectric conversion elements are stacked in a third direction D3 perpendicular to the first and second directions D1 and D2. Each unit pixel P may include one of the first and second photoelectric conversion elements PD1 and PD2, one of the first and second color filters CF1 and CF2, and the organic photoelectric conversion element OPD. For example, the unit pixel P may include the first photoelectric conversion element PD1, the first color filter CF1, and the organic photoelectric conversion element OPD, and the other unit pixel P may include the second photoelectric conversion element PD2, the second color filter CF2, and the organic photoelectric conversion element OPD, and so on.

The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be provided in a semiconductor substrate and may be arranged in a matrix shape. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be arranged in a zigzag manner.

As shown in fig. 14, the organic photoelectric conversion element OPD may be stacked on the first and second photoelectric conversion elements PD1 and PD2, respectively. For example, the organic photoelectric conversion element OPD may be stacked with a corresponding one of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 when viewed in a plane. The first color filter CF1 may be disposed between the first photoelectric conversion element PD1 and the organic photoelectric conversion element OPD, and the second color filter CF2 may be disposed between the second photoelectric conversion element PD2 and the organic photoelectric conversion element OPD, respectively.

In some example embodiments, the organic photoelectric conversion element OPD of the unit pixel P may receive corresponding incident light of the first, second, and third incident lights L1, L2, and L3 having the first, second, and third wavelength bands, respectively. The first and second photoelectric conversion elements PD1 and PD2 and the organic photoelectric conversion element OPD may each receive incident light having a wavelength band different from that of any other incident light, and may each generate photoelectric charges proportional to the amount of incident light.

For example, the first photoelectric conversion element PD1 may generate first photo-charges corresponding to first incident light L1 having a first wavelength band. The second photoelectric conversion element PD2 may generate second photo-charges corresponding to second incident light L2 having a second wavelength band. The organic photoelectric conversion element OPD may generate third photo-charges corresponding to third incident light L3 having a third wavelength band. The first band may be longer than the third band, and the second band may be shorter than the third band. For example, the first incident light L1 having the first wavelength band may appear red, the second incident light L2 having the second wavelength band may appear blue, and the third incident light L3 having the third wavelength band may appear green.

The first incident light L1 having the first wavelength band may pass through the organic photoelectric conversion element OPD and the first color filter CF1 and then may enter the first photoelectric conversion element PD1, and the second incident light L2 having the second wavelength band may pass through the organic photoelectric conversion element OPD and the second color filter CF2 and then may enter the second photoelectric conversion element PD 2. The third incident light L3 having the third wavelength band may enter the organic photoelectric conversion element OPD.

At the unit pixel P including the first photoelectric conversion element PD1, a first pixel signal S1 corresponding to the first incident light L1 having the first wavelength band may be output, and at the unit pixel P including the second photoelectric conversion element PD2, a second pixel signal S2 corresponding to the second incident light L2 having the second wavelength band may be output. Further, the organic photoelectric conversion element OPD of the unit pixel P may output a third pixel signal S3 corresponding to third incident light L3 having a third wavelength band. For example, the first photoelectric conversion element PD1 may generate a photo-charge corresponding to red light. The second photoelectric conversion element PD2 may generate a photo-charge corresponding to blue light. The organic photoelectric conversion element OPD can generate a photo-charge corresponding to green light.

Fig. 15 illustrates a cross-sectional view showing an image sensor according to some example embodiments.

Referring to fig. 15, as discussed above, the semiconductor substrate 100 may include the photoelectric conversion region 110 therein and a pixel separating structure defining the pixel regions P1 and P2 (see 103 of fig. 4A and 4B).

On each of the pixel regions P1 and P2, a transfer gate electrode TG may be disposed on the first surface 100a of the semiconductor substrate 100, and a first floating diffusion region FD1 may be disposed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The second floating diffusion region FD2 may be disposed in the semiconductor substrate 100 and spaced apart from the first floating diffusion region FD 1.

The first floating diffusion region FD1 and the second floating diffusion region FD2 may be formed by implanting the semiconductor substrate 100 with an impurity having a conductivity type opposite to that of the semiconductor substrate 100. For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 may be n-type impurity regions.

The pixel regions P1 and P2 may have a through electrode structure 130 therebetween that penetrates a portion of the pixel separation structure 103.

The through electrode structure 130 may include: a through electrode 134 vertically penetrating the semiconductor substrate 100; and a through dielectric pattern 132 surrounding sidewalls of the through electrode 134. The through electrode 134 may include a conductive material. The through electrode 134 may include polysilicon or metal doped with n-type or p-type impurities. The through electrode 134 may have a width gradually decreasing from the first surface 100a to the second surface 100b of the semiconductor substrate 100. The through dielectric pattern 132 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The interlayer

dielectric layers

211, 213, and 215 may be disposed on the first surface 100a of the semiconductor substrate 100, and may cover the transfer gate electrode TG and the MOS transistors constituting the first readout circuit and the second readout circuit. A plurality of bottom contact plugs BCP1 through BCP3 may be disposed in the interlayer

dielectric layers

211, 213, and 215. For example, the first bottom contact plug BCP1 may be bonded to the first floating diffusion region FD1, and the second bottom contact plug BCP2 may be bonded to the second floating diffusion region FD 2. Third bottom contact plug BCP3 may be coupled to through electrode 134.

The first bottom contact plug BCP1 may be electrically connected to the reset transistor (see RX of fig. 13) and the amplifier transistor (see AX of fig. 13) through a first connection line CL 1. The second bottom contact plug BCP2 may be connected to the third bottom contact plug BCP3 through a second connection line CL 2. For example, the through electrode 134 may be electrically connected to the second floating diffusion region FD2 through the second bottom contact plug BCP2, the third bottom contact plug BCP3, and the second connection line CL 2.

The flat dielectric layer 310 may be disposed on the second surface 100b of the semiconductor substrate 100. As discussed above, the planar dielectric layer 310 may comprise a single layer or multiple layers. The planar dielectric layer 310 may include a metal oxide such as aluminum oxide and/or hafnium oxide.

Color filters

345a and 345b may be disposed on the planar dielectric layer 310 at the corresponding pixel regions P1 and P2. The

color filters

345a and 345b may include a first color filter 345a on the first pixel region P1 and a second color filter 345b on the second pixel region P2.

Color filters

345a and 345b may be disposed in the openings defined by the mesh structure 320 disposed on the planar dielectric layer 310. The first color filter 345a may be disposed on the first pixel region P1, and the second color filter 345b may be disposed on the second pixel region P2. As discussed above, in some example embodiments, each of the

color filters

345a and 345b may have a substantially flat top surface parallel to its bottom surface. The top surfaces of the

color filters

345a and 345b may be positioned at a level lower than the level of the top surface of the mesh structure 320 or may be positioned at substantially the same level as the level of the top surface of the mesh structure 320.

The first upper planarization layer BPL may cover the top surfaces of the

color filters

345a and 345 b. The first upper planarization layer BPL is formed on the planarized top surface of the

color filters

345a and 345b, and may have a substantially planarized top surface.

The top contact plug TCP may penetrate the first upper planarization layer BPL, a portion of the mesh structure 320, and the planarization dielectric layer 310, thereby being bonded to the corresponding through electrode 134. Each of the top contact plugs TCP may include a barrier metal layer formed of a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, and may further include a metal layer formed of a metal such as tungsten or copper.

The organic photoelectric conversion element OPD may be disposed on the first upper planarization layer BPL disposed on the second surface 100b of the semiconductor substrate 100. The organic photoelectric conversion element OPD may include a bottom electrode BE, a top electrode TE, and an organic photoelectric conversion layer OPL between the bottom electrode BE and the top electrode TE.

The bottom electrode BE may BE disposed on the first upper planarization layer BPL having a planarized top surface. The bottom electrode BE may BE disposed to correspond to the pixel regions P1 and P2 when viewed in a plane, and may BE spaced apart from each other. Each bottom electrode BE may BE electrically connected to the second floating diffusion region FD2 through the corresponding top contact plug TCP, the through electrode 134, the second and third bottom contact plugs BCP2 and BCP3, and the second connection line CL 2.

The bottom electrode BE may include a transparent conductive material. For example, the bottom electrode BE may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), SnO₂ATO (antimony doped tin oxide), AZO (aluminum doped zinc oxide), GZO (gallium doped zinc oxide), TiO₂And FTO (fluorine-doped tin oxide)Or more.

The organic photoelectric conversion layer OPL may BE disposed on the bottom electrode BE. The organic photoelectric conversion layer OPL can selectively absorb light having a specific wavelength band, and thus can cause photoelectric conversion. The organic photoelectric conversion layer OPL may include a p-type organic semiconductor material and an n-type organic semiconductor material, which form a p-n junction. In other embodiments, the organic photoelectric conversion layer OPL may include quantum dots or chalcogenides.

The top electrode TE may be disposed on the organic photoelectric conversion layer OPL. The top electrode TE may include a transparent conductive material, and may completely cover the pixel regions P1 and P2.

The encapsulation layer TFE may be disposed on the top electrode TE. The encapsulation layer TFE may be formed from a single layer or multiple layers. The encapsulation layer TFE may include, for example, an aluminum layer and a silicon oxynitride layer. A second upper planarization layer TPL may be disposed on the encapsulation layer TFE, and the microlens array 350 may be disposed on the second upper planarization layer TPL. The second upper planarization layer TPL may include a transparent dielectric material, for example, a metal oxide or a silicon oxide. The microlens array 350 may include microlenses corresponding to the pixel regions P1 and P2.

Fig. 16A to 16H illustrate cross-sectional views taken along line I-I' of fig. 4A showing a method of manufacturing an image sensor according to some example embodiments.

Referring to fig. 4A and 16A, a semiconductor substrate 100 having a first conductivity type (e.g., p-type) may be provided. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other.

In some example embodiments, the semiconductor substrate 100 may include first, second, and third pixel regions (see P1, P2, and P3 of fig. 3), and each of the pixel regions P1, P2, and P3 may include a plurality of sub-pixel regions (see PG1/PG2, PR, and PB of fig. 3).

The photoelectric conversion region 110 may be formed in the semiconductor substrate 100. On each of the sub-pixel regions PG1/PG2, PR, and PB, the photoelectric conversion region 110 may be formed by implanting the semiconductor substrate 100 with impurities having a second conductivity type (e.g., n-type) different from the first conductivity type.

The device isolation layer 101 may be formed to be adjacent to the first surface 100a on each of the sub-pixel regions PG1/PG2, PR, and PB and to define an active region on the semiconductor substrate 100. The device isolation layer 101 may be formed by: shallow trenches are formed by patterning the first surface 100a of the semiconductor substrate 100, and then a dielectric material is deposited in the shallow trenches. The formation of the device isolation layer 101 may be performed before or after the formation of the photoelectric conversion region 110.

The pixel separation structure 103 may be formed on the semiconductor substrate 100, thereby defining sub-pixel regions PG1/PG2, PR, and PB. The pixel separation structure 103 may be formed by: the deep trench is formed by patterning the first surface 100a and/or the second surface 100b of the semiconductor substrate 100, and then filled with a dielectric material.

Referring to fig. 4A and 16B, a Metal Oxide Semiconductor (MOS) transistor may be formed on the first surface 100a of the semiconductor substrate 100 to constitute a readout circuit. For example, transfer gate electrodes TG may be formed on the first surface 100a of the semiconductor substrate 100, and a gate dielectric layer may be disposed between the semiconductor substrate 100 and each transfer gate electrode TG. A gate electrode (not shown) of the MOS transistor may also be formed together with the transfer gate electrode TG.

After forming the transfer gate electrode TG, a floating diffusion region FD may be formed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting an impurity having the second conductive type. In addition, source/drain impurity regions (not shown) of the MOS transistor may also be formed together with the floating diffusion region FD.

Referring to fig. 4A and 16C, interlayer

dielectric layers

211, 213, and 215, contact plugs CT, and connection lines CL may be formed on the first surface 100a of the semiconductor substrate 100. Interlayer dielectric layers 211, 213, and 215 may cover the first and second transfer transistors and the logic transistor. The interlayer

dielectric layers

211, 213, and 215 may be formed of a material having excellent gap filling characteristics, and may have their planarized upper portions.

Contact plugs CT may be formed in the interlayer

dielectric layers

211, 213, and 215 so as to be connected to the floating diffusion region FD or the MOS transistor. The connection line CL may be formed between the interlayer

dielectric layers

211, 213, and 215. The contact plug CT and the connection line CL may be formed of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or an alloy thereof.

Referring to fig. 4A and 16D, a thinning process may be performed to remove a portion of the semiconductor substrate 100, and thus the semiconductor substrate 100 may have a reduced vertical thickness. The semiconductor substrate 100 may be turned upside down to perform the thinning process thereon. A grinding process or a polishing process may be performed to remove a portion of the semiconductor substrate 100, and then an anisotropic etching process or an isotropic etching process may be performed to remove residual surface defects from the semiconductor substrate 100. The thinning process for the semiconductor substrate 100 may expose the pixel separation structure 103 from the second surface 100b of the semiconductor substrate 100. For example, the pixel separating structure 103 may have a surface at substantially the same level as that of the surface of the second surface 100b of the semiconductor substrate 100.

Thereafter, the fixed charge layer 300 may be formed on the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 may directly cover the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 may be formed of a metal oxide such as aluminum oxide and/or hafnium oxide.

A planar dielectric layer 310 may be formed on the fixed charge layer 300. The formation of the planar dielectric layer 310 may include sequentially depositing a first planar layer 311, a second planar layer 313, and a third planar layer 315. The first, second, and third planarization layers 311, 313, and 315 may be formed of a transparent dielectric material, and may have different thicknesses from each other. The first, second, and third planarization layers 311, 313, and 315 may include, for example, metal oxide or silicon oxide.

A light-shielding layer 321 and a low refractive index layer 323 may be sequentially formed on the flat dielectric layer 310. The light-shielding layer 321 may be formed of a metal material such as titanium, tungsten, or aluminum. As discussed above, the low refractive index layer 323 may be formed of a material having a refractive index in the range of about 1.1 to about 1.3. The low refractive index layer 323 may include an organic material and an oxide. The refractive index of the low refractive index layer 323 may depend on the concentration of the oxide contained in the low refractive index layer 323. The forming of the low refractive index layer 323 may include: spin-coating a composition including an organic material and a solvent on the light-shielding layer 321; and performing a soft baking process or a dry process to remove the solvent.

Referring to fig. 4A and 16E, the low refractive index layer 323 and the light-shielding layer 321 may be patterned to form a mesh structure 320 including a low refractive index pattern 324 and a light-shielding pattern 322. When viewed in plan, the mesh structure 320 may overlap the pixel separation structure 103 in the semiconductor substrate 100, as discussed above.

The forming of the mesh structure 320 may include: a mask pattern (not shown) is formed on the low refractive index layer 323, and the mask pattern is used as an etching mask through which the low refractive index layer 323 and the light-shielding layer 321 are sequentially etched to expose the flat dielectric layer 310. After the grid structure 320 is formed, the mask pattern may be removed.

The mesh structure 320 may include a first barrier portion FS1 disposed between the adjacent sub-pixel regions PG1/PG2, PR, and PB, and a second barrier portion FS2 disposed between the adjacent pixel regions P1, P2, and P3. The first and second fence portions FS1 and FS2 may have substantially the same height. Further, the first barrier portion FS1 and the second barrier portion FS2 may have substantially the same width.

Thereafter, a protective layer 330 may be formed to conformally cover the surface of the mesh structure 320 and the top surface of the planar dielectric layer 310 exposed by the mesh structure 320. The protective layer 330 may be formed by performing a chemical vapor deposition process or an atomic layer deposition process. The protective layer 330 may be formed of a single layer or a plurality of layers including one or more of an aluminum oxide layer and a silicon oxycarbide layer.

Referring to fig. 4A and 16F,

initial color filters

340a and 340b may be sequentially formed on corresponding pixel regions (see P1, P2, and P3 of fig. 3). For example, a first initial color filter 340a may be formed on the first pixel region P1, and a second initial color filter 340b may be formed on the second pixel region P2. In addition, a third initial color filter (not shown) may be formed on the third pixel region P3.

Each of the

initial color filters

340a and 340b may be formed by performing a spin coating process and a patterning process several times. The

initial color filters

340a and 340b may fill the empty space defined by the mesh structure 320. For example, the

initial color filters

340a and 340b may be formed through a coating process, a soft baking process, an exposure process, and a developing process, which are sequentially performed on a photoresist composition including a dye or a pigment.

In some example embodiments, each of the

initial color filters

340a and 340b may be commonly disposed with respect to the sub-pixel regions PG1/PG2, PR, and PB of the pixel regions P1, P2, and P3. For example, when each of the

initial color filters

340a and 340b is formed, a coating process may be performed such that each of the

initial color filters

340a and 340b may cover the first barrier portion FS1 of the mesh structure 320. Each of the

initial color filters

340a and 340b may have a relatively large thickness at a portion adjacent to the first barrier portion FS1 and a relatively small thickness at a portion adjacent to the second barrier portion FS 2. As such, each of the

initial color filters

340a and 340b may have a top surface that is upwardly convex. In addition, the

initial color filters

340a and 340b may be formed independently of each other, so that the

initial color filters

340a and 340b may have different thicknesses from each other.

Referring to fig. 4A and 16G, a sacrificial planarizing layer 355 may be formed to cover the top surfaces of the

initial color filters

340a and 340 b. The sacrificial planarizing layer 355 may be formed of a material having an etch selectivity of about 1:1 with respect to the

initial color filters

340a and 340b in an etch process using the same etch recipe for the

initial color filters

340a and 340 b. The sacrificial planarizing layer 355 may be formed of a transparent dielectric material. The sacrificial planarizing layer 355 may be formed of, for example, SOG (spin on glass), FSG (fluoride silicate glass), FOX (flowable oxide), or TOSZ (Tonen silazane). The sacrificial planarizing layer 355 can be formed by spin coating a flowable material. The sacrificial planarizing layer 355 may cover the uneven top surfaces of the

initial color filters

340a and 340b, but may have substantially flat top surfaces. For example, the sacrificial planarizing layer 355 may have different thicknesses on the first barrier portion FS1 and the second barrier portion FS 2. That is, for example, as shown in fig. 16G, the thickness of the sacrificial planarizing layer 355 on the second fence portion FS2 may be greater than the thickness on the first fence portion FS 1.

Referring to fig. 4A and 16H, after the sacrificial planarizing layer 355 is formed, a planarization process may be performed on the sacrificial planarizing layer 355 and the

initial color filters

340a and 340 b. Accordingly, the first, second, and

third color filters

345a, 345b, and (not shown) may be formed to correspond to the first, second, and third pixel regions P1, P2, and P3. For example, the planarization process may include an etch-back process or a chemical mechanical polishing process.

When performing the planarization process, the protection layer 330 covering the top surface of the mesh structure 320 may serve as an etch stop layer or a planarization stop layer. For example, the planarization process may continue until the protective layer 330 covering the top surface of the mesh structure 320 is exposed. After the planarization process, the first barrier portion FS1 of the mesh structure 320 may separate the first initial color filter 340a into four first color filters 345 a. The separation may be equally applied to the second initial color filter 340 b.

When the planarization process is performed, the sacrificial planarizing layer 355 may be etched at an etch selectivity of about 1:1 with respect to the

initial color filters

340a and 340 b. Accordingly, each of the first, second, and

third color filters

345a, 345b, and 35may have substantially the same thickness on the first and second barrier portions FS2 and FS 2. For example, each of the first, second, and

third color filters

345a, 345b, and 345b may have a substantially flat top surface. Further, after the planarization process, the top surfaces of the first, second, and

third color filters

345a, 345b, and the third color filters may be positioned at a level lower than that of the top surface of the mesh structure 320, or at substantially the same level as that of the top surface of the mesh structure 320.

Thereafter, as shown in fig. 4A and 4B, a microlens array 350 may be formed to include microlenses 353 corresponding to the sub-pixel regions PG1/PG2, PR, and PB.

The microlens array 350 may be formed by: forming a light-transmitting photoresist layer; partially patterning the photoresist layer to form a photoresist pattern corresponding to the sub-pixel regions PG1/PG2, PR, and PB; and reflowing the photoresist pattern. Accordingly, the microlens 353 may be formed in an upwardly convex shape having a constant curvature. In addition, the flat portion 351 may be formed to have a uniform thickness between the microlens 353 and the first, second, and

third color filters

345a, 345b, and third color filters.

Since the microlens array 350 is formed by coating a light-transmissive photoresist layer on the first, second, and

third color filters

345a, 345b, and 345b having a flat top surface, the microlens array 350 may have a substantially uniform thickness at the maximum thickness of the microlens array 350. Microlenses 353 may have a substantially constant curvature over the top surface of

color filters

345a and 345 b. In this case, the thickness distribution of the microlens array 350 can be improved.

Thereafter, a passivation layer 360 may be formed to conformally cover the surface of microlens 353. The passivation layer 360 may be formed of, for example, an inorganic oxide.

Referring to fig. 17A, after the planarization process is performed on the second surface 100b of the semiconductor substrate 100 as discussed above in fig. 16D, a fixed charge layer 300 may be formed on the second surface 100 b. A planar dielectric layer 310 may be formed on the fixed charge layer 300. In this case, the formation of the planar dielectric layer 310 may include sequentially depositing a first planar layer 311 and a second planar layer 313. The first and second

flat layers

311 and 313 may be formed of a transparent dielectric material, and may have different thicknesses and different refractive indices. The first planarization layer 311 may include a hafnium oxide layer, a tantalum oxide layer, or a titanium oxide layer. The second planarization layer 313 may include a silicon oxide layer such as TEOS.

Thereafter, a sacrificial pattern MP may be formed on the planar dielectric layer 310. The sacrificial pattern MP may have a thickness greater than that of the planar dielectric layer 310. The forming of the sacrificial pattern MP may include: coating a sacrificial layer on the planar dielectric layer 310; forming a photoresist pattern on the sacrificial layer; and etching the sacrificial layer using the photoresist pattern as an etching mask. The sacrificial pattern MP may define a mesh-shaped initial recess RR1 on the planar dielectric layer 310. The initial recess RR1 may expose the planar dielectric layer 310. The sacrificial pattern MP may include carbon in an amount equal to or greater than about 70 wt%. For example, the sacrificial pattern MP may include a spin on hard mask (SOH) layer.

Referring to fig. 17B, the sacrificial pattern MP may be used as an etch mask to pattern the planarization dielectric layer 310. Accordingly, the planar dielectric layer 310 may have a recess RR2 therein, the recess RR2 being formed to expose the fixed charge layer 300. Alternatively, in some example embodiments, the fixed charge layer 300 may be etched when the recess RR2 is formed, and thus the recess RR2 may expose the pixel separation structure 103.

After forming recess RR2, low refractive index layer 323 may be formed to fill recess RR 2. The low refractive index layer 323 may be formed by performing a spin coating process. Accordingly, the low refractive index layer 323 may completely fill the recess RR2, and may cover the top surface of the sacrificial pattern MP.

Thereafter, a planarization process may be performed with respect to the low refractive index layer 323 until the top surface of the sacrificial pattern MP is exposed.

The sacrificial pattern MP may be selectively removed to expose the top surface of the planar dielectric layer 310 for each of the sub-pixel regions PG1/PG2, PR, and PB. For example, the sacrificial pattern MP may be removed by an ashing process using oxygen.

Referring to fig. 17C, after selectively removing the sacrificial pattern MP, a protective layer 330 may be conformally formed. For example, the protective layer 330 may have a uniform thickness, the protective layer 330 covering the top surface of the planar dielectric layer 310 and the sidewalls and top surface of the mesh structure 320. The removal of the sacrificial pattern MP and the formation of the protective layer 330 may form openings defined by sidewalls of the mesh structure 320 and the top surface of the flat dielectric layer 310. As a result, as shown in fig. 17C, a mesh structure 320 including a low refractive index pattern may be formed.

Referring to fig. 17D, the first, second, and third

initial color filters

340a, 340b, and 340b may be formed to correspond to the first, second, and third pixel regions P1, P2, and P3.

Since the coating process is performed to form each of the first, second, and third

initial color filters

340a, 340b, and 340F as discussed with reference to fig. 16F, each of the first, second, and third

initial color filters

340a, 340b, and 340F may cover the first barrier portion FS1 of the mesh structure 320. As such, each of the first, second, and third

initial color filters

340a, 340b, and 340b may have a top surface that is upwardly convex.

Thereafter, as discussed with reference to fig. 16G, a sacrificial planarizing layer 355 may be formed to cover the top surfaces of the first, second, and third

initial color filters

340a, 340b, and the third initial color filters. The sacrificial planarizing layer 355 may cover the uneven top surfaces of the

initial color filters

340a and 340b, but may have substantially flat top surfaces.

Thereafter, as discussed above, a planarization process may be performed on the sacrificial planarizing layer 355 and on the first, second, and third

initial color filters

340a, 340b, and 340 b. Accordingly, the first, second, and

third color filters

345a, 345b, and 345b may be formed to correspond to the first, second, and third pixel regions P1, P2, and P3.

Color filters

345a and 345b may have substantially flat top surfaces.

According to some example embodiments, each pixel region of the image sensor may include a color filter whose top surface is flat and whose thickness at opposite sidewalls thereof is substantially the same. Accordingly, the image sensor can improve its sensitivity deterioration due to thickness unevenness of the color filter filling the empty space defined by the mesh structure.

In addition, microlenses having a uniform radius of curvature may be disposed on the color filters. Therefore, crosstalk between pixel regions of the image sensor can be minimized. As a result, the sensitivity characteristic and the signal-to-noise ratio characteristic of the image sensor can be improved.

Although the inventive concept has been described in connection with some exemplary embodiments shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the claims.

Claims

1. An image sensor, the image sensor comprising:

a substrate including a pixel separation structure defining a plurality of pixel regions and a plurality of sub-pixel regions for each of the plurality of pixel regions;

a mesh structure disposed on the substrate and including first barrier portions disposed between the sub-pixel regions and second barrier portions disposed between adjacent pixel regions, the mesh structure defining a plurality of openings corresponding to the plurality of sub-pixel regions, respectively; and

a plurality of color filters disposed in the openings defined by the grid structure, each color filter having a flat top surface, the flat top surface of each color filter being parallel to the bottom surface of each color filter.

2. The image sensor of claim 1, wherein the color filter has a first height adjacent to the first barrier portion and a second height adjacent to the second barrier portion, and a difference between the first height and the second height is

To

3. The image sensor of claim 1, wherein the grid structure includes an overcoat layer covering a top surface of the grid structure, and the planar top surface of the color filter is coplanar with the top surface of the overcoat layer.

4. The image sensor of claim 1, wherein a top surface of the color filter is lower than a top surface of the grid structure.

5. The image sensor of claim 1, wherein the mesh structure comprises a protective pattern covering only sidewalls of the mesh structure and a bottom surface of the color filter, and

the top surface of the color filter is lower than the top surface of the grid structure.

6. The image sensor of claim 1, further comprising a fixed charge layer and a flat dielectric layer sequentially stacked between a substrate and a grid structure,

wherein the mesh structure includes a light shielding pattern disposed on the flat dielectric layer and a low refractive index pattern disposed on the light shielding pattern.

7. The image sensor of claim 6, wherein the low refractive index pattern has a height of

To

Each color filter has a thickness of

To

8. The image sensor of claim 1, further comprising a microlens array disposed on the color filter, the microlens array comprising a flat portion disposed on the color filter and a plurality of microlenses on the flat portion corresponding to the sub-pixel regions.

9. The image sensor of claim 1, wherein a height of the grid structure is less than a thickness of each color filter.

10. The image sensor of claim 1, wherein the substrate includes a pixel array area and a pad area around the pixel array area, the pixel array area including the plurality of pixel areas,

the pixel array region includes a central region and an edge region surrounding the central region,

the mesh structure is superposed with the pixel separation structure in the central region in a plan view, and

the plurality of color filters have a thickness in the edge region smaller than a thickness in the center region.

11. An image sensor, the image sensor comprising:

a substrate having a first surface and a second surface opposite to the first surface, the substrate including a pixel isolation structure defining a plurality of pixel regions;

a device isolation layer disposed adjacent to the first surface of the substrate on each of the plurality of pixel regions, the device isolation layer defining an active region in the plurality of pixel regions;

a plurality of interlayer dielectric layers stacked on the first surface of the substrate and including contact plugs and connection lines;

a fixed charge layer disposed on the second surface of the substrate;

a flat dielectric layer disposed on the fixed charge layer;

a mesh structure disposed on the flat dielectric layer to overlap the pixel separating structure in a plan view, the mesh structure including barrier portions disposed between adjacent pixel regions, the mesh structure defining a plurality of openings corresponding to the plurality of pixel regions, respectively;

a plurality of color filters disposed in the openings defined by the mesh structure;

a sacrificial planarizing layer located between adjacent ones of the plurality of color filters, the sacrificial planarizing layer having a top surface coplanar with an uppermost surface of each color filter; and

a microlens array disposed on the plurality of color filters.

12. The image sensor of claim 11, wherein the sacrificial planarizing layer fills the space above each barrier portion such that a top surface of the sacrificial planarizing layer is coplanar with an uppermost surface of each color filter.

13. The image sensor of claim 11, wherein the pixel separation structure defines a plurality of sub-pixel regions for each of the plurality of pixel regions,

the barrier portion is a second barrier portion, and the mesh structure further includes a first barrier portion disposed between the sub-pixel regions, and

each color filter has a first height at a portion adjacent to the first barrier portion greater than a second height at a portion adjacent to the second barrier portion.

14. The image sensor of claim 13, wherein the microlens array comprises a flat portion disposed on the color filter and a plurality of microlenses on the flat portion corresponding to the sub-pixel regions.

15. The image sensor of claim 11, wherein the plurality of pixel regions form a 2 x2 matrix and a sacrificial planarizing layer fills spaces between pixel regions.

16. The image sensor of claim 11, wherein the grid structure includes an overcoat layer covering a top surface of the grid structure, and an uppermost surface of each color filter is coplanar with the top surface of the overcoat layer.

17. The image sensor of claim 11, wherein the grid structure comprises a light blocking pattern disposed on the planar dielectric layer and a low refractive index pattern disposed on the light blocking pattern.

18. The image sensor of claim 17, wherein the low refractive index pattern has a height of

To

Each color filter has a thickness of

To

19. The image sensor of claim 11, wherein a height of the grid structure is less than a maximum thickness of each color filter.

20. The image sensor of claim 11, wherein the substrate includes a pixel array area and a pad area around the pixel array area, the pixel array area including the plurality of pixel areas,

the maximum thickness of each color filter in the edge region is smaller than the maximum thickness of each color filter in the center region.