CN114068592A

CN114068592A - Image sensor including barrier pattern

Info

Publication number: CN114068592A
Application number: CN202110777511.4A
Authority: CN
Inventors: 方善煐; 罗承柱; 郑会敏; 郑熙根
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2020-07-29
Filing date: 2021-07-09
Publication date: 2022-02-18
Also published as: KR20220014951A; US20220037385A1; JP2022027609A; US11848342B2

Abstract

An image sensor includes: a substrate having a first surface and a second surface opposite to each other; a plurality of color filters on the substrate; a barrier pattern between adjacent color filters of the plurality of color filters; and an overcoat layer between the substrate and the plurality of color filters, wherein the overcoat layer covers the barrier pattern. The barrier pattern includes: a first barrier pattern having a first bottom surface and a first top surface opposite to each other; and a second barrier pattern on the first top surface of the first barrier pattern. The first barrier patterns have a width at the first bottom surface smaller than that of the second barrier patterns, and the protective layer covers sidewalls of the first barrier patterns.

Description

Image sensor including barrier pattern

Cross Reference to Related Applications

This us non-provisional application claims priority from korean patent application No.10-2020-0094782, filed at the korean intellectual property office on 29/7/2020, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to an image sensor, and more particularly, to an image sensor including a barrier pattern.

Background

Generally, an image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into a Charge Coupled Device (CCD) type and a Complementary Metal Oxide Semiconductor (CMOS) type. The CMOS type image sensor is abbreviated as CIS (CMOS image sensor). In general, a CIS has a plurality of pixels arranged on a plane. Each of the pixels includes a photodiode. The photodiode is used to convert incident light into an electrical signal.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, an image sensor includes: a substrate having a first surface and a second surface opposite to each other; a plurality of color filters on the substrate;

a barrier pattern between adjacent color filters of the plurality of color filters; and an overcoat layer between the substrate and the plurality of color filters, wherein the overcoat layer covers the barrier pattern. The barrier pattern includes: a first barrier pattern having a first bottom surface and a first top surface opposite to each other; and a second barrier pattern on the first top surface of the first barrier pattern. The first barrier patterns have a width at the first bottom surface smaller than that of the second barrier patterns, and the protective layer covers sidewalls of the first barrier patterns.

According to an exemplary embodiment of the inventive concept, an image sensor includes: a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a plurality of photoelectric conversion regions; a separation pattern in the substrate and between the photoelectric conversion regions; a plurality of color filters on the substrate; and a barrier pattern on the partition pattern and between adjacent color filters of the plurality of color filters. The barrier pattern includes: a first barrier pattern having a bottom surface and a top surface opposite to each other; and a second barrier pattern on the first barrier pattern. The width of the first barrier pattern at the bottom surface is less than that of the first barrier pattern at the top surface, and the maximum width of the second barrier pattern is about 100% to about 102% of the minimum width of the second barrier pattern.

According to an exemplary embodiment of the inventive concept, an image sensor includes: a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a plurality of photoelectric conversion regions therein; a partition pattern in the substrate and between adjacent ones of the plurality of photoelectric conversion regions; a plurality of color filters on the substrate; a barrier pattern on the partition pattern and between adjacent color filters of the plurality of color filters, wherein the barrier pattern includes: a first barrier pattern having a first bottom surface and a first top surface opposite to each other; and a second barrier pattern on the first top surface of the first barrier pattern, wherein a width of the first barrier pattern at the first bottom surface is smaller than a width of the first barrier pattern at the first top surface; a dielectric layer between the substrate and the color filter and between the barrier pattern and the partition pattern; an overcoat layer between the dielectric layer and the color filter, wherein the overcoat layer covers sidewalls of the first barrier patterns, sidewalls of the second barrier patterns, and top surfaces of the second barrier patterns; a microlens layer on the color filter and the barrier pattern; a gate pattern on the second surface of the substrate; and a wiring layer on the second surface of the substrate, wherein the wiring layer includes a lower dielectric layer and a wiring structure, wherein the lower dielectric layer covers the gate pattern, and wherein the wiring structure is in the lower dielectric layer.

Drawings

Fig. 1 illustrates a circuit diagram of a pixel of an image sensor according to an exemplary embodiment of the inventive concept.

Fig. 2A illustrates a plan view of an image sensor according to an exemplary embodiment of the inventive concept.

Fig. 2B shows a cross-sectional view taken along line I-I' of fig. 2A.

Fig. 3A illustrates an enlarged plan view of a portion a of fig. 2A, which illustrates a pixel array region of an image sensor according to an exemplary embodiment of the inventive concept.

Fig. 3B shows an enlarged cross-sectional view of portion B of fig. 2B taken along line II-II' of fig. 3A.

Fig. 3C shows an enlarged view of a portion C in fig. 3B.

Fig. 4A, 4B, 4C, 4D, and 4E illustrate a cross-sectional view of a portion C of fig. 3B, which shows a pixel array region of an image sensor according to an exemplary embodiment of the inventive concept.

Fig. 5 illustrates a cross-sectional view taken along line II-II' of fig. 3A, which illustrates a pixel array region of an image sensor according to an exemplary embodiment of the inventive concept.

Fig. 6 illustrates a sectional view taken along line I-I' of fig. 2A, which illustrates an image sensor according to an exemplary embodiment of the inventive concept.

Detailed Description

In the present description, like reference numerals may refer to like parts. Now, an image sensor according to an exemplary embodiment of the inventive concept will be described below.

Referring to fig. 1, each pixel of the image sensor may include a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax. The transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax may include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG, respectively.

The photoelectric conversion region PD may be a photodiode including an n-type impurity region and a p-type impurity region. The floating diffusion FD may serve as a drain of the transfer transistor Tx. The floating diffusion region FD may also serve as a source of the reset transistor Rx. The floating diffusion region FD may be electrically connected to a source follower gate SG of the source follower transistor Sx. The source follower transistor Sx may be connected to the selection transistor Ax.

The operation of the image sensor will be explained with reference to fig. 1. In addition, the power supply voltage VDD may be applied to the drain of the reset transistor Rx and the drain of the source follower transistor Sx in a light-blocking state (the reset transistor Rx may be turned on to release charges remaining on the floating diffusion region FD during the light-blocking state). After that, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs may be generated from the photoelectric conversion region PD. Holes may be transferred to and accumulated on the p-type impurity region of the photoelectric conversion region PD, and electrons may be transferred to and accumulated on the n-type impurity region of the photoelectric conversion region PD. When the transfer transistor Tx is turned on, charges such as electrons and holes may be transferred to the floating diffusion region FD and accumulated thereon. The gate bias voltage of the source follower transistor Sx may vary in proportion to the amount of accumulated charge, and this may bring about a variation in the source potential of the source follower transistor Sx. In this case, when the select transistor Ax is on, charge can be read out as a signal sent through the column line.

The connection line may be electrically connected to one or more of the transfer gate TG, the source follower gate SG, the reset gate RG, and the selection gate AG. The connection line may be configured to apply the power supply voltage VDD to the drain of the reset transistor Rx or the drain of the source follower transistor Sx. The connecting line may include a column line connected to the select transistor Ax. The connection line may be a first conductive structure 830, which will be discussed below in fig. 2B and 3B.

Fig. 1 illustrates a pixel including one photoelectric conversion region PD and four transistors Tx, Rx, Ax, and Sx by way of example, but the inventive concept is not limited thereto. For example, a pixel may be provided in plurality, and adjacent pixels may share at least one of the reset transistor Rx, the source follower transistor Sx, and the selection transistor Ax. Therefore, the integration degree of the image sensor can be improved.

Fig. 2A illustrates a plan view of an image sensor according to an exemplary embodiment of the inventive concept. Fig. 2B shows a cross-sectional view taken along line I-I' of fig. 2A.

Referring to fig. 2A and 2B, the image sensor may include a sensor chip 10. The sensor chip 10 may include a first substrate 100, a first wiring layer 800, a dielectric layer 400, an overcoat layer 470, a color filter CF, a barrier pattern 300, and a microlens layer 500.

The first substrate 100 may include a pixel array region APS, an optical black region OB, and a PAD region PAD when viewed in a plan view. The pixel array area APS may be disposed on a central portion of the first substrate 100 when viewed in a plan view. The pixel array area APS may include a plurality of pixel areas PX. The pixels discussed with reference to fig. 1 may be formed on the corresponding pixel area PX of the first substrate 100. For example, components of the pixels may be disposed on the corresponding pixel regions PX. The pixel area PX may output an optical electrical signal based on incident light. The pixel regions PX may be arranged in a plurality of rows and columns on a plane. The rows may be parallel to the first direction D1. The columns may be parallel to the second direction D2. In this description, the first direction D1 may be parallel to the first surface 100a of the first substrate 100. The second direction D2 may be parallel to the first surface 100a of the first substrate 100 and may be different from the first direction D1. For example, the second direction D2 may be substantially perpendicular to the first direction D1. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be substantially perpendicular to the first surface 100a of the first substrate 100.

For example, the PAD area PAD may be disposed on an edge portion of the first substrate 100, and may at least partially surround the pixel array area APS. The PAD terminal 900 may be disposed on the PAD area PAD. The pad terminal 900 may output an electrical signal generated from the pixel area PX to the outside. In addition, an external electrical signal or voltage may be transmitted to the pixel area PX through the pad terminal 900. When the PAD area PAD is disposed on the edge portion of the first substrate 100, the PAD terminal 900 may be coupled to the outside. For simplicity of description, the single pad terminal 900 will be discussed below. The optical black area OB will be discussed below. The following description will be focused on the pixel array area APS of the sensor chip 10 included in the image sensor.

Fig. 3A illustrates an enlarged plan view of a portion a of fig. 2A, which illustrates a pixel array region of an image sensor according to an exemplary embodiment of the inventive concept. Fig. 3B shows an enlarged cross-sectional view of portion B of fig. 2B taken along line II-II' of fig. 3A. Fig. 3C shows an enlarged view of a portion C in fig. 3B. Duplicate description will be omitted below.

Referring to fig. 3A, 3B, and 3C, the image sensor may include a first substrate 100, a first wiring layer 800, partition patterns 200, a dielectric layer 400, a color filter CF, barrier patterns 300, and a microlens layer 500.

The first substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. For example, the first surface 100a of the first substrate 100 may be a rear surface, and the second surface 100b of the first substrate 100 may be a front surface. The first substrate 100 may receive light on the first surface 100 a. For example, the first substrate 100 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. For example, the semiconductor substrate may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The first substrate 100 may further include a group III element. The group III element may be a first conductive type impurity. The first substrate 100 may include first conductive type impurities to have a first conductive type. For example, the first conductive type impurity may include a p-type impurity, such as one or more of aluminum (Al), boron (B), indium (In), and/or gallium (Ga). The first substrate 100 may have a pixel area PX. As shown in fig. 3B, the pixel area PX may include a first pixel area PX1 and a second pixel area PX2 adjacent to each other.

The first substrate 100 may include a photoelectric conversion region PD. The photoelectric conversion region PD may be interposed between the first surface 100a and the second surface 100b of the first substrate 100. In the first substrate 100, the photoelectric conversion regions PD may be disposed on the corresponding pixel regions PX. The photoelectric conversion region PD may have the same function and role as those of the photoelectric conversion region PD shown in fig. 1. For example, the photoelectric conversion regions PD may each further include a group V element. The group V element may be a second conductive type impurity. The photoelectric conversion region PD may be a region of the first substrate 100 doped with second conductive type impurities. The second conductive type impurities may have a conductive type opposite to that of the first conductive type impurities. The second conductive type impurities may include n-type impurities such as one or more of phosphorus, arsenic, bismuth and/or antimony. For example, the photoelectric conversion region PD may be disposed below the first surface 100a of the first substrate 100.

The partition pattern 200 may be disposed in the first substrate 100, and may form a pixel region PX. For example, the partition pattern 200 may be disposed between the pixel regions PX of the first substrate 100. The separation pattern 200 may be a pixel separation pattern. The partition pattern 200 may be disposed in the first trench 201, and the first trench 201 may extend from the second surface 100b of the first substrate 100. For example, the separation pattern 200 may be a Deep Trench Isolation (DTI) layer. The partition pattern 200 may pass through the first surface 100a of the first substrate 100. As shown in fig. 3B, the width W11 of the partition pattern 200 at the top surface may be smaller than the width W12 of the partition pattern 200 at the bottom surface. For example, the top surface of the partition pattern 200 may be coplanar with the first surface 100a of the first substrate 100. The bottom surface of the partition pattern 200 may be opposite to the top surface of the partition pattern 200. The partition pattern 200 may include a first partition pattern 210 and a second partition pattern 220. The first partition pattern 210 may be disposed along sidewalls of the first trench 201. For example, the first partition pattern 210 may include one or more of a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, and/or silicon oxynitride) and/or a high-k dielectric material (e.g., hafnium oxide and/or aluminum oxide). For example, the first partition pattern 210 may include a plurality of layers, and the plurality of layers may include materials different from each other. However, the inventive concept is not limited thereto, and for example, the first partition pattern 210 may be a single layer. The refractive index of the first partition pattern 210 may be less than that of the first substrate 100. Accordingly, crosstalk between the pixel areas PX of the first substrate 100 may be prevented or reduced.

The second partition pattern 220 may be disposed in the first partition pattern 210. The first partition pattern 210 may be interposed between the second partition pattern 220 and the first substrate 100. The first partition pattern 210 may separate the second partition pattern 220 from the first substrate 100. Accordingly, the second partition pattern 220 may be electrically separated from the first substrate 100 when the image sensor operates. The second partition pattern 220 may include a crystalline semiconductor material, for example, polysilicon. For example, the second partition pattern 220 may further include a dopant, which may include a first conductive type impurity or a second conductive type impurity. For example, the second partition pattern 220 may include doped polysilicon.

In the corresponding pixel area PX, the color filter CF is disposed on the first surface 100a of the first substrate 100. For example, the color filter CF may be disposed at a position corresponding to the position of the photoelectric conversion region PD. Each of the color filters CF may include one of a red color filter, a blue color filter, and a green color filter. The color filter CF may constitute a color filter array. For example, the color filters CF may form an array along the first direction D1 and the second direction D2 when viewed in a plan view.

The barrier pattern 300 may be disposed on the partition pattern 200. For example, the barrier pattern 300 may overlap with the partition pattern 200 when viewed in a plan view. The barrier pattern 300 may be interposed between two adjacent color filters CF to separate the color filters CF. For example, the barrier pattern 300 may physically and optically separate the plurality of color filters CF from each other.

The barrier pattern 300 may overlap the partition pattern 200 when viewed in a plan view. The barrier pattern 300 may have a shape corresponding to the shape of the partition pattern 200. For example, the barrier pattern 300 may have a grid shape as shown in fig. 3A. The barrier pattern 300 may surround each pixel area PX when viewed in a plan view. For example, the barrier pattern 300 may surround each color filter CF. The barrier pattern 300 may include a first portion and a second portion. The first portions may extend parallel to the first direction D1 and may be spaced apart from each other in the second direction D2. Each of the second portions may extend parallel to the second direction D2. The second portions may be spaced apart from each other in the first direction D1. The second portion may be connected to the first portion.

As shown in fig. 3B, the barrier patterns 300 may include a first barrier pattern 310 and a second barrier pattern 320. The first barrier patterns 310 may be disposed between the partition patterns 200 and the second barrier patterns 320. For example, the first barrier pattern 310 may include a conductive material, such as one or more of a metal and/or a metal nitride. For example, the first barrier patterns 310 may include one or more of titanium and titanium nitride.

The second barrier pattern 320 may be disposed on the first barrier pattern 310. The second barrier patterns 320 may include a material different from that of the first barrier patterns 310. For example, the second barrier patterns 320 may include an organic material. The second barrier patterns 320 may include a material having a low refractive index and may have a dielectric property. For example, the refractive index of the second barrier pattern 320 may be lower than that of the substrate 100; however, the inventive concept is not limited thereto. The second barrier patterns 320 may have, for example, a rectangular cross-section. The width of the barrier pattern 300 at the bottom surface may be smaller than the width of the barrier pattern 300 at the top surface. Accordingly, the first substrate 100 may receive an increased amount of incident light. The barrier pattern 300 will be further discussed below with reference to fig. 3C.

The dielectric layer 400 may be interposed between the first substrate 100 and the color filter CF and between the partition pattern 200 and the barrier pattern 300. The dielectric layer 400 may cover the first surface 100a of the first substrate 100 and the top surface of the separation pattern 200. For example, dielectric layer 400 may be a backside dielectric layer. For example, the dielectric layer 400 may include a bottom anti-reflective coating (BARC) layer. The dielectric layer 400 may include a plurality of layers, and the plurality of layers may have different functions from each other. However, the inventive concept is not limited thereto. For example, the dielectric layer 400 may be a single layer.

The dielectric layer 400, the color filter CF, the overcoat layer 470, and the microlens layer 500 according to an exemplary embodiment of the inventive concept will be described in detail below.

Referring to fig. 3B and 3C, the color filters CF may be disposed on the first surface 100a of the first substrate 100 and may be placed laterally adjacent to each other. The color filters CF may include a first color filter CF1 and a second color filter CF2 adjacent to each other. The first color filter CF1 and the second color filter CF2 may correspond to the first pixel area PX1 and the second pixel area PX2, respectively. For example, a first color filter CF1 and a second color filter CF2 may be disposed on the first pixel area PX1 and the second pixel area PX2, respectively. The type of the second color filter CF2 may be different from that of the first color filter CF 1. For example, the color of the second color filter CF2 may be different from the color of the first color filter CF 1. For example, the second color filter CF2 may be one of a red color filter, a blue color filter, and a green color filter, and the first color filter CF1 may be one of the remaining ones of the red color filter, the blue color filter, and the green color filter. For another example, the type of the second color filter CF2 may be the same as the type of the first color filter CF 1.

On the dielectric layer 400, the barrier pattern 300 may be interposed between the color filters CF. The barrier pattern 300 may vertically overlap the partition pattern 200. In this description, the term "vertical" may mean "parallel to the third direction D3 or parallel to the opposite direction to the third direction D3". The first surface 100a of the first substrate 100 may receive external light passing through the microlens layer 500 and the color filter CF. In this case, light may be incident to the first surface 100a of the first substrate 100. For example, the light may be incident in a direction inclined with respect to the first surface 100 a. The barrier pattern 300 may prevent light from being transmitted from the first color filter CF1 corresponding to the first pixel area PX1 toward the photoelectric conversion area PD of the second pixel area PX 2. Similarly, the barrier pattern 300 may prevent light from being transmitted from the second color filter CF2 corresponding to the second pixel area PX2 toward the photoelectric conversion area PD of the first pixel area PX 1. Accordingly, crosstalk between the pixel areas PX of the image sensor may be reduced.

The barrier patterns 300 may include a first barrier pattern 310 and a second barrier pattern 320. The first barrier pattern 310 may have a first bottom surface 310b, a first sidewall 310c, and a first top surface 310 a. The first bottom surface 310b of the first barrier pattern 310 may correspond to the bottom surface of the barrier pattern 300. The first top surface 310a of the first barrier pattern 310 may be opposite to the first bottom surface 310b of the first barrier pattern 310. The first sidewall 310c may connect an edge of the first top surface 310a to an edge of the first bottom surface 310 b. The first sidewall 310c may be inclined with respect to the first bottom surface 310 b. The first barrier pattern 310 may function as a barrier layer. According to an exemplary embodiment of the inventive concept, charges may be trapped at an interface between the first substrate 100 and the dielectric layer 400. The first bottom surface 310b of the first barrier pattern 310 may contact the dielectric layer 400, thereby removing the trapped charges. For example, the first barrier patterns 310 may be used as an adhesive layer, and thus the second barrier patterns 320 may be attached to the dielectric layer 400.

When the barrier pattern 300 has a relatively large width, the barrier pattern 300 may absorb or reflect light incident thereon from the outside, and thus may not transmit the light to the first substrate 100. The increase in the area of the bottom surface of the barrier pattern 300 may reduce the amount of light incident on the first substrate 100. According to an exemplary embodiment of the inventive concept, the first bottom surface 310b of the first barrier pattern 310 may have a relatively small width W1. The width W1 of the first barrier pattern 310 at the first bottom surface 310b may be less than the width W3 of the first barrier pattern 310 at the first top surface 310 a. The width W1 of the first barrier pattern 310 at the first bottom surface 310b may be in the range of about 45nm to about 55 nm. When the width W1 of the first barrier pattern 310 at the first bottom surface 310b is equal to or less than about 55nm, an increased amount of light may be incident on each pixel area PX of the first substrate 100. For example, an increased amount of light may be incident on each photoelectric conversion region PD of the first substrate 100. When the width W1 of the first substrate 100 at the first bottom surface 310b is equal to or greater than about 45nm, the first barrier patterns 310 may prevent crosstalk between the pixel areas PX. The width W1 of the first barrier pattern 310 at the first bottom surface 310b may be less than the width W11 of the partition pattern 200 at the top surface.

In exemplary embodiments of the inventive concept, the width W3 of the first top surface 310a of the first barrier pattern 310 may be substantially equal to the width W11 of the partition pattern 200 at the top surface.

In exemplary embodiments of the inventive concept, the width W1 of the first barrier pattern 310 at the first bottom surface 310b may be the same as the width W3 of the first barrier pattern 310 at the first top surface 310 a.

For example, the first barrier pattern 310 may have an hourglass shape or a hourglass shape. For example, the first barrier pattern 310 may include a lower portion, a middle portion, and an upper portion. The lower portion of the first barrier pattern 310 may have a first bottom surface 310 b. The upper portion of the first barrier pattern 310 may have a first top surface 310 a. The middle portion of the first barrier pattern 310 may be disposed between the lower and upper portions of the first barrier pattern 310. The width of the middle portion of the first barrier pattern 310 may be less than the width W1 of the first barrier pattern 310 at the first bottom surface 310b and the width W3 of the first barrier pattern 310 at the first top surface 310 a. For example, the first barrier patterns 310 may have a minimum width measured at a position higher than the first bottom surface 310b and lower than the first top surface 310 a.

The second barrier patterns 320 may be disposed on the first top surfaces 310a of the first barrier patterns 310. The second barrier patterns 320 may have second bottom and top surfaces 320a opposite to each other. The second bottom surface of the second barrier pattern 320 may physically contact the first top surface 310a of the first barrier pattern 310. The first top surface 310a of the first barrier pattern 310 may have an edge portion not covered by the second barrier pattern 320.

The width W2 of the second barrier pattern 320 may be less than the width W3 of the first barrier pattern 310 at the first top surface 310a and greater than the width W1 of the first barrier pattern 310 at the first bottom surface 310 b. For example, the width W2 of the second barrier pattern 320 may be in the range of about 72nm to about 88 nm. The width W2 of the second barrier pattern 320 may refer to the width of the second barrier pattern 320 at the second bottom surface unless otherwise specifically limited in this description. When the width W2 of the second barrier pattern 320 is equal to or greater than about 72nm, the second barrier pattern 320 may substantially prevent crosstalk between the color filters CF and crosstalk between the pixel areas PX of the first substrate 100. When the width W2 of the second barrier pattern 320 is equal to or less than about 88nm, an increased amount of light may be incident on each pixel area PX of the first substrate 100. For example, the width W2 of the second barrier pattern 320 may be less than the width W11 of the partition pattern 200 at the top surface. However, the inventive concept is not limited thereto. For example, the width W2 of the second barrier pattern 320 may be substantially the same as or similar to the width W11 of the partition pattern 200 at the top surface.

The second top surface 320a of the second barrier pattern 320 may correspond to the top surface of the barrier pattern 300. The width of the second top surface 320a of the second barrier pattern 320 may be substantially equal to the width of the second bottom surface of the second barrier pattern 320. For example, the width of the second top surface 320a of the second barrier pattern 320 may be about 72nm to about 88 nm.

When the second barrier patterns 320 have irregular widths, the second barrier patterns 320 may have reduced structural stability or may reflect incident light outward. According to an exemplary embodiment of the inventive concept, the width W2 of the second barrier pattern 320 may be constant along the vertical level. For example, the width of the second top surface 320a of the second barrier pattern 320 may be substantially equal to the width of the second barrier pattern 320 at the second bottom surface. The maximum width and the minimum width of the second barrier patterns 320 may each fall within a range of about 72nm to about 88 nm. The maximum width of the second barrier pattern 320 may be about 100% to about 102% of the minimum width of the second barrier pattern 320. Accordingly, the structural stability of the second barrier patterns 320 may be improved, and an increased amount of light may be incident on the pixel area PX of the first substrate 100.

The height H2 of the second barrier pattern 320 may be greater than the height H1 of the first barrier pattern 310.

The second barrier patterns 320 may include a material having a low refractive index. The refractive index of the second barrier pattern 320 may be smaller than that of the first substrate 100. For example, the refractive index of the second barrier pattern 320 may be equal to or less than about 1.3. As shown in fig. 3C, the second barrier pattern 320 may include a polymer structure 321 and nanoparticles 323 in the polymer structure 321. The nanoparticles 323 may be distributed in the polymer structure 321. For example, the nanoparticles 323 may be spaced apart from one another. For example, the nanoparticles 323 can include silicon dioxide. Light may be reflected from the interface between the polymer structure 321 and the nanoparticles 323. Accordingly, the second barrier patterns 320 may have a low refractive index. The second barrier patterns 320 may effectively prevent crosstalk between the color filters CF and may also effectively prevent optical interference between the pixel areas PX of the first substrate 100. In figures other than fig. 3C, neither the polymer structures 321 nor the nanoparticles 323 are shown for the sake of brevity.

The dielectric layer 400 may be interposed between the partition patterns 200 and the barrier patterns 300 and between the first substrate 100 and the color filter CF. The dielectric layer 400 may include a first dielectric layer 410, a second dielectric layer 420, a third dielectric layer 430, a fourth dielectric layer 440, and a fifth dielectric layer 450 stacked on the first surface 100a of the first substrate 100. For example, the first dielectric layer 410 may contact the first surface 100a of the first substrate 100 and the top surface of the partition pattern 200, and may overlap the pixel region PX of the first substrate 100. A second dielectric layer 420 may be disposed on the first dielectric layer 410. For example, the second dielectric layer 420 may be disposed on the top surface of the first dielectric layer 410. The first dielectric layer 410 and the second dielectric layer 420 may be fixed charge layers. For example, each fixed charge layer may be formed of a metal oxide layer or a metal fluoride layer. The metal oxide layer may include oxygen in an amount less than a stoichiometric ratio, and the metal fluoride layer may include fluorine in an amount less than the stoichiometric ratio. For example, the first dielectric layer 410 may be formed of one of a metal oxide and a metal fluoride, each of which includes at least one metal of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and/or lanthanoid. The second dielectric layer 420 may include one of the metal oxides and metal fluorides discussed in the example of the first dielectric layer 410. In addition, the second dielectric layer 420 may include a material different from that of the first dielectric layer 410. For example, the first dielectric layer 410 may include aluminum oxide and the second dielectric layer 420 may include hafnium oxide. Each of the first dielectric layer 410 and the second dielectric layer 420 may have negative fixed charges and may generate hole accumulation. The first and second

dielectric layers

410 and 420 may effectively reduce white spots and dark currents of the first substrate 100. The thickness of the second dielectric layer 420 may be greater than the thickness of the first dielectric layer 410.

A third dielectric layer 430 may be disposed on the second dielectric layer 420. The third dielectric layer 430 may comprise a first silicon-containing material. For example, the first silicon-containing material may comprise Tetraethylorthosilicate (TEOS) or silicon oxide. The third dielectric layer 430 may exhibit excellent filling characteristics. For example, the third dielectric layer 430 may be formed by plasma enhanced chemical vapor deposition, but the inventive concept is not limited thereto. For example, the thickness of the third dielectric layer 430 may be greater than the thickness of the first dielectric layer 410 and the thickness of the second dielectric layer 420.

A fourth dielectric layer 440 may be disposed on the third dielectric layer 430. The fourth dielectric layer 440 may include a material different from that of the third dielectric layer 430. For example, the fourth dielectric layer 440 may include a second silicon-containing material, which may be different from the first silicon-containing material of the third dielectric layer 430. For example, fourth dielectric layer 440 may comprise silicon nitride. The thickness of the fourth dielectric layer 440 may be greater than the thickness of the third dielectric layer 430.

The fifth dielectric layer 450 may be interposed between the fourth dielectric layer 440 and the first barrier patterns 310 and between the fourth dielectric layer 440 and the color filters CF. For example, the fifth dielectric layer 450 may physically contact the first bottom surface 310b of the first barrier pattern 310. The fifth dielectric layer 450 may be an adhesive layer or a capping layer. The fifth dielectric layer 450 may include a metal oxide or a high-k dielectric material. The fifth dielectric layer 450 may include the same material as the second dielectric layer 420. For example, fourth dielectric layer 440 may comprise hafnium oxide. The thickness of the fifth dielectric layer 450 may be greater than the thickness of each of the first and second

dielectric layers

410 and 420 and less than the thickness of each of the third and fourth

dielectric layers

430 and 440. The thickness of the dielectric layer 400 may mean the sum of the thicknesses of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430, the fourth dielectric layer 440, and the fifth dielectric layer 450.

The number of layers in the dielectric layer 400 may be variously changed. For example, at least one of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430, the fourth dielectric layer 440, and the fifth dielectric layer 450 may be omitted.

The protective layer 470 may cover the dielectric layer 400. For example, the protective layer 470 may cover the top surface of the dielectric layer 400, and may also cover the sidewalls and the top surface of the barrier pattern 300. For example, the protective layer 470 may conformally cover the first sidewalls 310c of the first barrier patterns 310, the second sidewalls of the second barrier patterns 320, and the second top surfaces 320a of the second barrier patterns 320. For example, a thickness of the protective layer 470 on the first sidewalls 310c of the first barrier patterns 310 may be substantially the same as a thickness of the protective layer 470 on the second top surfaces 320a of the second barrier patterns 320. The protective layer 470 may physically contact a portion of the first top surface 310a of the first barrier pattern 310. For example, the protective layer 470 may cover an edge portion of the first top surface 310a of the first barrier pattern 310. The thickness of the protective layer 470 may be less than the thickness of the dielectric layer 400. The protective layer 470 may include a high-k dielectric material and may have dielectric properties. For example, the protective layer 470 may include aluminum oxide or hafnium oxide. For example, the protective layer 470 may include aluminum oxide, but the inventive concept is not limited thereto. The protective layer 470 may protect the photoelectric conversion region PD of the first substrate 100 from an external environment such as moisture.

The color filters CF may be laterally spaced apart from each other on the overcoat layer 470. The sidewalls of the barrier pattern 300 may include first and second sidewalls opposite to each other. The first and second color filters CF1 and CF2 may be disposed on the first and second sidewalls of the barrier pattern 300, respectively. The color filter CF may not extend onto the second top surfaces 320a of the second barrier patterns 320.

Still referring to fig. 3B and 3C, each color filter CF may include a top surface CFa having an upwardly protruding convex shape. For example, the top surface CFa of each color filter CF may have a center portion and an edge portion. The central portion of the top surface CFa of each color filter CF may be located at a level higher than the level of the edge portion of the top surface CFa of the respective color filter CF. However, the shape of the color filter CF is not limited thereto. In this description, the term "horizontal" may mean vertical horizontal. The level difference between the two planes may be measured in a third direction D3.

The microlens layer 500 may be disposed on the first surface 100a of the first substrate 100. For example, the microlens layer 500 may be disposed on the color filters CF and the barrier pattern 300. The protective layer 470 may be interposed between the microlens layer 500 and the second top surface 320a of the second barrier pattern 320.

Microlens layer 500 can include a planarized portion 520 and a lens portion 510. The lens portion 510 may be disposed at a position corresponding to the position of the photoelectric conversion region PD of the first substrate 100. For example, the lens portion 510 may be disposed on and correspond to the color filter CF. The lens portions 510 may constitute an array along the first direction D1 and the second direction D2 when viewed in a plan view. Each lens portion 510 may protrude away from the first surface 100a of the first substrate 100. Each lens portion 510 may have a hemispherical cross-section. The lens portion 510 may collect incident light.

The planarization part 520 of the microlens layer 500 may be interposed between the color filter CF and the lens part 510 and between the barrier pattern 300 and the lens part 510. The planarizing portion 520 may be integrally formed with the lens portion 510 and may be connected to the lens portion 510 without an interface between the planarizing portion 520 and the lens portion 510. The planarization portion 520 may include the same material as the lens portion 510. In addition, the planarization part 520 may be omitted from the microlens layer 500, and the lens parts 510 of the microlens layer 500 may not be connected to each other.

The microlens layer 500 can be transparent to allow light to pass therethrough. The microlens layer 500 may include an organic material such as a polymer. For example, the microlens layer 500 may include a photoresist material or a thermosetting resin.

The image sensor may also include a lens coating 530. The lens coating 530 may be transparent. The lens coating 530 may conformally cover the microlens layer 500. The lens coating 530 may protect the microlens layer 500.

As shown in fig. 3B, the first substrate 100 may include an impurity region 111. In the first substrate 100, the impurity regions 111 may be disposed on the corresponding pixel regions PX. The impurity region 111 may be disposed adjacent to the second surface 100b of the first substrate 100. The bottom surface of the impurity region 111 may be spaced apart from the photoelectric conversion region PD. The impurity region 111 may be a region doped with a second conductive type impurity (e.g., an n-type impurity). The impurity region 111 may be an active portion. The active portion may be an area for operation of the transistor and may include source/drain regions of the transistor and the floating diffusion region FD discussed with reference to fig. 1. The transistors may include the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, or the selection transistor Ax discussed with reference to fig. 1.

The device isolation pattern 240 may be disposed in the first substrate 100. The device isolation pattern 240 may provide an active portion. For example, on each of the pixel regions PX, the device isolation pattern 240 may define the impurity regions 111, and may separate the impurity regions 111 from each other. For example, in the first substrate 100, the device isolation pattern 240 may be disposed on one side of one of the impurity regions 111. The device isolation pattern 240 may be disposed in a second trench, which may be recessed from the second surface 100b of the first substrate 100. For example, the device isolation pattern 240 may be a Shallow Trench Isolation (STI) layer. For example, the height of the device isolation pattern 240 may be less than the height of the separation pattern 200. A portion of the device isolation pattern 240 may be connected to a sidewall of the first partition pattern 210. For example, the device isolation pattern 240 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The gate pattern 700 may be disposed on the second surface 100b of the first substrate 100. The gate pattern 700 may be used as a gate electrode of one of the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax discussed above with reference to fig. 1. For example, the gate pattern 700 may include one of a transfer gate TG, a source follower gate SG, a reset gate RG, and a select gate AG. For simplicity, fig. 3B depicts a single gate pattern 700 disposed on each pixel area PX, but a plurality of gate patterns 700 may be disposed on each pixel area PX. For simplicity of description, the single gate pattern 700 will be discussed below.

The gate pattern 700 may have a buried gate structure. For example, the gate pattern 700 may include a first portion 710 and a second portion 720. The first portion 710 of the gate pattern 700 may be disposed on the second surface 100b of the first substrate 100. The second portion 720 of the gate pattern 700 may protrude into the first substrate 100. The second portion 720 of the gate pattern 700 may be connected to the first portion 710 of the gate pattern 700. However, the inventive concept is not limited thereto. For example, the gate pattern 700 may have a planar gate structure. In this case, the gate pattern 700 may not include the second portion 720. For example, the gate pattern 700 may include a metal, a metal silicide, a polysilicon, or any combination thereof. In this case, the polysilicon may comprise doped polysilicon.

The gate dielectric pattern 740 may be interposed between the gate pattern 700 and the first substrate 100. For example, the gate dielectric pattern 740 may include one or more of a silicon-based dielectric material (e.g., silicon oxide, silicon nitride, and/or silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and/or aluminum oxide).

The first wiring layer 800 may be disposed on the second surface 100b of the first substrate 100. The first wiring layer 800 may include a first lower dielectric layer 810, a second lower dielectric layer 820, and a first conductive structure 830. The first lower dielectric layer 810 may cover the gate pattern 700 and the second surface 100b of the first substrate 100. A second lower dielectric layer 820 may be stacked on the first lower dielectric layer 810. The first lower dielectric layer 810 and the second lower dielectric layer 820 may include a silicon-based dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The first conductive structure 830 may be disposed in the first lower dielectric layer 810 and the second lower dielectric layer 820. For example, the first conductive structures 830 may each include a contact plug portion, a line portion, and a feedthrough portion. For example, a contact plug portion may be disposed in the first lower dielectric layer 810 and may be electrically connected to one of the gate pattern 700 or the impurity region 111. For example, a line portion of the first conductive structure 830 may be interposed between two adjacent lower

dielectric layers

810 and 820. For example, the line portion may be connected to the contact plug portion. For example, the feedthrough portion of the first conductive structure 830 may pass through at least one of the second lower dielectric layers 820 and may be connected to the line portion. The first conductive structure 830 may receive a photoelectric signal output from the photoelectric conversion region PD.

Barrier patterns according to exemplary embodiments of the inventive concept will be discussed below.

Fig. 4A to 4E illustrate cross-sectional views of a portion C of fig. 3B, which illustrate a pixel array region of an image sensor according to an exemplary embodiment of the inventive concept. Reference will also be made to fig. 3A and 3B.

Referring to fig. 4A to 4E, the image sensor may include a first substrate 100, a partition pattern 200, a dielectric layer 400, a barrier pattern 300, an overcoat layer 470, a color filter CF, and a microlens layer 500. The barrier patterns 300 may include a first barrier pattern 310 and a second barrier pattern 320. The first barrier patterns 310 and the second barrier patterns 320 may be substantially the same as those discussed in fig. 3A to 3C. For example, the width W1 of the first barrier pattern 310 at the first bottom surface 310b and the width W2 of the second barrier pattern 320 may satisfy the conditions discussed in fig. 3A to 3C. In addition, the shape of the barrier pattern 300 may be variously changed.

As shown in fig. 4A, the first barrier pattern 310 may have a polygonal shape. For example, the first barrier pattern 310 may have an inverse trapezoidal shape. The width W1 of the first barrier pattern 310 at the first bottom surface 310b may be the minimum width of the first barrier pattern 310, and the width W3 of the first barrier pattern 310 at the first top surface 310a may be the maximum width of the first barrier pattern 310. The first barrier patterns 310 may have a width gradually decreasing as approaching from the first top surface 310a to the first bottom surface 310 b.

As shown in fig. 4B, the first barrier pattern 310 may include a lower portion and an upper portion. For example, the lower portion of the first barrier pattern 310 may have a rectangular cross-section. The first bottom surface 310b of the first barrier pattern 310 may be a bottom surface of a lower portion of the first barrier pattern 310. For example, the lower portion of the first barrier pattern 310 may have a substantially uniform width. For example, the upper portion of the first barrier pattern 310 may have an inverted trapezoidal shape. The upper portion of the first barrier pattern 310 may have a width gradually increasing as approaching the first top surface 310a of the first barrier pattern 310. The first top surface 310a of the first barrier pattern 310 may correspond to a top surface of an upper portion of the first barrier pattern 310. The upper and lower portions of the first barrier pattern 310 may include the same material as each other and may be connected to each other without an interface therebetween.

As shown in fig. 4C, the width W3' of the first top surface 310a of the first barrier pattern 310 may be substantially the same as the width W2 of the second barrier pattern 320. For example, the width W3' of the first barrier pattern 310 at the first top surface 310a may be in the range of about 72nm to about 88 nm. In an embodiment of the inventive concept, a width W3' of the first barrier pattern 310 at the first top surface 310a may be less than a width W2 of the second barrier pattern 320. The first top surface 310a of the first barrier pattern 310 may be covered by the second barrier pattern 320.

Referring to fig. 4D, a width W1 of the first barrier pattern 310 at the first bottom surface 310b may be substantially the same as a width W11 of the partition pattern 200 at the top surface.

As shown in fig. 4E, the width W1 of the first barrier pattern 310 at the first bottom surface 310b may be greater than the width W11 of the partition pattern 200 at the top surface. Accordingly, a portion of the first bottom surface 310b of the first barrier pattern 310 may vertically overlap the first surface 100a of the first substrate 100.

In the embodiment of fig. 4A to 4E, the first substrate 100, the partition pattern 200, the dielectric layer 400, the barrier pattern 300, the protective layer 470, the color filter CF, and the microlens layer 500 may be substantially the same as those discussed in the example of fig. 3A to 3C. The first substrate 100 may further include the device isolation pattern 240 and the impurity region 111 discussed in the example of fig. 3A to 3C, and the image sensor may further include the first wiring layer 800, the gate pattern 700, and the gate dielectric pattern 740 discussed in the example of fig. 3A to 3C.

Fig. 5 illustrates an enlarged cross-sectional view of a portion B of fig. 2B taken along a line II-II' of fig. 3A, showing a pixel array region of an image sensor according to an embodiment of the inventive concept.

Referring to fig. 5, the image sensor may include a first substrate 100, a partition pattern 200', a dielectric layer 400, a barrier pattern 300, an overcoat layer 470, a color filter CF, and a microlens layer 500.

The separation pattern 200' may be disposed in the first substrate 100. The partition pattern 200 ' may be disposed in the first trench 201 ', and the first trench 201 ' may pass through the first surface 100a of the first substrate 100. The first trench 201' may have a bottom surface disposed in the first substrate 100. The partition pattern 200' may have a bottom surface spaced apart from the second surface 100b of the first substrate 100. For example, the top surface of the partition pattern 200' may be located at substantially the same level as the first surface 100a of the first substrate 100; however, the inventive concept is not limited thereto. The width W11 of the top surface of the partition pattern 200 'may be greater than the width W12 of the partition pattern 200' at the bottom surface. For example, the width of the separation pattern 200' may be gradually decreased toward the second surface 100b of the first substrate 100. The partition pattern 200' may include the first partition pattern 210, but may not include the second partition pattern 220 discussed in fig. 3A and 3B.

The separation region 120 may be disposed in the first substrate 100. The separation region 120 may be disposed between the bottom surface of the separation pattern 200' and the second surface 100b of the first substrate 100. The separation region 120 may include a group III element. For example, the separation region 120 may be a region doped with impurities having a first conductivity type (e.g., p-type). The separation region 120 and the separation pattern 200' may provide the pixel region PX. In exemplary embodiments of the inventive concept, the separation pattern 200' may also pass through the second surface 100b of the first substrate 100.

According to exemplary embodiments of the inventive concept, the examples of fig. 3A to 3C, 4A, 4B, 4C, 4D, 4E, and 5 may be combined with each other. For example, as discussed in the example of fig. 3C, the first barrier pattern 310 may have an hourglass shape, and as discussed in the example of fig. 4E, the width W1 of the first barrier pattern 310 at the first bottom surface 310b may be greater than the width W11 of the partition pattern 200 at the top surface.

The circuit chip 20 of the image sensor and the optical black area OB and the PAD area PAD of the first substrate 100 will be described below.

Referring back to fig. 2A and 2B, the optical black region OB of the first substrate 100 may be interposed between the pixel array region APS and the PAD region PAD. The optical black region OB may include a first reference pixel region RPX1 and a second reference pixel region RPX 2. The first reference pixel region RPX1 may be disposed between the second reference pixel region RPX2 and the pixel array region APS. On the optical black area OB, the photoelectric conversion area PD may be disposed in the first reference pixel area RPX 1. The photoelectric conversion region PD on the first reference pixel region RPX1 may have the same planar area and volume as each of the photoelectric conversion regions PD on the pixel region PX. The photoelectric conversion region PD may not be disposed on the second reference pixel region RPX 2; however, the inventive concept is not limited thereto. The impurity region 111, the gate pattern 700, and the device isolation pattern 240 may be disposed on each of the first and second reference pixel regions RPX1 and RPX 2. The impurity region 111, the gate pattern 700, and the device isolation pattern 240 may be the same as those discussed in fig. 3B.

The dielectric layer 400 may extend onto the optical black region OB and the PAD region PAD of the first substrate 100 and may cover the first surface 100a of the first substrate 100.

The light shielding layer 950 may be disposed on the first surface 100a on the optical black region OB of the first substrate 100. The light shielding layer 950 may be disposed on the top surface of the dielectric layer 400. The light-shielding layer 950 may not allow light to enter the photoelectric conversion region PD on the optical black region OB. The pixels of the first reference pixel region RPX1 and the second reference pixel region RPX2 on the optical black region OB may output noise signals without outputting photoelectric signals. The noise signal may be generated from electrons generated by heat or dark current. The light shielding layer 950 may not cover the pixel array area APS, and thus, light may be incident on the photoelectric conversion area PD on the pixel array area APS. The noise signal may be removed from the photoelectric signal output from the pixel area PX. The light shielding layer 950 may include a metal such as tungsten, copper, aluminum, or any alloy thereof.

On the optical black region OB of the first substrate 100, the first conductive pattern 911 may be disposed between the dielectric layer 400 and the light shielding layer 950. For example, the first conductive pattern 911 may be used as a barrier layer or an adhesive layer. The first conductive pattern 911 may include one or more of metal and/or metal nitride. For example, the first conductive pattern 911 may include one or more of titanium and/or titanium nitride. The first conductive pattern 911 may not extend onto the pixel array region APS of the first substrate 100.

On the optical black region OB of the first substrate 100, a contact plug 960 may be disposed on the first surface 100a of the first substrate 100. The contact plug 960 may be disposed in the dielectric layer 400 and on the top surface of the outermost portion of the partition pattern 200. For example, the outermost portion of the separation pattern 200 may be closest to the PAD area PAD. A contact trench may be formed on the first surface 100a of the first substrate 100, and a contact plug 960 may be disposed in the contact trench. For example, the contact plug 960 may include a material different from that of the light shielding layer 950. For example, the contact plug 960 may include a metal material such as aluminum. The first conductive pattern 911 may extend into a space between the contact plug 960 and the dielectric layer 400 and a space between the contact plug 960 and the partition pattern 200. The contact plug 960 may be electrically connected to the second partition pattern 220 through the first conductive pattern 911. Accordingly, a negative bias may be applied to the second partition pattern 220.

On the optical black region OB of the first substrate 100, a protective dielectric layer 471 may be disposed on the light shielding layer 950 and the contact plug 960. For example, the protective dielectric layer 471 may be disposed on the top surface of the light shielding layer 950 and the top surface of the contact plug 960. The protective dielectric layer 471 may include the same material as that of the protective layer 470 and may be connected to the protective layer 470. For example, the protective dielectric layer 471 may be integrally formed with the protective layer 470. In addition, the protective dielectric layer 471 may be formed through a process separate from a process for forming the protective layer 470, and the protective dielectric layer 471 may be spaced apart from the protective layer 470. The protective dielectric layer 471 may include a high-k dielectric material (e.g., aluminum oxide and/or hafnium oxide).

The filter layer 550 may be disposed on the first surface 100a on the optical black area OB. The filter layer 550 may cover the protective dielectric layer 471. For example, the filter layer 550 may cover a top surface of the protective dielectric layer 471. The filter layer 550 may block light having a wavelength different from that of light generated from the color filter CF. For example, filter layer 550 may block infrared rays. The filter layer 570 may include a blue color filter, but the inventive concept is not limited thereto.

The optical black region OB may include an organic layer 501 disposed on the filter layer 550. For example, organic layer 501 may be disposed on the top surface of filter layer 550. The organic layer 501 may be transparent. The organic layer 501 may have a top surface opposite to the first substrate 100 and substantially flat. For example, the organic layer 501 may include a polymer. The organic layer 501 may have dielectric properties. In exemplary embodiments of the inventive concept, the organic layer 501 may be connected to the microlens layer 500. For example, the organic layer 501 may include the same material as that of the microlens layer 500.

The coating 531 may be disposed on the organic layer 501. For example, the coating 531 may conformally cover the top surface of the organic layer 501. The coating 531 may include a dielectric material and may be transparent. For example, the coating 531 may comprise the same material as the lens coating 530.

The first wiring layer 800 may cover the second surface 100b of the first substrate 100 and may be disposed on the pixel array region APS, the optical black region OB, and the PAD region PAD of the first substrate 100.

The image sensor may further include a circuit chip 20. The circuit chip 20 may be stacked on the sensor chip 10. The circuit chip 20 may include a second wiring layer 1800 and a second substrate 1000. The second wiring layer 1800 may be interposed between the first wiring layer 800 and the second substrate 1000. The integrated circuit 1700 may be disposed on a top surface of the second substrate 1000, or may be disposed inside the second substrate 1000. Integrated circuit 1700 may include logic circuits, memory circuits, or any combination thereof. Integrated circuit 1700 may include transistors, for example. The second wiring layer 1800 may include a third lower dielectric layer 1820 and a second conductive structure 1830. The second conductive structures 1830 may be disposed between the third lower dielectric layers 1820 or may be disposed in the third lower dielectric layers 1820. Second conductive structure 1830 may be electrically connected to integrated circuit 1700. The second wiring layer 1800 may further include a punch through pattern, and in the third lower dielectric layer 1820, the punch through pattern may pass through the third lower dielectric layer 1820 to be coupled to the second conductive structure 1830. For simplicity of description, a single second conductive structure 1830 will be discussed below.

The parts on the PAD area PAD of the first substrate 100 will be explained below.

The PAD terminal 900 may be disposed on a PAD area PAD of the first substrate 100. The pad terminal 900 may be disposed on the first surface 100a of the first substrate 100. For example, the pad terminal 900 may be buried in the first substrate 100. For example, a PAD groove 990 may be formed on the first surface 100a on the PAD area PAD of the first substrate 100, and the PAD terminal 900 may be disposed in the PAD groove 990. The pad terminal 900 may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof. When the image sensor is mounted, the bonding wire may be formed on the pad terminal 900 and coupled to the pad terminal 900. The pad terminal 900 may be electrically connected to the outside through a bonding wire.

The first via 901 may be disposed on a first side of the pad terminal 900. The first via 901 may be disposed between the pad terminal 900 and the contact plug 960. The first via 901 may pass through the dielectric layer 400, the first substrate 100, and the first wiring layer 800. The first via 901 may also pass through at least a portion of the second wiring layer 1800. For example, the first via 901 may have a first bottom surface and a second bottom surface. The first bottom surface of the first via 901 may expose the first conductive structure 830. The second bottom surface of the first through hole 901 may be located at a lower level than the first bottom surface of the first through hole 901. A second bottom surface of the first via 901 may expose the second conductive structure 1830. For example, a portion of the first via 901 may pass through the dielectric layer 400, the first substrate 100, and the second lower dielectric layer 820 of the first wiring layer 800 to expose the first conductive structure 830, and another portion of the first via 901 may pass through the dielectric layer 400, the first substrate 100, the first wiring layer 800, and the third lower dielectric layer 1820 to expose the second conductive structure 1830.

The first conductive pattern 911 may extend onto the PAD area PAD of the first substrate 100. On the PAD region PAD of the first substrate 100, the first conductive pattern 911 may be disposed on the first surface 100a of the first substrate 100 and may cover an inner sidewall of the first via 901. As shown in fig. 2A, the pad terminal 900 may be provided in plurality. For example, the plurality of pad terminals 900 may include a first pad terminal and a second pad terminal. The first conductive pattern 911 may be disposed on a bottom surface and a sidewall of one (e.g., a first pad terminal) of the plurality of pad terminals 900, and may be electrically connected to the one pad terminal 900 (e.g., the first pad terminal).

The first conductive pattern 911 may cover the sidewall and the first bottom surface of the first via 901. The first conductive pattern 911 may contact the top surface of the first conductive structure 830. Accordingly, the first conductive structure 830 may be electrically connected to the one pad terminal 900 (e.g., a first pad terminal) through the first conductive pattern 911. When the image sensor operates, a voltage may be applied to the first conductive structure 830 through the one pad terminal 900 and the first conductive pattern 911. A voltage may also be applied to the second partition pattern 220 through the first conductive pattern 911 and the contact plug 960. The voltage may be a negative bias.

The first conductive pattern 911 may cover a second bottom surface of the first via 901 and may be coupled to a top surface of the second conductive structure 1830. The integrated circuit 1700 in the circuit chip 20 may be electrically connected to the one pad terminal 900 (e.g., the first pad terminal) through the second conductive structure 1830 and the first conductive pattern 911. The first conductive pattern 911 and the first via 901 may each be provided in plurality. In this case, one of the first conductive patterns 911 may be coupled to the first conductive structure 830 or the second conductive structure 1830 without being coupled to the contact plug 960. The first conductive pattern 911 may serve as an electrical path between the transistors of the sensor chip 10 and the integrated circuit 1700 of the circuit chip 20. The first conductive pattern 911 may include a metal such as copper, tungsten, aluminum, titanium, tantalum, or any alloy thereof.

The first buried pattern 921 may be disposed in the first via hole 901, thereby filling the first via hole 901. The first buried pattern 921 may not extend onto the first surface 100a of the first substrate 100. The first buried pattern 921 may include a material having a low refractive index and may have a dielectric property. The first buried pattern 921 may include the same material as that of the first barrier pattern 310. The first buried pattern 921 may include the polymer structures 321 and the nanoparticles 323 as discussed in the example of the first barrier pattern 310 shown in fig. 3C. The top surface of the first buried pattern 921 may be recessed. For example, a center portion of the top surface of the first buried pattern 921 may be located at a lower level than an edge portion of the top surface of the first buried pattern 921. For example, the top surface of the first buried pattern 921 may be recessed.

The first capping pattern 931 may be disposed on a top surface of the first buried pattern 921. For example, the first capping pattern 931 may have a shape conforming to the top surface of the first buried pattern 921 to fill the recess portion of the first buried pattern 921. For example, the first capping pattern 931 may have a convex shape. The first capping pattern 931 may have a substantially flat top surface. The first capping pattern 931 may include a dielectric polymer such as a photoresist material.

The second via 902 may be disposed on a second side of the pad terminal 900. The second side of the pad terminal 900 may be different from the first side of the pad terminal 900. The second via 902 may pass through the dielectric layer 400, the first substrate 100, and the first wiring layer 800. The second via 902 may pass through a portion of the second wiring layer 1800 and may expose the second conductive structure 1830.

On the PAD region PAD of the first substrate 100, a second conductive pattern 912 may be disposed on the first surface 100a of the first substrate 100. As shown in fig. 2B, the second conductive pattern 912 may be interposed between the first substrate 100 and the other of the pad terminals 900 (e.g., a second pad terminal), and may be electrically connected to the other pad terminal (e.g., a second pad terminal). The second conductive pattern 912 may extend into the second via 902 and may conformally cover sidewalls and a bottom surface of the second via 902. The second conductive pattern 912 may be electrically connected to the second conductive structure 1830. When the image sensor operates, the integrated circuit 1700 of the circuit chip 20 may transmit and receive an electrical signal through the second conductive structure 1830, the second conductive pattern 912, and the other pad terminal (e.g., the second pad terminal).

Second buried pattern 922 may be disposed in second via 902, thereby filling second via 902. The second buried pattern 922 may not extend onto the first surface 100a of the first substrate 100. The second buried pattern 922 may include a material having a low refractive index and may have a dielectric property. For example, the second buried pattern 922 may include the same material as that of the first barrier pattern 310. The top surface of the second buried pattern 922 may be recessed.

A second capping pattern 932 may be disposed on a top surface of the second buried pattern 922. For example, the second capping pattern 932 may have a shape conforming to the top surface of the second embedded pattern 922 to fill the recessed portion of the second embedded pattern 922. The second capping pattern 932 may have a substantially flat top surface. The second capping pattern 932 may include a dielectric polymer such as a photoresist material.

The protective dielectric layer 471 may extend onto the PAD area PAD of the first substrate 100. A protective dielectric layer 471 may be disposed on the top surface of the dielectric layer 400 and may extend into the first and second vias 901, 902. In the first via 901, a protective dielectric layer 471 may be interposed between the first conductive pattern 911 and the first buried pattern 921. In the second via 902, a protective dielectric layer 471 may be interposed between the second conductive pattern 912 and the second buried pattern 922. The protective dielectric layer 471 may expose the pad terminal 900.

The organic layer 501 and the overcoat 531 may also be disposed on the PAD area PAD of the first substrate 100. On the first surface 100a of the first substrate 100, the organic layer 501 may cover a portion of the protective dielectric layer 471 and the first capping pattern 931. The organic layer 501 may expose the top surface of the pad terminal 900.

Fig. 6 illustrates a sectional view taken along line I-I' of fig. 2A, which illustrates an image sensor according to an exemplary embodiment of the inventive concept. Fig. 2A will also be referred to below, and a repetitive description will be omitted below.

Referring to fig. 6, the image sensor may include a sensor chip 10 and a circuit chip 20. The sensor chip 10 and the circuit chip 20 may be substantially the same as those discussed above with reference to fig. 2A and 2B. For example, the sensor chip 10 may include a first substrate 100, a first wiring layer 800, a partition pattern 200, a dielectric layer 400, a barrier pattern 300, a color filter CF, an overcoat layer 470, a microlens layer 500, a pad terminal 900, a first conductive pattern 911, and a second conductive pattern 912. The circuit chip 20 may include a second substrate 1000 and a second wiring layer 1800.

In addition, the sensor chip 10 may further include first connection pads 850. The first connection pads 850 may be exposed on the bottom surface of the sensor chip 10. For example, the first connection pads 850 may be disposed in the second lower dielectric layer 820 of the first wiring layer 800. The first connection pad 850 may be electrically connected to the first conductive structure 830. The first connection pad 850 may include a conductive material such as a metal. For example, the first connection pad 850 may include copper. For another example, the first connection pad 850 may include aluminum, tungsten, titanium, or any alloy thereof.

The circuit chip 20 may include a second connection pad 1850. The second connection pad 1850 may be exposed on the top surface of the circuit chip 20. The second connection pad 1850 may be disposed in the third lower dielectric layer 1820. The second connection pad 1850 may be electrically connected to the integrated circuit 1700. The second connection pad 1850 may include a conductive material such as a metal. For example, the second connection pad 1850 may include copper. For another example, the second connection pad 1850 may include aluminum, tungsten, titanium, or any alloy thereof.

For example, the circuit chip 20 and the sensor chip 10 may be connected to each other by direct bonding. For example, the first connection pad 850 and the second connection pad 1850 may be vertically aligned and contact each other. Accordingly, the second connection pad 1850 may be directly bonded to the first connection pad 850. Electrical signals may be transmitted from the integrated circuit 1700 of the circuit chip 20 to the pad terminals 900 or the transistors of the sensor chip 10 through the second conductive structures 1830, the second connection pads 1850, the first connection pads 850, and the first conductive structures 830. For example, the second lower dielectric layer 820 may be directly bonded to the third lower dielectric layer 1820. In this case, a chemical bond may be formed between the second lower dielectric layer 820 and the third lower dielectric layer 1820.

The first through hole 901 may include a first through hole portion 91, a second through hole portion 92, and a third through hole portion 93. The first via part 91 may pass through the dielectric layer 400, the first substrate 100, and the first wiring layer 800, and may have a first bottom surface. The second via portion 92 may pass through the dielectric layer 400, the first substrate 100, and the first wiring layer 800, and may extend into an upper portion of the second wiring layer 1800. The second through-hole portion 92 may have a second bottom surface, which may expose a top surface of the second conductive structure 1830. For example, the second bottom surface of the second through-hole portion 92 may be lower than the first bottom surface of the first through-hole portion 91. The second through-hole portion 92 may have a sidewall spaced apart from a sidewall of the first through-hole portion 91. The third through hole portion 93 may be disposed between an upper portion of the first through hole portion 91 and an upper portion of the second through hole portion 92 and connected to the upper portion of the first through hole portion 91 and the upper portion of the second through hole portion 92. The first via 901 may have a first conductive pattern 911, a protective dielectric layer 471, and a first buried pattern 921 disposed therein. The first conductive pattern 911 may cover inner sidewalls of the first through hole portion 91, the second through hole portion 92, and the third through hole portion 93.

According to the inventive concept, the barrier patterns may include a first barrier pattern and a second barrier pattern. The width of the first barrier pattern at the bottom surface may be smaller than the width of the first barrier pattern at the top surface. Therefore, an increased amount of light may be incident on the photoelectric conversion region of the substrate. The image quality of the image sensor can be improved.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept.

Claims

1. An image sensor, comprising:

a substrate having a first surface and a second surface opposite to each other;

a plurality of color filters on the substrate;

a barrier pattern between adjacent color filters of the plurality of color filters; and

an overcoat layer between the substrate and the plurality of color filters, wherein the overcoat layer covers the barrier patterns,

wherein the barrier pattern includes:

a first barrier pattern having a first bottom surface and a first top surface opposite to each other; and

a second barrier pattern on a first top surface of the first barrier pattern,

wherein a width of the first barrier patterns at the first bottom surface is smaller than a width of the second barrier patterns, and

wherein the protective layer covers sidewalls of the first barrier patterns.

2. The image sensor of claim 1, further comprising a dielectric layer between the substrate and the plurality of color filters,

wherein the first barrier pattern is on the dielectric layer.

3. The image sensor as claimed in claim 1, wherein a maximum width of the second barrier pattern is 100 to 102% of a minimum width of the second barrier pattern.

4. The image sensor of claim 1, wherein a width of the first barrier pattern at the first top surface is greater than a width of the second barrier pattern.

5. The image sensor of claim 1, wherein a width of the first barrier pattern at the first bottom surface is smaller than a width of the first barrier pattern at the first top surface.

6. The image sensor of claim 1, wherein the first barrier pattern includes a lower portion, an upper portion, and a middle portion between the lower portion and the upper portion, and

wherein a width of the first barrier pattern at the middle portion is smaller than a width of the first barrier pattern at the first bottom surface.

7. The image sensor of claim 1, wherein the protective layer covers a portion of the first top surface of the first barrier pattern.

8. The image sensor of claim 1, further comprising a microlens layer on the plurality of color filters and the barrier pattern,

wherein the second barrier patterns have a second bottom surface and a second top surface opposite to each other, and

wherein the protective layer is between the microlens layer and the second top surface of the second barrier pattern.

9. The image sensor of claim 1,

each of the plurality of color filters is disposed on a corresponding sidewall of the barrier pattern, and

at least a portion of a top surface of the second barrier pattern is not covered by the plurality of color filters.

10. The image sensor of claim 1, further comprising a pixel separation pattern in the substrate, wherein the pixel separation pattern defines a plurality of pixel regions, and

wherein the barrier pattern overlaps the pixel separating pattern.

11. An image sensor, comprising:

a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a plurality of photoelectric conversion regions;

a separation pattern in the substrate and between the plurality of photoelectric conversion regions;

a plurality of color filters on the substrate; and

a barrier pattern on the partition pattern and between adjacent color filters of the plurality of color filters,

wherein the barrier pattern includes:

a first barrier pattern having a bottom surface and a top surface opposite to each other; and

a second barrier pattern on the first barrier pattern,

wherein a width of the first barrier pattern at the bottom surface is smaller than a width of the first barrier pattern at the top surface, and

wherein a maximum width of the second barrier patterns is 100% to 102% of a minimum width of the second barrier patterns.

12. The image sensor of claim 11, wherein the second fence pattern comprises a material different from a material of the first fence pattern.

13. The image sensor of claim 12,

the first barrier pattern includes a metal, and

the second barrier pattern includes a polymer structure and a plurality of nanoparticles in the polymer structure.

14. The image sensor of claim 11, further comprising an overcoat layer between the substrate and the plurality of color filters, wherein the overcoat layer covers the barrier pattern, and

wherein the protective layer covers sidewalls of the first barrier patterns.

15. The image sensor of claim 14, further comprising:

a dielectric layer between the substrate and the plurality of color filters and between the partition pattern and the barrier pattern; and

a microlens layer on the plurality of color filters and the barrier pattern,

wherein the microlens layer covers the protective layer.

16. The image sensor of claim 11, wherein a height of the second fence pattern is greater than a height of the first fence pattern.

17. An image sensor, comprising:

a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a plurality of photoelectric conversion regions therein;

a partition pattern in the substrate and between adjacent ones of the plurality of photoelectric conversion regions;

a plurality of color filters on the substrate;

wherein the barrier pattern includes:

a second barrier pattern on a first top surface of the first barrier pattern,

wherein a width of the first barrier pattern at the first bottom surface is smaller than a width of the first barrier pattern at the first top surface;

a dielectric layer between the substrate and the plurality of color filters and between the barrier patterns and the partition patterns;

an overcoat layer between the dielectric layer and the plurality of color filters, wherein the overcoat layer covers sidewalls of the first barrier patterns, sidewalls of the second barrier patterns, and top surfaces of the second barrier patterns;

a microlens layer on the plurality of color filters and the barrier pattern;

a gate pattern on a second surface of the substrate; and

a wiring layer on the second surface of the substrate, wherein the wiring layer includes a lower dielectric layer and a wiring structure,

wherein the lower dielectric layer covers the gate pattern, and

wherein the wiring structure is in the lower dielectric layer.

18. The image sensor as claimed in claim 17, wherein the second barrier pattern includes a second bottom surface and a second top surface opposite to each other, and

wherein a width of the second barrier pattern at the second top surface is substantially equal to a width of the second barrier pattern at the second bottom surface.

19. The image sensor of claim 17,

a width of the first barrier pattern at the first bottom surface is in a range of 45nm to 55nm, and

the width of the second barrier pattern is in a range of 72nm to 88 nm.

20. The image sensor of claim 17, wherein the dielectric layer comprises:

a first dielectric layer on the substrate and comprising a metal oxide or a metal fluoride;

a second dielectric layer on the first dielectric layer and comprising a metal oxide, wherein the second dielectric layer comprises a material different from a material of the first dielectric layer;

a third dielectric layer on the second dielectric layer and comprising a first silicon-based dielectric material;

a fourth dielectric layer on the third dielectric layer and comprising a second silicon-based dielectric material different from the first silicon-based dielectric material; and

a fifth dielectric layer between the fourth dielectric layer and the first barrier pattern, and including a metal oxide.