JP2013016702A - Solid-state imaging device and camera module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve image quality of a solid-state imaging device.SOLUTION: A solid-state imaging device according to an embodiment comprises: a first region 2 provided in a semiconductor substrate 10 and including a plurality of first photoelectric converters irradiated with light; a second region 3 provided in the semiconductor substrate 10 so as to be adjacent to the first region 2; a plurality of first lenses 9 provided in a position overlapping with the first region 2 in a vertical direction with respect to an acceptance surface and corresponding to the respective first photoelectric converters; and a second lens 7A provided adjacent to a step of an interface part between two regions 2, 3 between the first region 2 and the first lens 9 and corresponding to the first region 2.

Description

  Embodiments described herein relate generally to a solid-state imaging device and a camera module.

  Solid-state imaging devices such as CCD image sensors and CMOS image sensors are used in various applications such as digital still cameras, video cameras, and surveillance cameras.

  In the image sensor, a pixel array having a photoelectric conversion unit and a peripheral circuit for controlling the operation of the pixel array are provided on the same chip.

  For example, a photodiode is used in the photoelectric conversion unit of the image sensor. Light incident on the photodiode is photoelectrically converted to obtain an electrical signal corresponding to the light from the subject.

  Due to the difference in the structure of the area where the pixel array and the peripheral circuit are formed, the amount of incident light corresponding to the subject is changed between the photoelectric conversion unit at the center of the pixel array and the outer peripheral part (peripheral circuit side) of the pixel array. It may be different from the photoelectric conversion unit. This difference in the amount of incident light may cause shading in the formed image.

Japanese Patent Laid-Open No. 06-163866

  A technique for improving the image quality of the formed image is proposed.

  The solid-state imaging device according to the present embodiment is provided in a semiconductor substrate and includes a first region having a plurality of first photoelectric conversion units irradiated with light, the first region provided in the semiconductor substrate, and the first region. A second region adjacent to the first photoelectric conversion unit and a position overlapping the first region in a direction perpendicular to the light receiving surface of the first photoelectric conversion unit, and each of the plurality of regions corresponding to the first photoelectric conversion unit Adjacent to the step of the boundary between the first lens, the first region, and the first lens between the first lens and the first lens, and corresponds to the first region A second lens.

The top view which shows the structure of the solid-state imaging device of embodiment. Sectional drawing which shows the structure of the solid-state imaging device of embodiment. 1 is a cross-sectional view illustrating a structure of a solid-state imaging device according to a first embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional drawing which shows the structure of the solid-state imaging device of 2nd Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 2nd Embodiment. Sectional drawing which shows the structure of the solid-state imaging device of 3rd Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 3rd Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 3rd Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 3rd Embodiment. Sectional drawing which shows the structure of the solid-state imaging device of 4th Embodiment. Sectional drawing which shows the application example of the solid-state imaging device of embodiment. The top view which shows the modification of the solid-state imaging device of embodiment. Sectional drawing which shows the modification of the solid-state imaging device of embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

(1) First embodiment
A solid-state imaging device and a method for manufacturing the same according to the first embodiment will be described with reference to FIGS.

(A) Structure
The structure of the solid-state imaging device according to the first embodiment will be described with reference to FIGS. 1 to 3.

  FIG. 1 is a schematic diagram illustrating a chip layout example of a solid-state imaging device (hereinafter referred to as an image sensor). FIG. 2 is a schematic cross-sectional view schematically showing a cross-sectional structure of the chip of FIG.

  As shown in FIG. 1, in the image sensor of the present embodiment, a pixel array 2 and a region 30 in which a plurality of circuits for controlling the operation of the pixel array 2 are formed are in one semiconductor substrate (chip) 10. Is provided. Hereinafter, a circuit group for controlling the pixel array 2 is referred to as a peripheral circuit, and a region where the peripheral circuit is formed is referred to as a peripheral circuit region 3.

  The image sensor of this embodiment may be a CMOS image sensor or a CCD image sensor.

  The pixel array 2 in the semiconductor substrate 10 includes a plurality of unit cells 20, and each unit cell 20 has a photoelectric conversion unit (pixel). The photoelectric conversion unit acquires light corresponding to the subject and converts the acquired light into an electrical signal.

  For example, the pixel array 2 includes an imaging region where light is incident (also referred to as an effective region) and an ineffective region where light is not incident.

  The photoelectric conversion unit in the imaging region is referred to as an effective pixel. The invalid area has a unit cell having substantially the same structure as the imaging area. The unit cells in the invalid area are shielded from light by a light shielding film (for example, a metal film) so that light from the outside is not incident. For example, the invalid area includes a black reference area and a dummy area. The black reference region is provided in the pixel array 2 in order to form a reference potential (dark voltage or reset voltage) for the photoelectrically converted signal. The black reference area is also called an OB (Optical Black) area. Hereinafter, the photoelectric conversion unit in the black reference region is referred to as a black reference pixel. On the other hand, the unit cell in the dummy area does not have a function as a circuit. A unit cell in the dummy area is called a dummy cell. In some cases, at least one of the dummy area and the black reference area may not be provided in the pixel array 2.

  The unit cell 20 includes at least one photoelectric conversion unit (pixel) PD and a signal scanning circuit unit. The photoelectric conversion unit PD is, for example, a photodiode.

  When the image sensor of this embodiment is a CMOS image sensor, the signal scanning circuit section of the unit cell 20 is formed by, for example, four field effect transistors (for example, n-channel MOS transistors). The four field effect transistors included in the unit cell 20 are referred to as a transfer gate (read transistor), an amplifier transistor, an address transistor, and a reset transistor, respectively.

  Each unit cell 20 may not include an address transistor. The unit cell 20 may have a cell structure (one pixel one cell structure) including one photoelectric conversion unit and one signal scanning circuit unit, or may be shared by a plurality of photoelectric conversion units. You may have a cell structure (for example, 2 pixel 1 cell structure) containing one signal scanning circuit part.

  The peripheral circuit region 3 is provided adjacent to the pixel array 2. An analog circuit or a logic circuit is formed in the peripheral circuit region 3. In the peripheral circuit region 3, a field effect transistor, a resistor element, a capacitor element, and the like are provided. Hereinafter, the constituent elements forming the peripheral circuit are referred to as peripheral elements.

  In the direction perpendicular to the light receiving surface of the pixel array 2 (perpendicular to the surface on which the element is formed), the microlens array 9 is disposed at a position overlapping with the pixel array 2 with the interlayer insulating film interposed therebetween. ing.

  The microlens array 9 includes a plurality of microlenses (first lenses). The microlens array 9 is formed so that one microlens 90 corresponds to one photoelectric conversion unit (pixel, photodiode).

  As shown in FIGS. 1 and 2, in the image sensor of this embodiment, a lens (second lens) is disposed between the microlens array 9 and the pixel array 2 in the direction perpendicular to the light receiving surface of the pixel array 2. Lens) 7A is provided.

  The lens 7A is provided so as to correspond to the pixel array 2, and covers the upper side of the pixel array 2 on the light irradiation surface side.

  The lens 7A has, for example, a circular planar shape. The diameter L1 of the lens 7A is set to a dimension equal to or larger than the maximum dimension (for example, a square diagonal line) L2 of the pixel array 2. For example, when viewed from the direction perpendicular to the light receiving surface of the pixel array 2, the pixel array 2 is inscribed in a circular planar lens 7A. In this case, the entire pixel array 2 is covered with one lens 7A. For example, the lens 7A is formed in an intermediate layer between the microlens array 9 and the pixel array 2 so that one lens 7A corresponds to all the photoelectric conversion units (pixels) in the pixel array 2. . For example, as shown in FIG. 2, the lens 7A is provided, for example, in a groove 92B in the interlayer insulating film 79A.

  The maximum dimension (for example, diameter) of the lens 7A in the horizontal direction with respect to the light receiving surface (element formation surface of the semiconductor substrate) of the pixel array 2 is the maximum dimension of the micro lens 90 in the horizontal direction with respect to the light receiving surface of the pixel array 2. Greater than (eg diameter).

  Hereinafter, the lens 7A provided between the pixel array 2 and the microlens array 9 is referred to as a large lens or an internal lens.

  With reference to FIG. 3, the structure of the image sensor of the first embodiment will be described more specifically. FIG. 3 shows an example of a cross-sectional structure of the image sensor of this embodiment.

A plurality of active areas are provided in the pixel array 2. Each active region is partitioned in the semiconductor substrate 10 by an element isolation region.
A plurality of unit cells 20 are provided in the pixel array 2. The unit cell 20 is provided in each active area. The unit cells 20 adjacent to each other are electrically isolated by the element isolation layer 15 in the element isolation region. The element isolation layer 15 may be, for example, an impurity layer or an insulating film having an STI structure.

  As described above, the unit cell 20 includes at least one photodiode PD as a photoelectric conversion unit (pixel). In the photodiode PD, a charge corresponding to the amount of incident light is generated inside the photodiode, and a potential difference is generated between (inside) the terminals of the photodiode PD. The photodiode PD can store the generated charges.

  The photodiode PD is formed in the semiconductor substrate 10. The photodiode PD includes at least one impurity layer (diffusion layer) 21 formed in the semiconductor substrate 10. For example, when the semiconductor substrate 10 has a P-type conductivity, the impurity layer 21 for forming the photodiode PD has an N-type conductivity. In order to improve the characteristics (eg, sensitivity) of the photodiode PD, the photodiode PD may include a plurality of N-type and P-type impurity layers having different impurity concentrations.

  In FIG. 3, only the photodiode PD is shown in the active region surrounded by the element isolation layer 15 for simplification of illustration, but each unit cell 20 includes the same region. Transistors and floating diffusions (floating diffusion layers) are provided.

  The peripheral circuit region 3 is electrically isolated from the pixel array 2 by an element isolation layer (for example, an insulating layer having an STI structure) 19 in the element isolation region. In the peripheral circuit region 3, a field effect transistor (for example, a MOS transistor) Tr is provided in the well region 12 in the semiconductor substrate 10. Two diffusion layers (impurity layers) 33 are provided in the well region 12. These two diffusion layers 33 function as the source / drain of the transistor Tr. A gate electrode 31 is provided on the surface of the well region (channel region) between the two diffusion layers 33 via the gate insulating film 32.

  Whether the field effect transistor Tr is a P-channel type or an N-channel type depends on the conductivity type of the well region 12 in which the transistor Tr is provided or the conductivity type of the diffusion layer 33 serving as the source / drain.

  For simplification of illustration, only a field effect transistor Tr is illustrated as an element (peripheral element) formed in the peripheral circuit region 3, but a resistor element, a capacitive element, A diode or a bipolar transistor is provided.

An interlayer insulating film 70 in which a plurality of insulating layers are stacked is provided on the semiconductor substrate 10. The interlayer insulating film 70 covers the elements PD and Tr formed in the semiconductor substrate 10. A plurality of metal films 50 and 55 are provided in the interlayer insulating film 70.
The interlayer insulating film 70 and the metal films 50 and 55 are formed by a multilayer wiring technique, and are respectively provided within a predetermined wiring level (height from the substrate surface).

Interlayer insulating film 70 has a laminated structure of a plurality of insulating layers _{70 1,} 70 _2, 70 3, 70 _4. For example, the interlayer insulating film 70 is formed using silicon oxide. The metal film 50 is formed using aluminum (Al) or copper (Cu).

  The metal film 55 above the pixel array 2 is used as a light shielding film for preventing light leakage between adjacent pixels so that light transmitted through the microlens 60 is incident on the pixel 20 corresponding to the microlens. It is done.

  The metal film 50 in the peripheral circuit region 3 is used as wiring for forming a circuit. The metal film 50 as a wiring is connected between different wiring levels by plugs VP and CP. For example, the lowermost wiring 50 immediately above the substrate surface is connected to the impurity layer 33 in the semiconductor substrate 10 via the contact plug CP. The lower layer wiring 50 is connected to the upper layer wiring 50 via the via plug VP.

  The base layers 71 and 72 having a laminated structure are provided on the interlayer insulating film 70. The lower base layer 71 is in contact with the interlayer insulating film 70. The upper base layer 72 is in contact with the interlayer insulating film 70. The lower base layer 71 has a film thickness of, for example, about several tens of nm to 0.2 μm. The base layers 71 and 72 are formed of an insulating layer such as a silicon oxide film, an organic film, a coating film, or a resin.

The color filter layer (pigment layer) 8 is provided on the base layers 71 and 72.
The color filter layer 8 is formed of a plurality of filters, and includes red, blue and green filters. The filters of each color are arranged in the color filter layer 8 so as to have a Bayer arrangement. The color filter layer 8 may include white or yellow filters in addition to red, blue and green filters. Each filter forming the color filter layer 8 is provided above the pixel array 2 so as to have a one-to-one correspondence with the photoelectric conversion unit PD.

  An overcoat layer (also referred to as a planarizing layer) 73 is provided on the color filter layer 8 and the base layers 71 and 72. For example, the overcoat layer 73 is formed using at least one insulating layer of a silicon oxide film, an organic film, a coating film, a resin, or the like. Hereinafter, the base layers 71 and 72 and the overcoat layer 73 may be described as being included in an interlayer insulating film.

  The microlens 9 is provided on the overcoat layer 73. The microlens array 9 is disposed above the pixel array 2 with a plurality of insulating films 70, 71, 72, 73 on the substrate 10 interposed therebetween.

  For example, a pad (not shown) may be provided on the surface side (surface side) on which the interlayer insulating film 70 is provided by a rewiring formation technique. In addition, a pad may be provided on the opposite side (back side) to the surface of the semiconductor substrate 10 on which the interlayer insulating film 70 is provided by a via (through via) penetrating the semiconductor substrate 10. The through via (not shown) is formed by a TSV (Through Substrate Via) technique.

In the present embodiment, the surface (first surface) of the semiconductor substrate 10 provided with the interlayer insulating film 70 is referred to as the surface of the semiconductor substrate 10 and the surface of the semiconductor substrate 10 facing the surface provided with the interlayer insulating film 75. The surface (second surface) is referred to as the back surface of the semiconductor substrate 10.
In the present embodiment, the light corresponding to the acquired image is irradiated from the surface side of the semiconductor substrate 10. As described above, the image sensor that takes in the light irradiated from the surface side of the semiconductor substrate 10 into the pixel (photodiode) is called a surface irradiation type image sensor.

  For example, at the same wiring level as the uppermost layer wiring in the peripheral circuit region 3, the light shielding film and the insulating layer in the pixel array 2 corresponding to the wiring level improve the light collection characteristics of the image sensor and the light quantity to the photodiode PD. Is not provided above the pixel array 2. For example, when n layers (in this case, 3 layers) of wiring levels (wirings) are provided in the peripheral circuit region 3 in the direction perpendicular to the substrate surface, (n−1) ) Layer (here, two layers) wiring level (light-shielding film) is provided.

Due to the difference in the number of wiring levels (the number of stacked metal films and insulating layers) in the pixel array 2 and the peripheral circuit region 3, the upper surface of the interlayer insulating film 70 covering the pixel array 2 and the interlayer insulating film covering the peripheral circuit region 3 A step 92 </ b> A occurs between the upper surface of 70. Therefore, a groove (recess) 92 </ b> B is formed on the upper surface of the interlayer insulating film 70 above the pixel array 2. For example, the interlayer insulating film 70, if the grooves 92B are formed, the uppermost insulating layer 70 _fourth interlayer insulating film 70 has an opening. Incidentally, the upper surface of the second insulating layer 70 ₃ from the uppermost layer side may be exposed by the groove or opening 92B, may be covered with the uppermost insulating layer 70 _4.

  The step 92A of the interlayer insulating film 70 is located above the element isolation region (element isolation layer) at the boundary between the pixel array 2 and the peripheral circuit region 3.

The large lens 7 </ b> A is provided in the groove 92 </ b> B in the interlayer insulating film 70. For example, large lenses 7A is disposed on the uppermost layer of the insulating layer 70 in the _fourth opening portion of the interlayer insulating film 70. The large lens 7A is adjacent to the step 92A of the interlayer insulating film 70 in the horizontal direction with respect to the light receiving surface of the pixel array.

  The large lens 7A is provided on the lower base layer 71. The lower base layer 71 covers the top surface of the interlayer insulating film 70 and the inner and bottom surfaces of the trench 92B. The upper base layer 72 covers the lower base layer 71 and the upper surface of the large lens 7A. For example, a part of the upper surface of the large lens 7 </ b> A may be in contact with a part of the bottom surface of the color filter layer 8.

  The large lens 7A is formed using a material having transparency. The large lens 7A is formed of a material different from that of the interlayer insulating film 70, the base layers 71 and 72, and the planarization layer 73, for example. The material of the large lens 7A preferably has a refractive index different from that of the interlayer insulating film 70, the base layers 71 and 72, and the planarizing layer 73. The large lens 7A is formed using at least one material selected from the group including an inorganic film, an organic film, a resin (synthetic resin), and a coating film.

  The large lens 7A condenses the light from each microlens above the large lens 7A and irradiates the condensed light to each pixel (photodiode PD) corresponding to each microlens. As described above, the large lens 7 </ b> A provided in the interlayer insulating film 70 assists the condensing of the microlens array 9.

  As described above, the large lens 7A is provided at a position that overlaps the pixel array 2 in the vertical direction (perpendicular to the substrate surface) with respect to the light receiving surface of the pixel array 2. The large lens 7A has, for example, a shape that covers the entire pixel array 2 when viewed from the direction perpendicular to the light receiving surface of the pixel array 2. For example, when the large lens 7A has a circular planar shape, the size of the large lens 7A (see FIG. 3) is such that the pixel array 2 is inscribed in the large lens 7A when viewed from the direction perpendicular to the light receiving surface of the pixel array 2. (Diameter) is set. The planar layout of the pixel array 2 and the large lens 7 </ b> A is a layout in which the large lens 7 </ b> A has a circumscribed circle relationship with the pixel array 2. The diameter of the large lens 7A may be larger than the maximum dimension (for example, a diagonal line) of the pixel array 2 in the direction perpendicular to the substrate surface.

  The planar shape of the groove (opening) 92B may be the same shape (for example, a circular shape) as that of the large lens 7A, or may be a different shape (for example, a rectangular shape).

  The size of the step 92A between the upper surface of the interlayer insulating film 70 in the peripheral circuit region 3 and the upper surface of the interlayer insulating film 70 in the pixel array 2, that is, the depth of the groove 92B is, for example, about 1.5 μm to 2 μm. is there. In this case, the thickness of the thickest portion of the large lens 7A is, for example, about 1.0 μm to 1.5 μm. The large lens 7A functions as a spacer layer for the groove 92B and the members 8, 9, 72, 73 formed above the groove, and reduces the step 92A of the interlayer insulating film 78.

  In order to improve the light condensing characteristics of the image sensor, the metal film (light shielding film) and the insulating layer located at the uppermost wiring level may be selectively removed from above the pixel array 2 in some cases. In this case, a step 92A occurs between the upper surface of the interlayer insulating film 70 covering the pixel array 2 and the upper surface of the interlayer insulating film 70 covering the peripheral circuit region 3. Due to the step 92A, the thickness of the base layer covering the upper surface of the interlayer insulating film 70, the thickness of the color filter layer, and the thickness of the overcoat layer may be nonuniform. Furthermore, due to the unevenness in the thickness of the step 92A of the interlayer insulating film 70 and the layers 71, 72, 73 below the microlens array 9, the shapes of the plurality of microlenses included in the microlens array may vary.

  For example, when a material with poor coverage is used for the base layer 71 immediately above the interlayer insulating film 70 having the step 92A, the adverse effect of film thickness non-uniformity is further increased. Further, as the elements formed on the image sensor chip are miniaturized, the step 92A of the interlayer insulating film generated between the pixel array 2 and the peripheral circuit region 3 tends to be relatively large with respect to the cell size. .

  Due to the step 92A and the non-uniformity of the underlying layers 70, 71, 72, 73 of the microlens array 9, the characteristics of the microlens deteriorate near the boundary between the pixel array 2 and the peripheral circuit region 3, and the pixel array The amount of light irradiated on the outer peripheral portion of the pixel array is lower than that in the central portion of the pixel array. As a result, shading occurs in the image sensor, and the quality (image quality) of the image formed by the image sensor deteriorates.

In the image sensor of the present embodiment, the internal or the groove (insulating layer 70 _fourth opening portion) in 92B of the interlayer insulating film 70 due to the step 92A, the lens (large lens between the pixel array 2 and the peripheral circuit region 3 Lens) 7A is provided.

  In the image sensor of this embodiment, the lens 7A in the groove 92B functions as a spacer layer for the step 92A of the interlayer insulating film 70, and the step 92A generated above the pixel array 2 and the peripheral circuit region 3 is the lens 7A. Is reduced by. Therefore, it is possible to suppress the non-uniformity of the thickness of each layer 71, 72, 73 serving as the base of the microlens array 9, and to reduce the characteristic variation of the microlens formed above these layers 71, 72, 73.

  In the image sensor of this embodiment, the lens 7A is provided between the microlens array 9 and the pixel array 2. Therefore, the light from the microlens is condensed by the lens 7A in the interlayer insulating film 70, the incident angle with respect to the photoelectric conversion unit (photodiode) is relaxed, and the photoelectric conversion unit PD is irradiated.

  As in the image sensor of the present embodiment, the lens 7A is provided in the groove 92B of the interlayer insulating film 70 caused by the step 92A in the vicinity of the boundary between the pixel array 2 and the peripheral circuit region 3, thereby Condensing characteristics can be improved, and a reduction in the amount of light applied to the photoelectric conversion unit PD can be prevented. Therefore, the image sensor of this embodiment can suppress shading of the image sensor.

  Furthermore, in the image sensor of this embodiment, one lens 7 </ b> A is provided in the interlayer insulating film 70 so as to correspond to the pixel array 2. Therefore, in the image sensor of this embodiment, it is necessary to consider variation in the characteristics of the lenses in the interlayer insulating film, compared to the case where a plurality of lenses are provided in the interlayer insulating film 7A so as to correspond to the photoelectric conversion unit. No, it is possible to suppress an excessive increase in the lens manufacturing process.

  As described above, according to the solid-state imaging device of the first embodiment, it is possible to suppress the deterioration of the image quality of the formed image.

(B) Manufacturing method
A method for manufacturing the solid-state imaging device (image sensor) according to the first embodiment will be described with reference to FIGS. 4 to 6 show cross-sectional structures in the respective steps of the image sensor manufacturing method of the present embodiment. Note that in the image sensor manufacturing method of the present embodiment, the order in which components of the image sensor described later are formed may be appropriately changed as long as process consistency is ensured.

  As shown in FIG. 4, P-type and N-type well regions 12 and element isolation layers 15 and 19 are formed in a semiconductor substrate 10, for example, a P-type silicon substrate 10. The semiconductor substrate 10 may be an SOI substrate.

  The well region 12 and the element isolation layer of the impurity layer are formed at predetermined positions in the semiconductor substrate 10 by a mask formed by a photolithography technique or by controlling acceleration energy of impurity ions in ion implantation.

  In the step of forming an element isolation layer made of an insulator, an element isolation groove is formed in the semiconductor substrate 10 by photolithography and RIE (Reactive Ion Etching). An insulator is embedded in the element isolation trench by a CVD (Chemical Vapor Deposition) method or a coating method. As a result, an insulating element isolation layer 15 is formed at a predetermined position in the semiconductor substrate 10.

  As described above, an element isolation region (insulating film or impurity layer) for electrically isolating adjacent elements is formed in the semiconductor substrate 10, and the pixel array 2 and the peripheral circuit region 3 adjacent thereto are respectively connected to the semiconductor. It is partitioned in the substrate 10. In the pixel array 2, an active region as a unit cell formation region is defined by the formed element isolation region.

  A resist mask (not shown) is formed on the semiconductor substrate 10 by photolithography. The resist mask has an opening corresponding to the formation region of the photodiode. The impurity layer 21 is formed in the semiconductor substrate 10 by an ion implantation method using a resist mask having an opening as a mask. When the semiconductor substrate 10 is a P-type semiconductor substrate, for example, at least one N-type impurity layer 21 is formed in the semiconductor substrate 10. As a result, a photodiode PD corresponding to each pixel of the image sensor is formed in the pixel array 2. In order to improve the characteristics of the photodiode, a plurality of P-type and N-type impurity layers may be formed in the photodiode formation region.

  In the transistor formation region, a gate insulating film 32 is formed on the semiconductor substrate 10 by, for example, a thermal oxidation method. For example, a silicon layer is deposited on the gate insulating film 32 by a CVD method. Then, a gate electrode 31 having a predetermined gate length and gate width is formed on the surface (first surface) of the semiconductor substrate 10 with the gate insulating film 32 interposed therebetween by a photolithography technique and an RIE method. For example, the formed gate electrode 51 is used as a mask, and an impurity layer 33 as a source and a drain is formed in the semiconductor substrate 10 by ion implantation. As a result, the field effect transistor (not shown) of the unit cell 20 and the field effect transistor Tr of the peripheral circuit are formed in the pixel array 2 and the peripheral circuit region 3 on the surface of the semiconductor substrate 10, respectively.

  An impurity layer (not shown) as a floating diffusion is formed in the semiconductor substrate 10 at a predetermined position in the active region of the pixel array 2 by photolithography and ion implantation. The floating diffusion may be formed in a process common to the impurity layer included in the photodiode, may be formed in a process common to the impurity layer as the source / drain, or formed in a process different from these processes. May be.

  The field effect transistor of the unit cell 20 and the field effect transistor Tr of the peripheral circuit may be formed in the same process or may be formed in different processes.

A plurality of insulating layers 70 ₁ , 70 ₂ , 70 ₃ , 70 ₄ , metal films 50, 55, and plugs CP, VP as an interlayer insulating film 70 are formed on the surface of the semiconductor substrate 10 on which the element is formed by a multilayer wiring technique. Are sequentially formed for each wiring level.

For example, the lowermost insulating layer 70 _first interlayer insulation film 70 so as to cover the upper surface of the gate electrode 31 and the photodiode PD of the transistor Tr, by CVD (Chemical Vapor Deposition), deposited on the surface of the semiconductor substrate 10 Is done. Then, the deposited upper surface of the insulating layer 70 _1, for example, is planarized by CMP (Chemical Mechanical Polishing) method. Upper and impurity layer of the gate electrode 31 so as to expose the upper portion of the (source / drain or the contact area), contact holes, the insulating layer 70 _1, using photolithography and RIE, is formed. The contact plug CP is embedded in the formed contact hole.

Metal film such as aluminum or copper, for example, by sputtering, is deposited on the insulating layer 70 ₁ and on the contact plug CP. The deposited metal films 50 and 55 are processed into a predetermined shape so as to be connected to the contact plug CP by the photolithography technique and the RIE method. So as to cover the processed metal film (wiring or the light shielding film), a second interlayer insulating film 70 ₂ is deposited on the interlayer insulating film 70 ₁ of the bottom layer. By substantially the same process, an insulating layer, a via plug VP, and a plurality of metal films 50 and 55 are sequentially formed from the lower wiring level (substrate surface side) at each wiring level.

As described above, the metal film 55 as the light shielding film is formed in the pixel array 2 in the interlayer insulating film 70 including the plurality of insulating layers 70 ₁ , 70 ₂ , 70 ₃ , and 70 ₄ so as to reach a predetermined number of wiring levels. A metal film 50 as a wiring is formed in the peripheral circuit region 3.

  A resist is applied on the interlayer insulating film 70. The resist is patterned by photolithography and RIE so that an opening is formed above the pixel array 2. A resist mask 80 having a predetermined pattern is formed on the interlayer insulating film 70. Using the patterned resist mask 80 as a mask, the metal film and insulating layer located at the uppermost wiring level are removed from above the pixel array 2. For example, when three wiring levels of multilayer wiring are formed in the peripheral circuit region 3, two wiring levels of multilayer wiring (light-shielding film) are formed in the pixel array 2 by removing the metal film.

As a result, a step 92A is formed on the upper surface of the interlayer insulating film 70 in the vicinity of the boundary between the pixel array 2 and the peripheral circuit region 3. A groove (recess) 92 </ b> B is formed in the interlayer insulating film 70 above the pixel array 2. For example, in the upper region of the pixel array 2, the uppermost insulating layer 70 in the _4, the opening portion is formed, part of one top surface of the lower insulating layer 70 ₃ of the uppermost layer is etched. The size of the step 92A (groove depth) is, for example, about 1.5 μm to 2.0 μm. In a later step, it is preferable that the groove 92B having an area larger than that of the pixel array 2 is formed so that a lens covering the entire upper portion of the pixel array 2 is formed in the groove 92B. It grooves planar shape of 92B (opening of the insulating layer 70 _4), may be the rectangular shape (rectangular shape), may be circular (or elliptical). Incidentally, the upper surface of the second insulating layer 70 ₃ from the uppermost layer side may be exposed by the groove or opening 92B, may be covered with the uppermost insulating layer 70 _4.

  After the resist mask 80 is removed, a rewiring layer may be formed on the interlayer insulating film 70 so as to be connected to the metal film 55 as a wiring by a rewiring formation technique. The rewiring layer is used as a pad, for example.

  As shown in FIG. 5, after the resist mask on interlayer insulating film 70 is removed, first base layer 71 is deposited on interlayer insulating film 70 so as not to fill trench 92B. The base layer 71 is formed by a coating method or a CVD method. The base layer 71 is formed to have a film thickness of about several tens of nm to 0.2 μm. The base layer 71 is preferably made of a material with good coverage.

  Then, a layer (first lens forming layer) 7 </ b> A for forming a lens is deposited on the base layer 71. The material of the lens forming layer 7A is formed using a material different from that of the base layer 71 and the interlayer insulating film 70 so that the refractive indexes of the layers 7A, 70, and 71 are different from each other.

  The lens forming layer 7A is processed by, for example, the RIE method so that the light receiving surface side is hemispherical (lens shape). As a result, the large lens 7A is formed in the groove 92B of the interlayer insulating film 70. The large lens 7 </ b> A is adjacent to the step 92 </ b> A generated in the interlayer insulating film 70.

  The height of the large lens 7A (the dimension of the thickest part of the lens) is, for example, about 1.0 μm to 1.5 μm.

  As shown in FIG. 6, the second base layer 72 is formed on the first base layer 71 and the large lens 7A by, for example, a CVD method or a coating method. For the second base layer 72, a material different from the material of the large lens 7A (for example, a material having a different refractive index) is used.

By removing the metal film above the pixel array 2 in the above-described process, a step 92A is formed on the upper surface of the interlayer insulating film 70 at the boundary between the pixel array 2 and the peripheral circuit region 3.
In the present embodiment, the large lens 7A is provided in a recess (groove) 92B in the interlayer insulating film 71 due to the step 92A. Since the large lens 7A serves as a spacer layer for the step 92A, the size of the step 92A is reduced. As a result, the step between the pixel array 2 and the peripheral circuit region 3 is reduced, and nonuniformity (thickness unevenness) of the second base layer 72 due to the step 92A is suppressed.

  A color filter layer (pigment layer) 8 including red, blue and green filters is formed on the second base layer 72 at a position overlapping the pixel array 2 and the large lens 7A. The color filter layer 8 is formed so that one color filter corresponds to one pixel (photodiode).

  Note that the color filter layer 8 may come into contact with the upper portion of the lens 7A depending on the thickness of the base layer 72.

  As described above, the step 92A generated in the lower interlayer insulating film 70 is relaxed by the large lens 7A, and the thickness non-uniformity of the base layer 72 is suppressed. Therefore, in this embodiment, compared with the case where the large lens layer 7A is not provided in the groove 92B, the non-uniformity (thickness unevenness) of the color filter layer 8 due to the base layers 70, 71, 72, or Distortion (filter inclination) of the color filter filter layer 8 in the vicinity of the boundary between the pixel array 2 and the peripheral circuit region 3 is suppressed.

  As shown in FIG. 3, an overcoat layer (planarization layer) 73 is formed on the second base layer 72 and the color filter layer 8 by, for example, a coating method. For the overcoat layer 73, a material different from the material of the large lens 7A (for example, a material having a different refractive index) is preferably used. The overcoat layer 73 may be a resin layer formed by a coating method or a layer formed by a CVD method.

  A lens forming layer (second lens forming layer) is deposited on the overcoat layer 73 in order to form the microlens array 9. The lens layer is processed by, for example, etching (RIE method) so that a plurality of microlenses are formed from the lens forming layer. As a result, a microlens array 9 including a plurality of microlenses is formed above the pixel array 2 and the large lens 7A. The microlens is formed so as to correspond to the photodiode 30 on a one-to-one basis.

  In the manufacturing method of this embodiment, the large lens 7A is provided in the groove 92B of the interlayer insulating film 71 due to the step 92A, whereby the step 92A of the interlayer insulating film 71 is reduced, and the base layer 72 and the color filter layer are formed. 8 non-uniformity is mitigated. The non-uniformity (thickness unevenness) of the overcoat layer 73 is alleviated, and the step 92A generated in the overcoat layer 73 is further reduced than the step 92A of the underlayers 8 and 72. As a result, since the microlens array 9 is formed on the overcoat layer 71 with small steps and non-uniformity, variations in the shape of the plurality of microlenses are reduced.

  Pads are formed on the front side or back side of the image sensor chip by rewiring technology or TSV technology.

  Through the above manufacturing process, the image sensor of the first embodiment is manufactured.

  In the method of manufacturing the solid-state imaging device (image sensor) according to the present embodiment, the step 92A at the boundary between the pixel array 2 and the peripheral circuit region 3 is removed after the metal film and the insulating layer above the pixel array 1 are selectively removed. A lens 7A corresponding to the pixel array 2 is formed in the groove (opening portion of the insulating layer) 92B of the interlayer insulating film 70 so as to be adjacent to the pixel array 2.

  The lens 7 </ b> A in the groove 92 </ b> B functions as a spacer layer for the step 92 </ b> A generated in the interlayer insulating film 70. The lens in the interlayer insulating film 70 can reduce the step 92A at the boundary between the pixel array 2 and the peripheral circuit region 3, and the non-existence of the layers 71, 72, 73 formed above the pixel array 2 and the peripheral circuit region 3 can be reduced. Uniformity (unevenness in film thickness) can be suppressed. Furthermore, by forming the lens 7 </ b> A in the groove 92 </ b> B of the interlayer insulating film 70, the non-uniformity of the underlying layers 8, 70, 71, 72, 73 of the microlens array 9 is reduced. Therefore, the non-uniformity of the shape of the microlens formed on the underlying layers 8, 70, 71, 72, 73 is suppressed. As a result, the deterioration of the condensing characteristics of the microlens due to the level difference or non-uniformity of the base is suppressed.

  Light from the microlens is collected by the lens 7A provided in the interlayer insulating film 70, and the collected light is irradiated to the photodiodes (pixels) 21 corresponding to the microlenses. The amount of light applied to the pixel array 2 is increased by the lens (large lens) 7 </ b> A in the interlayer insulating film 70 and the lens (microlens) 9 on the interlayer insulating film 70.

  Therefore, the amount of light with respect to the photodiode on the outer peripheral portion (peripheral circuit region side) of the pixel array 2 is suppressed from decreasing compared to the amount of light with respect to the photodiode in the center portion of the pixel array 2, and shading of the image sensor is suppressed. Can be suppressed.

  Further, in the image sensor manufacturing method of the present embodiment, since one lens 7A is formed for the pixel array 2, a plurality of lenses are provided in the interlayer insulating film 7A so as to correspond to the photoelectric conversion unit. Compared to the above, it is not necessary to consider the characteristic variation of the lens in the interlayer insulating film, and it is possible to suppress an excessive increase in the lens manufacturing process.

  As described above, according to the method of manufacturing the solid-state imaging device of the first embodiment, it is possible to provide a solid-state imaging device that can suppress deterioration in the image quality of the formed image.

(2) Second embodiment
The solid-state imaging device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. In addition, regarding the members common to the configuration of the first embodiment, overlapping description will be given as necessary.

  FIG. 7 shows a cross-sectional structure of the image sensor in the present embodiment.

  As shown in FIG. 7, the inside of the groove 92B in which the large lens 7A is provided may be embedded with a second base layer (insulator) 72A. In this case, a base layer 72A having a flat upper surface is formed above the pixel array 2 and the peripheral circuit region 3. For example, the position of the upper surface (surface on the microlens array side) of the second base layer 72Z in the groove 92 in the direction perpendicular to the light receiving surface (surface of the semiconductor substrate) of the pixel array is within the peripheral circuit region 3. The position is substantially the same as the position of the upper surface of the second base layer 72Z. Alternatively, the position of the upper surface of the second base layer 72Z in the groove 92 may be substantially the same as the position of the upper surface of the first base layer 71 in the peripheral circuit region 3. Further, when the first base layer 71 is not provided on the interlayer insulating film 70, the position of the upper surface of the second base layer 72 </ b> Z in the trench 92 is the position of the upper surface of the interlayer insulating film 70 in the peripheral circuit region 3. It may be substantially the same as the position.

  The color filter layer 8, the overcoat layer 73, and the microlens array 9 are each formed on a flat surface. The color filter layer 8 is a flat layer in which the inclination (distortion) of the filter layer due to the step 92A at the boundary between the pixel array 2 and the peripheral circuit region 3 is reduced.

  Thus, by filling the groove 92 with the large lens 7A and the base layer 72Z, the step 92A on the upper surface of the interlayer insulating film 70 in the vicinity of the boundary between the pixel array 2 and the peripheral circuit region 3 substantially disappears. The area above the pixel array 2 and the peripheral circuit area 3 is flat. Therefore, the uneven thickness of each layer 8, 72A, 70 on the interlayer insulating film and the large lens 7A is suppressed, and the variation in the shape of the microlens is reduced.

  Therefore, the image sensor of this embodiment can suppress shading of the formed image.

  The image sensor of this embodiment is formed as follows, for example. FIG. 8 shows a cross-sectional structure in one step of the method of manufacturing the image sensor of the present embodiment.

  The large lens 7A is formed in the groove 92B in the interlayer insulating film 70 so as to be adjacent to the step 92A of the interlayer insulating film 70 by the same process as in the first embodiment.

  As shown in FIG. 8, the insulator 72Z is formed in the groove (opening) 92B by, for example, a coating method so that the inside of the groove 92B is filled. A material different from that of the large lens 7A is used for the insulator 72Z.

  For example, as shown in FIG. 7, the upper surface of the insulator 72Z is planarized by, eg, CMP. As a result, the upper surface of the insulating film 72Z covering the upper side of the pixel array 2 and the peripheral circuit region 3 becomes flat. When the insulator 72Z is formed on the base layer 71 and the large lens 7A by a coating method, a substantially flat surface is formed by the coating solution having high fluidity, so that the insulator 72Z is planarized. The process may be omitted.

  Thus, the lens 7A is provided in the groove 92B above the pixel array 2, and the inside of the groove 92B is filled with the insulator (second base layer). As a result, a flat surface is formed above the pixel array 2 and the peripheral circuit region 3, and the step generated in the interlayer insulating film 70 at the boundary between the pixel array 2 and the peripheral circuit region 3 is eliminated.

  Therefore, the color filter layer 8 and the microlens array 9 are formed on a substantially flat surface above the pixel array 2 and the peripheral circuit region 3. As a result, unevenness in the thickness of the color filter layer 8 and the overcoat layer 73, inclination of the color filter layer 8, and variation in the shape of the microlens can be suppressed.

  Therefore, the image sensor of the second embodiment can suppress shading that occurs in the image sensor, similarly to the image sensor of the first embodiment.

  As described above, according to the solid-state imaging device and the manufacturing method thereof according to the second embodiment, it is possible to provide a solid-state imaging device that can suppress deterioration in image quality of an image to be formed.

(3) Third embodiment
With reference to FIGS. 9 to 12, a solid-state imaging device and a method for manufacturing the same according to the third embodiment will be described. In addition, the overlapping description regarding the member common to the component of 1st and 2nd embodiment is performed as needed.

(A) Structure
The structure of the solid-state imaging device (image sensor) of the third embodiment will be described with reference to FIG.

In the first and second embodiments, the surface irradiation type image sensor has been described. However, the image sensor according to the embodiment may be a back-illuminated image sensor.
FIG. 9 shows a cross-sectional structure of the backside illuminated image sensor in the present embodiment.

  In the back side illumination type image sensor, the back side of the substrate is an irradiation surface of light from the subject. The back-illuminated image sensor has a surface (back surface, second surface) opposite to a surface (front surface, first surface) provided with an interlayer insulating film 70 covering an element (for example, a gate electrode of a transistor). The color filter layer 8 and the microlens 9 are provided. In the back-illuminated image sensor, the support substrate 19 is attached on the interlayer insulating film 71 on the substrate surface side by an adhesive layer (not shown).

  In the image sensor of the present embodiment, a large lens 7 </ b> A is provided on the irradiation surface side of the back side illumination type image sensor, that is, on the back side of the semiconductor substrate 10.

  In the backside illuminated image sensor, a light shielding film 59 of a metal film is provided on the back side of the substrate 10 via a protective film (insulating film) 75 on the back side of the semiconductor substrate 10. The light shielding film 59 is covered with the first and second base layers 76 and 77.

  The light shielding film 59 is disposed below (on the irradiation surface side) the unit cell (invalid cell) 20X and the field effect transistor Tr in the invalid region 2X so that the invalid region (second region) 2X of the pixel array 2 is not irradiated with light. ). For example, the black reference region as the invalid region 2X is provided for generating and outputting a dark voltage (dark current) as a reference potential. For example, the reset voltage is generated based on the voltage output from the photodiode PD of the invalid cell (black reference cell) 20X.

  The light shielding film 59 has an opening 92B at a position that overlaps with the imaging region (first region) 2A of the pixel array 2 in the vertical direction with respect to the light irradiation surface. On the back side of the semiconductor substrate 10, the light receiving surface of the imaging region 2A is exposed, and light from the subject is irradiated onto the imaging region 2A.

  In the backside illuminated image sensor of the present embodiment, a step 92A according to the presence or absence of the light shielding film 59 occurs at the boundary between the imaging region 2A and the invalid region 2X.

  The large lens 7 </ b> A is provided between the pixel array 2 and the microlens array 9 on the back surface side on the back surface side of the semiconductor substrate 10.

  The large lens 7A is provided in a groove (opening of the light shielding film 59) 92B caused by the step 92A. The groove 92 </ b> B is formed by the side surface of the light shielding film 59 and the back surface of the semiconductor substrate 10. The large lens 7A is provided on the back surface side of the semiconductor substrate 10 so as to be adjacent to the step 92A (side surface of the light shielding film 59). The large lens 7A is arranged at a position overlapping the imaging region 2A in the vertical direction with respect to the irradiation surface of the pixel. The large lens 7A is formed so as to cover the entire irradiation surface side of the imaging region 2A. For example, when viewed from the direction perpendicular to the light receiving surface of the pixel array, the imaging region 2A of the pixel array 2 is inscribed in the large lens 7A. An insulating film 75 and a base layer 76 are provided between the large lens 7 </ b> A and the back surface of the semiconductor substrate 10.

  In the back-illuminated image sensor of this embodiment, the large lens 7A is provided in the opening 92B of the light shielding film 59. The large lens 7A functions as a spacer layer for the step 92A. Thereby, the step 92A caused by the presence or absence of the light shielding film 59 at the boundary between the imaging region 2A and the invalid region 2X in the pixel array 2 is alleviated.

  Therefore, nonuniformity (unevenness in film thickness) due to the step 92A occurs in the second base layer 77, the color filter layer 8, and the overcoat layer 78 formed under the light shielding film 59 having the opening. Can be suppressed. And since the non-uniformity of the underlayers 8, 77, 78 of the microlens array 9 is suppressed, the variation in the shape (characteristics) of the microlenses is reduced.

  In the backside illuminated image sensor of the present embodiment, light from the microlens array 9 provided on the backside of the semiconductor substrate 10 is collected by the large lens 7A and collected in each photoelectric conversion unit PD in the imaging region 2A. Irradiated with light.

  Therefore, also in the back side illumination type image sensor as in the third embodiment, shading of the image sensor can be suppressed as in the above-described front side illumination type image sensor.

  As described above, according to the solid-state imaging device of the third embodiment, it is possible to suppress the deterioration of the image quality of the formed image.

(B) Manufacturing method
A manufacturing method of the solid-state imaging device according to the third embodiment will be described with reference to FIGS. The manufacturing method of the solid-state imaging device of this embodiment is related with the manufacturing method of a back irradiation type image sensor. 10 to 12 show cross-sectional structures in respective steps of the image sensor manufacturing method of the present embodiment.

  As shown in FIG. 10, as in the first and second embodiments, unit cells 20 including photodiodes are formed in the pixel array 2 of the semiconductor substrate 10 to form peripheral circuits such as transistors Tr. Elements are formed in the peripheral circuit region 3 of the semiconductor substrate 10. The gate electrode 31 of the transistor Tr is formed on the surface of the semiconductor substrate 10. An interlayer insulating film 70 including a wiring (metal film) 50 is formed on the surface (first surface) of the semiconductor substrate 10. The upper surface of the interlayer insulating film 70 is planarized.

  The support substrate 17 is attached to the interlayer insulating film 70 via an adhesive layer (not shown) on the surface side of the semiconductor substrate 10.

  As shown in FIG. 11, for example, gliding (polishing), a CMP method, wet etching, or the like is performed on the back surface of the semiconductor substrate 10 to reduce the thickness of the semiconductor substrate 10.

After the semiconductor substrate 10 is thinned, a protective film (insulating film) 75 is formed on the back surface of the semiconductor substrate 10.
A metal film 59 is deposited on the protective film 75 by sputtering, for example. A resist mask 82 having a predetermined pattern is formed on the metal film 59 by photolithography. The resist mask 82 has an opening at a position corresponding to the imaging region 2 </ b> A of the pixel array 2.

  Using the patterned resist mask 82 as a mask, the metal film 59 on the back surface side of the semiconductor substrate 10 is etched by, for example, the RIE method. As a result, a light shielding film 59 having an opening is formed on the back side of the semiconductor substrate. By the light shielding film 59, the imaging region 2A and the invalid region 2X are formed in the pixel array 2. The imaging region 2A is formed at a position that vertically overlaps the opening 92B of the light shielding film 59 in the direction perpendicular to the surface of the substrate 10, and an invalid area (black reference region) is formed at a position that overlaps the light shielding film 59 vertically. Is done. In this way, the light irradiation surface of the pixel array 2 of the back-illuminated image sensor is exposed. The film thickness of the metal film for forming the light shielding film 59 is preferably thick in order to ensure the light shielding property for the ineffective region.

  On the back side of the semiconductor substrate 10, at the boundary portion between the portion not covered by the light shielding film 59 and the portion covered by the light shielding film 59, that is, at the boundary portion between the imaging region 2 </ b> A and the invalid region 2 </ b> X of the pixel array 2, A step 92A is formed. As a result, the portion 92B corresponding to the opening of the light shielding film 59 becomes the groove 92B.

  As shown in FIG. 12, after the resist mask is removed, the first base layer 76 is formed on the light shielding film 59 and the protective film 75 on the back surface side of the semiconductor substrate 10 by, for example, the CVD method or the coating method. Is done.

  A lens forming layer is deposited on the first base layer 76. The lens forming layer is processed into a hemispherical shape by etching, and the large lens 7A is formed in the opening 92B of the light shielding film 59.

  As shown in FIG. 9, after the large lens 7A is formed, the first base layer 76 and the large lens are formed on the back surface side of the semiconductor substrate 10 by substantially the same process as in the first and second embodiments. A second base layer 77, a color filter layer 8, and an overcoat layer 78 are formed on 7A.

  The large lens 7A provided in the opening 92B relaxes the size of the step 92A due to the presence or absence of the light shielding film 59 as a spacer layer. As a result, the non-uniformity (unevenness of film thickness) of each layer 8, 77, 78 laminated on the base layer 76 and the large lens 7A can be suppressed.

  On the overcoat layer 78, the microlens array 9 is formed. The microlens array 9 on the back surface side of the semiconductor substrate is formed on the underlayers 8, 77, 78 in which the step 92A is small and nonuniformity is suppressed. Therefore, the variation in the shape of the microlens in the microlens array 9 is reduced.

  As described above, in the manufacturing method of the present embodiment, the lens 7A has the opening (groove) of the light shielding film 59 so that the step 92A caused by the presence or absence of the light shielding film on the back side of the semiconductor substrate is adjacent to the step 92A. ) Relaxed by being formed in 92B.

  Therefore, according to the manufacturing method of the third embodiment, as in the first and second embodiments, after the large lens 7A is provided in the groove (opening) 92B, the step 92A is generated. It is possible to suppress the occurrence of non-uniformity (unevenness in film thickness) due to the step 92A in each of the formed layers 8, 77, and 78. Then, in the microlens array 9 formed on each of the layers 8, 77, and 78 as the base layer, variation in the shape of the microlens can be reduced. Further, in the backside illumination side image sensor, a large lens 7A corresponding to the pixel array 2 is formed between the imaging region 2A of the pixel array 2 and the microlens array 9, so that the large lens 7A is converted into a photoelectric conversion unit. Assists in the irradiation of light.

  Thereby, in the backside illuminated image sensor of the present embodiment, the light condensing characteristics of the image sensor are improved.

  Therefore, an image sensor capable of suppressing shading can be formed by the manufacturing method of the present embodiment.

  As described above, according to the method of manufacturing the solid-state imaging device of the third embodiment, it is possible to provide a solid-state imaging device that can suppress deterioration in the image quality of the formed image.

(4) Fourth embodiment
With reference to FIG. 13, the solid-state imaging device of 4th Embodiment and its manufacturing method are demonstrated. The solid-state imaging device according to the present embodiment is a back-illuminated image sensor as in the third embodiment.

  FIG. 13 shows a cross-sectional structure of the backside illuminated image sensor in the present embodiment.

  In the backside illuminated image sensor of this embodiment, the inside of the groove 92B in which the large lens 7A is disposed, that is, the inside of the opening 92B in the light shielding film 59 formed so as to correspond to the imaging region 2A is the second. Similar to the embodiment, the insulator (second base layer) 77A may be filled. As a result, the step 92A at the boundary between the imaging region 2A and the invalid region 2X is eliminated. Then, on the back side of the semiconductor substrate (the side where the microlens is provided), the step 92A does not occur in the base layer 77A, and the base layer 77A has a flat surface.

  The second base layer 77A may be formed by a coating method as described in the second embodiment, or may be planarized by a CMP method.

  In the backside illuminated image sensor of this embodiment, the color filter layer 8, the overcoat layer 78, and the microlens array 9 on the backside of the semiconductor substrate 10 are respectively formed on a base layer (base layer) 77A having a flat surface. It is formed. Therefore, the backside illuminated image sensor according to the present embodiment can suppress the non-uniformity of the layers 8 and 78 and reduce the variation in the shape of the microlens 9.

Therefore, the image sensor of this embodiment can suppress shading of the formed image.
Therefore, according to the solid-state imaging device and the manufacturing method of the fourth embodiment, it is possible to suppress the deterioration of the image quality of the formed image.

(5) Application examples
An application example of the solid-state imaging device according to the embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the component described in each above-mentioned embodiment, and description of those components is performed as needed.

  The solid-state imaging device (image sensor) described in the first to fourth embodiments can be applied to the camera module 100, for example.

  FIG. 14 is a cross-sectional view schematically showing a camera module 100 including the image sensor 1 of the present embodiment.

  The camera module 100 includes a chip of the image sensor 1. In addition to the chip of the image sensor 1, the camera module 100 includes, for example, a signal processing unit (not shown), a calculation unit (not shown), an input / output unit (not shown), and an optical lens unit 200.

  A signal processing unit (for example, DSP: Digital Signal Processor) processes an electrical signal output from the image sensor 1. The input / output unit functions as an interface for signals from within the module 100 and signals from the outside. The optical lens unit 200 condenses incident light on the image sensor 1 and forms an image corresponding to the incident light on the image sensor 1. A calculation unit (for example, MPU: Micro-Processing Unit) controls the operation of the entire module 100 based on an external signal.

  As shown in FIG. 14, the image sensor 1 of the present embodiment is mounted in shields (envelopes) 101 and 102 having light shielding properties.

  For example, the image sensor 1 is provided on a mounting board (not shown) inside the lower shield 101. The image sensor is connected to wiring (not shown) formed on the mounting substrate by electrodes (for example, solder balls or bumps) 6 or bonding wires (not shown).

  On the bottom of the lower shield 101, for example, solder balls (or solder bumps) 109 are provided. The camera module 100 is connected to another circuit on the mounting substrate (not shown) via the solder ball 109.

  The optical lens unit 200 is mounted in the shields 101 and 102. The optical lens unit 200 is held by the upper shield 102 so as to be positioned perpendicular to the light receiving surface of the image sensor 1. The optical lens unit 200 has a plurality of lenses 201 and 202. For example, the plurality of lenses 201 and 202 have different refractive indexes. 14 shows an example in which two lenses 201 and 202 are provided in the optical lens unit 200. However, the number of lenses is not limited to two, and may be one. Of course, three or more may be used.

  For example, a glass substrate (cover glass) 105 is provided in the shield 102 between the image sensor 1 and the optical lens unit 200. The glass substrate 105 is held in the shields 101 and 102 by being sandwiched between the lower shield 101 and the upper shield 102.

  Light from the subject is applied to the optical lens unit 200 through the openings formed in the shield units 101 and 102, and the optical lens unit 200 condenses the irradiated light. The incident angle of light from the subject with respect to the irradiation surface of the image sensor 1 is changed (adjusted) by the combination of the plurality of lenses 201 and 202 in the optical lens unit 200. Light from the optical lens unit 200 is applied to the image sensor 1 through the glass substrate 105. The light is irradiated to each pixel 20 in the pixel array (imaging region) 2 through the microlens array 9 of the image sensor 1 and the large lens 7A in the interlayer insulating film.

  The image sensor of this embodiment includes a large lens 7 </ b> A corresponding to the pixel array 2 between the microlens 9 and the pixel array 2. The large lens 7A functions as a spacer layer by being provided adjacent to the step 92A at the boundary between two regions adjacent to each other in the chip, and each member provided on the interlayer insulating film 70 and the large lens 7A. In contrast, the size of the step 92A is reduced. Thereby, non-uniformity (thickness unevenness) of each layer due to the step 92A is suppressed, and variations in the shape and characteristics of each microlens of the microlens array 9 are reduced. The large lens 7A further collects the light from the microlens array 9 and irradiates each photoelectric conversion unit (photodiode) 20 of the pixel array. Thus, the large lens 7A improves the light collection characteristics of the image sensor.

  Therefore, the camera module including the image sensor according to the present embodiment can suppress deterioration in image quality such as shading.

  Since the chip of the image sensor 1 of the present embodiment includes the large lens 7A in addition to the microlens 9, the camera module including the image sensor of the present embodiment reduces the number of lenses 201 and 202 in the optical lens unit 200. it can. Furthermore, since the number of lenses of the optical lens unit 200 can be reduced, the camera module can be thinned.

The optical lens unit 200 of the camera module is subject to various design restrictions depending on the specifications required for the camera module. For example, it may be difficult to set the incident angle of light with respect to the light receiving surface of the image sensor to 30 ° C. or less by the optical lens unit 200 due to the specifications of the area and thickness of the module.
On the other hand, in the image sensor 1 of the present embodiment and the camera module 100 including the image sensor 1, the large lens 7A in the chip condenses light from the outside of the chip. Moreover, the optical design of the lenses 201 and 202 of the optical lens unit 200 can be assisted by adjusting the shape and material of the large lens 7A. As a result, in the camera module 100 including the image sensor 1 of the present embodiment, image distortion due to the lens can be suppressed.

  As described above, the image sensor of the present embodiment and the camera module including the image sensor can alleviate restrictions on the lens design of the camera module.

  Therefore, the camera module including the image sensor of the present embodiment can reduce the design load of the camera module in addition to improving the image quality.

(6) Modification
A modification of the solid-state imaging device according to the first to fourth embodiments will be described with reference to FIGS. 15 and 16.

  In each of the above-described embodiments, the case where the planar shape of the large lens 7A is circular has been described. However, as shown in FIGS. 15 and 16, the large lens may have a planar shape other than a circular shape.

  FIG. 15 schematically shows a plan view of a chip of an image sensor in a modification of the present embodiment. As shown in FIG. 15A, the planar shape of the large lens 7B may be an elliptical shape. Further, as shown in FIG. 15B, the planar shape of the large lens 7C may be a square shape.

  The elliptical or quadrangular large lenses 7B and 7C are arranged between the pixel array 2 and the microlens array 9 so as to cover the entire pixel array 2 similarly to the structure shown in FIG.

  For example, when viewed from the direction perpendicular to the light receiving surface, the pixel array 2 is inscribed in an elliptical large lens 7B. For example, in the elliptical large lens 7B, the long axis dimension L3A of the large lens 7B is larger than the long side dimension L2A of the pixel array 2, and the short axis dimension L3B of the large lens 7B is the short side of the pixel array 2. Is larger than the dimension L2B.

  For example, in the rectangular large lens 7C, the long side dimension L4A of the large lens 7C is greater than or equal to the long side dimension L2A of the pixel array 2, and the short side dimension L4B of the large lens 7C is the short side of the pixel array 2. The dimension L2B or more. The planar shape of the large lens 7 </ b> C may be a shape in which square corners are round as long as the planar layout covers the entire pixel array 2.

  As shown in FIG. 16, in the surface irradiation type image sensor, an imaging region 2 </ b> A and an invalid region (for example, a black reference region) 2 </ b> X are provided in the pixel array 2. For example, in order to improve the light shielding property of the invalid region 2, the metal film located at the uppermost wiring level in the invalid region 2 </ b> X may remain as the light shielding film 59. In this case, a step 92A is formed on the upper surface of the interlayer insulating film 70 at the boundary between the imaging region 2A and the ineffective region 2X, and a groove 92B is provided above the imaging region 2A.

  In this case, as shown in FIG. 16, the large lens 7 </ b> A may be provided so as to correspond only to the imaging region 2 </ b> A in the pixel array 2. The large lens 7A is not provided above the invalid area 2X. For example, when the large lens 7A has a circular planar shape, the imaging region 2A is a circular large lens 7A when viewed from the direction perpendicular to the light receiving surface of the pixel array 2 (the direction perpendicular to the substrate surface). Inscribed. The large lens 7A is formed so that one lens 7A corresponds to all the photoelectric conversion units (effective pixels) in the imaging region 2A.

  In the modification shown in FIGS. 15 and 16, the same effects as those of the image sensor of the first to fourth embodiments and the camera module including the image sensor can be obtained.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  2: pixel array, 2A: imaging area, 2X: invalid area, 3: peripheral circuit area, 20: pixel, 7A: lens, 9: microlens array, 100: camera module, 1: image sensor, 200: optical lens unit 201, 202: lens, 92A: step, 92B: groove, opening.

Claims (5)

A first region provided in a semiconductor substrate and including a plurality of first photoelectric conversion units irradiated with light;
A second region provided in the semiconductor substrate and adjacent to the first region;
A plurality of first lenses disposed at positions overlapping the first region in a direction perpendicular to the light receiving surface of the first photoelectric conversion unit, each corresponding to the first photoelectric conversion unit;
A second lens corresponding to the first region adjacent to a step at the boundary between the first region and the second region between the first region and the first lens;
A solid-state imaging device comprising: An interlayer insulating film provided on the first surface of the semiconductor substrate and having the trench at a position overlapping with the first region;
A peripheral element provided in the second region;
In addition,
The first lens is provided on the interlayer insulating film on the first surface side,
The second lens is provided in the groove in the interlayer insulating film;
The solid-state imaging device according to claim 1. An interlayer insulating film provided on the first surface of the semiconductor substrate;
A second photoelectric conversion unit provided in the second region and not irradiated with light;
A metal film provided on the second surface side opposite to the first surface of the semiconductor substrate and having an opening at a position overlapping with the first region;
In addition,
The first lens is provided on the second surface side,
The second lens is provided in the opening.
The solid-state imaging device according to claim 1.   The said 2nd lens has a plane layout which covers the whole said 1st area | region in the light-receiving surface side of the said 1st photoelectric conversion part, The any one of Claim 1 thru | or 3 characterized by the above-mentioned. The solid-state imaging device according to claim 1. The solid-state imaging device according to any one of claims 1 to 4,
A lens unit that emits light to the solid-state imaging device;
An exterior device for holding the solid-state imaging device and the lens unit;
A camera module comprising:

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