JP2012114160A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of preventing that a depletion layer existing in the area from the conjunction portion between an i-type photoelectric conversion film and a blocking layer composed of an impurity semiconductor material to the i-type photoelectric conversion film spreads to the i-type photoelectric conversion film and the region in which an interface state occurring at a side surface of the blocking layer composed of the impurity semiconductor material occurs, and to provide a method of manufacturing the same.SOLUTION: A solid-state imaging device in which a plurality of pixels are two-dimensionally arranged comprises: a semiconductor substrate; interlayer insulating films formed on the semiconductor substrate; lower electrodes formed on the interlayer insulating films with a space between every pixel; photoelectric conversion films that are composed of an intrinsic semiconductor material and are formed on the lower electrodes with a space between every pixel; a blocking layer that is composed of an impurity semiconductor material, is formed on the photoelectric conversion films over the plurality of pixels, and covers portions of or the entire photoelectric conversion films by filling the spaces with portions corresponding to the spaces between the photoelectric conversion films; and an upper electrode with translucency formed on the blocking layer over the plurality of pixels.

Description

  The present invention relates to a stacked solid-state imaging device in which a photoelectric conversion film is stacked on a semiconductor substrate.

As a conventional stacked solid-state imaging device, for example, as shown in FIG. 18, a pixel unit 900 includes a p-type semiconductor substrate 305, an emitter electrode 310, a p-type base layer 315, and an n ⁺ -type emitter layer 320. And a base electrode 325, an insulating film 347, a transparent electrode 344, a lower electrode 340, an i-type photoelectric conversion film 341, and a p-type blocking layer 342. In this solid-state imaging device, there is a gap between the photoelectric conversion films 341 in adjacent pixels. In addition, a blocking layer 342 is formed on the upper surface of the photoelectric conversion film 341, and side surfaces of the photoelectric conversion film 341 and the blocking layer 342 are covered with an insulating film 347.

  The signal charge generated in the photoelectric conversion film 341 passes through the lower electrode 340 and moves to the base layer 315 through the base electrode 325, so that the potential of the base layer 315 is decreased. At this time, a negative pulse is applied to the transparent electrode 344. Then, after a predetermined accumulation time, the emitter electrode 310 is connected to a signal readout capacitor, and a positive pulse is applied to the transparent electrode 344, whereby the signal charge of the base layer 315 is read out through the emitter layer 320 (not shown). Is read out. Thereafter, the signal charge is output to the outside through an amplifier (not shown). A MOS transistor is used when outputting signal charges to the outside.

JP-A-2-275670

  However, in the conventional stacked solid-state imaging device, the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the p-type blocking layer to the i-type photoelectric conversion film is an i-type photoelectric conversion film. In addition, there is a problem that the interface state that occurs on the side surface of the p-type blocking layer extends to a region where the interface state is generated. This occurs because the depletion layer is in contact with the interface between the insulating film and the semiconductor. The interface state is also called a surface state, and is an energy level that captures and emits electrons and holes generated at the interface of different substances. Since the interface state is energetically located between the valence band and the conduction band, the energy between the interface state and the valence band or the conduction band is the energy between the valence band and the conduction band. Smaller and easier to move the charge by heat.

  The charge read out as the signal charge is a charge existing in the depletion layer. In addition, when the depletion layer extends to the region where the interface states exist on the side surfaces of the photoelectric conversion film and the blocking layer, a large number of interface states are included in the depletion layer. Then, the charge in the valence band in the depletion layer is thermally excited from the valence band to the interface state, and then excited from the interface state to the conduction band, and may be read as a signal charge. This readout of signal charges is a phenomenon that occurs even when no light is incident, and is called dark current. In addition, the charge trapped in the interface state from the conduction band in the depletion layer may be excited to the conduction band at a timing delayed from the original readout frame and read out as a signal charge. This readout of signal charges causes afterimages. These dark currents and afterimages degrade the image quality of the output image.

  The present invention has been made to solve the above problem, and is a depletion layer existing in a range from a junction between an i-type photoelectric conversion film and a blocking layer made of an impurity semiconductor material to an i-type photoelectric conversion film. Is to provide a solid-state imaging device and a method for manufacturing the same that can prevent the interface state generated on the side surface of the blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material from being spread And

  In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device in which a plurality of pixels are two-dimensionally arranged, and includes a semiconductor substrate and an interlayer insulating film formed on the semiconductor substrate. A lower electrode formed on the interlayer insulating film with a gap for each pixel; and a photoelectric conversion film made of an intrinsic semiconductor material and formed on the lower electrode with a gap for each pixel; A part of a side surface of the photoelectric conversion film, which is made of an impurity semiconductor material, is formed on the photoelectric conversion film over a plurality of pixels, and a portion corresponding to the gap between the photoelectric conversion films enters the gap. Or it has the blocking layer which has covered all, and the upper electrode which has translucency formed over the said blocking layer over several pixels, It is characterized by the above-mentioned.

  Further, the method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device in which a plurality of pixels are two-dimensionally arranged, the step of forming an interlayer insulating film on a semiconductor substrate, and the interlayer Forming a lower electrode on the insulating film with a gap for each pixel; forming a photoelectric conversion film on the lower electrode with a gap for each pixel; and the photoelectric conversion film. An impurity semiconductor material is formed so as to cover a part or all of the side surface of the photoelectric conversion film formed over a plurality of pixels, and a portion corresponding to the gap between the photoelectric conversion films enters the gap. The manufacturing method of the solid-state imaging device characterized by including the process of forming the blocking layer which becomes, and the process of forming the translucent upper electrode over several pixels on the said blocking layer.

  In the solid-state imaging device according to the present invention, the blocking layer covers part or all of the side surface of the photoelectric conversion film. That is, the side surface of the depletion layer present in the range of the i-type photoelectric conversion film from the junction between the blocking layer and the photoelectric conversion film is covered with the blocking layer. Therefore, the depletion layer does not contact the interface state generated on the side surface of the blocking layer and the translucent upper electrode.

  In this way, the blocking layer covers part or all of the side surface of the photoelectric conversion film, so that the depletion layer and the interface state can be prevented from coming into contact with each other. Generation of current and trapping afterimages can be suppressed. The depletion layer existing in the range of the i-type photoelectric conversion film from the junction between the i-type photoelectric conversion film and the blocking layer made of the impurity semiconductor material is a blocking layer made of the i-type photoelectric conversion film and the impurity semiconductor material. It can be suppressed that the interface state generated on the side surface is expanded to a region where the interface state is generated.

  Furthermore, in the solid-state imaging device according to the present invention, the blocking layer covers the upper surface of the photoelectric conversion film, and signal charges generated in the photoelectric conversion film can be retained in the photoelectric conversion film. Therefore, the transfer efficiency of signal charges can be improved.

  According to the manufacturing method of the present invention, the depletion layer existing in the range from the junction between the i-type photoelectric conversion film and the blocking layer formed of the impurity semiconductor material to the i-type photoelectric conversion film is an i-type photoelectric conversion. It is possible to manufacture a solid-state imaging device that can suppress spreading to a region where an interface state generated on a side surface of a blocking layer formed of a film and an impurity semiconductor material is generated.

1 is a block diagram schematically showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a top view for 6 pixels in the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device concerning Embodiment 2 of this invention. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is process sectional drawing which shows typically a part of manufacturing process of the pixel part of the solid-state imaging device shown in FIG. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 3 of this invention. FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. FIG. 13 is a process cross-sectional view schematically showing a part of the manufacturing process of the pixel portion of the solid-state imaging device shown in FIG. 12. It is sectional drawing of the pixel part of the solid-state imaging device which concerns on Embodiment 4 of this invention. FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. FIG. 16 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the pixel portion of the solid-state imaging device illustrated in FIG. 15. It is sectional drawing of the conventional solid-state imaging device.

[Embodiment 1]
1. Overall Configuration of Solid-State Imaging Device 1 The overall configuration of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG.

As shown in FIG. 1, in the solid-state imaging device 1, a plurality of pixels 100 are arranged in a two-dimensional arrangement, for example, a matrix (matrix) in the pixel region 61. A pulse generation circuit 62, a vertical shift register 63, and a horizontal shift register 64 are formed so as to surround the pixel region 61. The vertical shift register 63 and the horizontal shift register 64 sequentially output drive pulses to each pixel 100 in response to the application of the timing pulse from the pulse generation circuit 62.
2. Configuration of Pixel 100 FIG. 2 is a plan view showing six pixels as a partial region in the solid-state imaging device 1 shown in FIG. Each pixel 100 is partitioned by a pixel boundary 43. Each pixel 100 includes a reset gate 10, an amplification transistor 11, a storage diode 15 in an n-type impurity diffusion layer, and a floating diffusion in an n-type impurity diffusion layer. 16, an n-type impurity diffusion layer reset transistor drain 17, a transfer gate 18, contacts 31 to 34, and a metal wiring 45.

  FIG. 3 is a cross-sectional view of the pixel 100 of the solid-state imaging device 1 shown in FIG. 1, and shows a cross-section A-A ′ of FIG. For the sake of convenience, the description will be made using three pixels 100 as the pixels of the solid-state imaging device 1. As shown in FIG. 3, an STI (Shallow Trench Isolation) 12 is formed in the semiconductor substrate 5 on which the p-type well is formed. Each pixel 100 includes a channel stopper 13, a storage diode 15, a floating diffusion 16, and a reset transistor drain 17.

  On the semiconductor substrate 5, a gate oxide film 14 and an interlayer insulating film 20 are sequentially stacked. Within the interlayer insulating film 20, a reset gate 10, a transfer gate 18, an amplification transistor gate 19, A connection electrode 23 is formed.

  Interlayer insulating films 21 and 22 are sequentially laminated on the interlayer insulating film 20. In the interlayer insulating films 21 and 22, wirings 24 and 25 (for example, formed of Al or Cu) and connection electrodes 26 is formed. The interlayer insulating films 20 to 22 are formed of an oxide film using, for example, a CVD (Chemical Vapor Deposition) method.

  On the interlayer insulating film 22, the pixel electrode 40 is formed with a gap for each pixel. On each pixel electrode 40, photoelectric conversion films 41a having spectral sensitivity with respect to red light and photoelectric conversion films 41b having spectral sensitivity with respect to green light are formed alternately and with a gap therebetween. ing. Note that the solid-state imaging device 1 also has a photoelectric conversion film having spectral sensitivity to blue light. However, since a Bayer array is adopted, it appears in FIG. 3 which is a cross section taken along line AA ′ in FIG. Not. Hereinafter, when the spectral sensitivity is not related, the photoelectric conversion films of the respective colors are collectively referred to as the photoelectric conversion film 41 without being distinguished.

The photoelectric conversion film 41 is formed of an i-type semiconductor material made of an inorganic photoconductive film or the like, and the red, green, and blue spectral sensitivities are adjusted by changing the composition ratio of the same semiconductor material. When an α-Si film is used as the inorganic photoconductive film, specifically, the spectral sensitivity of the photoelectric conversion film 41 is controlled by changing the ratio of α-Si _1-x C _x : x. It has gained.

  A p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels. The blocking layer 42 includes a part 42 a formed on the upper surface of the photoelectric conversion film 41 and a part 42 b corresponding to a gap between the photoelectric conversion films 41. A portion 42 b corresponding to the gap of the photoelectric conversion film 41 of the blocking layer 42 enters the gap of the photoelectric conversion film 41 and covers the entire side surface of the photoelectric conversion film 41. In addition, a gap is provided between the blocking layer 42 and the side surface of the pixel electrode 40 so that the blocking layer 42 and the pixel electrode 40 do not contact each other, and the photoelectric conversion film 41 exists in this gap. .

  On the blocking layer 42, a transparent electrode 44 (formed of, for example, ITO or ZnO) is formed as a translucent upper electrode over a plurality of pixels. The transparent electrode 44 is formed on the entire pixel region 61. It has spread to. In the pixel boundary portion 43 that is a gap between the photoelectric conversion films 41, a transparent electrode 44 is formed so as to cover a blocking layer portion 42 b corresponding to the gap between the photoelectric conversion films 41.

A metal wiring 45 is formed on the transparent electrode 44 in the pixel boundary portion 43. The shape of the metal wiring 45 passes between all adjacent pixels in the pixel region 61 and has a mesh shape in the whole plan view. Further, the metal wiring 45 is formed so as to surround the pixel region 61, and the metal wiring 45 extends from the center of the pixel region 61 toward the periphery of the pixel region 61. And the periphery of the pixel region 61 are connected. For the metal wiring 45, a material having an electric resistivity lower than that of the material of the transparent electrode 44 is used. In addition, since the metal wiring 45 is provided in the pixel boundary part 43 which is not a light-receiving part, the metal wiring 45 does not reduce an aperture ratio. The maximum allowable width of the metal wiring 45 is the same as the width of the pixel boundary 43.
3. Driving of the solid-state imaging device 1 The incident light is converted into electric charges by the photoelectric conversion film 41. A bias voltage is applied to the transparent electrode 44, and the generated charges are attracted to the pixel electrode 40 by the bias voltage between the transparent electrode 44 and the pixel electrode 40, and the connection electrodes 23 and 26 are connected from the pixel electrode 40. It is temporarily stored in the storage diode 15. Next, the data is transferred and accumulated from the storage diode 15 to the floating diffusion 16 by the action of the transfer gate 18. At this time, the potential of the floating diffusion 16 fluctuates according to the signal charge amount, and this fluctuation amount is transmitted to the amplifying transistor 11 via the amplifying transistor gate 19 and further amplified by the amplifying transistor 11 and taken out as a signal to the outside. .

The reset transistor drain 17 is electrically connected to the power supply voltage terminal Vdd. Therefore, the potential of the reset transistor drain 17 is always Vdd. By turning on the reset gate 10, the potential of the floating diffusion 16 is reset to the potential Vdd of the reset transistor drain 17.
4). Effect A depletion layer exists in the range of the i-type photoelectric conversion film 41 from the junction between the photoelectric conversion film 41 and the blocking layer 42. In this configuration, the part 42 b corresponding to the gap between the photoelectric conversion films 41 of the blocking layer 42 enters the gap between the photoelectric conversion films 41, and all of the side surfaces of the i-type photoelectric conversion film 41 are p-type blocking layers 42. Covered. Therefore, the side surface of the depletion layer is covered with the blocking layer 42, and the depletion layer does not extend to the region where the interface state is generated. Therefore, dark current and trapping afterimages due to interface states can be suppressed.

  Furthermore, since the photoelectric conversion film 41 having a predetermined spectral sensitivity is used for each pixel without using a color filter, light is not absorbed by the color filter, and light loss can be avoided.

  Further, since the metal wiring 45 is formed on the transparent electrode 44, the combined resistance obtained by combining the transparent electrode 44 and the metal wiring 45 becomes smaller than the resistance of only the transparent electrode 44. Therefore, the voltage drop at the center of the pixel region 61 that has been increased due to the resistance of the transparent electrode 44 is reduced, and the voltage drop at the center of the pixel region 61 can be suppressed. Accordingly, it is possible to reduce image quality degradation that occurs when the magnitude of the voltage drop differs depending on the location of the pixel region 61.

In addition, since the photoelectric conversion film 41 is separated for each pixel, the resolution is high, color mixing and inter-pixel leakage can be suppressed, and deterioration in image quality can be reduced.
5. Manufacturing Method of Solid-State Imaging Device 1 With respect to the manufacturing method of the pixel 100 according to the first embodiment of the present invention, processes that are essential parts will be described with reference to FIGS.

In FIG. 4A, an STI (Shallow Trench Isolation) 12 that separates transistors and diffusion layer elements is formed on a p-type semiconductor substrate 5. Specifically, the semiconductor substrate 5 is dry-etched to form a trench having a depth of 200 nm to 400 nm serving as an isolation region. In order to reduce the defect region between the formed groove and the Si substrate interface, for example, sacrificial oxidation with an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like, and for example, 10 keV to 20 keV, 1 × 10 ¹³ cm ^{−2 to} 3 The ion implantation of B is performed at × 10 ¹³ cm ⁻² to form the channel stopper 13 of the p ⁺ layer. Next, the inside of the formed trench is filled with an insulating film, and planarized by CMP (Chemical Mechanical Polishing), thereby forming the STI 12. Further, by implanting ions of P or As into the p-type semiconductor substrate 5 at, for example, 50 keV to 80 keV, 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² , the storage diode 15 and the floating diffusion 16 are formed. And n-type impurity layers of the reset transistor drain 17 are simultaneously formed. The gate oxide film 14 that becomes the gate oxide film of the transistors constituting the transfer gate 18 and the reset gate 10 is formed by thermal oxidation, plasma oxidation, or the like, for example, 5 nm to 10 nm.

  Next, as shown in FIG. 4B, a Poly-Si film is deposited by, for example, 100 nm to 200 nm by thermal CVD, plasma CVD, or the like, and then a predetermined resist pattern is formed by a general photolithography technique. Form. Then, by selectively etching the Poly-Si film, the transfer gate 18, the amplification transistor gate 19 and the reset gate 10 made of the Poly-Si film are formed.

  Here, after the gate oxide film 14 is formed, a part of the floating diffusion 16 is opened to form an amplification transistor gate 19 composed of a Poly-Si film. The electrical connection between the floating diffusion 16 and the amplification transistor gate 19 is made. Connected.

  An interlayer insulating film 20 made of a CVD oxide film is formed, for example, 500 nm to 1000 nm. Then, the contact 31, the contact 32, and the contact 33 are formed at predetermined positions by a general photolithography technique and an etching technique. A W (tungsten) plug is embedded in the opened contact opening to form a connection electrode 23 of the W plug, and electrical connection to the storage diode 15 and the reset transistor drain 17 is formed. For example, a wiring 24 made of Al, Cu or the like having a thickness of 200 nm to 300 nm and an interlayer insulating film 21 made of a CVD oxide film are formed. By repeating the same, the wiring 25 and the interlayer insulating film 22 are formed, and the formation of the multilayer wiring is completed. Here, a contact is opened on the connection electrode 23 and a W plug is embedded to form the connection electrode 26.

  In FIG. 5A, after the interlayer insulating film 22 is formed, a metal film made of Al, W, Mo (molybdenum) or the like is deposited to 100 nm to 300 nm, and a pixel electrode having a predetermined shape is formed by a general photolithography technique and etching technique. 40 is formed. The pixel electrode 40 is formed with a gap for each pixel, and this area determines the effective aperture ratio of the pixel. For example, when the separation width between pixels is 1/10 to 2/10 of the pixel size in a pixel size of 1.0 μm to 1.4 μm, the aperture ratio is estimated to be about 64% to about 81%.

5B, after the pixel electrode 40 is formed, an α-Si film having a red spectral sensitivity characteristic is deposited to 100 nm to 1 μm by plasma CVD or sputtering so as to cover the pixel electrode 40 and the interlayer insulating film 22. An i-type photoelectric conversion film 41a is formed. Specifically, the spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si _1-x C _x : x.

  In FIG. 6A, a predetermined resist pattern 70 is formed on the photoelectric conversion film 41a by a general photolithography technique. The size of each pixel of the photoelectric conversion film 41a is, for example, 0.9 μm to 1.3 μm in a pixel size of 1.0 μm to 1.4 μm, respectively.

In FIG. 6B, the photoelectric conversion film 41a is etched by a general etching technique using the resist pattern 70 as a mask to form a photoelectric conversion film 41a having a predetermined pattern.
In FIG. 7A, by repeating the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 5B to 6B, in each pixel 100, on each corresponding pixel electrode 40, The i-type photoelectric conversion film 41b is formed with a gap for each pixel. Note that the spectral sensitivity is controlled by changing the ratio of α-Si _1-x C _x : x so that the adjacent photoelectric conversion films 41 a and 41 b have different spectral sensitivities. In addition, there is a gap between adjacent photoelectric conversion films 41, and the pixel boundary portions 43 are formed by forming the photoelectric conversion films 41 in each pixel separately.

  In FIG. 7B, an α-Si film having a predetermined energy gap so as to be a blocking layer of the i-type photoelectric conversion film 41 by plasma CVD or sputtering so as to cover the upper surface and side surfaces of the photoelectric conversion film 41. Is deposited to a thickness of 10 nm to 100 nm, and a p-type blocking layer 42 is formed over a plurality of pixels. The blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to a gap between the photoelectric conversion films 41.

  In FIG. 8A, a transparent electrode 44 made of ITO or ZnO is formed on the blocking layer 42 formed on the photoelectric conversion film 41 by sputtering or CVD to several tens to several hundreds nm. Both the portion 42 a and the portion 42 b of the blocking layer 42 are covered with the transparent electrode 44.

  In FIG. 8B, a metal wiring 45 is deposited to 100 nm to 300 nm on the transparent electrode 44 by sputtering or CVD. Next, a predetermined resist pattern 71 is formed on the metal wiring 45 by a general photolithography technique. Using the resist pattern 71 as a mask, the metal wiring 45 is etched by a general etching technique to form a mesh-like metal wiring 45 on the transparent electrode 44. Thereby, the solid-state imaging device shown in FIG. 3 is obtained.

After this step, an on-chip microlens is formed and the manufacture of the solid-state imaging device is completed. However, the description is omitted because it is not the main point of the present invention.
[Embodiment 2]
1. Configuration of Pixel 200 FIG. 9 is a cross-sectional view of the pixel 200 of the solid-state imaging device 1 according to Embodiment 2 of the present invention. For the sake of convenience, the description will be made using three pixels 200 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.

Each pixel 200 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an insulating film 46.
Each of the photoelectric conversion films 41a and 41b is formed with a gap for each pixel, and at least two of them have different spectral sensitivity characteristics. On the photoelectric conversion film 41, a blocking layer 42 is formed across a plurality of pixels. The blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to a gap between the photoelectric conversion films 41. The upper half of the side surface of the photoelectric conversion film 41 is covered with a portion 42 b corresponding to the gap between the photoelectric conversion films 41 of the blocking layer 42. An insulating film 46 is embedded in the gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. Here, “upper half” and “lower half” do not indicate that the upper half is strictly divided into upper and lower halves, but indicate respective portions where the photoelectric conversion film 41 is divided into upper and lower portions. In other words, the height of the lower half of the photoelectric conversion film 41 from the interlayer insulating film 22 may be slightly higher or lower than one half of the height of the photoelectric conversion film 41 from the interlayer insulating film 22. If the insulating film 46 is formed to be higher than half of the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the subsequent blocking layer 42, the transparent electrode 44, and the metal wiring 45 can be easily embedded. Further, if the insulating film 46 is formed to be lower than half the height of the photoelectric conversion film 41 from the interlayer insulating film 22, the subsequent blocking layer 42, the transparent electrode 44 and the metal wiring 45 can be formed deeply. The photoelectric conversion efficiency by the photoelectric conversion film 41 can be improved.

The height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. This is to prevent the pixel electrode 40 and the p-type blocking layer 42 from coming into contact with each other and causing a short circuit. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the insulating film 46 is embedded in the lower half of the gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. It is possible to form up to a location where both ends of 40 are in contact with the pixel boundary portion 43. That is, the pixel electrode 40 can be formed wider than that in the first embodiment. When the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.
3. Manufacturing Method With respect to the manufacturing method of the pixel 200 according to the second embodiment of the present invention, the main steps will be described with reference to FIGS. 10 and 11, focusing on differences from the first embodiment of the present invention.

In FIG. 10A, after the pixel electrode 40 is formed for each pixel, an α-Si film having a red spectral sensitivity characteristic is deposited on the pixel electrode 40 by plasma CVD or sputtering to have a thickness of 100 nm to 1 μm. A photoelectric conversion film 41a is formed. Specifically, the spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si _1-x C _x : x. A predetermined resist pattern 72 is formed on the photoelectric conversion film 41a by a general photolithography technique.

  In FIG. 10B, the photoelectric conversion film 41a is etched by a general etching technique using the resist pattern 72 as a mask, and a photoelectric conversion film 41a having a predetermined pattern is formed with a gap for each pixel. Unlike the one in the first embodiment, this photoelectric conversion film 41 a is formed so that both ends of the photoelectric conversion film 41 a coincide with both ends of the pixel electrode 40.

11A, the manufacturing method of the i-type photoelectric conversion film 41a described in FIGS. 10A to 10B is repeated, and in each pixel 200, on each corresponding pixel electrode 40, i-type photoelectric conversion films 41a and 41b are formed. Note that the spectral sensitivity is controlled by changing the ratio of α-Si _1-x C _x : x so that the photoelectric conversion films 41 a and 41 b have different spectral sensitivities.
In addition, the photoelectric conversion films 41 a and 41 b can be made smaller than the pixel electrode 40. That is, it is possible to improve sensitivity by forming the pixel electrode 40 larger than the photoelectric conversion films 41a and 41b. In this embodiment, since the insulating film 46 is formed later, even if the pixel electrode 40 is larger than the photoelectric conversion films 41a and 41b, it does not come into contact with the blocking layer 42 or the transparent electrode 44. That is, the present invention is also effective for misalignment between the mask pattern when the pixel electrode 40 is formed and the mask pattern when the photoelectric conversion film 41a and the photoelectric conversion film 41b are formed.

In FIG. 11B, an insulating film 46 made of a CVD oxide film is formed so as to fill a gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the photoelectric conversion film 41. A pixel boundary 43 is formed by forming each pixel separately. Here, for example, if the separation width of the pixel boundary portion 43 is 1/10 of the pixel size in a pixel size of 1.0 μm to 1.4 μm, it becomes 0.1 μm to 0.14 μm.
Since the manufacturing method of the process after this process is only forming the blocking layer 42, the transparent electrode 44, the metal wiring 45, and the on-chip microlens (not shown) similarly to Embodiment 1 of this invention, description is abbreviate | omitted. To do.
[Embodiment 3]
1. Configuration FIG. 12 is a cross-sectional view of the pixel 300 of the solid-state imaging device 1 according to Embodiment 3 of the present invention. For the sake of convenience, the description will be made using three pixels 300 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.

Each pixel 300 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, and an n-type blocking layer 47.
At least two of the photoelectric conversion films 41 a and 41 b have different spectral sensitivity characteristics, and a p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels. The photoelectric conversion film 41 is formed on each pixel electrode 40 formed for each pixel, and there is a gap between the adjacent photoelectric conversion films 41a and 41b. The entire side surface of the photoelectric conversion film 41 is covered with a p-type blocking layer 42.

Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. The n-type blocking layer 47 is formed so as to go around the side surface of the pixel electrode 40 and cover the entire side surface of the pixel electrode 40. That is, the entire upper surface and side surfaces of the pixel electrode 40 are covered with the n-type blocking layer 47. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40, and also on the side surface of the pixel electrode 40. It wraps around and covers the entire side surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality is improved.
3. Manufacturing Method Next, a manufacturing method of the pixel 300 according to the third embodiment of the present invention configured as described above will be described with reference to FIGS. 13 and 14, focusing on differences from the first embodiment of the present invention. To do.

In FIG. 13A, a pixel electrode 40 is formed on the interlayer insulating film 22 for each pixel.
In FIG. 13B, several α-Si films having a predetermined energy gap are formed on each pixel electrode 40 and the interlayer insulating film 22 so as to become a blocking layer of the i-type photoelectric conversion film by plasma CVD or sputtering. The n-type blocking layer 47 is formed by depositing 10 nm to several 100 nm. Specifically, the predetermined energy gap is obtained by controlling the spectral sensitivity by changing the ratio of α-Si _1-x C _x : x.

In FIG. 14A, a predetermined resist pattern 73 is formed on the blocking layer 47 by a general photolithography technique.
In FIG. 14B, the blocking layer 47 is etched by a general etching technique using the resist pattern 73 as a mask to form the blocking layer 47 having a predetermined pattern on the pixel electrode 40. At this time, the blocking layer 47 is formed to cover the upper surface and side surfaces of the pixel electrode 40. Thereafter, when the photoelectric conversion film 41 is formed on the pixel electrode 40, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. Further, the structure is such that it is formed so as to go around the side surface of the pixel electrode 40 and cover the entire side surface of the pixel electrode 40.

Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate | omitted.
[Embodiment 4]
1. Configuration FIG. 15 is a cross-sectional view of the pixel 400 of the solid-state imaging device 1 according to Embodiment 4 of the present invention. For the sake of convenience, the description will be made using three pixels 400 as the pixels of the solid-state imaging device 1. Since the configuration other than the following is the same as that of the pixel 100, the description thereof is omitted.

  Each pixel 400 includes a pixel electrode 40, an i-type photoelectric conversion film 41, a p-type blocking layer 42, a transparent electrode 44, a metal wiring 45, an insulating film 46, and an n-type blocking layer 47. Prepare.

  The photoelectric conversion films 41a and 41b are formed with a gap for each pixel, and at least two of them have different spectral sensitivity characteristics. A p-type blocking layer 42 is formed on the photoelectric conversion film 41 over a plurality of pixels. There is a gap between the adjacent photoelectric conversion films 41. The p-type blocking layer 42 includes a portion 42 a formed on the upper surface of the photoelectric conversion film 41 and a portion 42 b corresponding to a gap between the photoelectric conversion films 41.

  The upper half of the side surface of the photoelectric conversion film 41 is covered with a portion 42 b corresponding to the gap between the photoelectric conversion films 41 of the p-type blocking layer 42. An insulating film 46 is embedded in the gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41.

The height of the insulating film 46 from the interlayer insulating film 22 is formed higher than the height of the pixel electrode 40 from the interlayer insulating film 22. Further, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. A mesh-like metal wiring 45 is formed on the transparent electrode 44 of the photoelectric conversion film 41.
2. Effect In this configuration, the insulating film 46 is embedded in the gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the side surface of the photoelectric conversion film 41. The pixel electrode 40 can be formed so that both ends thereof are in contact with the pixel boundary portion 43. That is, the pixel electrode 40 can be formed larger than in the first embodiment. When the pixel electrode 40 becomes large, a large amount of signal charge converted by the photoelectric conversion film 41 can be picked up, leading to output of a large amount of signal charge, and the sensitivity of the solid-state imaging device 1 is improved.

In this configuration, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40. Therefore, the photoelectric conversion film 41 is not in contact with the pixel electrode 40. Therefore, the photoconductive film characteristics of the photoelectric conversion film 41 are improved, the dark current is improved, and the image quality is improved.
3. Manufacturing Method Next, a manufacturing method of the pixel 400 according to the fourth embodiment of the present invention configured as described above will be described with reference to FIGS. 16 and 17, focusing on differences from the first to third embodiments of the present invention. I will explain.

  In FIG. 16A, as shown in the third embodiment, after an n-type blocking layer 47 is formed on the pixel electrode 40 and the interlayer insulating film 22, a general photolithography technique is formed on the blocking layer 47. A predetermined resist pattern 74 is formed.

  In FIG. 16B, the blocking layer 47 is etched by a general etching technique using the resist pattern 74 as a mask to form a blocking layer 47 having a predetermined pattern on each pixel electrode 40. At this time, the blocking layer 47 has a shape that covers only the upper surface of the pixel electrode 40.

In FIG. 17A, after the blocking layer 47 is formed, an α-Si film having a red spectral sensitivity characteristic is deposited on the blocking layer 47 by plasma CVD or sputtering to a thickness of 100 nm to 1 μm to form an i-type photoelectric conversion film. 41a is formed. Specifically, the spectral sensitivity is obtained by controlling the spectral sensitivity by changing the ratio of α-Si _1-x C _x : x. Thereafter, the manufacturing method of the i-type photoelectric conversion film 41a shown in Embodiment 1 and the like is repeated. In each pixel 400, the i-type photoelectric conversion films 41a and 41b are formed on the corresponding pixel electrodes 40. Each is formed with a gap. Note that the spectral sensitivity is controlled by changing the ratio of α-Si _1-x C _x : x so that the photoelectric conversion films 41 a and 41 b have different spectral sensitivities. By this step, the n-type blocking layer 47 is interposed between the photoelectric conversion film 41 and the pixel electrode 40 in each pixel so as to cover the upper surface of the pixel electrode 40.

  Further, there is a gap between the photoelectric conversion films 41 in the adjacent pixels, and the pixel boundary portions 43 are formed by forming the photoelectric conversion films 41 in the respective pixels separately. Here, for example, assuming that the separation width of the pixel boundary portion is 1/10 of the pixel size in the pixel size of 1.0 μm to 1.4 μm, it is 0.10 μm to 0.14 μm.

In FIG. 17B, an insulating film 46 made of a CVD oxide film is formed so as to fill a gap between the photoelectric conversion films 41, and as a result, the insulating film 46 covers the lower half of the photoelectric conversion film 41.
Since the manufacturing method of the process after this process is the same as Embodiment 1 of this invention, description is abbreviate | omitted.
[Modification]
1. Scanning circuit As the scanning circuit, for example, an arbitrary scanning circuit such as a MOS scanning circuit or a CCD may be used.
2. Metal wiring In the embodiment, the shape of the metal wiring has been a mesh shape that passes through all adjacent pixels, but other wiring shapes such as a stripe shape may be employed. The material of the metal wiring 45 can be selected from W, Mo, Ti, etc. in addition to copper, aluminum and the like.
3. Photoelectric Conversion Film In the embodiment, the spectral sensitivity of the photoelectric conversion film 41 is varied in order to vary the spectral sensitivity of each pixel. However, the present invention is not limited to this. For example, if color filters having different spectral sensitivities are used for each pixel, the spectral sensitivities for each pixel can be made different. In this way, even if the pixels have different colors, the photoelectric conversion film 41 can be formed in a common manner, and the process can be simplified.
4). Others The configuration of the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device 1 according to the above embodiment, and various modifications and applications can be made within the scope of the effects of the present invention. Is possible. In addition, the processes used in the above steps can be replaced with other equivalent processes without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind.

  For example, with respect to the arrangement of the pixels, in addition to the matrix (matrix) arrangement shown in the embodiment, a configuration in which the pixels are arranged by being rotated by 45 ° can be employed.

  The present invention can be used for a digital camera or the like, and is useful for realizing a solid-state imaging device in which deterioration of image quality is suppressed.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 5 Semiconductor substrate 15 Storage diode 16 Floating diffusion 100,200,300,400 Pixel 900 Pixel part

Claims (12)

A solid-state imaging device in which a plurality of pixels are two-dimensionally arranged,
A semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
On the interlayer insulating film, a lower electrode formed with a gap for each pixel,
A photoelectric conversion film made of an intrinsic semiconductor material and formed on each of the lower electrodes with a gap for each pixel;
Made of an impurity semiconductor material, formed on the photoelectric conversion film over a plurality of pixels, and a portion corresponding to the gap between the photoelectric conversion films enters the gap, and a part of the side surface of the photoelectric conversion film or A blocking layer covering everything,
A solid-state imaging device comprising: a translucent upper electrode formed over a plurality of pixels on the blocking layer. The solid-state imaging device according to claim 1, wherein the blocking layer is made of a p-type semiconductor material. The portion corresponding to the gap between the photoelectric conversion films of the blocking layer covers the upper half of the side surface of the photoelectric conversion film,
The lower half of the side surface of the photoelectric conversion film is covered with an insulating film,
The solid-state imaging device according to claim 1, wherein a height of the insulating film from the interlayer insulating film is higher than a height of the lower electrode from the interlayer insulating film. The another blocking layer made of an impurity semiconductor material is interposed between the photoelectric conversion film and the lower electrode in each pixel so as to cover the upper surface of the lower electrode. The solid-state imaging device according to any one of 3. The solid-state imaging device according to claim 4, wherein the another blocking layer is formed so as to go around the side surface of the lower electrode and cover the entire side surface of the lower electrode. The solid-state imaging device according to claim 4, wherein the another blocking layer is made of an n-type semiconductor material. The solid-state imaging device according to any one of claims 1 to 6, wherein the photoelectric conversion films in adjacent pixels have different wavelength ranges of light to be converted. The metal wiring made of a material having an electric resistivity lower than that of the material of the upper electrode is laminated on at least a part of the upper electrode, passing between adjacent pixels. The solid-state imaging device according to any one of 7. A method for manufacturing a solid-state imaging device in which a plurality of pixels are two-dimensionally arranged,
Forming an interlayer insulating film on the semiconductor substrate;
Forming a lower electrode on the interlayer insulating film with a gap for each pixel; and
A step of forming a photoelectric conversion film on each lower electrode with a gap for each pixel, and
On the photoelectric conversion film, formed over a plurality of pixels, a portion corresponding to the gap between the photoelectric conversion films enters the gap, and covers a part or all of the side surface of the photoelectric conversion film, Forming a blocking layer made of an impurity semiconductor material;
Forming a translucent upper electrode over a plurality of pixels on the blocking layer. A method for manufacturing a solid-state imaging device, comprising: The part corresponding to the gap between the photoelectric conversion films of the blocking layer is formed so as to cover the upper half of the side surface of the photoelectric conversion film,
After the step of forming the lower electrode,
Before the step of forming the blocking layer,
Forming an insulating film so as to cover the lower half of the side surface of the photoelectric conversion film,
The method for manufacturing a solid-state imaging device according to claim 9, wherein a height of the insulating film from the interlayer insulating film is higher than a height of the lower electrode from the interlayer insulating film. After the step of forming the lower electrode,
Before the step of forming the photoelectric conversion film,
The method further comprises a step of interposing another blocking layer made of an impurity semiconductor material between the photoelectric conversion film and the lower electrode in each pixel so as to cover the upper surface of the lower electrode. Or a method for producing a solid-state imaging device according to 10; The method of manufacturing a solid-state imaging device according to claim 11, further comprising a step of forming the another blocking layer so as to go around the side surface of the lower electrode and cover the entire side surface of the lower electrode. .

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