Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
  • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/158—Dispositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
  • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
• • H10P54/00—
• • H10P58/00—

Definitions

• This relates to integrated circuits and, more particularly, to extended drain
• MOS transistors in integrated circuits MOS transistors in integrated circuits.
• An integrated circuit may contain an extended drain metal oxide semiconductor (MOS) transistor with a drift region in the drain region adjacent to the channel region, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, a double-diffused metal oxide semiconductor (DMOS) transistor or a drain extended metal oxide semiconductor (DEMOS) transistor.
• MOS metal oxide semiconductor
• LDMOS double-diffused metal oxide semiconductor
• DEMOS drain extended metal oxide semiconductor
• an average doping in the drift region is less than half an average doping density in the source region of the MOS transistor.
• An extended drain MOS transistor with the drift region covered by a gate extension field plate sometimes referred to as a field gap MOS transistor, may exhibit a breakdown voltage above 10 volts, but may have an undesirably large resistance in the drain due to a field oxide element in the drain to terminate the field plate.
• An extended drain MOS transistor with no field plate over the drift region sometimes referred to as an active gap MOS transistor, may undesirably exhibit a breakdown voltage below 10
• An integrated circuit may include an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions.
• the extended drain MOS transistor includes a gate having field plates over the field gap drift regions.
• a symmetric nested configuration of the extended drain MOS transistor may be formed.
• a process of forming the integrated circuit is disclosed.
• FIGS. 1A and IB are perspective views of an integrated circuit containing a hybrid active-field gap extended drain MOS transistor formed according to an embodiment, depicted in successive stages of fabrication.
• FIG. 2 is a perspective view of an integrated circuit containing a hybrid active-field gap extended drain MOS transistor formed according to another embodiment.
• FIG. 3 is a perspective view of an integrated circuit containing a hybrid active-field gap extended drain MOS transistor formed according to a further embodiment.
• FIGS. 4A and 4B are a top view and a cross sectional view, respectively, of an integrated circuit containing a hybrid active-field gap extended drain MOS transistor formed in a symmetric nested configuration according to an embodiment.
• An integrated circuit may include a hybrid active-field gap extended drain
• MOS transistor with multiple parallel alternating active gap drift regions and field gap drift regions.
• the field plates are extensions of the gate.
• the field plates terminate on field oxide elements in a drain of the extended drain MOS transistor.
• FIGS. 1A and IB illustrate an integrated circuit 100 containing a hybrid active-field gap extended drain MOS transistor 102 formed according to an embodiment, depicted in successive stages of fabrication.
• the integrated circuit 100 is formed in and on a substrate 104, which may be a single crystal silicon wafer, a silicon-on-insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, or other material appropriate for fabrication of the integrated circuit 100.
• An extended drain 106 of the extended drain MOS transistor 102 is formed in the substrate 104 abutting a channel region 108 of the extended drain MOS transistor 102.
• the extended drain 106 includes a drift region 110.
• the extended drain 106 may be formed, for example, by a process including the steps of: forming an ion implant mask of photoresist over the substrate 104 by a photolithographic process so as to expose an area for the extended drain 106, ion implanting dopants into the substrate 104 in the areas exposed by the ion implant mask, removing the ion implant mask and annealing the substrate 104 so as to activate the implanted dopants.
• Field oxide elements 112 are formed in the extended drain 106 adjacent to the drift region 110.
• the field oxide 112 may be, for example, primarily composed of silicon dioxide 250 to 600 nanometers thick.
• the field oxide elements 112 may be formed by shallow trench isolation (STI) processes as depicted in FIG.
• STI shallow trench isolation
• An STI process may include the steps of: forming an oxide layer on the substrate 104, forming a silicon nitride layer on the oxide layer, patterning the silicon nitride layer so as to expose an area for the field oxide 112, etching a trench in the substrate 104 in the exposed area to an appropriate depth for a desired thickness of the field oxide 112, growing a layer of thermal oxide on sidewalls and a bottom of the trench, filling the trench with silicon dioxide by chemical vapor deposition (CVD), high density plasma (HDP) or high aspect ratio process (HARP), removing unwanted silicon dioxide from a top surface of the silicon nitride layer, and removing the silicon nitride layer.
• CVD chemical vapor deposition
• HDP high density plasma
• HTP high aspect ratio process
• a LOCOS process may include the steps of: forming an oxide layer on the substrate 104, forming a silicon nitride layer on the oxide layer, patterning the silicon nitride layer so as to expose an area for the field oxide 112, growing thermal oxide at the top surface of the substrate 104 in the exposed area to an appropriate thickness for a desired thickness of the field oxide 1 12, and removing the silicon nitride layer.
• the extended drain 106 extends below the field oxide elements 112.
• the field oxide elements 112 may be formed prior to forming the extended drain 106.
• a gate dielectric layer 114 is formed on the substrate
• the gate dielectric layer 114 may be, for example, one or more layers of silicon dioxide, silicon oxy-nitride, aluminum oxide, aluminum oxy-nitride, hafnium oxide, hafnium silicate, hafnium silicon oxy- nitride, zirconium oxide, zirconium silicate, zirconium silicon oxy-nitride, a combination of the aforementioned materials, or other insulating material.
• the gate dielectric layer 114 may include nitrogen as a result of exposure to a nitrogen containing plasma or a nitrogen containing ambient gas at temperatures between 50 C and 800 C.
• a thickness of the gate dielectric layer 114 may be 2.5 to 3.0 nanometers per volt of gate-source bias.
• the gate dielectric layer 114 may be formed by any of a variety of gate dielectric formation processes, for example thermal oxidation, plasma nitridation of an oxide layer, and/or dielectric material deposition by atomic layer deposition (ALD).
• a gate 116 of the extended drain MOS transistor 102 is formed on the gate dielectric layer 114, so as to expose active gap regions 118 of the drift region 110, and so as to form field plates 120 between the active gap regions 118 extending onto the field oxide elements 112.
• the gate 116 may be formed, for example, by a process including the steps of: forming a layer of gate material such as poly crystalline silicon, commonly referred to as polysilicon, over the gate dielectric layer 114, forming a gate etch mask including photoresist over the gate material layer using a photolithographic process so as to cover an area for the gate 116, performing a gate etch process by a reactive ion etch (RIE) process which removes material from the gate material layer in areas exposed by the gate etch mask, and removing the gate etch mask.
• RIE reactive ion etch
• Areas of the drift region 110 under the field plates 120 are field gap drift regions.
• an active gap width 122 of each active gap region 118 between adjacent field plates 120 is less than 2 microns. In a further version, the active gap width 122 of each active gap region 118 is less than 1 micron.
• Gate sidewall spacers may be formed on lateral surfaces of the gate 116.
• a drain contact diffused region 124 is formed in the extended drain 106 abutting the active gap regions 118 and the field oxide elements 112.
• a source 126 of the extended drain MOS transistor 102 is formed in the substrate 104 abutting the channel region 108 and opposite the extended drain 106.
• the drain contact diffused region 124 and the source 126 may be formed concurrently, for example, by a process including the steps of: forming an ion implant mask of photoresist over an existing top surface of the integrated circuit 100 by a photolithographic process so as to expose an area for the drain contact diffused region 124 and an area for the source 126, ion implanting dopants into the substrate 104 in the areas exposed by the ion implant mask, removing the ion implant mask and annealing the substrate 104 so as to activate the implanted dopants.
• a backgate contact diffused region 128 may be formed in the substrate
• the backgate contact diffused region 128, if formed, may be distributed as depicted in FIG. IB or may be localized.
• the backgate contact diffused region 128 may be formed, for example, by a process including the steps of: forming an ion implant mask of photoresist over an existing top surface of the integrated circuit 100 by a photolithographic process so as to expose an area for the backgate contact diffused region 128, ion implanting dopants into the substrate 104 in the areas exposed by the ion implant mask, removing the ion implant mask and annealing the substrate 104 so as to activate the implanted dopants.
• Source contacts 130 are formed on the source 126 and optionally the backgate contact diffused region 128 if present.
• Drain contacts 132 are formed on the drain contact diffused region 124. In one version of the instant embodiment, a drain contact 132 is formed adjacent to each active gap region 118 and adjacent to each field oxide element 112 opposite each field plate 120 overlapping the field oxide element 112.
• the contacts 130 and 132 may be formed, for example, by a process including the steps of: defining contact areas on a top surface of a pre-metal dielectric (PMD) layer over the substrate 104 with a contact photoresist pattern formed by a photolithographic process, etching contact holes in the contact areas by removing PMD layer material using an RIE process to expose the substrate 104, and filling the contact holes with a contact liner metal, such as titanium, and a contact fill metal, typically tungsten, followed by removal of the contact fill metal from the top surface of the PMD layer using etching and/or CMP methods.
• a contact liner metal such as titanium
• a contact fill metal typically tungsten
• the active gap regions 118 may provide a desired impedance through the drift region 110 while the field plates 120 may reduce an electric field in the active gap regions 118 so as to provide a desired high breakdown voltage and desired level of hot carrier reliability.
• the extended drain MOS transistor 102 may be n-channel, as shown in FIGS. 1A and IB. In another version, the extended drain MOS transistor 102 may be p-channel.
• FIG. 2 illustrates an integrated circuit 200 containing a hybrid active-field gap extended drain MOS transistor 202 formed according to another embodiment.
• a gate 206 of the extended drain MOS transistor 202 is formed on a gate dielectric layer 204 so as to have tapered field plates 208.
• a drain end width 210 of each tapered field plate 208 over field oxide elements 212 is at least 100 nanometers less than a source end width 214 of each tapered field plate 208 on an opposite side of the tapered field plate 208 from the corresponding field oxide element 212.
• a source end active gap width 216 of each active gap region 218 is less than 2 microns.
• each active gap region 218 is less than 1 micron.
• the drain end width 210 and the source end width 214 of each tapered field plate 208 are such that each point at a top surface of an active gap region is within a micron of an adjacent field plate in the field gap drift regions. Dimensions of the tapered field plates 208 and active gap regions 218 may be adjusted to provide desired values of breakdown voltage, on- state current and hot carrier reliability.
• the extended drain MOS transistor 202 may be n-channel, as shown in FIG. 2. In another version, the extended drain MOS transistor 202 may be p-channel.
• FIG. 3 is a perspective view of an integrated circuit 300 containing a hybrid active-field gap extended drain MOS transistor 302 formed according to a further embodiment.
• a gate 306 of the extended drain MOS transistor 302 is formed over a gate dielectric layer 304 so as to have retrograde tapered field plates 308.
• a drain end width 310 of each retrograde tapered field plate 308 over field oxide elements 312 is at least 100 nanometers more than a source end width 314 of each retrograde tapered field plate 308 on an opposite side of the retrograde tapered field plate 308 from the corresponding field oxide element 312.
• a source end active gap width 316 of each active gap region 318 is less than 2 microns.
• each active gap region 318 is less than 1 micron.
• Dimensions of the retrograde tapered field plates 308 and active gap regions 318 may be adjusted to provide desired values of breakdown voltage, on-state current and hot carrier reliability.
• the extended drain MOS transistor 302 may be n-channel, as shown in FIG. 3. In another version, the extended drain MOS transistor 302 may be p-channel.
• FIGS. 4A and 4B illustrate an integrated circuit 400 containing a hybrid active-field gap extended drain MOS transistor 402 formed in a symmetric nested configuration according to an embodiment.
• the extended drain MOS transistor 402 includes a first portion 404 and a second portion 406.
• Field oxide elements 408 are formed in an extended drain of the extended drain MOS transistor 402 in the first portion 404 and the second portion 406 in an alternating linear configuration as depicted in FIG. 4.
• the extended drain extends under the field oxide elements 408 and laterally past the field oxide elements 408 and includes a first drift region in the first portion 404 and a second drift region in the second portion 406.
• the extended drain MOS transistor 402 includes a first channel region in the first portion 404 abutting the first drift region, and includes a second channel region in the second portion 406 abutting the second drift region, so that the second channel region is located on an opposite side of the extended drain from the first channel region.
• a first gate section 410 and a second gate section 412 are formed on a gate dielectric layer over the first drift region and first channel region, and over the second drift region and second channel region, respectively.
• the first gate section 410 and the second gate section 412 may optionally be joined at one or both ends of the extended drain MOS transistor 402.
• the first gate section 410 includes first field plates 414 extending onto the field oxide elements 408.
• the first field plates 414 cover first field gap drift regions, alternating with first active gap regions 416, in the first portion 404.
• the second gate section 412 includes second field plates 418 extending onto the field oxide elements 408.
• the second field plates 418 cover second field gap drift regions, alternating with second active gap regions 420, in the second portion 406.
• the first field plates 414 are aligned with the second active gap regions 420, and the second field plates 418 are aligned with the first active gap regions 416.
• an active gap width of each first active gap region 416 between adjacent first field plates 414 and of each second active gap region 420 between adjacent second field plates 418 is less than 2 microns.
• the active gap width of each first active gap region 416 and each second active gap region 420 is less than 1 micron.
• a first source 422 is formed in the first portion 404 abutting the first channel region and adjacent to the first gate section 410.
• a first backgate contact diffused region 424 may be formed adjacent to the first source 422 so as to make electrical connection with the first channel region.
• a second source 426 is formed in the second portion 406 abutting the second channel region and adjacent to the second gate section 412.
• a second backgate contact diffused region 428 may be formed adjacent to the second source 426 so as to make electrical connection with the second channel region.
• a drain contact diffused region 430 is formed in the extended drain abutting the first active gap regions 416 and the second active gap regions 420 and abutting the field oxide elements 408.
• Drain contacts 432 are formed on the drain contact diffused region 430 adjacent to the first active gap regions 416 and the second active gap regions 420, so that each drain contact 432 provides drain current to the corresponding adjacent active gap region 416 or 420 and the corresponding field gap drift region opposite the active gap region.
• a drain contact 432 is formed adjacent to each first active gap region 416 and each second active gap region 420.
• First source contacts 434 are formed on the first source 422, and optionally on the first backgate contact diffused region 424 if present.
• Second source contacts 436 are formed on the second source 426, and optionally on the second backgate contact diffused region 428 if present.
• Dimensions and locations of the field oxide elements 408, the first active gap regions 416 and the second active gap regions 420, the first field gap drift regions and the second field gap drift regions, and the drain contact diffused region 430 may be adjusted to reduce a total area of the extended drain MOS transistor 402 while providing a desired on-state current, a desired breakdown voltage and a desired hot carrier reliability.
• the extended drain 438 is formed in a substrate 440 and includes a first drift region 442 in the first portion 404 and a second drift region 444 in the second portion 406.
• the first gate section 410 is formed on a first gate dielectric layer 446 and the second gate section 412 is formed on a second gate dielectric layer 448.
• the extended drain MOS transistor 402 may be n-channel, as shown in FIG. 4B. In another version, the extended drain MOS transistor 402 may be p-channel.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2011
  • 2011-10-25 US US13/281,260 patent/US8754469B2/en active Active
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  • 2011-10-26 WO PCT/US2011/057843 patent/WO2012058281A2/en not_active Ceased
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