WO2012057020A1 - 薄膜トランジスタおよびその製造方法 - Google Patents

薄膜トランジスタおよびその製造方法 Download PDF

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WO2012057020A1
WO2012057020A1 PCT/JP2011/074289 JP2011074289W WO2012057020A1 WO 2012057020 A1 WO2012057020 A1 WO 2012057020A1 JP 2011074289 W JP2011074289 W JP 2011074289W WO 2012057020 A1 WO2012057020 A1 WO 2012057020A1
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Prior art keywords
film
gate insulating
active layer
insulating film
substrate
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English (en)
French (fr)
Japanese (ja)
Inventor
文彦 望月
真宏 高田
雅司 小野
田中　淳
鈴木　真之
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Fujifilm Corp
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Fujifilm Corp
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Priority to KR1020137010637A priority Critical patent/KR20130139950A/ko
Priority to KR1020167014266A priority patent/KR20160075763A/ko
Publication of WO2012057020A1 publication Critical patent/WO2012057020A1/ja
Priority to US13/871,305 priority patent/US20130234135A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

Definitions

  • Field effect transistors are used as unit elements of semiconductor memory integrated circuits, high-frequency signal amplifying elements, liquid crystal driving elements, and the like, and particularly thin-film transistors are used in a wide range of fields as thin film transistors (TFTs).
  • TFTs thin film transistors
  • a silicon semiconductor or a compound thereof is often used, and high-frequency amplifying elements and integrated circuits that require high-speed operation, such as single-crystal silicon, operate at low speed
  • amorphous silicon is used for a liquid crystal driving device that is required to cope with a large area such as a display application.
  • Amorphous silicon usually requires high-temperature heat treatment exceeding 300 ° C. in its production process, so it is difficult to use it for a supporting substrate such as a flexible substrate in a current display having low heat resistance.
  • IGZO In-Ga-Zn-O-based oxide semiconductor
  • IGZO In-Ga-Zn-O-based oxide semiconductor
  • it is regarded as a promising TFT material for next-generation displays (Non-Patent Documents 1 and 2).
  • an IGZO oxide semiconductor film is attracting attention because it can be formed at room temperature and operates as a TFT, it is not easy to control the characteristics uniformly, particularly in terms of electrical characteristics stability and a large area.
  • Patent Document 1 describes that a protective film is provided to eliminate the influence of moisture on the IGZO from the outside. This means that the IGZO film is not limited to the inside and the outside, and the electrical characteristics affect the moisture content.
  • Patent Document 1 discloses a bottom gate type TFT as an element structure, and a gate insulating film used for this TFT is silicon oxide, silicon oxynitride, silicon nitride film, aluminum oxide, aluminum nitride, aluminum oxynitride. Alternatively, it can be formed of a single layer or a stacked layer of tantalum oxide and is described to be formed by a sputtering method (see [0042]).
  • Patent Document 1 describes that by forming an insulating film or a gate insulating film as a dense film, moisture and oxygen can be prevented from entering the oxide semiconductor layer from the substrate side ([0043 ]reference).
  • Patent Document 1 The purpose of Patent Document 1 is to function as a gate insulating film and to prevent entry of moisture / oxygen, Na, and the like from the outside.
  • SiO 2 when SiO 2 is used as a gate insulating film and formed by sputtering, moisture is mixed into SiO 2 .
  • Patent Document 1 describes that heat treatment is performed at 200 to 600 ° C., typically 300 to 500 ° C. (see [0152]), and at this temperature, moisture in SiO 2 is sufficiently removed. It is possible to do.
  • a flexible substrate such as PEN or PES
  • it is difficult to eliminate the influence of moisture in SiO 2 because it cannot withstand a thermal process having a maximum temperature of about 200 ° C. It is necessary to reduce the amount of water present in
  • the active layer is made of an oxide containing at least one of In, Ga, and Zn, and this active layer has 1 desorption gas observed as water molecules by temperature programmed desorption analysis. Insulated gate transistors with 4 / nm 3 or less are described.
  • an oxide semiconductor thin film that exhibits no hysteresis, has a stable threshold voltage, and has excellent TFT characteristics can be realized.
  • As a method for adding moisture after film formation for example, annealing in water vapor or H 2 O implantation is described.
  • the active layer is likely to fluctuate due to the influence of moisture, oxygen, and the like.
  • moisture for example, when there is an influence of moisture from the gate insulating film or the insulating layer on the active layer, there is a concern that the electrical characteristics of the active layer made of the IGZO film may be affected, and the active layer made of the IGZO film. It is necessary to eliminate the influence from the gate insulating film in contact with the insulating layer.
  • the moisture content of the oxide semiconductor thin film is set to 1.4 pieces / in order to realize TFT characteristics which do not show hysteresis, have a stable threshold voltage, and have good reproducibility.
  • the intake of moisture, oxygen, or the like is specified to be 3 nm or less.
  • no consideration is given to the intake of moisture, oxygen, or the like from the insulating layer into the active layer.
  • no consideration is given to eliminating the influence of moisture, oxygen, and the like from the gate insulating film in contact with the active layer made of the IGZO film and the insulating layer.
  • An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which solve the problems based on the above-described prior art and particularly suppress a change in TFT characteristics caused by moisture.
  • a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode are provided on a substrate, and the source electrode is provided on the active layer.
  • the present invention provides a thin film transistor characterized in that the amount of water is less than 2.
  • the amorphous oxide semiconductor preferably contains at least one of In, Ga, and Zn.
  • the gate insulating film may be a single layer of a SiO 2 film, a SiN film, a SiON film, an Al 2 O 3 film, a HfO 2 film, and a Ga 2 O 3 film, or a laminate thereof. It is preferable that Furthermore, the substrate is preferably a flexible substrate. Furthermore, it is preferable that the gate insulating film has a water content released up to a temperature of 200 ° C. of 1.53 ⁇ 10 20 pieces / cm 3 or less. Moreover, it is preferable that the said board
  • At least a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode are provided on a substrate, and the source electrode and the drain electrode are formed on the active layer.
  • a method of manufacturing a thin film transistor, wherein the active layer is composed of an amorphous oxide semiconductor, and includes a step of forming the gate insulating film and a step of heat-treating the gate insulating film, and the gate The present invention provides a method for manufacturing a thin film transistor, characterized in that a first moisture content existing in an insulating film is less than a second moisture content existing in the active layer.
  • a step of forming the active layer on the gate insulating film after the step of performing heat treatment after forming the gate insulating film.
  • a step of forming the active layer on the substrate and forming the source electrode and the drain electrode on the substrate so as to cover a part of the active layer. It is preferable to have.
  • a step of forming the gate electrode on the gate insulating film is provided after the step of performing a heat treatment after the formation of the gate insulating film.
  • Each said process is made
  • the substrate is preferably a flexible substrate.
  • the amorphous oxide semiconductor includes, for example, at least one of In, Ga, and Zn.
  • the present invention it is possible to suppress a change in TFT characteristics due to moisture in the active layer composed of an amorphous oxide semiconductor, thereby improving electrical characteristic control and stability of the active layer. For this reason, the stability of the TFT characteristic control of the thin film transistor is improved, and further the TFT characteristic can be stabilized.
  • FIG. (A) is typical sectional drawing which shows the thin-film transistor which concerns on the 1st Embodiment of this invention
  • (b) is typical sectional which shows the other example of the thin-film transistor which concerns on the 1st Embodiment of this invention
  • FIG. (A)-(g) is typical sectional drawing which shows the manufacturing method of the thin-film transistor shown to Fig.1 (a) in order of a process. It is typical sectional drawing which shows the thin-film transistor concerning the 2nd Embodiment of this invention.
  • (A)-(g) is typical sectional drawing which shows the manufacturing method of the thin-film transistor shown in FIG. 3 in order of a process.
  • FIG. 1A is a schematic cross-sectional view showing a thin film transistor according to the first embodiment of the present invention
  • FIG. 1B is a schematic view showing another example of the thin film transistor according to the first embodiment of the present invention.
  • the gate electrode 18 is formed on the surface 16 a of the inorganic surface protective film 16 on the substrate 12, and the gate insulating film 20 is formed on the surface 16 a of the inorganic surface protective film 16 so as to cover the gate electrode 18. Is formed.
  • An active layer 22 is formed on the surface 20 a of the gate insulating film 20.
  • a cap layer 24 that covers the channel region of the active layer 22 is provided on the surface 22 a of the active layer 22.
  • a source electrode 26 and a drain electrode 28 are formed on the surface 22a of the active layer 22 with a cap layer 24 interposed.
  • an organic substrate and a metal substrate having the following materials and configurations can be used as the flexible substrate.
  • flexible substrates include polyvinyl alcohol resins, polycarbonate derivatives (Teijin Limited: WRF), cellulose derivatives (cellulose triacetate, cellulose diacetate), polyolefin resins (Nippon Zeon Corporation: ZEONOR, ZEONEX).
  • the transistor 10 of this embodiment was set as the structure which provides the inorganic surface protective film 16, it is not limited to this. If the moisture, oxygen, and the like from the substrate 12 can be prevented in the same manner as the inorganic surface protective film 16 by only the planarizing film 14, the inorganic surface protective film 16 is not provided as in the transistor 10a shown in FIG. Also good. Thus, it is preferable to omit the inorganic surface protective film 16 because the manufacturing process can be simplified.
  • the influence of moisture on the active layer 22 is reduced by making the amount of the first moisture present in the gate insulating film 20 smaller than the amount of the second moisture present in the active layer 22. Therefore, the electrical property control of the active layer 22 and the stability of the electrical properties are improved. Thereby, in particular, the stability of the TFT characteristic control of the transistor due to moisture is improved, and the TFT characteristic of the transistor 10 can be stabilized.
  • a metal mask (not shown) in which openings are formed in the pattern of the gate electrode 18 is disposed on the surface 20 a of the gate insulating film 20.
  • a molybdenum film to be the gate electrode 18 is formed on the surface 20a of the gate insulating film 20 to a thickness of, for example, 50 nm from above the metal mask by using a DC sputtering method.
  • the gate electrode 18 is formed above the active layer 22 and at a position corresponding to the channel region.
  • a Mo film is formed on the surface 30b of the insulating film 30 as a conductive film to be the electrode 32 so as to fill the contact hole 30a.
  • the electrode 32 is patterned by using, for example, a photolithography method. As described above, the transistor 10b illustrated in FIG. 3 can be formed.
  • the effect of reducing the amount of the first moisture present in the gate insulating film to be smaller than the amount of the second moisture present in the active layer will be described in detail.
  • the electrical characteristics of a single film of the oxide semiconductor layer IGZO were grasped and the amount of H 2 O degas obtained by temperature programmed desorption analysis was calculated.
  • a test substrate in which an IGZO film 42 having a thickness of about 50 nm is formed on a film formation substrate 40 made of a synthetic quartz substrate is used for grasping the electrical characteristics and calculating the H 2 O degas amount. 50 was used.
  • a DC sputtering method was used as a method for forming the IGZO film 42.
  • the sputtering conditions were: the ultimate vacuum was about 3 ⁇ 10 ⁇ 6 Pa, the DC power was 50 W, the Ar gas flow rate was 30 SCCM, the O 2 gas flow rate was 0.3 SCCM, and the deposition pressure was 0.4 Pa.
  • the film formation time was about 18 minutes.
  • the film formation substrate 40 was set to room temperature (RT) without being heated.
  • the sheet resistance ( ⁇ / ⁇ ) was measured as the electrical characteristics of the IGZO film 42. This sheet resistance was measured with Hiresta MCP-HT450 manufactured by Mitsubishi Chemical Analytech. In the annealing treatment, the temperature was kept for 10 minutes on a hot plate and then lowered to room temperature.
  • Curve beta 1 shown in FIG. 6 shows the relationship between the annealing temperature and the sheet resistance indicates the change in sheet resistance by the annealing of the IGZO characteristics. The resistance has been reduced after the annealing temperature exceeds 150 ° C.
  • the IGZO characteristics shown in FIG. 6 are first defined as the electrical characteristics of IGZO alone.
  • the total accumulated H 2 O amount up to 600 ° C. from the SiO 2 film calculated by temperature rising desorption gas analysis (TDS) is about 3.1 ⁇ 10 21 pieces / cm 3 , and the accumulated H 2 O up to 200 ° C. The amount was about 4 ⁇ 10 20 pieces / cm 3 . Since the amount of H 2 O from the IGZO film shown in FIG. 7 was 1.4 ⁇ 10 20 pieces / cm 3 , it became clear that the amount of H 2 O degas was larger from the SiO 2 film, and the IGZO characteristics were sufficient. Will be affected. Therefore, it is necessary to make the amount of H 2 O (degas amount) in the SiO 2 film, that is, the gate insulating film 20 smaller than at least the amount of H 2 O in the IGZO film.
  • TDS temperature rising desorption gas analysis
  • the test substrate 52 shown in FIG. 9 is formed on the film formation substrate 40 under the above film formation conditions except that the SiO 2 film as the gate insulating film 20 has a thickness of 100 nm and the O 2 gas flow rate is 1 SCCM. did.
  • annealing was performed under vacuum (4 ⁇ 10 ⁇ 6 Pa) at a temperature of 200 ° C. for 30 minutes. Thereafter, the film formation substrate 40 and the SiO 2 film were cooled to room temperature, and then an IGZO film was formed to a thickness of 50 nm under the above film formation conditions. Thereafter, the sheet resistance was measured as described above as electrical characteristics.
  • Curve beta 3 shown in FIG. 14 shows the relationship between the annealing temperature and the sheet resistance indicates the change in sheet resistance by the annealing of the IGZO characteristics.
  • FIG. 14 also shows the sheet resistance (curve ⁇ 1 ) of the test substrate 50 shown in FIG.
  • the electrical characteristics when the SiO 2 film is annealed at a temperature of 200 ° C. approach the electrical characteristics of the IGZO film. Although it is on the high resistance side as a whole, the electrical characteristics of the IGZO film are further approximated by increasing the annealing time. As described above, the effect of annealing after forming the SiO 2 film as the gate insulating film 20 can be obtained.
  • FIG. 16 shows the amount of H 2 O released from the SiN film and the Ga 2 O 3 film, calculated by elevated temperature desorption gas analysis (TDS).
  • FIG. 16 also shows an active layer (IGZO film), an SiO 2 film having an O 2 gas flow rate of 1 SCCM, and an unannealed SiO 2 film, and an SiON film.
  • the SiN film and the Ga 2 O 3 film emit less H 2 O than the unannealed SiO 2 film, and the active layer (IGZO film) can be reduced by reducing the H 2 O amount. ) Can be reduced, and hence the influence can be eliminated.
  • the SiO 2 film, the SiN film, and the Ga 2 O 3 film have an electric field strength of 5 MV / cm, and leakage currents of 1 ⁇ 10 ⁇ 9 to 1 ⁇ 10 ⁇ 10 A / cm 2 . It can be used as a gate insulating film.
  • the thermal oxide film of SiO 2 had a leakage current of 3 ⁇ 10 ⁇ 10 A / cm 2 under the same conditions and an actually measured value.
  • transistors were manufactured by changing the type of the gate insulating film, and the TFT characteristics were compared.
  • a semiconductor parameter analyzer 4156C manufactured by Agilent Technologies
  • Vg-Ig characteristics representing transistor characteristics were measured.
  • the transistor characteristics were measured under the condition that the drain voltage (Vd) was fixed at 5 V, the gate voltage (Vg) was changed within the range of ⁇ 15 V to +15 V, and the drain current (Id) at each gate voltage (Vg) was measured.
  • the manufactured sample was a bottom gate TFT (channel length: 180 ⁇ m, channel width: 1 mm) shown in FIG.
  • FIG. 17A to 17E show a method for manufacturing the transistors of Experimental Examples 2 to 5.
  • FIG. 18A and 18B show a method for manufacturing the transistor of Experimental Example 1.
  • FIG. 17A a synthetic quartz substrate (trade name T-4040) is prepared as a substrate 60, and after alkaline ultrasonic cleaning, pure water rinsing is performed. Let dry for a minute.
  • a metal mask (not shown) in which openings are formed in the pattern of the gate electrode 18 is disposed above the surface 60 a of the substrate 60.
  • a molybdenum film to be the gate electrode 18 is formed on the surface 60a of the substrate 60 with a thickness of 50 nm from above the metal mask by DC sputtering. Thereby, the gate electrode 18 is formed as shown in FIG.
  • a metal mask (not shown) in which openings are formed in a pattern of the gate insulating film 20 is disposed on the surface 60a of the substrate 60 on which the gate electrode 18 is formed.
  • an RF 2 sputtering method is used to cover the gate electrode 18 with a SiO 2 film, a SiN film, or a Ga 2 O 3 film from above the metal mask depending on the film type to be the gate insulating film 20.
  • the substrate 60 is formed with a thickness of 100 nm on the surface 60a. Thereby, as shown in FIG. 17C, the gate insulating film 20 is formed. Note that the reactive gas shown in the following 2 is appropriately supplied to the gate insulating film 20 in accordance with the film type.
  • a metal mask (not shown) in which openings are formed in the pattern of the active layer 22 is disposed on the surface 20 a of the gate insulating film 20.
  • an IGZO film amorphous oxide semiconductor film
  • the active layer 22 is formed as shown in FIG. Note that DC sputtering is performed using, for example, a polycrystalline sintered body having a composition of InGaZnO 4 as a target and using Ar gas and O 2 gas as sputtering gases.
  • Example 1 Also in Experimental Example 1, an insulating film for protecting the active layer 22, the source electrode 26, and the drain electrode 28 is not formed because the element operating environment is in a dry air state. In this way, the device operation was confirmed for the configuration shown in FIG. In Example 1, a P-type silicon substrate (substrate 62) shown in FIG. 18B serves as a gate electrode.
  • Experimental Example 6 is a process shown in FIGS. 2A to 2G using a PEN film for the substrate 12, JM531 made by JSR Co., for the planarizing film 14, and SiON for the inorganic surface protective film 16. It was produced. Also in this Experimental Example 6, since the element operating environment is in a dry air state, an insulating film that protects the active layer 22, the source electrode 26, and the drain electrode 28 is not formed. In this way, the device operation was confirmed for the configuration shown in FIG.
  • the gate insulating film is a SiN film or a Ga 2 O 3 film. As shown in FIG. 16, the SiN film and the Ga 2 O 3 film are considered to be within an allowable range because the moisture content is smaller than the second moisture content of the active layer.

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PCT/JP2011/074289 2010-10-28 2011-10-21 薄膜トランジスタおよびその製造方法 Ceased WO2012057020A1 (ja)

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KR1020167014266A KR20160075763A (ko) 2010-10-28 2011-10-21 박막 트랜지스터 및 그 제조 방법
US13/871,305 US20130234135A1 (en) 2010-10-28 2013-04-26 Thin film transistor and method for manufacturing same

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