WO2011122408A1 - 多層セラミック基板およびその製造方法 - Google Patents
多層セラミック基板およびその製造方法 Download PDFInfo
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- WO2011122408A1 WO2011122408A1 PCT/JP2011/056915 JP2011056915W WO2011122408A1 WO 2011122408 A1 WO2011122408 A1 WO 2011122408A1 JP 2011056915 W JP2011056915 W JP 2011056915W WO 2011122408 A1 WO2011122408 A1 WO 2011122408A1
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- overcoat layer
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- multilayer ceramic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/30—Apparatus or processes specially adapted for manufacturing resistors adapted for baking
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/003—Thick film resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
Definitions
- FIG. 6 is a cross-sectional view showing a part of the multilayer ceramic substrate 51.
- the ceramic laminate 52 provided in the multilayer ceramic substrate 51, the resistor 54, the resistance connection conductor 55 having a portion overlapping with the resistor 54, and the resistor 54 formed on the main surface 53 are covered.
- An overcoat layer 56 is shown.
- the overcoat layer 56 is formed thin, due to differences in sintering behavior, thermal expansion coefficient, etc., between the ceramic laminate 52, the resistance connection conductor 55 and the resistor 54 and the overcoat layer 55 during firing. Cracks are likely to occur in the overcoat layer 56 due to the generated stress. In particular, cracks are likely to occur at portions where interfaces of different materials exist, such as portions 57 and 58 surrounded by a broken line in FIG. As described above, when a crack is generated, the plating solution that is carried out thereafter infiltrates below the overcoat layer 56 and the resistance value of the resistor 54 fluctuates, resulting in a decrease in reliability. cause.
- a multilayer ceramic substrate according to the present invention includes a ceramic laminate formed by laminating a plurality of ceramic layers, a resistor formed on at least one main surface of the ceramic laminate, and a resistance connection having a portion overlapping the resistor
- An overcoat layer covering the conductor and the resistor is provided, and a region of the overcoat layer that covers a portion where the resistor and the resistance connection conductor overlap is thicker than a region that covers the other portion.
- the region covering the other portion is typically a region where a trimming groove is to be formed when trimming is performed.
- the method for producing a multilayer ceramic substrate since the method includes a step of reducing the thickness of the overcoat layer by physically scraping the surface of the overcoat layer after the firing step, the overcoat layer is fired. Sometimes it is thicker, while on the other hand it can be thinned during trimming. Therefore, even when the resistor and the overcoat layer are formed by simultaneous firing with the ceramic green laminate, the overcoat layer is hardly cracked and the trimming property can be improved.
- the region covering the portion where the resistor and the resistance connection conductor overlap in the overcoat layer is made thicker than the region covering the other portion.
- the overcoat layer is thinned in the region covering the substrate, ie, the region to be trimmed to improve the trimming property, the resistor is damaged by, for example, thermal shock after firing and at the stage of becoming a product. Can be difficult. This is because stress is easily generated at the end portion of the portion where the resistor and the resistance connection conductor overlap, and therefore the resistor in this portion is easily damaged not only during firing but also after the above.
- the content of the glass component in the inorganic material component contained as a starting material in the overcoat layer is 50% by weight or more based on the total of the inorganic material components, The layer becomes easier to scrape, and the thickness adjustment of the overcoat layer becomes easier. This is because, in an inorganic material, it is easier to cut if it contains more glass components than a ceramic material.
- the multilayer ceramic substrate to be obtained includes the surface exposed conductor exposed from the overcoat layer, and further includes the step of plating the surface exposed conductor, as described above.
- the step of reducing the thickness of the overcoat layer is performed after the step of performing plating, the plating solution resistance decreases due to the decrease in the thickness of the overcoat layer, compared to the case of performing before the step of performing plating. Therefore, the thickness of the overcoat layer can be further reduced. This leads to an improvement in trimming properties.
- FIG. 1 is an enlarged cross-sectional view showing a portion where an overcoat layer is formed in a conventional multilayer ceramic substrate for explaining a problem to be solved by the present invention.
- the multilayer ceramic substrate 1 includes a ceramic laminate 3 formed by laminating a plurality of ceramic layers 2, a resistor 5 made of a thick film, formed on one main surface 4 a of the ceramic laminate 3, and a resistance A resistance connection conductor 6 having a portion overlapping the body 5 and an overcoat layer 7 covering the resistance body 5 are provided.
- the ceramic laminate 3 includes various wiring conductors.
- the wiring conductor is for forming a passive element such as a capacitor or an inductor, or for connecting wiring such as electrical connection between elements.
- the wiring conductor includes several in-plane wiring conductors 8 and interlayer connection conductors 9 formed inside the ceramic laminate 3. Some wiring conductors are formed on the outer surface of the ceramic laminate 3.
- the resistance connecting conductor 6 described above is covered with the overcoat layer 7 but is a kind of wiring conductor formed on the outer surface of the ceramic laminate 3. Further, as a wiring conductor formed on the outer surface of the ceramic laminate 3 and exposed from the overcoat layer 7, there is also a surface exposed conductor 10.
- the surface exposed conductor 10 is formed on both the one main surface 4 a and the other main surface 4 b of the ceramic laminate 3.
- the region 7 a that covers the portion where the resistor 5 and the resistance connection conductor 6 overlap in the overcoat layer 7 is preferably other portions, that is, typically, trimming is performed. It is preferable to make it thicker than the region 7b covering the portion to be applied. As a result, it is possible to prevent cracks due to thermal shock from being generated in the overcoat layer 7 after firing and further at the stage of becoming a product, while improving trimming properties.
- the multilayer ceramic substrate 1 shown in FIG. 3 is obtained through a step of firing the unfired composite laminate 11 shown in FIG.
- the unfired composite laminate 11 includes an unfired ceramic layer 12 corresponding to the ceramic layer 2, an unfired ceramic green laminate 13 corresponding to the ceramic laminate 3, and an unfired resistor 15 corresponding to the resistor 5.
- the unfired resistive connection conductor 16 corresponding to the resistance connection conductor 6, the unfired overcoat layer 17 corresponding to the overcoat layer 7, the unfired in-plane wiring conductor 18 corresponding to the in-plane wiring conductor 8, the interlayer connection
- An unfired interlayer connection conductor 19 corresponding to the conductor 9 and an unfired surface exposed conductor 20 corresponding to the surface exposed conductor 10 are provided.
- the unfired composite laminate 11 includes constraining green sheets 21 and 22 disposed on the main surfaces 14a and 14b, respectively.
- the constraining green sheets 21 and 22 include inorganic material powders that are not substantially sintered under the firing conditions in the firing step described below.
- the restraining green sheet 22 disposed on the main surface 14b on the side where the resistor 15 is not formed may be omitted.
- an unfired ceramic green laminate 13 formed by laminating a plurality of unfired ceramic layers 12 is first prepared.
- unfired resistance connection conductor 16 In-plane wiring conductor 18, interlayer connection conductor 19 and surface exposed conductor 20 are formed.
- an unfired resistor 15 is formed on one main surface 14a of the ceramic green laminate 13 described above, and an unfired overcoat layer 16 is formed thereon.
- the unfired resistor 15 is formed so as to partially overlap the unfired resistor connection conductor 16.
- the unfired resistance connection conductor 16 may be formed after the unfired resistor 15 is formed.
- the restraining green sheets 21 and 22 are arranged so as to sandwich the ceramic green laminate 13 on which the unfired resistor 15 and the overcoat layer 17 are formed in the laminating direction. In this way, an unfired composite laminate 11 is obtained.
- a ceramic green sheet to be the unfired ceramic layer 12 a resistor paste for forming the unfired resistor 15, an unfired Overcoat paste for forming overcoat layer 16, conductive paste for forming unfired resistance connection conductor 16, in-plane wiring conductor 18, interlayer connection conductor 19, and surface exposed conductor 20, respectively, and restraint Green sheets 21 and 22 are prepared.
- these ceramic green sheets are laminated in a predetermined order, thereby producing a ceramic green laminate 13 in which a plurality of unfired ceramic layers 12 are laminated.
- the constraining layer green sheets 21 and 22 are laminated so as to sandwich the ceramic green laminate 13 in the laminating direction.
- the overcoat green sheet a sheet having the same planar dimensions as the ceramic green sheet to be the unfired ceramic layer 12 may be used.
- the constraining layer derived from the constraining green sheets 21 and 22 is removed, whereby the multilayer ceramic substrate 1 in the state shown in FIG. 2 is taken out.
- the constraining layer is in a porous state, and thus can be easily removed.
- a step of plating the surface exposed conductor 10 is performed.
- a step of reducing the thickness of the overcoat layer 7 is performed.
- the step of reducing the thickness of the overcoat layer 7 is performed after the step of performing plating.
- a step of reducing the thickness of the overcoat layer 7 is performed. This step is intended to increase the efficiency of a trimming step that can be performed thereafter. Specifically, steps such as wet blasting, sand blasting, chemical blasting, and polishing are performed to physically scrape the surface of the overcoat layer.
- the plating step is interposed between the constraining layer removing step and the step of reducing the thickness of the overcoat layer.
- the thickness of the overcoat layer is subsequently reduced. You may implement a process. In the latter case, there is an advantage that the surface of the overcoat layer can be scraped off continuously using the same equipment as the constraining layer removing step.
- the region 7a covering the portion where the resistor 5 and the resistance connection conductor 6 overlap in the overcoat layer 7 is more than the other portion, that is, the region 7b typically covering the portion to be trimmed. Also thickened.
- the overcoat layer 7 includes an inorganic material component as a starting material
- the inorganic material component includes a glass component
- the content of the glass component is 50% by weight or more based on the total of the inorganic material components
- a step of trimming the resistor 5 is performed as necessary.
- the laser beam 25 is applied to the resistor 5 through the overcoat layer 7.
- trimming can be efficiently performed.
- region 7a covering the portion where the resistor 5 and the resistance connection conductor 6 overlap in the overcoat layer 7 is thicker than the region 7b covering the other portion may be as shown in FIG. .
- a more limited region 7 a that covers a portion where the resistor 5 and the resistance connection conductor 6 overlap is made thicker than a region 7 b that covers the other portion.
- the overcoat layer 7 having such a form is formed in a region 7 b other than the region 7 a covering the portion where the resistor 5 and the resistance connection conductor 6 overlap in the overcoat layer 7. It can be easily formed by blasting the surface of the overcoat layer 7 through the mask 31 having the facing opening 32.
- a region covering a portion where the unfired resistor 15 and the resistance connection conductor 16 overlap is set as another region. If the thickness of the overcoat layer 7 is reduced over the entire thickness of the overcoat layer 7 after being formed thicker in advance, the region covering the portion of the overcoat layer 7 where the resistor 5 and the resistance connection conductor 6 overlap. 7a can be easily made thicker than the region 7b covering the other part.
- the unfired resistor 15 and the resistance connection conductor are increased by increasing the number of times of printing.
- a region covering a portion overlapping with 16 can be formed thicker.
- the mask 31 as described above may be used, or the region 7a may be formed thicker in advance.
- Example 1 A SiO 2 —CaO—B 2 O 3 —Al 2 O 3 based crystallized glass powder was prepared as a glass material, and an alumina powder was prepared as a ceramic material.
- the glass powder, the alumina powder, and the acrylic binder and dispersant are weighed so that the weight ratio is 55: 45: 10: 2, and a solvent is added to them and mixed in a ball mill. Then, a slurry was prepared, and then the slurry was formed into a sheet shape by a doctor blade method to obtain a ceramic green sheet having a thickness of 200 ⁇ m.
- This ceramic green sheet is for forming a ceramic layer provided in a ceramic laminate, and for these ceramic green sheets, an in-plane wiring conductor is suitably formed by screen printing using a silver paste, and a surface layer and Similarly, the silver paste was used for the ceramic green sheet to be formed, and a resistance connection conductor and a surface exposed conductor were formed by screen printing.
- RuO 2 30 parts by weight
- SiO 2 —CaO—Al 2 O 3 —B 2 O 3 —K 2 O glass 70 parts by weight
- Ag 5 parts by weight
- resin 6 parts by weight
- a resistor paste containing 1 part by weight of a dispersant and 50 parts by weight of a solvent is prepared, and this resistor paste is screen-printed on a ceramic green sheet to be a surface layer, whereby the above-mentioned resistor connecting conductor and A partially overlapping resistor was formed.
- inorganic material component 100 parts by weight, resin: 6 parts by weight, and dispersion including the above-mentioned glass powder and alumina powder in a weight ratio shown in “Glass / alumina weight ratio of overcoat material” in Table 1
- the overcoat layer is formed by preparing an overcoat paste containing 1 part by weight of the agent and 50 parts by weight of the solvent and applying the overcoat paste by screen printing so as to cover the entire resistor. did.
- the overcoat layer was made to have the thickness shown in the column of “overcoat thickness after firing” in Table 1 after firing.
- the “post-firing overcoat thickness” shown in Table 1 is a thickness in a region covering the resistor in a portion that does not overlap the resistance connection conductor.
- alumina powder, dispersant, and butyral binder are weighed so as to have a weight ratio of 100: 2: 8, and a solvent is added thereto and mixed in a ball mill to prepare a slurry.
- the slurry was formed into a sheet by a doctor blade method to obtain a restraining green sheet having a thickness of 200 ⁇ m.
- This firing condition is a condition in which the constraining green sheet is not sintered, but the ceramic green sheet, the overcoat layer, the resistor, and the conductor can be sufficiently sintered.
- the resistor was laser trimmed, the resistance value was adjusted, and the trimming speed was obtained as shown in the “Trimming speed” column of Table 1. .
- the multilayer ceramic substrate according to each sample was evaluated for the presence or absence of cracks in the overcoat layer and the plating solution resistance, as shown in the “crack” and “anti-plating” columns of Table 1, respectively.
- the “crack” is a part to be evaluated is diced and hardened with a cured resin, a sample cross section is polished, this cross section is observed with an SEM, and the presence or absence of cracks is evaluated. Evaluation was performed.
- Platinum resistance is a comparison between the resistance values of the resistors covered by the overcoat layer before and after the plating treatment, and if the resistance value variation of all the resistors is less than ⁇ 0.5%, It was determined that the plating solution was good, and if there was one or more resistors whose resistance value exceeded ⁇ 0.5%, it was determined that the plating solution resistance was poor. The number of evaluations was 135 for each sample. In “Plating Resistance” in Table 1, “G” indicates that the plating solution resistance was good, and “NG” indicates that the plating solution resistance was inferior.
- Samples 4 and 5 which are within the scope of the present invention, have the same crack thickness as the above-mentioned Samples 2 and 1, but the “overcoat thickness after thickness reduction” is the same.
- the plating solution resistance was good and the trimming speed was almost the same.
- the same is true between samples 9 and 10 and samples 7 and 6, between samples 14 and 15 and samples 12 and 11, and between samples 19 and 20 and samples 17 and 16. This can also be said in the comparison.
- the overcoat layer during plating that is, the “overcoat thickness after firing” is 10 ⁇ m as in sample 1, the plating solution resistance is poor. Yes, as in Samples 2 and 3, when the thickness is 12 ⁇ m or more, the plating solution resistance is good. That is, under the conditions of Samples 1 to 5, there is a restriction that the thickness of the overcoat layer must be 12 ⁇ m or more at the time of plating in order to ensure good plating solution resistance. Therefore, in the sample 4 whose “thickness reduction timing” is “before plating”, in order to ensure good plating solution resistance, the overcoat layer can be used only until the “overcoat thickness after thickness reduction” becomes 12 ⁇ m. The thickness of can not be reduced. On the other hand, in Sample 5, the “thickening timing” is “after plating”, so that the thickness of the overcoat layer can be reduced to 10 ⁇ m or less, which is less than 12 ⁇ m. it can.
- the “post-baking overcoat thickness” is both “8 ⁇ m”
- the “glass / alumina weight ratio of the overcoat material” is In Example 6, “70/30” and Sample 13 “50/50”
- the content of alumina is higher in this order.
- the “post-baking overcoat thickness” is “7 ⁇ m” thinner than that in the sample 6, but the “glass / alumina weight ratio of the overcoat material” is “40 / 60 ”and so on.
- the sample 17 is considered to be good although the “post-baking overcoat thickness” is the thinnest.
- the fired composite laminate was wet blasted to remove the constraining layer derived from the constraining green sheet on the surface, and the sintered multilayer ceramic substrate according to each sample was taken out. Thereafter, the multilayer ceramic substrate according to each sample was subjected to a plating process on the surface-exposed conductor, followed by a wet blasting process to reduce the thickness of the overcoat layer.
- the thickness was uniformly reduced over the entire overcoat layer, but for sample 22, a portion where the resistor and the resistance connection conductor overlap from the middle of the step. The thickness was reduced through a mask having an opening facing an area other than the covered area.
- the minimum thickness in the region covering the portion where the resistor and the resistance connection conductor overlap in the overcoat layer and the average thickness in the other region were determined.
- Table 2 the former is shown in the “resistance + conductor overcoat minimum thickness” column, and the latter is shown in the “resistance overcoat average thickness” column.
- the resistor was laser trimmed and the resistance value was adjusted, as shown in the “Trimming speed” column of Table 2.
- the trimming speed was determined, and as shown in the “crack” column of Table 2, the presence or absence of cracks in the overcoat layer was evaluated.
- the plating solution resistance was evaluated.
- a “heat cycle test” in which 2000 cycles of a heat cycle from ⁇ 40 ° C. to 250 ° C. was applied to the multilayer ceramic substrate according to each sample. Then, in the evaluation number of 135, when there was one or more resistors whose resistance value fluctuated by ⁇ 0.5% or more compared to the resistance value before the “heat cycle test”, it was determined as defective.
- the “heat cycle test” of Table 1 “G” indicates that it was not determined to be defective, and “NG” indicates that it was determined to be defective.
- the sample 21 shown in Table 2 corresponds to the sample 5 shown in Table 1 as can be seen from the above description.
- the sample 22 When compared with the sample 21, the sample 22 has the same “average overcoat thickness on resistance”, and shows the same results in terms of “crack”, “plating resistance” and “trimming speed”. However, when compared in terms of the “heat cycle test”, the sample 21 was “NG” while the sample 22 was “G”.
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Abstract
Description
ガラス材料として、SiO2-CaO-B2O3-Al2O3系結晶化ガラス粉末を用意するとともに、セラミック材料として、アルミナ粉末を用意した。
実験例2では、オーバーコート層における、抵抗体と抵抗接続導体とが重なる部分を覆う領域が、その他の部分を覆う領域よりも厚くした場合の影響を調査した。
2 セラミック層
3 セラミック積層体
5 抵抗体
6 抵抗接続導体
7 オーバーコート層
10 表面露出導体
11 未焼成の複合積層体
12 未焼成のセラミック層
13 セラミックグリーン積層体
15 未焼成の抵抗体
16 未焼成の抵抗接続導体
17 未焼成のオーバーコート層
20 未焼成の表面露出導体
21,22 拘束用グリーンシート
25 レーザ光
31 マスク
32 開口
Claims (8)
- 複数のセラミックグリーン層を積層してなるセラミックグリーン積層体を備えるとともに、前記セラミックグリーン積層体の少なくとも一方の主面にそれぞれ形成された、抵抗体、前記抵抗体と重なる部分を有する抵抗接続導体、および前記抵抗体を覆うオーバーコート層を備える、未焼成の多層セラミック基板を作製する工程と、
前記未焼成の多層セラミック基板を焼成する工程と
を有する、多層セラミック基板の製造方法であって、
前記焼成工程の後に前記オーバーコート層の表面を物理的に削り取ることにより前記オーバーコート層の厚みを減じる工程をさらに備える、多層セラミック基板の製造方法。 - 前記オーバーコート層は出発原料として無機材料成分を含み、前記無機材料成分はガラス成分を含み、前記ガラス成分の含有量は前記無機材料成分の合計に対して50重量%以上である、請求項1に記載の多層セラミック基板の製造方法。
- 得ようとする多層セラミック基板は、前記オーバーコート層から露出する表面露出導体を備え、
前記表面露出導体にめっきを施す工程をさらに備え、
前記オーバーコート層の厚みを減じる工程は、前記めっきを施す工程の後に実施される、
請求項1または2に記載の多層セラミック基板の製造方法。 - 前記オーバーコート層の厚みを減じる工程において、前記オーバーコート層における、前記抵抗体と前記抵抗接続導体とが重なる部分を覆う領域は、その他の部分を覆う領域よりも厚くなるようにされる、請求項1ないし3のいずれかに記載の多層セラミック基板の製造方法。
- 前記オーバーコート層の厚みを減じる工程は、前記オーバーコート層における、前記抵抗体と前記抵抗接続導体とが重なる部分を覆う領域以外の領域に向く開口を有するマスクを介して、前記オーバーコート層の表面をブラスト処理する工程を備える、請求項4に記載の多層セラミック基板の製造方法。
- 未焼成の多層セラミック基板を作製する工程において、前記オーバーコート層は、前記抵抗体と前記抵抗接続導体とが重なる部分を覆う領域が他の領域に比べて予め厚く形成される、請求項4に記載の多層セラミック基板の製造方法。
- 前記焼成工程における焼成条件では実質的に焼結しない無機材料粉末を含む拘束用グリーンシートを用意する工程をさらに備え、
前記未焼成の多層セラミック基板を作製する工程は、前記セラミックグリーン積層体の、前記抵抗体が形成された主面を含む少なくとも一方の前記主面に沿って前記拘束用グリーンシートを積層してなる未焼成の複合積層体を作製する工程を含み、
前記焼成工程は、前記未焼成の複合積層体に対して実施され、
焼成工程の後に前記拘束用グリーンシートに由来する拘束層を除去する工程をさらに備える、
請求項1ないし6のいずれかに記載の多層セラミック基板の製造方法。 - 複数のセラミック層を積層してなるセラミック積層体と、
前記セラミック積層体の少なくとも一方の主面にそれぞれ形成された、抵抗体、前記抵抗体と重なる部分を有する抵抗接続導体、および前記抵抗体を覆うオーバーコート層と
を備え、
前記オーバーコート層における、前記抵抗体と前記抵抗接続導体とが重なる部分を覆う領域は、その他の部分を覆う領域よりも厚い、
多層セラミック基板。
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DE112011100633T DE112011100633T5 (de) | 2010-03-31 | 2011-03-23 | Mehrschichtkeramiksubstrat und Verfahren zum Herstellen desselben |
JP2012508232A JP5397539B2 (ja) | 2010-03-31 | 2011-03-23 | 多層セラミック基板およびその製造方法 |
US13/627,013 US8754742B2 (en) | 2010-03-31 | 2012-09-26 | Multilayer ceramic substrate and method for producing the same |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01147897A (ja) * | 1987-12-03 | 1989-06-09 | Nec Corp | 多層複合セラミック基板の製造方法 |
JP2001168500A (ja) * | 1999-12-08 | 2001-06-22 | Yamaichi Electronics Co Ltd | 配線基板 |
JP2008277628A (ja) * | 2007-05-01 | 2008-11-13 | Murata Mfg Co Ltd | セラミック基板の製造方法、セラミック基板、および電子装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4650923A (en) * | 1984-06-01 | 1987-03-17 | Narumi China Corporation | Ceramic article having a high moisture proof |
JPS6165464A (ja) * | 1984-09-07 | 1986-04-04 | Toshiba Corp | 厚膜多層基板における膜抵抗体の製造方法 |
JPS63141301A (ja) * | 1986-12-03 | 1988-06-13 | 富士通テン株式会社 | 厚膜回路製造方法 |
JPH05234726A (ja) | 1992-02-20 | 1993-09-10 | Murata Mfg Co Ltd | 厚膜抵抗回路の形成方法 |
US5396397A (en) * | 1992-09-24 | 1995-03-07 | Hughes Aircraft Company | Field control and stability enhancement in multi-layer, 3-dimensional structures |
US6205032B1 (en) * | 1999-03-16 | 2001-03-20 | Cts Corporation | Low temperature co-fired ceramic with improved registration |
JP3687443B2 (ja) * | 1999-10-12 | 2005-08-24 | 株式会社村田製作所 | 低温焼成セラミック組成物及びセラミック多層基板 |
JP2002368420A (ja) * | 2001-06-05 | 2002-12-20 | Murata Mfg Co Ltd | ガラスセラミック多層基板の製造方法およびガラスセラミック多層基板 |
US6893710B2 (en) * | 2003-04-18 | 2005-05-17 | Yageo Corporation | Multilayer ceramic composition |
JP2005039164A (ja) | 2003-06-25 | 2005-02-10 | Kyocera Corp | ガラスセラミック配線基板の製造方法 |
TWI266568B (en) * | 2004-03-08 | 2006-11-11 | Brain Power Co | Method for manufacturing embedded thin film resistor on printed circuit board |
JP3928665B2 (ja) * | 2004-09-13 | 2007-06-13 | 株式会社村田製作所 | チップ型電子部品内蔵型多層基板及びその製造方法 |
JP5071559B2 (ja) * | 2009-01-20 | 2012-11-14 | 株式会社村田製作所 | 積層型セラミック電子部品およびその製造方法 |
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- 2011-03-23 WO PCT/JP2011/056915 patent/WO2011122408A1/ja active Application Filing
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01147897A (ja) * | 1987-12-03 | 1989-06-09 | Nec Corp | 多層複合セラミック基板の製造方法 |
JP2001168500A (ja) * | 1999-12-08 | 2001-06-22 | Yamaichi Electronics Co Ltd | 配線基板 |
JP2008277628A (ja) * | 2007-05-01 | 2008-11-13 | Murata Mfg Co Ltd | セラミック基板の製造方法、セラミック基板、および電子装置 |
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US20130027175A1 (en) | 2013-01-31 |
US8754742B2 (en) | 2014-06-17 |
JPWO2011122408A1 (ja) | 2013-07-08 |
DE112011100633T5 (de) | 2013-06-20 |
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