Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/82—Heterojunctions
  • H10D62/826—Heterojunctions comprising only Group II-VI materials heterojunctions, e.g. CdTe/HgTe heterojunctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• This disclosure relates generally to semiconductor devices. More specifically, this disclosure relates to normally- off gallium nitride-based semiconductor devices.
• III-V compounds are being investigated for use in high-power electronics applications. These compounds include III-V nitrides such as gallium nitride (GaN) , aluminum gallium nitride (AlGaN) , and aluminum indium gallium nitride (AlInGaN) . These compounds can be used to form High Electron Mobility Transistors (HEMTs) for use in high-power high-voltage applications .
• HEMTs High Electron Mobility Transistors
• FIGURE 1 illustrates a first example normally-off gallium nitride-based semiconductor device according to this di sclosure ;
• FIGURE 2 illustrates example polarizations in the semiconductor device of FIGURE 1 according to this disclosure
• FIGURE 3 illustrates an example band diagram associated with the semiconductor device of FIGURE 1 according to this disclosure ;
• FIGURES 4A and 4B illustrate example relationships between electrical characteristics and composition of the semiconductor device of FIGURE 1 according to this disclosure
• FIGURE 5 illustrates a second example normally-off gallium nitride-based semiconductor device according to this disclosure.
• FIGURE 6 illustrates an example method for forming a normally-off gallium nitride-based semiconductor device according to this disclosure.
• FIGURES 1 through 6, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the invention may be implemented in any type of suitably arranged device or system.
• FIGURE 1 illustrates a first example normally-off gallium nitride-based semiconductor device 100 according to this disclosure.
• the semiconductor device 100 is formed over a substrate 102.
• the substrate 102 represents any suitable semiconductor substrate that supports or carries other structures of the semiconductor device 100.
• the substrate 102 could, for example, represent a silicon, sapphire, or silicon carbide substrate.
• a buffer layer 104 is formed over the substrate 102.
• the buffer layer 104 typically represents a thin layer used to help isolate other structures in the semiconductor device 100 from the substrate 102 (such as from defects in the substrate 102) .
• the buffer layer 104 could be formed from any suitable material (s) and in any suitable manner.
• the buffer layer 104 could represent an epitaxial layer, such as a gallium nitride (GaN) or aluminum gallium nitride (AlGaN) epitaxial layer.
• a relaxed layer 106 is formed over the buffer layer 104.
• the ' relaxed layer 106 represents an active layer formed from material (s) generally not under tensile or compressive stress or under only a small amount of tensile or compressive stress.
• the relaxed layer 106 could be formed from any suitable material (s) and in any suitable manner.
• the relaxed layer 106 could represent a GaN epitaxial layer.
• a tensile layer 108 is formed over the relaxed layer 106.
• the tensile layer 108 represents a barrier layer formed from material (s) under tensile stress.
• the tensile layer 108 could be formed from any suitable material (s) and in any suitable manner.
• the tensile layer 108 could represent an AlGaN epitaxial layer. Note that the aluminum concentration (if any) in the buffer layer 104 could be much less than the aluminum concentration in the tensile layer 108.
• a compressive layer 110 is formed over the tensile layer 108.
• the compressive layer 110 represents a barrier layer formed from material (s) under compressive stress.
• the compressive layer 110 could be formed from any suitable material (s) and in any suitable manner.
• the compressive layer 110 could be formed by depositing an epitaxial layer of AlInGaN and etching the AlInGaN to leave a portion of the AlInGaN over the tensile layer 110.
• the compressive layer 110 could also be formed by depositing AlInGaN in a specified area defined by a mask. Note that the aluminum concentration (if any) in the buffer layer 104 could be much less than the aluminum concentration in the compressive layer 110.
• a source region 112 and a drain region 114 are formed in the tensile layer 108 and possibly in the relaxed layer 106.
• the source region 112 and the drain region 114 could be formed in any suitable manner, such as by masking the structure and performing a doping process (like an implantation or diffusion process). Also, any suitable dopant (s) could be used to form each of the source and drain regions 112-114.
• a gate 116 is formed over the compressive layer 110.
• the gate 116 could be formed from any suitable conductive material (s) and in any suitable manner.
• the gate 116 could be formed by depositing conductive material (s) over the structure and etching the conductive material (s) to form the gate 116.
• the gate 116 could also be formed by depositing conductive material (s) in a specified area defined by a mask.
• many conventional GaN-based transistor devices operate in a normally-on state or in a depletion mode.
• strain engineering is used in the semiconductor device 100 to compensate for the spontaneous polarization.
• the strain engineering is also used to invert the charge generated at the relaxed layer /tensile layer interface.
• FIGURE 2 illustrates example polarizations in the semiconductor device 100 of FIGURE 1.
• spontaneous polarization P S p in the layers 106 and 110 are in the same direction, but piezoelectric polarization P PE in the layer 110 is in the opposite direction. This can generate a depleted electron region under the gate 116.
• the source and drain regions 112-114 may have electrons accumulate at their interfaces with the layers 106-108.
• the compressive layer 110 is used to compensate for the spontaneous polarization.
• the compressive layer 110 is formed from AlInGaN
• the aluminum composition could be about 20%
• the indium composition could be about 20%.
• a compressive strain is generated on top of the tensile layer 108, which can result in a total strain that is slightly compressive.
• the AlInGaN compressive layer 110 could generate as much as 0.04C/m 2 of polarization, which can be slightly higher and opposite to the total spontaneous polarization in the device 100.
• FIGURE 3 illustrates an example band diagram 300 associated with the semiconductor device 100 of FIGURE 1.
• the threshold voltage V T of the device 100 can be adjusted using the strain in the compressive layer 110 to compensate for the spontaneous polarization.
• a piezoelectric polarization that is greater than or equal to the spontaneous polarization, at a zero gate voltage bias there may be little or no two-dimensional electron gas formed at the relaxed layer/tensile layer interface or at the relaxed layer/buffer layer interface.
• FIGURES 4A and 4B illustrate example relationships between electrical characteristics and composition of the semiconductor device 100 of FIGURE 1.
• FIGURE 4A shows a graph 400 illustrating how the spontaneous polarization P S p in the device 100 varies based on the indium component of the compressive layer 110 (assuming an AlInGaN compressive layer with 20% aluminum) .
• the spontaneous polarization P S p varies but only slightly, increasing only about 0.0008C/m 2 for an indium component that varies from a zero mole fraction to a 0.25 mole fraction.
• FIGURE 4B shows a graph 450 illustrating how the piezoelectric polarization P PE in the device 100 varies based on the indium component of the compressive layer 110 (assuming an AlInGaN compressive layer with 20% aluminum) . As shown here, the piezoelectric polarization P PE varies to a much greater extent, increasing more than 0.05C/m for an indium component that varies from a zero mole fraction to a 0.25 mole fraction.
• These graphs 400 and 450 illustrate that the indium component of an AlInGaN compressive layer 110 can be adjusted to arrive at a suitable piezoelectric polarization P PE .
• This piezoelectric polarization P PE can be selected so that it is slightly larger than the spontaneous polarization P SP .
• FIGURE 5 illustrates a second example normally-off gallium nitride-based semiconductor device 500 according to this disclosure.
• the semiconductor device 500 includes a substrate 502, a buffer layer 504, and a relaxed layer 506. These components 502-506 may be the same as or similar to the corresponding components 102-106 in FIGURE 1.
• a compressive layer 508 is formed over the relaxed layer 506.
• the compressive layer 508 could be formed from any suitable material (s) and in any suitable manner.
• the compressive layer 508 could be formed by depositing an epitaxial layer of AlInGaN and etching the AlInGaN to leave a portion of the AlInGaN over the relaxed layer 506.
• the compressive layer 508 could also be formed by depositing AlInGaN in a specified area defined by a mask. Again, the compressive layer 508 has enough compressive strain to compensate for the total spontaneous polarization generated in the semiconductor device 500.
• a tensile layer 510 is formed over the relaxed layer
• the tensile layer 510 could be formed from any suitable material (s) and in any suitable manner.
• the tensile layer 510 could be formed from AlGaN.
• the tensile layer 510 could be formed by a selective epitaxial growth of AlGaN with a 20% aluminum content.
• Source and drain regions 512-514 are formed in the tensile layer 510 and possibly in the relaxed layer 506, and a gate 516 is formed over the compressive layer 508.
• two-dimensional electron gas can still form at the interface between the source region 112 and the layers 106-108 and at the interface between the drain region 114 and the layers 106-108.
• two-dimensional electron gas can form at the interface between the source region 512 and the layers 506 and 510 and at the interface between the drain region 514 and the layers 506 and 510.
• This two-dimensional electron gas helps to provide high current and low specific-on resistance.
• the two-dimensional electron gas is located away from the gates 116 and 516 in areas where it does not cause the semiconductor devices 100 and 500 to be normally on.
• the two-dimensional electron gas can form in the semiconductor devices 100 and 500 because the compressive layers 110 and 508 are etched away from or not formed where the source and drain regions are located.
• FIGURES 1 through 5 illustrate two example normally-off gallium nitride-based semiconductor devices and related details
• various changes may be made to FIGURES 1 through 5.
• any other materials and manufacturing processes could be used to form various layers or other structures of the semiconductor devices 100 and 500.
• specific electrical or other characteristics are described above, these details are examples only.
• FIGURE 6 illustrates an example method 600 for forming a normally-off gallium nitride-based semiconductor device according to this disclosure.
• a buffer layer is formed over a substrate at step 602. This could include, for example, forming the buffer layer 104, 504 over the substrate 102, 502.
• a relaxed layer is formed over the buffer layer at step 604. This could include, for example, forming the relaxed layer 106, 506 over the buffer layer 104, 504. Both layers could represent epitaxial layers.
• Tensile and compressive layers are formed over the relaxed layer at step 606. This could include, for example, forming the tensile layer 108 over the relaxed layer 106 and forming the compressive layer 110 over the tensile layer 108. This could also include forming the compressive layer 508 over the relaxed layer 506 and forming the tensile layer 510 over the relaxed layer 506 and next to the compressive layer 508.
• the compressive layer has a piezoelectric polarization P PE that is greater than or equal to the spontaneous polarization P s p in the structure .
• Source, drain, and gate structures are formed at step 608. This could include, for example, forming source and drain regions 112-114, 512-514 in the tensile layer 108, 510 and optionally in the relaxed layer 106, 506. Formation of the semiconductor device is completed at step 610. This could include, for example, forming electrical connections to the source, drain, and gate structures. This could also include encapsulating the semiconductor device 100, 500 in a protective package or forming other structures to complete the formation of an HEMT transistor device.
• FIGURE 6 illustrates one example of a method 600 for forming a normally-off gallium nitride-based semiconductor device
• various changes may be made to FIGURE 6.
• steps in FIGURE 6 could overlap, occur in parallel, or occur in a different order.
• piezoelectric polarization management through strain can be obtained in many different ways, and the method 600 illustrates one example of this.

Landscapes

• Junction Field-Effect Transistors (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

Family

ID=44308311

Family Applications (1)

Country Status (5)

Families Citing this family (12)

Family Cites Families (26)

• 2010
  • 2010-01-27 US US12/657,757 patent/US8802516B2/en active Active
• 2011
  • 2011-01-26 TW TW100102794A patent/TWI574325B/zh active
  • 2011-01-27 CN CN201180014938.3A patent/CN102812554B/zh active Active
  • 2011-01-27 JP JP2012551278A patent/JP2013518445A/ja active Pending
  • 2011-01-27 WO PCT/US2011/022678 patent/WO2011094382A2/en not_active Ceased
• 2014
  • 2014-06-30 US US14/319,490 patent/US9385199B2/en active Active

Also Published As

Similar Documents

Legal Events