WO2011081428A2 - Ｐｏｐ 패키지 및 그 제조 방법 - Google Patents

Ｐｏｐ 패키지 및 그 제조 방법 Download PDF

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Publication number
WO2011081428A2
WO2011081428A2 PCT/KR2010/009468 KR2010009468W WO2011081428A2 WO 2011081428 A2 WO2011081428 A2 WO 2011081428A2 KR 2010009468 W KR2010009468 W KR 2010009468W WO 2011081428 A2 WO2011081428 A2 WO 2011081428A2
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WIPO (PCT)
Prior art keywords
solder ball
package
semiconductor chip
substrate
semiconductor
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PCT/KR2010/009468
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English (en)
French (fr)
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WO2011081428A3 (ko
Inventor
이현우
Original Assignee
하나마이크론㈜
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Application filed by 하나마이크론㈜ filed Critical 하나마이크론㈜
Priority to EP10841260.2A priority Critical patent/EP2521170A4/en
Priority to BR112012012520-6A priority patent/BR112012012520A2/ko
Priority to US13/510,382 priority patent/US20120326306A1/en
Publication of WO2011081428A2 publication Critical patent/WO2011081428A2/ko
Publication of WO2011081428A3 publication Critical patent/WO2011081428A3/ko

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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to a POP package and a method for manufacturing the same, and more particularly, to a POP package and a method for manufacturing the same, which can prevent a package defect caused by a top gate mold method by improving a laminated structure by solder balls.
  • semiconductor package technology is a method such as a package in package (PIP) and a package on package (POP) for mounting a plurality of semiconductor chips in a semiconductor package.
  • PIP package in package
  • POP package on package
  • Such a semiconductor package is required to reduce the thickness while stacking a plurality of semiconductor chips.
  • the POP package forms an upper semiconductor package and a lower semiconductor package each having semiconductor chips mounted on a substrate, and the upper semiconductor is molded in a commonly used transfer mold method, and the lower semiconductor is essentially a top gate.
  • the upper semiconductor package is stacked on the lower semiconductor package by Solder Bump Mount (SBM).
  • the conventional POP package has a problem in that it is caused by intrinsic defects such as die top delamination, mold flash, and cold solder due to warpage. have.
  • the present invention is to provide a POP package and a manufacturing method that can implement a POP package using a transfer mold method without using a top gate mold method.
  • the present invention for solving the above problems is formed by removing the upper part of the first solder ball and the first solder ball and the semiconductor chip formed on the upper side of the substrate and the upper surface of the substrate to expose a portion of the first solder ball formed A lower semiconductor package including a mold; And an upper semiconductor package including the at least one semiconductor chip stacked to be electrically connected to an exposed portion of the first solder ball through a second solder ball formed at a lower side.
  • the mold of the lower semiconductor package may be characterized in that the upper portion is removed by means of grinding or polishing.
  • the present invention also provides a semiconductor package comprising: a lower semiconductor package including a first solder ball and a semiconductor chip formed on an upper side of a substrate, and a mold molding the semiconductor chip and the first solder ball to expose a portion of the first solder ball; And an upper semiconductor package stacked to be connected to an exposed portion of the first solder ball through a second solder ball formed on a lower surface thereof.
  • At least one of the lower semiconductor package and the upper semiconductor package may be a multi-chip package.
  • the mold is a POP package, characterized in that the molding height of the solder ball is smaller than the molding height of the semiconductor chip.
  • the present invention provides a method for manufacturing a POP package, comprising: preparing a substrate on which an upper semiconductor package and a semiconductor chip are stacked; Solder ball forming step of forming a first solder ball on the upper side of the substrate; Molding the semiconductor chip and the first solder ball to expose a portion of the first solder ball; And stacking the upper semiconductor package on the lower semiconductor package to be electrically connected to an exposed portion of the first solder ball through a second solder ball formed on a lower surface of the upper semiconductor package.
  • the molding step may be molded so that the molding height of the solder ball is smaller than the molding height of the semiconductor chip.
  • the molding step may include a flash removing step of removing a mold flash formed on an exposed portion of the first solder ball.
  • the molding step may include removing a portion of the exposed upper portion of the first solder ball.
  • POP package and its manufacturing method according to the present invention by improving the laminated structure by the solder ball to implement the POP package without using the top gate mold method by the separation phenomenon according to the top gate mold method, mold flash, cold solder etc. There is an effect that can prevent the defect.
  • FIG. 1 is a cross-sectional view of a POP package according to an embodiment of the present invention
  • FIG. 2 is a flowchart illustrating a method of manufacturing a POP package according to an embodiment of the present invention.
  • 3A to 3G are diagrams illustrating a method of manufacturing a POP package according to an embodiment of the present invention.
  • connection terminal 114 connection terminal
  • connection terminal 220 third semiconductor chip
  • FIG. 1 is a cross-sectional view of a POP package according to an embodiment of the present invention.
  • the POP package includes an upper semiconductor package 100 in which the first semiconductor chip 120 and the second semiconductor chip 130 are mounted on the first substrate 110, the third semiconductor chip 220, and the fourth semiconductor chip 230.
  • the lower semiconductor package 200 mounted on the second substrate 210 is included.
  • the upper semiconductor package 100 may include a first substrate 110, a first semiconductor chip 120 mounted on the first substrate 110, a second semiconductor chip 130 bonded to the first semiconductor chip 120, and wires.
  • a wire 140 for bonding, a mold 150 for molding the upper semiconductor package 100, and a second solder ball 160 connected to the second substrate 210 are included.
  • the upper semiconductor package 100 is a multi-chip package.
  • the upper semiconductor package 100 may be configured as a single chip.
  • a second solder ball 160 is formed on an external connection terminal (not shown) on the bottom surface, and the first semiconductor chip 120 and the second semiconductor chip 130 are connected to both sides of the top surface. Connection terminals 112 and 114 are formed.
  • the first semiconductor chip 120 is bonded to the upper surface of the first substrate 110 through an adhesive or the like, and chip pads 122 are formed on both sides thereof, and the chip pad 122 is a connection terminal of the first substrate 110. And electrically connected to 112.
  • the second semiconductor chip 130 is bonded to the upper surface of the first semiconductor chip 120 through an adhesive or the like, and chip pads 132 are formed on both sides thereof, and the chip pads 132 are connected to the first substrate 110. It is electrically connected to the terminal 114.
  • the wire 140 connects the chip pad 122 of the first semiconductor chip 120 and the connection terminal 112 of the first substrate 110 by wire bonding, and the chip pad of the second semiconductor chip 130 ( 132 and the connection terminal 114 of the first substrate 110 are connected by wire bonding.
  • the mold 150 is molded to completely cover the first semiconductor chip 120 and the second semiconductor chip 130 to protect the first semiconductor chip 120 and the second semiconductor chip 130 from external influences.
  • the second solder ball 160 electrically connects the external connection terminal (not shown) of the first substrate 110 and the first solder ball 250 of the lower semiconductor package 200.
  • the lower semiconductor package 200 may include a second substrate 210, a third semiconductor chip 220 mounted on the second substrate 210, a fourth semiconductor chip 230 bonded to the third semiconductor chip 220, and wires.
  • the lower semiconductor package 200 has been described as a multi-chip package, but may also be configured as a single chip.
  • the second substrate 210 has a solder ball 270 formed on an external connection terminal (not shown) on a lower surface thereof, and a connection terminal connected to the third semiconductor chip 220 and the fourth semiconductor chip 230 on both sides of the upper surface. (212, 214) are formed.
  • the third semiconductor chip 220 is bonded to the upper surface of the second substrate 210 through an adhesive or the like, chip pads 222 are formed on both sides, and the chip pads 222 are connection terminals of the second substrate 210. Is electrically connected to 212.
  • the fourth semiconductor chip 230 is bonded to the upper surface of the third semiconductor chip 220 through an adhesive or the like, and chip pads 232 are formed on both sides thereof, and the chip pads 232 are connected to the second substrate 210. It is electrically connected to the terminal 214.
  • the wire 240 connects the chip pad 222 of the third semiconductor chip 220 and the connection terminal 212 of the second substrate 210 by wire bonding, and the chip pad of the fourth semiconductor chip 230. 232 and the connection terminal 214 of the second substrate 210 are connected by wire bonding.
  • the first solder balls 250 are formed at positions corresponding to the second solder balls 160 of the upper semiconductor package 100 on both sides of the second substrate 210.
  • the mold 260 is molded to completely cover the third semiconductor chip 220 and the fourth semiconductor chip 230 to protect the third semiconductor chip 220 and the fourth semiconductor chip 230 from external influences.
  • the mold 260 is molded to expose a part of the first solder ball 250 to the outside, and the molding height of the first solder ball 250 is greater than that of the third semiconductor chip 220 and the fourth semiconductor chip 230. Molded to be smaller than the molding height.
  • the solder ball 270 electrically connects an external connection terminal (not shown) and an external device (not shown) of the second substrate 210.
  • FIGS. 3A to 3G are diagrams illustrating a method of manufacturing a POP package according to an exemplary embodiment of the present invention.
  • the method for manufacturing the POP package includes preparing a top semiconductor package (step S201), forming a bottom semiconductor package 200 (steps S202 to S207), and attaching the top semiconductor package 100 to the bottom semiconductor package 200. Laminating (step S208).
  • the forming of the lower semiconductor package 200 may include mounting the third semiconductor chip 220 and the fourth semiconductor chip 230 (step S202), and forming the third semiconductor chip 220 and the fourth semiconductor chip 230. Wire bonding to the second substrate 210 (step S203), forming the first solder ball 250 on the second substrate 210 (step S204), and transferring the lower semiconductor package 200 to the molding. Step (step S205), removing the mold flash formed on the surface of the mold 260 (step S206), and forming a solder ball 270 under the second substrate 210 (step S207). do.
  • the preparing step (step S201) prepares the upper semiconductor package 100 in the same manner as the conventional method.
  • the first semiconductor chip 120 and the second semiconductor chip 130 are mounted on the first substrate 110, and the first semiconductor chip 120 and the second semiconductor chip 130 are mounted on the first substrate 110.
  • the lower semiconductor package 200 is transferred and molded, and a second solder ball 160 is formed on the lower side of the first substrate 110 after undergoing mold curing.
  • the upper semiconductor package 100 uses a multi-chip package as an example, the upper semiconductor package 100 may be configured as a single chip.
  • the third semiconductor chip 220 is adhered and mounted on the upper surface of the second substrate 210 by using an adhesive or the like, and the upper surface of the third semiconductor chip 220 is mounted.
  • the fourth semiconductor chip 230 is attached to and mounted through an adhesive or the like.
  • the first substrate 110 has connection terminals 212 and 214 for connecting to the third semiconductor chip 220 and the fourth semiconductor chip 230 on both sides of an upper surface thereof, and the third semiconductor chip 220 Chip pads 222 are formed at both sides thereof, and chip pads 232 are formed at both sides of the fourth semiconductor chip 230.
  • the lower semiconductor package 200 uses a multi-chip package as an example, but may also be configured as a single chip.
  • step S203 the chip pad 222 of the third semiconductor chip 220 and the connection terminal 212 of the second substrate 210 are wire-bonded by the wire 240, and the fourth semiconductor chip ( The chip pad 232 of the 230 and the connection terminal 214 of the second substrate 210 are wire bonded by the wire 240.
  • the step of forming the first solder balls 250 may be performed at positions corresponding to the second solder balls 160 of the upper semiconductor package 100 on both sides of the second substrate 210.
  • the first solder ball 250 is formed.
  • the molding step includes the third semiconductor chip 220 and the fourth semiconductor chip to protect the third semiconductor chip 220 and the fourth semiconductor chip 230 from external influences. Molded with mold 260 to completely cover 230.
  • the first solder ball 250 having a connection role with the upper semiconductor package 100 is molded by exposing a part thereof to the outside so as not to be completely covered. That is, molding is performed such that the molding height of the first solder ball 250 is smaller than the molding height of the third semiconductor chip 220 and the fourth semiconductor chip 230.
  • Such molding may be the most common transfer mold method at present as described above. After molding, a series of curing processes are performed.
  • the deflashing step removes the mold flash 252 formed on the exposed portion of the first solder ball 250 in the molding step. That is, a marking process in which a laser deflashing process is performed on the surface of the mold 260 to remove the mold flash 252 that may occur on the first solder ball 250 when the mold is performed after the SBM. Perform with
  • the forming of the solder balls 270 may include solder balls (not shown) for electrically connecting an external connection terminal (not shown) and an external device (not shown) of the second substrate 210. 270).
  • the laminating step laminates the upper semiconductor package 100 to the lower semiconductor package 200 through the second solder balls 160 formed on the lower surface thereof.
  • the second solder ball 160 is disposed so as to be connected to the exposed portion of the first solder ball 250 and then laminated to complete the POP package.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 POP 패키지 및 그 제조 방법에 관한 것으로, 탑 게이트 몰드 방식을 사용하지 않고 트랜스퍼 몰드 방식을 사용하여 POP 패키지를 구현할 수 있는 POP 패키지 및 그 제조 방법을 제공한다. 이를 위한 본 발명은 기판의 상측에 형성된 제 1 솔더 볼 및 반도체 칩과, 상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 솔더 볼을 몰딩하는 몰드를 포함하는 하부 반도체 패키지; 및 하면에 형성된 제 2 솔더 볼을 통하여 상기 솔더 볼의 노출부위에 접속되도록 적층되는 상부 반도체 패키지;를 포함하는 것을 특징으로 한다. 상기와 같은 구성에 의해 본 발명은 탑 게이트 몰드 방식에 따른 박리현상, 몰드 플래시, 냉납 등의 고질적인 불량을 방지할 수 있고, 소재(material) 선택 및 공정 안정화를 향상시킬 수 있는 효가 있다.

Description

ＰＯＰ 패키지 및 그 제조 방법
본 발명은 POP 패키지 및 그 제조 방법에 관한 것으로, 특히, 솔더 볼에 의한 적층구조를 개선하여 탑 게이트 몰드 방식에 따른 패키지 불량을 방지할 수 있는 POP 패키지 및 그 제조 방법에 관한 것이다.
최근의 반도체 패키지가 실장되는 제품들은 경박단소화되고, 많은 기능이 요구됨에 따라 반도체 패키지 기술은 반도체 패키지 내에 복수의 반도체 칩을 실장하는 PIP(package in package) 및 POP(package on package) 등과 같은 방식을 사용하는 추세이다.
이와 같은 반도체 패키지는 여러 개의 반도체 칩을 적층하면서도 그 두께는 축소될 것이 요구되고 있다.
이를 해결하기 위하여 EMC(Epoxy molding compound), 에폭시 등의 반도체 패키지를 구성하는 소재(material)들을 상황에 맞추어 최적화하여 선택적으로 사용하고 있으나 이는 많은 제약이 따르고 있다.
한편, POP 패키지는 기판에 반도체 칩을 각각 실장한 상부 반도체 패키지 및 하부 반도체 패키지를 각각 형성하고, 상부 반도체는 보편적으로 사용하는 트랜스퍼 몰드(transfer mold) 방식으로 몰딩하며, 하부 반도체는 필수적으로 탑 게이트 몰드(Top Gate Mold) 방식으로 몰딩한 다음, 솔더 범프 실장(SBM; Solder Bump Mount)에 의해 상부 반도체 패키지를 하부 반도체 패키지에 적층(stack)한다.
그러나 종래의 POP 패키지는 탑 게이트 몰드 방식을 사용함에 따른 박리현상(Die Top Delamination), 몰드 플래시(Mold Flash), 뒤틀림(warpage)에 의한 냉납(cold solder) 등의 고질적인 불량이 발생하는 문제점이 있다.
상기와 같은 종래 기술의 문제점을 해결하기 위해, 본 발명은 탑 게이트 몰드 방식을 사용하지 않고 트랜스퍼 몰드 방식을 사용하여 POP 패키지를 구현할 수 있는 POP 패키지 및 그 제조 방법을 제공하고자 한다.
위와 같은 과제를 해결하기 위한 본 발명은 기판의 상측에 형성된 제 1 솔더볼 및 반도체 칩과, 상기 제 1 솔더볼의 일부가 노출되도록 상기 기판의 상면을 몰딩 후 상기 제1 솔더볼의 상부 일부를 제거하여 형성된 몰드를 포함하는 하부 반도체 패키지; 및 하측에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더볼의 노출부위에 전기적으로 접속되도록 적층되는 상기 적어도 하나의 반도체 칩을 포함하는 상부 반도체 패키지를 포함할 수 있다.
바람직하게는 상기 하부 반도체 패키지의 몰드는 그라인딩(Grinding) 또는 폴리싱(Polishing)의 수단을 이용하여 상부 일부를 제거하는 것을 특징으로 할 수 있다.
또한 본 발명은 기판의 상측에 형성된 제 1 솔더 볼 및 반도체 칩과, 상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 제1 솔더 볼을 몰딩하는 몰드를 포함하는 하부 반도체 패키지; 및 하면에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더 볼의 노출부위에 접속되도록 적층되는 상부 반도체 패키지;를 포함할 수 있다.
바람직하게는 상기 하부 반도체 패키지 및 상부 반도체 패키지 중 적어도 하나가 멀티 칩 패키지인 것을 특징으로 할 수 있다.
바람직하게는 상기 몰드는 상기 솔더 볼의 몰딩 높이가 상기 반도체 칩의 몰딩 높이보다 작은 것을 특징으로 하는 POP 패키지.
그리고 본 발명인 POP 패키지 제조 방법은 상부 반도체 패키지와, 반도체 칩이 적층된 기판을 준비하는 준비 단계; 상기 기판의 상측에 제 1 솔더 볼을 형성하는 솔더 볼 형성 단계; 상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 제1 솔더 볼을 몰딩하는 몰딩 단계; 및 상기 상부 반도체 패키지를 그 하면에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더 볼의 노출부위에 전기적으로 접속되도록 상기 하부 반도체 패키지에 적층하는 스택(stack) 단계;를 포함할 수 있다.
바람직하게는 상기 몰딩 단계는 상기 솔더 볼의 몰딩 높이가 상기 반도체 칩의 몰딩 높이보다 작게 되도록 몰딩하는 것을 특징으로 할 수 있다.
바람직하게는 상기 몰딩 단계는 상기 제 1 솔더 볼의 노출부위에 형성되는 몰드 플래시(mold flash)를 제거하는 플래시 제거 단계를 포함하는 것을 특징으로 할 수 있다.
바람직하게는 상기 몰딩 단계는 상기 제 1 솔더 볼의 노출된 상부의 일부를 제거하는 단계를 포함하는 것을 특징으로 할 수 있다.
본 발명에 따른 POP 패키지 및 그 제조 방법은 솔더 볼에 의한 적층 구조를 개선하여 탑 게이트 몰드 방식을 사용하지 않고 POP 패키지를 구현함으로써 탑 게이트 몰드 방식에 따른 박리현상, 몰드 플래시, 냉납 등의 고질적인 불량을 방지할 수 있는 효과가 있다.
도 1은 본 발명의 실시예에 따른 POP 패키지의 단면도이고,
도 2는 본 발명의 실시예에 따른 POP 패키지의 제조 방법을 나타낸 순서도이며,
도 3a 내지 도 3g는 본 발명의 실시예에 따른 POP 패키지의 제조 방법을 나타낸 도면도이다.
* 도면의 주요 부분에 대한 부호의 설명 *
100 : 상부 반도체 패키지 110 : 제 1 기판
112 : 접속 단자 114 : 접속 단자
120 : 제 1 반도체 칩 122 : 칩 패드
130 : 제 2 반도체 칩 132 : 칩 패드
140 : 와이어 150 : 몰드
160 : 제 2 솔더 볼 200 : 하부 반도체 패키지
210 : 제 2 기판 212 : 접속 단자
214 : 접속 단자 220 : 제 3 반도체 칩
222 : 칩 패드 230 : 제 4 반도체 칩
232 : 칩 패드 240 : 와이어
250 : 제 1 솔더 볼 260 : 몰드
270 : 솔더 볼
이하, 본 발명을 바람직한 실시예와 첨부한 도면을 참고로 하여 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되는 것은 아니다.
먼저, 도 1을 참조하여 본 발명의 한 실시예에 따른 POP 패키지를 설명한다.
도 1은 본 발명의 실시예에 따른 POP 패키지의 단면도이다.
POP 패키지는 제 1 반도체 칩(120)과 제 2 반도체 칩(130)이 제 1 기판(110)에 실장되는 상부 반도체 패키지(100), 제 3 반도체 칩(220)과 제 4 반도체 칩(230)이 제 2 기판(210)에 실장되는 하부 반도체 패키지(200)를 포함한다.
상부 반도체 패키지(100)는 제 1 기판(110), 제 1 기판(110)에 실장되는 제 1 반도체 칩(120), 제 1 반도체 칩(120)에 접착되는 제 2 반도체 칩(130), 와이어 본딩을 위한 와이어(140), 상부 반도체 패키지(100)를 몰딩하는 몰드(150) 및 제 2 기판(210)에 접속되는 제 2 솔더 볼(160)을 포함한다.
본 실시예에서는 상부 반도체 패키지(100)가 멀티 칩 패키지인 경우를 설명하였지만, 단일 칩으로 구성될 수도 있다.
제 1 기판(110)은 하면의 외부접속단자(미도시)에 제 2 솔더 볼(160)이 형성되고, 상면의 양측에 제 1 반도체 칩(120) 및 제 2 반도체 칩(130)과 접속되는 접속단자(112,114)가 형성된다.
제 1 반도체 칩(120)은 접착제 등을 통하여 제 1 기판(110)의 상면에 접착되고, 양측에 칩 패드(122)가 형성되며, 칩 패드(122)는 제 1 기판(110)의 접속 단자(112)에 전기적으로 접속된다.
제 2 반도체 칩(130)은 접착제 등을 통하여 제 1 반도체 칩(120)의 상면에 접착되고, 양측에 칩 패드(132)가 형성되며, 칩 패드(132)는 제 1 기판(110)의 접속 단자(114)에 전기적으로 접속된다.
와이어(140)는 제 1 반도체 칩(120)의 칩 패드(122)와 제 1 기판(110)의 접속 단자(112)를 와이어 본딩에 의해 연결하고, 제 2 반도체 칩(130)의 칩 패드(132)와 제 1 기판(110)의 접속 단자(114)를 와이어 본딩에 의해 연결한다.
몰드(150)는 제 1 반도체 칩(120) 및 제 2 반도체 칩(130)을 외부의 영향으로부터 보호하기 위하여 제 1 반도체 칩(120) 및 제 2 반도체 칩(130)을 완전히 덮도록 몰딩된다.
제 2 솔더 볼(160)은 제 1 기판(110)의 외부접속단자(미도시)와 하부 반도체 패키지(200)의 제 1 솔더 볼(250)을 전기적으로 연결한다.
하부 반도체 패키지(200)는 제 2 기판(210), 제 2 기판(210)에 실장되는 제 3 반도체 칩(220), 제 3 반도체 칩(220)에 접착되는 제 4 반도체 칩(230), 와이어 본딩을 위한 와이어(240), 하부 반도체 패키지(200)를 몰딩하는 몰드(250), 제 1 기판(110)의 제 2 솔더 볼(160)과 접속되는 제 1 솔더 볼(250), 및 외부장치에 접속되는 솔더 볼(270)을 포함한다.
본 실시예에서는 하부 반도체 패키지(200)가 멀티 칩 패키지인 경우를 설명하였지만, 단일 칩으로 구성될 수도 있다.
제 2 기판(210)은 하면의 외부접속단자(미도시)에 솔더 볼(270)이 형성되고, 상면의 양측에 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)과 접속되는 접속단자(212,214)가 형성된다.
제 3 반도체 칩(220)은 접착제 등을 통하여 제 2 기판(210)의 상면에 접착되고, 양측에 칩 패드(222)가 형성되며, 칩 패드(222)는 제 2 기판(210)의 접속 단자(212)에 전기적으로 접속된다.
제 4 반도체 칩(230)은 접착제 등을 통하여 제 3 반도체 칩(220)의 상면에 접착되고, 양측에 칩 패드(232)가 형성되며, 칩 패드(232)는 제 2 기판(210)의 접속 단자(214)에 전기적으로 접속된다.
와이어(240)는 제 3 반도체 칩(220)의 칩 패드(222)와 제 2 기판(210)의 접속 단자(212)를 와이어 본딩에 의해 연결하고, 제 4 반도체 칩(230)의 칩 패드(232)와 제 2 기판(210)의 접속 단자(214)를 와이어 본딩에 의해 연결한다.
제 1 솔더 볼(250)은 제 2 기판(210)의 양측에서 상부 반도체 패키지(100)의 제 2 솔더 볼(160)에 대응하는 위치에 형성된다.
몰드(260)는 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 외부의 영향으로부터 보호하기 위하여 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 완전히 덮도록 몰딩된다. 또한 몰드(260)는 제 1 솔더 볼(250)의 일부가 외부로 노출되도록 몰딩되며, 제 1 솔더 볼(250)의 몰딩 높이가 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)의 몰딩 높이보다 작게 되도록 몰딩된다.
솔더 볼(270)은 제 2 기판(210)의 외부접속단자(미도시)와 외부장치(미도시)를 전기적으로 연결한다.
이러한 구성에 의해 하부 반도체 패키지를 형성하는 경우에도 상부 반도체 패키지의 형성시 또는 보편적으로 사용되는 트랜스퍼 몰드 방식을 채용할 수 있어 탑 게이트 몰드 방식에 따른 불량 문제를 방지할 수 있다.
이하, 도 2 내지 도 3f를 참조하여 본 발명의 POP 패키지의 제조 방법을 설명한다.
도 2는 본 발명의 실시예에 따른 POP 패키지의 제조 방법을 나타낸 순서도이며, 도 3a 내지 도 3g는 본 발명의 실시예에 따른 POP 패키지의 제조 방법을 나타낸 도면도이다.
POP 패키지의 제조 방법은 상부 반도체 패키지를 준비하는 단계(단계 S201), 하부 반도체 패키지(200)를 형성하는 단계(단계 S202 내지 단계 S207), 상부 반도체 패키지(100)를 하부 반도체 패키지(200)에 적층하는 단계(단계 S208)를 포함한다.
하부 반도체 패키지(200)의 형성 단계는 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 실장하는 단계(단계 S202), 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 제 2 기판(210)에 와이어 본딩하는 단계(단계 S203), 제 2 기판(210)의 상측에 제 1 솔더 볼(250)을 형성하는 단계(단계 S204), 하부 반도체 패키지(200)를 트랜스퍼 몰딩하는 단계(단계 S205), 몰드(260) 표면에 형성된 몰드 플래시를 제거하는 단계(단계 S206), 및 제 2 기판(210)의 하측에 솔더 볼(270)을 형성하는 단계(단계 S207)를 포함한다.
보다 상세하게는, 도 3a에 도시된 바와 같이, 준비 단계(단계 S201)는, 종래의 방식과 동일한 방식으로 상부 반도체 패키지(100)를 준비한다.
즉, 제 1 반도체 칩(120) 및 제 2 반도체 칩(130)을 제 1 기판(110)에 실장하고, 제 1 반도체 칩(120) 및 제 2 반도체 칩(130)을 제 1 기판(110)에 와이어 본딩한 다음, 하부 반도체 패키지(200)를 트랜스퍼 몰딩하고, 몰드 경화를 거친 후 제 1 기판(110)의 하측에 제 2 솔더 볼(160)을 형성한다. 여기서, 상부 반도체 패키지(100)는 멀티 칩 패키지를 예로 하였으나, 단일 칩으로 구성될 수도 있다.
도 3b에 도시된 바와 같이, 실장 단계(단계 S202)는 제 2 기판(210)의 상면에 접착제 등을 통하여 제 3 반도체 칩(220)을 접착하여 실장하고, 제 3 반도체 칩(220)의 상면에 접착제 등을 통하여 제 4 반도체 칩(230)을 접착하여 실장한다.
여기서, 제 1 기판(110)은 그 상면의 양측에 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)과 접속하기 위한 접속단자(212,214)가 형성되고, 제 3 반도체 칩(220)은 그 양측에 칩 패드(222)가 형성되며, 제 4 반도체 칩(230)은 그 양측에 칩 패드(232)가 형성된다. 본 실시예에서는 하부 반도체 패키지(200)는 멀티 칩 패키지를 예로 하였으나, 단일 칩으로 구성될 수도 있다.
와이어 본딩 단계(단계 S203)는 제 3 반도체 칩(220)의 칩 패드(222)와 제 2 기판(210)의 접속 단자(212)를 와이어(240)에 의해 와이어 본딩하고, 제 4 반도체 칩(230)의 칩 패드(232)와 제 2 기판(210)의 접속 단자(214)를 와이어(240)에 의해 와이어 본딩한다.
도 3c에 도시된 바와 같이, 제 1 솔더 볼(250) 형성 단계(단계 S204)는 제 2 기판(210)의 양측에서 상부 반도체 패키지(100)의 제 2 솔더 볼(160)에 대응하는 위치에 제 1 솔더 볼(250)을 형성한다.
이와 같이 종래의 공정과는 다르게 SBM 공정을 몰드 공정에 선행하여 수행함으로써, 뒤틀림에 의한 냉납 등의 불량을 최소화할 수 있다.
또한, 종래의 탑 게이트 몰드 설비를 사용하지 않고 현재 양산공정에서 가장 많이 사용하고 있는 트랜스퍼 몰드 방식을 사용할 수 있고, 이와 같이 탑 게이트 몰드 방식을 사용하지 않음으로써 그와 관련된 불량 문제를 방지할 수 있다.
도 3d에 도시된 바와 같이, 몰딩 단계(단계 S205)는 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 외부의 영향으로부터 보호하기 위하여 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)을 완전히 덮도록 몰드(260)로 몰딩한다. 이때, 상부 반도체 패키지(100)와 접속 역할을 갖는 제 1 솔더 볼(250)은 완전히 덮이지 않도록 그 일부를 외부로 노출시켜 몰딩한다. 즉, 제 1 솔더 볼(250)의 몰딩 높이가 제 3 반도체 칩(220) 및 제 4 반도체 칩(230)의 몰딩 높이보다 작게 되도록 몰딩한다.
이러한 몰딩은 상술한 바와 같이 현재 가장 보편적인 트랜스퍼 몰드 방식일 수 있다. 몰딩 후에는 일련의 경화 공정을 수행한다.
도 3e에 도시된 바와 같이, 디플래시 단계(단계 S206)는, 몰딩 단계에서 제 1 솔더 볼(250)의 노출부위에 형성되는 몰드 플래시(252)를 제거한다. 즉, SBM을 선행한 후 몰드 수행시 제 1 솔더 볼(250)의 위에 발생할 수 있는 몰드 플래시(252)를 제거하기 위하여 레이저 디플래시 공정을 몰드(260)의 표면에 수행되는 마킹(Marking) 공정과 함께 수행한다.
도 3f에 도시된 바와 같이, 솔더 볼(270) 형성 단계(단계 S207)는 제 2 기판(210)의 외부접속단자(미도시)와 외부장치(미도시)를 전기적으로 연결하기 위하여 솔더 볼(270)을 형성한다.
도 3g에 도시된 바와 같이, 적층 단계(단계 S208)는 상부 반도체 패키지(100)를 그 하면에 형성된 제 2 솔더 볼(160)을 통하여 하부 반도체 패키지(200)에 적층한다. 이때, 제 2 솔더 볼(160)이 제 1 솔더 볼(250)의 노출부위에 접속되도록 배치시킨 후 적층을 수행하여 POP 패키지를 완성한다.
이와 같은 방법에 의해 EMC, 에폭시 등의 소재의 선택이 자유롭고, 공정 안정화가 향상될 수 있으며, 탑 게이트 몰드 방식을 사용하지 않고 보편적인 트랜스 몰드 방식을 사용하여 POP 패키지를 제조할 수 있다.
상기에서는 본 발명의 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 본 발명의 기술 사상 범위 내에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 첨부된 특허 청구 범위에 속하는 것은 당연하다.

Claims (9)

  1. 기판의 상측에 형성된 제 1 솔더볼 및 반도체 칩과, 상기 제 1 솔더볼의
    일부가 노출되도록 상기 기판의 상면을 몰딩 후 상기 제1 솔더볼의 상부 일부를 제거하여 형성된 몰드를 포함하는 하부 반도체 패키지; 및
    하측에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더볼의 노출부위에 전기적으로 접속되도록 적층되는 상기 적어도 하나의 반도체 칩을 포함하는 상부 반도체 패키지;를 포함하는 것을 특징으로 하는 POP 패키지.
  2. 제 1항에 있어서,
    상기 하부 반도체 패키지의 몰드는 그라인딩(Grinding) 또는 폴리싱(Polishing)의 수단을 이용하여 상부 일부를 제거하는 것을 특징으로 하는 POP 패키지.
  3. 기판의 상측에 형성된 제 1 솔더 볼 및 반도체 칩과, 상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 제1 솔더 볼을 몰딩하는 몰드를 포함하는 하부 반도체 패키지; 및
    하면에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더 볼의 노출부위에 접속되도록 적층되는 상부 반도체 패키지;
    를 포함하는 것을 특징으로 하는 POP 패키지.
  4. 제 3 항에 있어서,
    상기 하부 반도체 패키지 및 상부 반도체 패키지 중 적어도 하나가 멀티 칩 패키지인 것을 특징으로 하는 POP 패키지.
  5. 제 3항에 있어서,
    상기 몰드는 상기 솔더 볼의 몰딩 높이가 상기 반도체 칩의 몰딩 높이보다 작은 것을 특징으로 하는 POP 패키지.
  6. 상부 반도체 패키지와, 반도체 칩이 적층된 기판을 준비하는 준비 단계;
    상기 기판의 상측에 제 1 솔더 볼을 형성하는 솔더 볼 형성 단계;
    상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 제1 솔더 볼을 몰딩하는 몰딩 단계; 및
    상기 상부 반도체 패키지를 그 하면에 형성된 제 2 솔더 볼을 통하여 상기 제1 솔더 볼의 노출부위에 전기적으로 접속되도록 상기 하부 반도체 패키지에 적층하는 스택(stack) 단계;
    를 포함하는 것을 특징으로 하는 POP 패키지 제조 방법.
  7. 제 6 항에 있어서,
    상기 몰딩 단계는 상기 솔더 볼의 몰딩 높이가 상기 반도체 칩의 몰딩 높이보다 작게 되도록 몰딩하는 것을 특징으로 하는 POP 패키지 제조 방법.
  8. 제 6 항에 있어서,
    상기 몰딩 단계는 상기 제 1 솔더 볼의 노출부위에 형성되는 몰드 플래시(mold flash)를 제거하는 플래시 제거 단계를 포함하는 것을 특징으로 하는 POP 패키지 제조 방법.
  9. 제 6 항에 있어서,
    상기 몰딩 단계는 상기 제 1 솔더 볼의 노출된 상부의 일부를 제거하는 단계를 포함하는 것을 특징으로 하는 POP 패키지 제조 방법.
PCT/KR2010/009468 2009-12-29 2010-12-29 Ｐｏｐ 패키지 및 그 제조 방법 WO2011081428A2 (ko)

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EP10841260.2A EP2521170A4 (en) 2009-12-29 2010-12-29 PACKAGE ON PACKAGE AND MANUFACTURING METHOD THEREFOR
BR112012012520-6A BR112012012520A2 (ko) 2009-12-29 2010-12-29 POP package and a method of manufacturing the same
US13/510,382 US20120326306A1 (en) 2009-12-29 2010-12-29 Pop package and manufacturing method thereof

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KR1020090133352A KR20110076604A (ko) 2009-12-29 2009-12-29 Ｐｏｐ 패키지 및 그 제조 방법
KR10-2009-0133352 2009-12-29

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KR101983132B1 (ko) 2012-11-29 2019-05-28 삼성전기주식회사 전자부품 패키지
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KR20110076604A (ko) 2011-07-06
WO2011081428A3 (ko) 2011-11-10

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