WO2011081428A3 - Ｐｏｐ 패키지 및 그 제조 방법 - Google Patents

Ｐｏｐ 패키지 및 그 제조 방법 Download PDF

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Publication number
WO2011081428A3
WO2011081428A3 PCT/KR2010/009468 KR2010009468W WO2011081428A3 WO 2011081428 A3 WO2011081428 A3 WO 2011081428A3 KR 2010009468 W KR2010009468 W KR 2010009468W WO 2011081428 A3 WO2011081428 A3 WO 2011081428A3
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WIPO (PCT)
Prior art keywords
package
solder ball
manufacturing
pop
mold
Prior art date
Application number
PCT/KR2010/009468
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English (en)
French (fr)
Other versions
WO2011081428A2 (ko
Inventor
이현우
Original Assignee
하나마이크론㈜
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Publication date
Application filed by 하나마이크론㈜ filed Critical 하나마이크론㈜
Priority to US13/510,382 priority Critical patent/US20120326306A1/en
Priority to EP10841260.2A priority patent/EP2521170A4/en
Priority to BR112012012520-6A priority patent/BR112012012520A2/ko
Publication of WO2011081428A2 publication Critical patent/WO2011081428A2/ko
Publication of WO2011081428A3 publication Critical patent/WO2011081428A3/ko

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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 POP 패키지 및 그 제조 방법에 관한 것으로, 탑 게이트 몰드 방식을 사용하지 않고 트랜스퍼 몰드 방식을 사용하여 POP 패키지를 구현할 수 있는 POP 패키지 및 그 제조 방법을 제공한다. 이를 위한 본 발명은 기판의 상측에 형성된 제 1 솔더 볼 및 반도체 칩과, 상기 제 1 솔더 볼의 일부가 노출되도록 상기 반도체 칩과 상기 솔더 볼을 몰딩하는 몰드를 포함하는 하부 반도체 패키지; 및 하면에 형성된 제 2 솔더 볼을 통하여 상기 솔더 볼의 노출부위에 접속되도록 적층되는 상부 반도체 패키지;를 포함하는 것을 특징으로 한다. 상기와 같은 구성에 의해 본 발명은 탑 게이트 몰드 방식에 따른 박리현상, 몰드 플래시, 냉납 등의 고질적인 불량을 방지할 수 있고, 소재(material) 선택 및 공정 안정화를 향상시킬 수 있는 효가 있다.
PCT/KR2010/009468 2009-12-29 2010-12-29 Ｐｏｐ 패키지 및 그 제조 방법 WO2011081428A2 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US13/510,382 US20120326306A1 (en) 2009-12-29 2010-12-29 Pop package and manufacturing method thereof
EP10841260.2A EP2521170A4 (en) 2009-12-29 2010-12-29 PACKAGE ON PACKAGE AND MANUFACTURING METHOD THEREFOR
BR112012012520-6A BR112012012520A2 (ko) 2009-12-29 2010-12-29 POP package and a method of manufacturing the same

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KR10-2009-0133352 2009-12-29
KR1020090133352A KR20110076604A (ko) 2009-12-29 2009-12-29 Ｐｏｐ 패키지 및 그 제조 방법

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WO2011081428A3 true WO2011081428A3 (ko) 2011-11-10

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JP5766593B2 (ja) * 2011-12-09 2015-08-19 日本特殊陶業株式会社 発光素子搭載用配線基板
KR101818507B1 (ko) 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
KR101983132B1 (ko) 2012-11-29 2019-05-28 삼성전기주식회사 전자부품 패키지
NL2011512C2 (en) * 2013-09-26 2015-03-30 Besi Netherlands B V Method for moulding and surface processing electronic components and electronic component produced with this method.
KR101953396B1 (ko) * 2013-10-23 2019-03-04 앰코테크놀로지코리아(주) 반도체 패키지 및 그 제작 방법
KR102154830B1 (ko) 2014-08-05 2020-09-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20200007509A (ko) 2018-07-13 2020-01-22 삼성전자주식회사 반도체 패키지

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KR20040057640A (ko) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 비지에이 패키지의 적층 방법
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US20070290376A1 (en) * 2006-06-20 2007-12-20 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same

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KR20110076604A (ko) 2011-07-06
US20120326306A1 (en) 2012-12-27
EP2521170A4 (en) 2013-06-19
BR112012012520A2 (ko) 2018-04-17
WO2011081428A2 (ko) 2011-07-07
EP2521170A2 (en) 2012-11-07

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