WO2011078335A1 - エッチング液及びこれを用いた半導体装置の製造方法 - Google Patents

エッチング液及びこれを用いた半導体装置の製造方法 Download PDF

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Publication number
WO2011078335A1
WO2011078335A1 PCT/JP2010/073367 JP2010073367W WO2011078335A1 WO 2011078335 A1 WO2011078335 A1 WO 2011078335A1 JP 2010073367 W JP2010073367 W JP 2010073367W WO 2011078335 A1 WO2011078335 A1 WO 2011078335A1
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Prior art keywords
semiconductor device
etching
acid
layer
mass
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PCT/JP2010/073367
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English (en)
French (fr)
Inventor
彰良 細見
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三菱瓦斯化学株式会社
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Priority to US13/518,714 priority Critical patent/US9177827B2/en
Priority to CN201080059307.9A priority patent/CN102696097B/zh
Priority to JP2011547653A priority patent/JP5794148B2/ja
Priority to EP10839564.1A priority patent/EP2518759B1/en
Publication of WO2011078335A1 publication Critical patent/WO2011078335A1/ja

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
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Definitions

  • the present invention relates to an etching solution that can be used for manufacturing a semiconductor device using a semiconductor substrate having electrodes and that can selectively etch copper without etching nickel, and a method for manufacturing a semiconductor device using the same.
  • a cover film having an electrode portion opened is provided on a substrate provided with an electrode made of a conductive material, and a copper film is further formed.
  • a base conductive film formed by sputtering, etc., a photoresist film having an opening extending from the electrode to a position where a corresponding bump electrode is formed, and copper wiring and nickel wiring are sequentially provided in the opening by electrolytic plating.
  • the photoresist film is removed, and an etching process is performed in which a portion of the base conductive film that is not covered with the wiring is etched.
  • an etching process is performed in which a portion of the base conductive film that is not covered with the wiring is etched.
  • the bump electrode forming method disclosed in Patent Document 2 is a method in which a seed layer is formed by sputtering with titanium or copper on a semiconductor substrate provided with an aluminum electrode, and a resist having an opening at a portion where the bump electrode is formed is formed. After forming a barrier metal layer formed by laminating a plurality of metals such as titanium, copper, nickel, etc., by electrolytic plating or the like, and further forming a solder to be a bump electrode thereon by electrolytic plating And an etching step of etching the seed layer after removing the resist.
  • the bump electrode made of solder is not simultaneously etched with the metal such as nickel forming the barrier metal layer. It is desirable to suppress a reduction in the performance of the electrode by preventing oxidation by the etching solution.
  • FIG. 4 is a schematic cross-sectional view (FIGS. A (a) to (g)) for each process of the semiconductor device for explaining a manufacturing method A of the semiconductor device having a bump electrode of the present invention.
  • FIG. 4 is a schematic cross-sectional view (FIGS. A (h) to (l)) for each process of the semiconductor device for explaining a manufacturing method A of the semiconductor device having a bump electrode of the present invention.
  • FIG. 7 is a schematic cross-sectional view (FIGS. B (a) to (h)) for each process of the semiconductor device, for explaining a manufacturing method B of the semiconductor device having a bump electrode of the present invention.
  • FIG. 6 is a schematic cross-sectional view (FIGS. B (i) to (p)) for each process of the semiconductor device for explaining a manufacturing method B of the semiconductor device having a bump electrode of the present invention.
  • the present invention has been made under such circumstances, and is used for manufacturing a semiconductor device using a semiconductor substrate having an electrode, and can selectively etch copper without etching nickel, and the performance of the bump electrode. It is an object of the present invention to provide an etching solution that can prevent a drop and a method for manufacturing a semiconductor device using the same.
  • the inventors of the present invention contain hydrogen peroxide, an organic acid, and an organic phosphonic acid in a specific composition, and the organic acid is a specific hydroxy acid. It has been found that the problem can be solved by using an etching solution which is at least one selected from acids and malic acid. That is, the present invention is used in the manufacture of a semiconductor device using a semiconductor substrate having the following electrodes, and can etch copper selectively without etching nickel, and can prevent deterioration in performance of bump electrodes and A method of manufacturing a semiconductor device using the same is provided.
  • the hydrogen peroxide content is 1.5 to 12% by mass
  • the organic acid content is 1.5 to 20% by mass
  • the organic phosphonic acid content is 0.001 to 0.25. 2.
  • Etching liquid of said 1 which is the mass%.
  • the hydrogen peroxide content is 1.5 to 5% by mass
  • the organic acid content is 1.5 to 10% by mass
  • the organic phosphonic acid content is 0.01 to 0.15.
  • Etching liquid of said 1 which is the mass%.
  • the organic phosphonic acid is at least one selected from diethylenetriaminepenta (methylenephosphonic acid), propanediaminetetra (methylenephosphonic acid) and 1-hydroxyethylidene-1,1-diphosphonic acid
  • the etching liquid as described in.
  • the etching solution as described in any one of 1 to 4 above, wherein the semiconductor device has bump electrodes formed of solder.
  • a method for manufacturing a semiconductor device comprising an etching step using the etching solution according to any one of 1 to 6 above.
  • an etching solution that is used in a manufacturing process of a semiconductor device using a semiconductor substrate having an electrode, can selectively etch copper without etching nickel, and can prevent performance degradation of the bump electrode, and A semiconductor device manufacturing method using the same can be provided.
  • the etching solution of the present invention is used in an etching process in a manufacturing process of a semiconductor device using a semiconductor substrate having an electrode, and contains hydrogen peroxide, an organic acid, and an organic phosphonic acid in a specific content.
  • organic phosphonic acids include diethylenetriaminepenta (methylenephosphonic acid), 3,3′-diaminodipropylaminepenta (methylenephosphonic acid), ethylenediaminetetra (methylenephosphonic acid), propanediaminetetra (methylenephosphonic acid), bis (hexa Methylene) triaminepenta (methylenephosphonic acid), triethylenetetraminehexa (methylenephosphonic acid), tri (2-aminoethyl) aminehexa (methylenephosphonic acid), tri (3-aminopropyl) aminehexa (methylenephosphonic acid), tetraethylene Pentaminehepta (methylenephosphonic acid), pentaethylenehexamineocta (methylenephosphonic acid), hexamethylenetetramineocta (methylenephosphonic acid), aminomethylphosphonic acid, and hydroxy
  • Such as dust diphthalic acid are preferably exemplified.
  • a part of the phosphonomethyl group of these compounds may be substituted with another group such as a hydrogen atom or a methyl group.
  • the phosphonic acid group of these phosphonic acid compounds can be used in the same manner even if they are not free acids but are salts such as ammonium salts.
  • diethylenetriaminepenta methylenephosphonic acid
  • propanediaminetetra methylenephosphonic acid
  • 1-hydroxyethylidene-1,1-diphosphonic acid are more preferable, and at least one selected from these is preferable.
  • the content of hydrogen peroxide is required to be 0.75 to 12% by mass.
  • the content of hydrogen peroxide is less than 0.75% by mass, an appropriate etching rate cannot be obtained.
  • the content is more than 12% by mass, it becomes difficult to manage hydrogen peroxide, and the concentration of hydrogen peroxide is reduced. Not stable.
  • the hydrogen peroxide content is 1.5 to 12% by mass from the viewpoint of easy management of hydrogen peroxide, stable hydrogen peroxide concentration, and obtaining an appropriate etching rate and good etching performance. Is preferable, and 1.5 to 5% by mass is more preferable.
  • the content of at least one organic acid selected from citric acid and malic acid, which are specific hydroxy acids, is required to be 0.75 to 25% by mass.
  • the content of the organic acid is less than 0.75% by mass or more than 25% by mass, an appropriate etching rate and etching performance cannot be obtained.
  • the content of the organic acid is preferably 1.5 to 20% by mass, and more preferably 1.5 to 10% by mass.
  • the content of the organic acid is within the above range, an appropriate etching rate and good etching performance can be obtained.
  • the organic acid is a combination of citric acid and malic acid
  • the total content of citric acid and malic acid is the content of the organic acid.
  • the content of organic phosphonic acid needs to be 0.0005 to 1% by mass.
  • the content of the organic phosphonic acid is less than 0.0005% by mass, oxidation of the bump electrode by the etching solution cannot be prevented, and the reduction in the performance of the electrode cannot be suppressed. If it is large, Ni will be etched.
  • the content of the organic phosphonic acid is preferably 0.001 to 0.25% by mass, and 0.01 to 0.15% by mass. More preferred. If the content of the organic phosphonic acid is within the above range, this suppression effect is particularly remarkable when the bump electrode is formed from solder.
  • the etching solution of the present invention preferably contains water as a component other than hydrogen peroxide, organic acid, and organic phosphonic acid.
  • the water is preferably water from which metal ions, organic impurities, particle particles, and the like have been removed by distillation, ion exchange treatment, filter treatment, various adsorption treatments, and the like, and pure water and ultrapure water are particularly preferred.
  • the etching solution of the present invention has a feature of selectively etching copper without etching nickel. Therefore, the etching solution of the present invention is particularly suitable for an etching process in a manufacturing process of a semiconductor device in which nickel and copper are used in particular among semiconductor devices, and it is necessary to selectively etch copper without etching nickel. It is done. In addition, the etching solution of the present invention suppresses the reduction of the performance of the electrode by preventing the oxidation of the bump electrode, and this effect is also remarkable when the electrode is formed from solder.
  • the etching solution of the present invention is preferably used in an etching process in a manufacturing process of a semiconductor device having a bump electrode, and particularly preferably used in an etching process in a semiconductor manufacturing process in which the bump electrode is formed of solder.
  • the method for manufacturing a semiconductor device of the present invention preferably includes an etching step using the etching solution of the present invention, and the semiconductor device preferably has a bump electrode. Further, in the etching step, from the viewpoint of effectively utilizing the characteristics of the etching solution of the present invention that can selectively etch copper without etching nickel, the nickel member and the copper member are simultaneously etched into the etching solution. It is preferable that the member made of copper is etched. Below, the manufacturing method of this invention is demonstrated more concretely.
  • the first aspect of the semiconductor device manufacturing method of the present invention includes a seed layer forming step A1, a photoresist forming step A2, a barrier metal forming step A3, a solder layer forming step A4, and the present invention.
  • the etching step A5 using the etching solution and the bump electrode formation step A6 are sequentially provided.
  • the production method A of the present invention will be described in detail with reference to FIGS. A (a) to (l).
  • Step A1 is a seed layer forming step in which an insulating film having an opening through which the electrode is exposed is provided on a semiconductor substrate provided with an electrode, and a seed layer is formed on the opening and the insulating film.
  • an electronic circuit including a semiconductor element manufactured by a well-known manufacturing method is formed on the surface of a silicon substrate 101, for example, as shown in FIG.
  • the conductive material include aluminum, aluminum alloy added with titanium or copper, copper or copper alloy, and gold.
  • An insulating film 103 made of silicon oxide or the like is formed on the semiconductor substrate 101 provided with the electrode 102 (surface on which the electrode is formed), and an opening 104 corresponding to the electrode 102 is formed in the insulating film 103.
  • the electrode 102 is formed so as to be exposed.
  • a seed layer is formed on the opening 104 and the insulating film 103 by normal sputtering.
  • Preferred examples of the metal forming the seed layer include titanium and copper.
  • a plurality of layers made of these metals, such as the titanium layer 105 and the copper layer 106, are used. Can be provided.
  • Step A2 is a photoresist formation step of forming a photoresist 107 having an opening 108 that exposes the seed layer by opening a region including a portion provided on the electrode of the seed layer and a portion where a bump electrode is to be formed. It is. First, as shown in FIG. A (d), a photoresist 107 is formed on the copper layer 106. Next, by exposing and developing the photoresist, as shown in FIG. A (e), a photoresist 107 having openings 108 for forming bump electrodes described later is formed.
  • Step A3 is a barrier metal forming step in which a barrier metal layer is provided in the opening 108.
  • a nickel layer 109 is provided by a method such as electrolytic plating, and the nickel layer 109, the titanium layer 105 and the copper layer 106 provided in step A1. Is called a barrier metal layer.
  • the barrier metal layer is a layer provided to prevent diffusion between the electrode 102 and a bump electrode 111 described later, and nickel or nickel alloy formed on the surface in contact with the bump electrode 111. It is preferable to provide the layer 109.
  • Step A4 is a step of providing a solder layer 110 on the nickel layer 109, as shown in FIG.
  • the solder layer 110 is usually formed by an electrolytic plating process using the titanium layer 105 and the copper layer 106 as a seed layer. At this stage, the solder layer 110 usually protrudes from the opening 108 to the surface of the photoresist 107 and has a mushroom shape. .
  • solder layer 110 As a material for forming the solder layer 110, in addition to tin, lead and alloys thereof (tin-lead alloy), tin-silver alloy, tin-silver-copper alloy, tin-copper alloy, tin-zinc
  • solder materials such as alloy based alloys, tin-bismuth based alloys and tin-zinc-bismuth based alloys.
  • step A5 In step A5, as shown in FIG. A (h), after removing the photoresist, as shown in FIGS. A (i) and (j), using the etching solution of the present invention, the titanium layer 105 and This is an etching process in which an exposed portion of the seed layer such as the copper layer 106 that is not covered with the nickel layer 109 or the solder layer 110 is etched.
  • the etching solution of the present invention copper can be selectively etched without etching nickel.
  • bump electrodes are formed of solder, and particularly when the solder contains tin, by using the etching solution of the present invention, the electrodes are not oxidized and the performance is not reduced. The effect is also obtained.
  • a method of bringing the etching solution into contact with the etching target there is no particular limitation on the method of bringing the etching solution into contact with the etching target.
  • a method of bringing the etching solution into contact with the target in the form of dripping or spraying, a method of immersing the target in the etching solution, etc. Can do.
  • a method in which an etching solution is sprayed onto an object to be contacted is preferably employed.
  • the use temperature of the etching solution is preferably 50 ° C. or less, more preferably 20 to 50 ° C., still more preferably 20 to 40 ° C., and particularly preferably 25 to 35 ° C.
  • the temperature of the etching solution is 50 ° C. or higher, the etching rate is increased, but the stability of the solution is deteriorated and it is difficult to keep the etching conditions constant.
  • the temperature of the etching solution By setting the temperature of the etching solution to 50 ° C. or lower, it is possible to suppress a change in the composition of the etching solution and obtain a stable etching rate. Moreover, if it is 20 degreeC or more, an etching rate will not become slow too much and production efficiency will not fall remarkably.
  • Step A6 is a bump electrode formation step for obtaining the bump electrode 111 by melting the solder layer 110.
  • the solder layer 110 may be melted by heating the substrate and performing a reflow process.
  • the reflow process allows the mushroom-shaped solder layer 111 to have a bump electrode 111 having a spherical shape as shown in FIG. Become. In this manner, a semiconductor device having bump electrodes can be manufactured from a semiconductor substrate having electrodes.
  • the second aspect of the semiconductor device manufacturing method of the present invention includes a seed layer forming step B1, a photoresist (I) forming step B2, a rewiring forming step B3, and a photoresist (II).
  • the process includes a forming process B4, a bump electrode forming process B5, and an etching process B6 using the etching solution of the present invention.
  • the production method B of the present invention will be described in detail with reference to FIGS. B (a) to (p).
  • Step B1 is a seed layer forming step in which an insulating film having an opening through which the electrode is exposed is provided on a semiconductor substrate provided with an electrode, and a seed layer is formed on the opening and the insulating film.
  • an opening 204 corresponding to the electrode 202 is provided on the semiconductor substrate 201 provided with the electrode 202 (the surface on which the electrode is formed).
  • An insulating film 203 is formed so as to expose the electrode 202, and a titanium layer 205 and a copper layer 206 are formed as seed layers on the opening 204 and the insulating film 203.
  • Step B2 forms a photoresist (I) 207 having an opening 208 that exposes the seed layer by opening a region including a portion provided on the electrode of the seed layer and a portion where a bump electrode is to be formed.
  • This is a resist (I) formation step.
  • a photoresist (I) 207 is formed on the copper layer 206.
  • a portion connecting the portion provided on the seed layer electrode 202 and a region including a bump electrode forming portion to be described later is connected.
  • a photoresist (I) 207 having an opening 208 for forming wiring is formed.
  • Step B3 is a rewiring forming step in which wiring is provided in the opening 208 and rewiring is performed. Through this rewiring forming step, rewiring is formed to form wiring on the electrode 202 of the semiconductor substrate 201 having the electrode 202.
  • the wiring is made of a material such as copper or nickel, and preferably has a copper layer 209 made of at least copper as shown in FIG. B (f).
  • the wiring is usually provided by electrolytic plating of copper or nickel.
  • a photoresist (II) 210 is formed so as to cover the seed layer and the wiring, and further, exposed and developed to form the photoresist (II).
  • This photoresist (II) 210 may be provided by a conventional method. It is also possible to form the photoresist (II) 210 after removing the photoresist (I) in advance.
  • step B5 In step B5, as shown in FIGS. B (i) and (j), an opening 211 is formed at the location where the bump electrode of the photoresist (II) 210 is formed so that the copper layer 209 of the rewiring is exposed.
  • This is a bump electrode forming step in which a bump electrode having at least one nickel layer 212 made of nickel is formed in the opening 211.
  • the bump electrode can be formed by electrolytic plating using gold, palladium, nickel, copper, or the like in addition to the solder material for forming the solder layer 110, and can be formed by one layer or a plurality of layers. For example, as shown in FIG.
  • the bump layer can be formed by providing the solder layer 213 made of a solder material.
  • the layer forming the bump electrode is a combination of the nickel layer 212 and the solder layer 213, the performance of selectively etching copper without etching the nickel included in the etching solution of the present invention And the performance that the performance is not reduced can be effectively utilized without oxidizing the electrode.
  • Step B6 is shown in FIGS. B (l) and (m) after removing photoresist (I) 207 and photoresist (II) 210 using a resist stripper as shown in FIG. B (k).
  • the seed layer such as the titanium layer 205 and the copper layer 206
  • the exposed portion that is not covered with the wiring such as the copper layer 209 is etched.
  • copper can be selectively etched without etching nickel.
  • bump electrodes are formed of solder, and particularly when the solder contains tin, by using the etching solution of the present invention, the electrodes are not oxidized and the performance is not reduced. The effect is also obtained.
  • the etching conditions in step B6 are the same as in step A5.
  • the nickel layer 212 is exposed to the etching solution.
  • the nickel layer 212 as shown in FIG. B (p) is not etched to form the recess 216, and only the copper layer 206 is selectively used. It becomes possible to perform etching.
  • an insulating film 214 can be formed in a portion other than the region where the bump electrode is formed.
  • an insulating organic material such as an epoxy resin or a polyimide resin is preferably used.
  • the convex solder layer 215 can be formed by melting the solder layer 213 formed in the step B5. The solder layer 213 may be melted by heating the substrate and performing a reflow process.
  • the manufacturing method B provides a semiconductor device having bump electrodes in which rewiring for forming wiring on the electrodes of the semiconductor substrate having electrodes has been performed.
  • a semiconductor substrate with a narrow pitch of electrodes of 150 ⁇ m or less, 100 ⁇ m or less, and even 50 ⁇ m or less.
  • a semiconductor device with a narrow pitch such that the pitch of the bump electrodes is 500 ⁇ m or less, 250 ⁇ m or less, and further 200 ⁇ m or less. Therefore, the semiconductor device obtained by the manufacturing method of the present invention can sufficiently cope with recent miniaturization, high integration, and multi-function.
  • the sample was immersed in the etching solution at 30 ° C. for 2 minutes.
  • the change in film thickness before and after immersion was measured using a fluorescent X-ray analyzer ("SEA2110L", manufactured by SSI Nanotechnology Co., Ltd.), and the copper etching rate ( ⁇ m / min) ) was calculated.
  • SE2110L fluorescent X-ray analyzer
  • Examples 39 to 44 and Comparative Examples 21 to 27 Manufacturing of a semiconductor device by manufacturing method A
  • a semiconductor device having electrodes and bump electrodes was manufactured according to the procedure of Manufacturing Method A (FIGS. A (a) to (k)).
  • Etching of the copper layer 106 and the titanium layer 105 was sequentially performed using the etching solutions of the respective examples and comparative examples. At this time, the etching temperature was 30 ° C., and the etching time was the time shown in Table 2.
  • Table 2 shows the results of evaluation of the semiconductor devices obtained in the examples and comparative examples according to the above evaluation criteria.
  • Examples 46 to 51 and Comparative Examples 29 to 35 Manufacturing of Semiconductor Device by Manufacturing Method B
  • a semiconductor device having electrodes and bump electrodes was manufactured according to the procedure of Manufacturing Method B (FIGS. B (a) to (k)).
  • the etching steps shown in FIGS. B (l) to (m) are shown in Table 3.
  • Etching of the copper layer 206 and the titanium layer 205 was sequentially performed using the etching solutions of the respective examples and comparative examples. At this time, the etching temperature was 30 ° C., and the etching time was the time shown in Table 3.
  • Table 3 shows the results of evaluation of the semiconductor devices obtained in the examples and comparative examples according to the above evaluation criteria.
  • Table 3 shows the evaluation results of the semiconductor devices obtained in the respective examples and comparative examples according to the evaluation items.
  • the etching solution of the present invention was less than 50 mm / min for electrolytic nickel plating, despite having a high etching rate of 0.1 ⁇ m / min or more for sputtered copper. It was confirmed that the etching rate was suppressed to a low level.
  • the etching rate was suppressed to a low level.
  • tin-lead solder plating and tin plating although slight discoloration was observed when the content of organic phosphonic acid was less than 0.01% by mass, there was no practical problem. In other examples, no discoloration was observed.
  • the etching rate of sputtered copper was as low as less than 0.1 ⁇ m / min.
  • Comparative Examples 9, 11 and 18 containing other organic acids instead of citric acid and malic acid the etching rate of sputtered copper was as low as less than 0.1 ⁇ m / min.
  • Comparative Examples 1 and 4 containing no organic phosphonic acid discoloration was observed in both the tin-lead solder plating and the tin plating.
  • Comparative Examples 15, 19, and 20 each containing 5% by mass of hydrogen peroxide and containing tartaric acid, glutaric acid, and itaconic acid as organic acids, etching performance equivalent to that of Examples 1 to 38 was obtained. However, it was confirmed that in each of Comparative Examples 25 to 27 in which the semiconductor device was manufactured using the etching solution used in these comparative examples, the copper layer after etching was remarkably remaining and could not be used for manufacturing the semiconductor device. .
  • the etching solution of the present invention is used in a manufacturing process of a semiconductor device using a semiconductor substrate having electrodes.
  • An etching solution is particularly effective.

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Abstract

　電極を有する半導体基板を用いた半導体装置の製造に用いられ、ニッケルをエッチングせずに銅を選択的にエッチングできるエッチング液及びこれを用いた半導体装置の製造方法を提供する。　過酸化水素と有機酸と有機ホスホン酸とを含み、有機酸がクエン酸及びリンゴ酸から選ばれる少なくとも一種であり、過酸化水素の含有量が０．７５～１２質量％であり、有機酸の含有量が０．７５～２５質量％であり、かつ有機ホスホン酸の含有量が０．０００５～１質量％である、電極を有する半導体基板を用いた半導体装置の製造に用いられるエッチング液、及びこれらのエッチング液を用いた半導体装置の製造方法である。

Description

エッチング液及びこれを用いた半導体装置の製造方法
　本発明は、電極を有する半導体基板を用いた半導体装置の製造に用いられ、ニッケルをエッチングせずに銅を選択的にエッチングできるエッチング液及びこれを用いた半導体装置の製造方法に関する。
　近年、電子機器の小型化の要請に伴い、当該機器に用いられる半導体装置の小型化や、高集積化及び多機能化が進んでおり、半導体装置と電子機器とを接続する電極が増加する傾向にある。ここで用いられる半導体装置としては、アルミニウムなどにより形成された半導体パッドの上に再配線し、バンプ電極を設けたものが多用されている。上記したような半導体装置の小型化、及び電極数の増加に同時に対応するため、様々なバンプ電極の形成方法が提案されている（例えば、特許文献１及び２）。
　これらのバンプ電極の形成方法においては、半導体パッド（以下、単に電極ともいう。）の上に設ける配線のエッチング工程が存在し、配線に用いられるニッケルをエッチングしないで、銅をエッチングしなければならない場合がある。
　より具体的には、特許文献１で開示されるバンプ電極の形成方法は、導電性材料で構成される電極が設けられた基板上に、該電極部分を開口させたカバー膜を設け、さらに銅などをスパッタして形成した下地導電膜、該電極から対応するバンプ電極を形成する箇所まで延在する開口部を有するフォトレジスト膜、及び該開口部に電解めっきにより銅配線ならびにニッケル配線を順次設けた後、フォトレジスト膜を除去し、当該下地導電膜のうち配線で覆われていない部分をエッチングするという、エッチングの工程を有する。当該エッチングの工程で下地導電膜を形成する銅をエッチングする際、より高い性能を確保するためには、電解めっきにより形成したニッケル配線をエッチングしないことが望ましい。
　また、特許文献２で開示されるバンプ電極の形成方法は、アルミ電極が設けられた半導体基板上に、チタンや銅によりシード層をスパッタで形成し、バンプ電極を形成する部分を開口したレジストを形成し、該開口した箇所にチタン、銅、ニッケルなどの複数の金属を積層してなるバリアメタル層を電解めっきなどにより形成し、さらにその上にバンプ電極となるはんだを電解めっきで形成した後、該レジストを除去してから、該シード層をエッチングするエッチング工程を有する。当該エッチングの工程でシード層を形成するチタンや銅をエッチングする際、より高い性能を確保するためには、バリアメタル層を形成するニッケルなどの金属をエッチングしないことと同時に、はんだからなるバンプ電極のエッチング液による酸化を防ぐことで、該電極の性能の低減を抑制することが望ましい。
　しかし、特許文献１や特許文献２のエッチング工程では、該工程で用いられるエッチング液についての検討が十分に行われておらず、銅からなる配線などの部材をエッチングする際に、ニッケルからなる部材までもエッチングしてしまい、またバンプ電極は酸化されて、その性能が低減することが十分に予想される。上記したように、半導体装置の小型化や、高集積化及び多機能化が進むにつれて、半導体装置を使用する顧客の要求性能が厳しくなってくると、これまでの半導体装置の製造方法で製造された半導体装置では、当該要求性能に十分に満足することができない場合が生じる傾向が顕著となっていた。
特開平１１－１９５６６５号公報 特開２００５－１７５１２８号公報
本発明のバンプ電極を有する半導体装置の製造方法Ａを説明するための、該半導体装置の工程毎の断面模式図（図Ａ（ａ）～（ｇ））である。 本発明のバンプ電極を有する半導体装置の製造方法Ａを説明するための、該半導体装置の工程毎の断面模式図（図Ａ（ｈ）～（ｌ））である。 本発明のバンプ電極を有する半導体装置の製造方法Ｂを説明するための、該半導体装置の工程毎の断面模式図（図Ｂ（ａ）～（ｈ））である。 本発明のバンプ電極を有する半導体装置の製造方法Ｂを説明するための、該半導体装置の工程毎の断面模式図（図Ｂ（ｉ）～（ｐ））である。
　１０１，２０１．シリコン基板
　１０２，２０２．電極
　１０３，２０３．絶縁膜
　１０４，２０４．開口部
　１０５，２０５．チタン層
　１０６，２０６．銅層
　１０７．フォトレジスト
　１０８，２０８．開口部
　１０９．ニッケル層
　１１０，２１３．はんだ層
　１１１．バンプ電極
　１１２．凹み部
　１１４，２１４．絶縁膜
　１１６．銅層の残渣
　２０７．フォトレジスト（Ｉ）
　２０９．ニッケル層
　２１０．フォトレジスト（ＩＩ）
　２１１．開口部
　２１２．ニッケル層
　２１５．凸面状はんだ層
　２１６．凹み部
　本発明は、このような状況下になされたもので、電極を有する半導体基板を用いた半導体装置の製造に用いられ、ニッケルをエッチングせずに銅を選択的にエッチングでき、かつバンプ電極の性能低下を防止しうるエッチング液及びこれを用いた半導体装置の製造方法を提供することを目的とするものである。
　本発明者らは、前記目的を達成するために鋭意研究を重ねた結果、過酸化水素と有機酸と有機ホスホン酸とを特定の組成で含有し、該有機酸を特定のヒドロキシ酸であるクエン酸及びリンゴ酸から選ばれる少なくとも一種とするエッチング液を用いることにより、当該課題を解決できることを見出した。すなわち本発明は、以下の電極を有する半導体基板を用いた半導体装置の製造に用いられ、ニッケルをエッチングせずに銅を選択的にエッチングでき、かつバンプ電極の性能低下を防止しうるエッチング液及びこれを用いた半導体装置の製造方法を提供するものである。
［１］過酸化水素と有機酸と有機ホスホン酸とを含み、有機酸がクエン酸及びリンゴ酸から選ばれる少なくとも一種であり、過酸化水素の含有量が０．７５～１２質量％であり、有機酸の含有量が０．７５～２５質量％であり、かつ有機ホスホン酸の含有量が０．０００５～１質量％である、電極を有する半導体基板を用いた半導体装置の製造に用いられるエッチング液。
［２］過酸化水素の含有量が１．５～１２質量％であり、有機酸の含有量が１．５～２０質量％であり、有機ホスホン酸の含有量が０．００１～０．２５質量％である、上記１に記載のエッチング液。
［３］過酸化水素の含有量が１．５～５質量％であり、有機酸の含有量が１．５～１０質量％であり、有機ホスホン酸の含有量が０．０１～０．１５質量％である、上記１に記載のエッチング液。
［４］有機ホスホン酸が、ジエチレントリアミンペンタ（メチレンホスホン酸）、プロパンジアミンテトラ（メチレンホスホン酸）及び１－ヒドロキシエチリデン－１，１－ジホスホン酸から選ばれる少なくとも一種である上記１～３のいずれかに記載のエッチング液。
［５］半導体装置がはんだにより形成されたバンプ電極を有する上記１～４のいずれかに記載のエッチング液。
［６］半導体装置が銅を用いて形成される配線を有する上記１～５のいずれかに記載のエッチング液。
［７］上記１～６のいずれかに記載のエッチング液を用いるエッチング工程を有する半導体装置の製造方法。
［８］半導体装置がはんだにより形成されたバンプ電極を有するものである上記７に記載の半導体装置の製造方法。
［９］電極を有する半導体基板の該電極上に配線を形成する再配線形成工程を有する上記７又は８に記載の半導体装置の製造方法。
［１０］半導体装置が銅を用いて形成される配線を有する請求項７～９のいずれかに記載の半導体装置の製造方法。
　本発明によれば、電極を有する半導体基板を用いた半導体装置の製造工程で用いられ、ニッケルをエッチングせずに銅を選択的にエッチングでき、かつバンプ電極の性能低下を防止しうるエッチング液及びこれを用いた半導体装置の製造方法を提供することができる。
［エッチング液］
　本発明のエッチング液は、電極を有する半導体基板を用いた半導体装置の製造工程における、エッチング工程で用いられ、過酸化水素と有機酸と有機ホスホン酸とを特定の含有量で含み、該有機酸を特定のヒドロキシ酸であるクエン酸及びリンゴ酸から選ばれる少なくとも一種とする液である。
　有機ホスホン酸としては、ジエチレントリアミンペンタ（メチレンホスホン酸）、３，３´－ジアミノジプロピルアミンペンタ（メチレンホスホン酸）、エチレンジアミンテトラ（メチレンホスホン酸）、プロパンジアミンテトラ（メチレンホスホン酸）、ビス（ヘキサメチレン）トリアミンペンタ（メチレンホスホン酸）、トリエチレンテトラミンヘキサ（メチレンホスホン酸）、トリ（２－アミノエチル）アミンヘキサ（メチレンホスホン酸）、トリ（３－アミノプロピル）アミンヘキサ（メチレンホスホン酸）、テトラエチレンペンタミンヘプタ（メチレンホスホン酸）、ペンタエチレンヘキサミンオクタ（メチレンホスホン酸）、ヘキサメチレンテトラミンオクタ（メチレンホスホン酸）、アミノメチルホスホン酸、及びヒドロキシエチリデンジホスホン酸などが好ましく挙げられる。これらの化合物の有するホスホノメチル基の一部分が水素原子やメチル基などの他の基に置換されたものであってもよい。また、これらのホスホン酸系化合物のホスホン酸基は、遊離の酸でなく、例えばアンモニウム塩のような塩であっても同様に用いることができる。
　これらのうち、ジエチレントリアミンペンタ（メチレンホスホン酸）、プロパンジアミンテトラ（メチレンホスホン酸）及び１－ヒドロキシエチリデン－１，１－ジホスホン酸がより好ましく、これらから選ばれる少なくとも一種であることが好ましい。
　本発明のエッチング液において、過酸化水素の含有量は、０．７５～１２質量％であることを要する。過酸化水素の含有量が０．７５質量％未満であると、適度なエッチング速度を得ることができず、１２質量％よりも多いと過酸化水素の管理が困難となり、過酸化水素の濃度が安定しない。また、過酸化水素の管理が容易で、過酸化水素の濃度が安定し、また適度なエッチング速度と良好なエッチング性能を得る観点から、過酸化水素の含有量は、１．５～１２質量％が好ましく、１．５～５質量％がより好ましい。
　特定のヒドロキシ酸であるクエン酸及びリンゴ酸から選ばれる少なくとも一種である有機酸の含有量は、０．７５～２５質量％であることを要する。有機酸の含有量が０．７５質量％未満あるいは２５質量％よりも多いと、適度なエッチング速度とエッチング性能が得られない。また、適度なエッチング速度とエッチング性能を得る観点からは、有機酸の含有量は１．５～２０質量％が好ましく、１．５～１０質量％がより好ましい。有機酸の含有量が上記範囲内であれば、適度なエッチング速度と良好なエッチング性能が得られる。ここで、有機酸がクエン酸とリンゴ酸とを併用したものである場合、クエン酸とリンゴ酸との含有量の総量が有機酸の含有量である。
　また、有機ホスホン酸の含有量は、０．０００５～１質量％であることを要する。有機ホスホン酸の含有量が０．０００５質量％未満であると、バンプ電極のエッチング液による酸化を防ぐことができず、該電極の性能の低減を抑制することができず、１質量％よりも多いとＮｉがエッチングされてしまう。また、バンプ電極の酸化を抑制し、電極性能の低減を抑制する観点から、有機ホスホン酸の含有量は、０．００１～０．２５質量％が好ましく、０．０１～０．１５質量％がより好ましい。有機ホスホン酸の含有量が上記範囲内であれば、この抑制効果は、特にバンプ電極がはんだから形成される場合に顕著である。
　本発明のエッチング液は、過酸化水素、有機酸、及び有機ホスホン酸以外の成分として、好ましくは水を含む。水としては、蒸留、イオン交換処理、フィルター処理、各種吸着処理などによって、金属イオンや有機不純物、パーティクル粒子などが除去されたものが好ましく、特に純水、超純水が好ましい。
　本発明のエッチング液は、ニッケルをエッチングせずに銅を選択的にエッチングするという特徴を有する。よって、本発明のエッチング液は、半導体装置のなかでも特にニッケルと銅が用いられ、ニッケルをエッチングせずに選択的に銅をエッチングする必要がある半導体装置の製造工程におけるエッチング工程に好適に用いられる。
　また、本発明のエッチング液は、バンプ電極の酸化を防ぐことで、該電極の性能の低減を抑制し、この効果は該電極がはんだから形成される場合に顕著であるという特徴をも有する。よって、本発明のエッチング液は、バンプ電極を有する半導体装置の製造工程におけるエッチング工程に好ましく用いられ、特に該バンプ電極がはんだにより形成される半導体の製造工程におけるエッチング工程に好ましく用いられる。
［半導体装置の製造方法］
　本発明の半導体装置の製造方法は、本発明のエッチング液を用いるエッチング工程を有し、該半導体装置がバンプ電極を有していることが好ましい。また、当該エッチング工程は、ニッケルをエッチングせずに銅を選択的にエッチングしうる本発明のエッチング液の特徴を有効に活用する観点から、ニッケルからなる部材と銅からなる部材とが同時にエッチング液に触れうる状態であり、該銅からなる部材をエッチングすることを特徴とするものであることが好ましい。以下に、本発明の製造方法をより具体的に説明する。
《半導体装置の製造方法Ａ》
　本発明の半導体装置の製造方法の第一の態様（以下、製造方法Ａという。）は、シード層形成工程Ａ１、フォトレジスト形成工程Ａ２、バリアメタル形成工程Ａ３、はんだ層形成工程Ａ４、本発明のエッチング液を用いるエッチング工程Ａ５、及びバンプ電極形成工程Ａ６を順に有するものである。本発明の製造方法Ａを、図Ａ（ａ）～（ｌ）を用いて、詳細に説明する。
（工程Ａ１）
　工程Ａ１は、電極が設けられた半導体基板上に、該電極が露出する開口部を有する絶縁膜を設け、さらに該開口部及び該絶縁膜上にシード層を形成する、シード層形成工程である。ここで、電極が設けられた半導体基板とは、図Ａ（ａ）に示されるように、例えばシリコン基板１０１の表面に、周知の製造方法により製造された半導体素子を含む電子回路が形成され、該電子回路が形成された面に、パッドと呼ばれる、例えばアルミニウムなどの導電性材料からなる電極１０２が形成されたものである。導電性材料としては、アルミニウムのほか、チタンや銅を添加したアルミニウム合金や、銅又は銅合金、金なども好ましく挙げることができる。
　この電極１０２が設けられた半導体基板１０１上（該電極が形成された面）に、酸化ケイ素などからなる絶縁膜１０３が形成され、該絶縁膜１０３には、電極１０２に対応する開口部１０４が、電極１０２を露出するように形成する。
　次いで、図Ａ（ｂ）及び（ｃ）に示されるように、開口部１０４及び絶縁膜１０３上に、通常スパッタによりシード層を形成する。シード層を形成する金属としては、チタン、銅などが好ましく挙げられ、図Ａ（ｂ）及び（ｃ）に示されるように、これらの金属による層、チタン層１０５や銅層１０６といった層を複数設けることができる。また、基板の上にはチタン層１０５を設けることが、電極１０２との密着性や半導体装置の作製管理の観点から好ましい。
（工程Ａ２）
　工程Ａ２は、前記シード層の電極上に設けた箇所及びバンプ電極を形成する箇所を含む領域を開口し、該シード層を露出する開口部１０８を有するフォトレジスト１０７を形成する、フォトレジスト形成工程である。まず、図Ａ（ｄ）に示されるように、銅層１０６上にフォトレジスト１０７を形成する。次いで、該フォトレジストを露光、現像することにより、図Ａ（ｅ）に示されるように、後述するバンプ電極を形成するための開口部１０８を有するフォトレジスト１０７を形成する。
（工程Ａ３）
　工程Ａ３は、前記開口部１０８内にバリアメタル層を設けるバリアメタル形成工程である。通常、工程Ａ３においては、図Ａ（ｆ）に示されるように、電解めっき処理などの方法によりニッケル層１０９が設けられ、該ニッケル層１０９、工程Ａ１で設けられたチタン層１０５及び銅層１０６をあわせて、バリアメタル層という。該バリアメタル層は、電極１０２と後述するバンプ電極１１１との間における拡散などの防止のために設けられる層であり、該バンプ電極１１１と接する面には、ニッケルあるいはニッケル合金により形成されるニッケル層１０９を設けることが好ましい。
（工程Ａ４）
　工程Ａ４は、図Ａ（ｆ）に示されるように、ニッケル層１０９の上に、はんだ層１１０を設ける工程である。はんだ層１１０は、通常チタン層１０５及び銅層１０６をシード層とした電解めっき処理により形成され、この段階では通常開口部１０８からフォトレジスト１０７の表面にはみだし、きのこ型の形状を有している。該はんだ層１１０を形成する材質としては、錫、鉛やこれらの合金（錫－鉛合金）のほか、錫－銀系合金、錫－銀－銅系合金、錫－銅系合金、錫－亜鉛系合金、錫－ビスマス系合金、錫－亜鉛－ビスマス系合金などのはんだ材料が好ましく挙げられる。
（工程Ａ５）
　工程Ａ５は、図Ａ（ｈ）に示されるように、フォトレジストを除去してから、さらに図Ａ（ｉ）及び（ｊ）のように、本発明のエッチング液を用いて、チタン層１０５及び銅層１０６などのシード層のうち、ニッケル層１０９あるいははんだ層１１０で覆われていない露出部分をエッチングする、エッチング工程である。本発明のエッチング液を用いることで、ニッケルをエッチングせずに銅を選択的にエッチングすることが可能となる。また、本製造方法のように、バンプ電極をはんだで形成し、特にはんだが錫を含む場合、本発明のエッチング液を用いることで、該電極が酸化することなく、性能が低減することがないという効果も得られる。
　エッチング対象物にエッチング液を接触させる方法には特に制限はなく、例えばエッチング液を滴下やスプレーなどの形式により対象物に接触させる方法や、対象物をエッチング液に浸漬させる方法などを採用することができる。本発明においては、エッチング液を対象物にスプレーして接触させる方法が好ましく採用される。
　エッチング液の使用温度としては、５０℃以下の温度が好ましく、より好ましくは２０～５０℃、さらに好ましくは２０～４０℃、特に好ましくは２５～３５℃である。エッチング液の温度が５０℃以上になれば、エッチング速度は上昇するが、液の安定性が悪くなり、エッチング条件を一定に保つのが困難になる。エッチング液の温度を５０℃以下にすることで、エッチング液の組成変化を小さく抑え、安定性したエッチング速度を得ることができる。また、２０℃以上であれば、エッチング速度が遅くなりすぎず、生産効率が著しく低下することがない。
　図Ａ（ｉ）で示されるように、本エッチング工程で銅層１０６をエッチングする際、ニッケル層１１２の側面がエッチング液に晒されることになる。このような場合に、本発明のエッチング液を用いると、図Ａ（ｌ）に示されるようなニッケル層１０９がエッチングされて凹み部１１２が形成するということがなく、銅層１０６だけを選択的にエッチングすることが可能となる。
（工程Ａ６）
　工程Ａ６は、はんだ層１１０を溶融させることにより、バンプ電極１１１を得るバンプ電極形成工程である。はんだ層１１０の溶融は、基板を加熱してリフロー処理により行えばよく、該リフロー処理によりきのこ型のはんだ層１１１は、図Ａ（ｋ）に示されるように、球状を呈したバンプ電極１１１となる。
　このようにして、電極を有する半導体基板から、バンプ電極を有する半導体装置を製造することができる。
《半導体装置の製造方法Ｂ》
　本発明の半導体装置の製造方法の第二の態様（以下、製造方法Ｂという。）は、シード層形成工程Ｂ１、フォトレジスト（Ｉ）形成工程Ｂ２、再配線形成工程Ｂ３、フォトレジスト（ＩＩ）形成工程Ｂ４、バンプ電極形成工程Ｂ５、本発明のエッチング液を用いるエッチング工程Ｂ６を順に有するものである。本発明の製造方法Ｂを、図Ｂ（ａ）～（ｐ）を用いて、詳細に説明する。
（工程Ｂ１）
　工程Ｂ１は、電極が設けられた半導体基板上に、該電極が露出する開口部を有する絶縁膜を設け、さらに該開口部及び該絶縁膜上にシード層を形成する、シード層形成工程であり、上記工程Ａ１と同じである。
　本工程により、図Ｂ（ａ）～（ｃ）に示されるように、電極２０２が設けられた半導体基板２０１上（該電極が形成された面）に、電極２０２に対応する開口部２０４を有する絶縁膜２０３が電極２０２を露出するように形成され、該開口部２０４及び絶縁膜２０３上に、シード層としてチタン層２０５及び銅層２０６が形成される。
（工程Ｂ２）
　工程Ｂ２は、前記シード層の電極上に設けた箇所及びバンプ電極を形成する箇所を含む領域を開口し、該シード層を露出する開口部２０８を有するフォトレジスト（Ｉ）２０７を形成する、フォトレジスト（Ｉ）形成工程である。まず、図Ａ（ｄ）に示されるように、銅層２０６上にフォトレジスト（Ｉ）２０７を形成する。次いで、該フォトレジストを露光、現像することにより、図Ａ（ｅ）に示されるように、シード層の電極２０２上に設けた箇所と後述するバンプ電極を形成する箇所を含む領域までをつなぐ再配線を形成するための開口部２０８を有するフォトレジスト（Ｉ）２０７を形成する。
（工程Ｂ３）
　工程Ｂ３は、前記開口部２０８に配線を設けて再配線する、再配線形成工程である。この再配線形成工程により、電極２０２を有する半導体基板２０１の該電極２０２上に配線を形成する再配線の形成がなされる。配線は、銅やニッケルなどの材料が使用され、図Ｂ（ｆ）に示されるように、少なくとも銅により形成される銅層２０９を有することが好ましい。また、配線は通常銅やニッケルを電解めっき処理することにより設けられる。
（工程Ｂ４）
　工程Ｂ４は、図Ｂ（ｇ）及び（ｈ）で示されるように、シード層及び配線を被覆するようにフォトレジスト（ＩＩ）２１０を形成し、さらに露光、現像することによりフォトレジスト（ＩＩ）２１０にバンプ電極を形成するための開口部２１１を形成する、フォトレジスト（ＩＩ）形成工程である。このフォトレジスト（ＩＩ）２１０は、常法により設ければよい。なお、予めフォトレジスト（Ｉ）を除去してから、フォトレジスト（ＩＩ）２１0を形成することもできる。
（工程Ｂ５）
　工程Ｂ５は、図Ｂ（ｉ）及び（ｊ）に示されるように、前記フォトレジスト（ＩＩ）２１０のバンプ電極を形成する箇所に、再配線の銅層２０９が露出するように開口部２１１を設け、該開口部２１１にニッケルからなるニッケル層２１２を少なくとも一層有するバンプ電極を形成する、バンプ電極形成工程である。
　バンプ電極は、上記はんだ層１１０を形成するはんだ材料のほか、金、パラジウム、ニッケル、銅などを用いて、電解めっきにより形成することができ、一層または複数層により形成することができる。例えば、図Ａ（ｊ）のように、ニッケル層２１２を設けた後に、はんだ材料からなるはんだ層２１３を設けてバンプ電極を形成することができる。本発明の製造方法においては、バンプ電極を形成する層がニッケル層２１２及びはんだ層２１３の組み合わせであると、本発明のエッチング液が有するニッケルをエッチングせずに銅を選択的にエッチングできるという性能、及び該電極を酸化することなく、性能が低減することがないという性能を有効に活用することができる。
（工程Ｂ６）
　工程Ｂ６は、図Ｂ（ｋ）のようにフォトレジスト（Ｉ）２０７及びフォトレジスト（ＩＩ）２１０をレジスト剥離液を用いて除去してから、さらに図Ｂ（ｌ）及び（ｍ）に示されるように、チタン層２０５や銅層２０６などのシード層のうち、銅層２０９のような配線で覆われていない露出部分をエッチングする、エッチング工程である。該エッチング工程においては、本発明のエッチング液が用いられることを要する。本発明のエッチング液を用いることで、ニッケルをエッチングせずに銅を選択的にエッチングすることが可能となる。また、本製造方法のように、バンプ電極をはんだで形成し、特にはんだが錫を含む場合、本発明のエッチング液を用いることで、該電極が酸化することなく、性能が低減することがないという効果も得られる。工程Ｂ６におけるエッチングの諸条件は、工程Ａ５と同じである。
　図Ｂ（ｌ）で示されるように、工程Ｂ６のエッチング工程で銅層２０６をエッチングする際、ニッケル層２１２がエッチング液に晒されることになる。このような場合に、本発明のエッチング液を用いると、図Ｂ（ｐ）に示されるようなニッケル層２１２が
エッチングされて凹み部２１６が形成するということがなく、銅層２０６だけを選択的にエッチングすることが可能となる。
　本発明の製造方法Ｂにおいて、図Ｂ（ｎ）に示されるように、さらにバンプ電極が形成された領域以外の部分に絶縁膜２１４を形成することができる。該絶縁膜２１４の形成は、エポキシ樹脂やポリイミド樹脂などの絶縁性有機材料などが好ましく用いられる。
　さらに、図Ｂ（ｏ）に示されるように、前記工程Ｂ５で形成したはんだ層２１３を溶融させることにより、凸面状はんだ層２１５を形成することもできる。はんだ層２１３の溶融は、基板を加熱してリフロー処理により行えばよい。
　本発明の製造方法のうち、製造方法Ｂにより、電極を有する半導体基板の該電極上に配線を形成する再配線がなされた、バンプ電極を有する半導体装置が得られる。これらの製造方法によれば、電極がピッチ１５０μｍ以下、１００μｍ以下、さらには５０μｍ以下という狭いピッチの半導体基板を用いることが可能である。また、バンプ電極のピッチが５００μｍ以下、２５０μｍ以下、さらには２００μｍ以下という狭いピッチの半導体装置を得ることができる。よって、本発明の製造方法により得られた半導体装置は、近年の小型化や、高集積化及び多機能化にも十分対応しうるものである。
　次に、本発明を実施例により、さらに詳しく説明するが、本発明は、これらの例によってなんら限定されるものではない。
《処理液の調製》
　表１に示される配合組成（質量％）に従い、各実施例及び比較例で用いるエッチング液を調整した。
《評価方法》
評価項目．めっきの外観（変色）の評価
　実施例１～３８及び比較例１～２０について、エッチング液による処理前後の錫－鉛はんだめっき及び錫めっきの外観（変色）の状態を目視により、以下の基準で評価した。
　○　：変色は全く確認されなかった
　△　：変色は若干あるものの、実用上問題ない
　×　：変色が著しく、使用できない
実施例１～３８及び比較例１～２０
　スパッタ銅（銅膜の厚さ：５０００Å）、錫－鉛はんだめっき（その含有比は錫：鉛＝６：４）、錫めっきを成膜した基板を、表１に示される各実施例及び比較例のエッチング液に３０℃で２分間浸漬した。
　浸漬後の基板において、スパッタ銅については、浸漬前後の膜厚変化を蛍光Ｘ線分析装置（「ＳＥＡ２１１０Ｌ）」，エスエスアイナノテクノロジー社製）を用いて測定し、銅のエッチングレート（μｍ／分）を算出した。錫－鉛はんだ、及び錫めっきについては、浸漬前後の外観、特に変色状況を目視にて観察し、上記の評価基準に基づき評価した。
　また、鋼材に電解めっきによりニッケルを成膜（ニッケル膜の厚さ：５μｍ）した基板を、各実施例及び比較例のエッチング液に、３０℃で１時間浸漬し、浸漬前後の重量を測定し、エッチングレート（Å／分）を算出した。これらの算出値及び評価の結果を表１に示す。
Figure JPOXMLDOC01-appb-T000001
《評価方法》
評価項目．半導体基板を用いたエッチングの評価
　実施例３９～４４及び比較例２１～２７のエッチング液を用い、Ａの手順で半導体装置を製造した。得られた半導体装置について、電解めっきにより設けたニッケル層の凹み部、シード層として設けた銅層のエッチング後の残存状態、及びバンプ電極の変色の状態を、各々下記の基準で評価した。
（ニッケル層の凹み部の状態について）
　○　：ニッケル層の凹み部は全く確認されなかった
　△　：ニッケル層の凹み部は若干あるものの、実用上問題ない
　×　：ニッケル層の凹み部が著しく、使用できない
（銅層の残存状態）
　○　：エッチング後、銅層の残存は全く確認されなかった
　△　：エッチング後、銅層の残存がわずかに確認されたが、実用上問題ない
　×　：エッチング後、銅層の残存が著しく、使用できない
（バンプ電極の変色の状態について）
　○　：変色は全く確認されなかった
　△　：変色は若干あるものの、実用上問題ない
　×　：変色が著しく、使用できない
実施例３９～４４及び比較例２１～２７（製造方法Ａによる半導体装置の製造）
　製造方法Ａ（図Ａ（ａ）～（ｋ））の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。ここで、はんだ層１１０の形成には錫－鉛はんだ（含有比は錫：鉛＝６：４）を用い、図Ａ（ｉ）～（ｊ）に示されるエッチング工程において、表２に示される各実施例及び比較例のエッチング液を用いて、銅層１０６及びチタン層１０５のエッチングを順に行った。このとき、エッチング温度は３０℃であり、エッチング時間は表２に示される時間とした。
　各実施例及び比較例で得られた半導体装置について、上記評価基準に従って評価した結果を表２に示す。
実施例４５及び比較例２８
　実施例３９及び比較例２１において、はんだ層１１０を錫－鉛はんだ（含有比は錫：鉛＝６：４）のかわりに錫－銀はんだ（銀の含有量：３質量％）を用いた以外は、実施例３９及び比較例２１と同様にして、各々実施例４５及び比較例２８の半導体装置を作製した。
　各実施例及び比較例で得られた半導体装置について、上記評価項目に従い評価した結果を表２に示す。
実施例４６～５１及び比較例２９～３５（製造方法Ｂによる半導体装置の製造）
　製造方法Ｂ（図Ｂ（ａ）～（ｋ））の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。ここで、はんだ層１１０の形成には錫－鉛はんだ（含有比は錫：鉛＝６：４）を用い、図Ｂ（ｌ）～（ｍ）に示されるエッチング工程において、表３に示される各実施例及び比較例のエッチング液を用いて、銅層２０６及びチタン層２０５のエッチングを順に行った。このとき、エッチング温度は３０℃であり、エッチング時間は表３に示される時間とした。
　各実施例及び比較例で得られた半導体装置について、上記評価基準に従って評価した結果を表３に示す。
実施例５２及び比較例３６
　実施例４６及び比較例２９において、はんだ層２１０を錫－鉛はんだ（含有比は錫：鉛＝６：４）のかわりに錫－銀はんだ（銀の含有量：３質量％）を用いた以外は、実施例４６及び比較例３６と同様にして、各々実施例５２及び比較例３６の半導体装置を作製した。
　各実施例及び比較例で得られた半導体装置について、上記評価項目に従い評価した結果を表３に示す。
Figure JPOXMLDOC01-appb-T000003
　実施例１～３８の結果より、本発明のエッチング液は、スパッタ銅に対して０．１μｍ／分以上という高いエッチング速度を有するにもかかわらず、電解ニッケルめっきに対しては５０Å／分未満という低いエッチング速度に抑えられていることが確認された。また、錫－鉛はんだめっき、及び錫めっきについては、有機ホスホン酸の含有量が０．０１質量％未満と少ない場合に若干の変色が認められたものの、実用上問題となることはなく、またその他の実施例において、変色は全く認められなかった。
　一方、過酸化水素の含有量が０．５質量％と少ない比較例２及び５、クエン酸の含有量が０．５質量％と少ない比較例３、リンゴ酸の含有量が０．５質量％と少ない比較例６では、スパッタ銅のエッチング速度は０．１μｍ／分未満と低いものだった。また、クエン酸やリンゴ酸のかわりに、他の有機酸を含む比較例９、１１及び１８でも、スパッタ銅のエッチング速度は０．１μｍ／分未満と低いものだった。
　有機ホスホン酸を含まない比較例１及び４では、錫－鉛はんだめっき、及び錫めっきのいずれにも変色が認められた。また、有機ホスホン酸を０．０５質量％含有するエッチング液であっても、有機酸としてクエン酸、リンゴ酸を含まない比較例７～１０及び１２では、錫－鉛はんだめっき、あるいは錫めっきに変色が認められた。
　過酸化水素を５質量％含み、有機酸としてクエン酸及びリンゴ酸を含まない比較例８、１３及び１７では、電解ニッケルめっきのエッチング速度は１５００Å／分以上となり、銅の選択的なエッチングはできなかった。
　過酸化水素を５質量％含み、有機酸として酒石酸、グルタル酸、イタコン酸を含む各々比較例１５、１９、２０では、実施例１～３８と同等のエッチング性能が得られた。しかし、これらの比較例で使用したエッチング液を用いて半導体装置を作製した各々比較例２５～２７では、エッチング後の銅層の残存が著しく、半導体装置の作製には使用できないことが確認された。
　本発明のエッチング液は、電極を有する半導体基板を用いた半導体装置の製造工程で用いられるものである。該半導体装置の製造工程に含まれるエッチング工程において、銅からなる層をエッチングする際にニッケルからなる層がエッチング液に晒される場合、該ニッケルからなる層をエッチングしたくないときに、本発明のエッチング液は特に有効である。

Claims (10)

  1. 　過酸化水素と有機酸と有機ホスホン酸とを含み、有機酸がクエン酸及びリンゴ酸から選ばれる少なくとも一種であり、過酸化水素の含有量が０．７５～１２質量％であり、有機酸の含有量が０．７５～２５質量％であり、かつ有機ホスホン酸の含有量が０．０００５～１質量％である、電極を有する半導体基板を用いた半導体装置の製造に用いられるエッチング液。
  2. 　過酸化水素の含有量が１．５～１２質量％であり、有機酸の含有量が１．５～２０質量％であり、有機ホスホン酸の含有量が０．００１～０．２５質量％である、請求項１に記載のエッチング液。
  3. 　過酸化水素の含有量が１．５～５質量％であり、有機酸の含有量が１．５～１０質量％であり、有機ホスホン酸の含有量が０．０１～０．１５質量％である、請求項１に記載のエッチング液。
  4. 　有機ホスホン酸が、ジエチレントリアミンペンタメチレンホスホン酸、プロパンジアミンテトラメチレンホスホン酸及び１－ヒドロキシエチリデン－１，１－ジホスホン酸から選ばれる少なくとも一種である請求項１～３のいずれかに記載のエッチング液。
  5. 　半導体装置がはんだにより形成されたバンプ電極を有する請求項１～４のいずれかに記載のエッチング液。
  6. 　半導体装置が銅を用いて形成される配線を有する請求項１～５のいずれかに記載のエッチング液。
  7. 　請求項１～６のいずれかに記載のエッチング液を用いるエッチング工程を有する半導体装置の製造方法。
  8. 　半導体装置がはんだにより形成されたバンプ電極を有するものである請求項７に記載の半導体装置の製造方法。
  9. 　電極を有する半導体基板の該電極上に配線を形成する再配線形成工程を有する請求項７又は８に記載の半導体装置の製造方法。
  10. 　半導体装置が銅を用いて形成される配線を有する請求項７～９のいずれかに記載の半導体装置の製造方法。
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JPWO2017188108A1 (ja) * 2016-04-27 2019-02-28 三洋化成工業株式会社 エッチング液及び電子基板の製造方法
JP2016135928A (ja) * 2016-05-06 2016-07-28 アドバンスド テクノロジー マテリアルズ，インコーポレイテッド 銅または銅合金用エッチング液
JP2021184508A (ja) * 2017-09-20 2021-12-02 大日本印刷株式会社 リードフレームおよび半導体装置
JP7180735B2 (ja) 2017-09-20 2022-11-30 大日本印刷株式会社 リードフレームおよび半導体装置
JP2020178044A (ja) * 2019-04-18 2020-10-29 パナソニックＩｐマネジメント株式会社 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法
JP7357243B2 (ja) 2019-04-18 2023-10-06 パナソニックＩｐマネジメント株式会社 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法
JP7573220B2 (ja) 2019-04-18 2024-10-25 パナソニックＩｐマネジメント株式会社 半導体装置および半導体装置の製造方法

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US9177827B2 (en) 2015-11-03
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JP5794148B2 (ja) 2015-10-14
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EP2518759A4 (en) 2014-11-05
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