TWI530589B - 蝕刻液及使用此蝕刻液的半導體裝置之製造方法 - Google Patents

蝕刻液及使用此蝕刻液的半導體裝置之製造方法 Download PDF

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Publication number
TWI530589B
TWI530589B TW099145796A TW99145796A TWI530589B TW I530589 B TWI530589 B TW I530589B TW 099145796 A TW099145796 A TW 099145796A TW 99145796 A TW99145796 A TW 99145796A TW I530589 B TWI530589 B TW I530589B
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Taiwan
Prior art keywords
etching
semiconductor device
electrode
layer
acid
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TW099145796A
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English (en)
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TW201132804A (en
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Akira Hosomi
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Mitsubishi Gas Chemical Co
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
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Description

蝕刻液及使用此蝕刻液的半導體裝置之製造方法
本發明係關於一種蝕刻液及使用此蝕刻液之半導體裝置之製造方法，用於製造使用包含電極之半導體基板之半導體裝置，可選擇性地不蝕刻鎳而蝕刻銅。
近年來，伴隨著業界要求電子設備小型化，用於該設備之半導體裝置小型化或高密度化及多功能化取得進展，連接半導體裝置與電子設備之電極傾向於增加。作為在此使用之半導體裝置，吾人頻繁使用在以鋁等形成之半導體接墊上再配線，設置凸塊電極者。為同時對應如上述之半導體裝置小型化及電極數之增加，有人提倡各種凸塊電極形成方法(例如專利文獻1及2)。
此等凸塊電極形成方法中，存在有設在半導體接墊(以下亦僅稱電極。)上的配線之蝕刻步驟，有時需不蝕刻用於配線之鎳而蝕刻銅。
更具體而言，於專利文獻1所揭示之凸塊電極形成方法包含下列程序的蝕刻步驟：在設有由導電性材料構成之電極之基板上，設置使該電極部分開口之表覆膜，更依序設置濺鍍銅等而形成之基底導電膜、包含自該電極起延伸至形成對應之凸塊電極處為止之開口部的光阻膜、及藉由電解電鍍方式於該開口部設置的銅配線以及鎳配線，然後去除光阻膜，蝕刻該基底導電膜中之未由配線包覆之部分。於該蝕刻步驟蝕刻形成基底導電膜之銅時，為確保更高的性能，宜不蝕刻藉由電解電鍍方式形成之鎳配線。
且於專利文獻2揭示之凸塊電極形成方法包含下列蝕刻步驟：在設有鋁電極之半導體基板上，藉由鈦或銅以濺鍍方式形成種子層，形成在形成凸塊電極之部分開口之光阻，於該開口處藉由電解電鍍方式等形成堆疊鈦、銅、鎳等複數金屬構成之阻障金屬層，且於其上以電解電鍍方式形成成為凸塊電極之焊料後，去除該光阻再蝕刻該種子層。於該蝕刻步驟蝕刻形成種子層之鈦或銅時，為確保更高的性能，宜不蝕刻形成阻障金屬層之鎳等金屬，同時藉由防止焊料所構成之凸塊電極因蝕刻液氧化，抑制該電極性能之降低。
然而，專利文獻1或專利文獻2之蝕刻步驟中，未充分檢視關於在該步驟中使用之蝕刻液，蝕刻銅所構成之配線等構件時，連鎳所構成之構件亦一併蝕刻，且可大致預測凸塊電極會受到氧化，其性能降低。如上述，一旦隨著半導體裝置小型化或高密度化及多功能化取得進展，使用半導體裝置之顧客嚴格要求其性能，發生藉由以至今為止之半導體裝置製造方法製造之半導體裝置無法充分滿足該要求性能之情形之傾向即會變得顯著。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開平11-195665號公報
[專利文獻2]日本特開2005-175128號公報
鑑於如此情事，本發明之目的在於提供一種蝕刻液及使用此蝕刻液之半導體裝置製造方法，用於製造使用包含電極之半導體基板之半導體裝置，可選擇性地不蝕刻鎳而蝕刻銅，且可防止凸塊電極性能降低。
為達成該目的，本案發明人等不斷戮力研究，結果發現藉由使用以特定組成含有過氧化氫、有機酸與有機膦酸，該有機酸為選自於係特定羥酸之枸櫞酸及蘋果酸至少其中一者之蝕刻液，可解決該課題。亦即本發明提供以下一種蝕刻液及使用此蝕刻液的半導體裝置之製造方法，用於製造使用有包含電極之半導體基板之半導體裝置，可選擇性地不蝕刻鎳而蝕刻銅，且可防止凸塊電極性能降低。
[1]一種蝕刻液，用於製造使用有包含電極之半導體基板之半導體裝置，包含過氧化氫、有機酸與有機膦酸，有機酸係選自於枸櫞酸及蘋果酸中至少一種酸，過氧化氫含量為0.75~12質量%，有機酸含量為0.75~25質量%，且有機膦酸含量為0.0005~1質量%。
[2]如1之蝕刻液，其中過氧化氫含量為1.5~12質量%，有機酸含量為1.5~20質量%，有機膦酸含量為0.001~0.25質量%。
[3]如1之蝕刻液，其中過氧化氫含量為1.5~5質量%，有機酸含量為1.5~10質量%，有機膦酸含量為0.01~0.15質量%。
[4]如1至3中任一之蝕刻液，其中有機膦酸係選自於二乙烯三胺五亞甲基膦酸、丙二胺四亞甲基膦酸及1-羥基亞乙基-1,1-二膦酸中至少一種酸。
[5]如1至4中任一之蝕刻液，其中半導體裝置包含藉由焊料形成之凸塊電極。
[6]如1至5中任一之蝕刻液，其中半導體裝置包含使用銅形成之配線。
[7]一種半導體裝置之製造方法，包含使用如1至6項任一之蝕刻液之蝕刻步驟。
[8]如7之半導體裝置之製造方法，其中半導體裝置包含藉由焊料形成之凸塊電極。
[9]如7或8之半導體裝置之製造方法，其中包含在具有電極之半導體基板該電極上形成配線之再配線形成步驟。
[10]如上述7至9中任一之半導體裝置之製造方法，其中半導體裝置包含使用銅形成之配線。
依本發明可提供一種蝕刻液及使用此蝕刻液之半導體裝置製造方法，用於使用包含電極之半導體基板之半導體裝置製造步驟中，選擇性地不蝕刻鎳而蝕刻銅，且可防止凸塊電極性能降低。
 [蝕刻液]
本發明之蝕刻液在使用包含電極之半導體基板之半導體裝置製造步驟中，於蝕刻步驟內被使用，以特定含量包含過氧化氫、有機酸與有機膦酸，該有機酸為選自於係特定羥酸之枸櫞酸及蘋果酸至少其中一者。
作為有機膦酸，舉例而言宜係二乙烯三胺五(亞甲基膦酸)、3,3'-二胺二丙胺五(亞甲基膦酸)、乙烯二胺四(亞甲基膦酸)、丙二胺四(亞甲基膦酸)、雙(六亞甲基)三胺五(亞甲基膦酸)、三乙烯四胺六(亞甲基膦酸)、三(2-胺乙烯)胺六(亞甲基膦酸)、三(3-胺丙基)胺六(亞甲基膦酸)、四乙烯五胺七(亞甲基膦酸)、五乙烯六胺八(亞甲基膦酸)、六亞甲基四胺八(亞甲基膦酸)、胺亞甲基膦酸及羥基亞乙基二膦酸等。此等化合物~含之膦羧亞甲基一部分亦可由氫原子或亞甲基等其他基取代。且此等膦酸類化合物之膦酸基即使非遊離酸而係例如銨鹽之鹽亦可同樣地使用。
此等者中，二乙烯三胺五(亞甲基膦酸)、丙二胺四(亞甲基膦酸)及1-羥基亞乙基-1,1-二膦酸尤佳，宜係選自於此等者至少其中一者。
本發明之蝕刻液中，過氧化氫含量需為0.75~12質量%。過氧化氫含量若未滿0.75質量%，即無法獲得適當的蝕刻速度，若多於12質量%則難以管理過氧化氫，過氧化氫濃度不穩定。且自輕易管理過氧化氫，過氧化氫濃度穩定，且獲得適當的蝕刻速度與良好的蝕刻性能之觀點而言，過氧化氫含量宜為1.5~12質量%，1.5~5質量%則更佳。
為選自於係特定羥酸之枸櫞酸及蘋果酸至少其中一者之有機酸含量需為0.75~25質量%。有機酸含量若未滿0.75質量%或是多於25質量%，即無法獲得適當的蝕刻速度與蝕刻性能。且自獲得適當的蝕刻速度與蝕刻性能之觀點而言，有機酸含量宜為1.5~20質量%，為1.5~10質量%則更佳。有機酸含量若在上述範圍內，即可獲得適當的蝕刻速度與良好的蝕刻性能。在此，有機酸併用枸櫞酸與蘋果酸時，枸櫞酸與蘋果酸之含量總量為有機酸含量。
且有機膦酸含量需為0.0005~1質量%。有機膦酸含量若未滿0.0005質量%，即無法防止凸塊電極因蝕刻液氧化，無法抑制該電極性能降低，若多於1質量%則會蝕刻Ni。且自抑制凸塊電極氧化，抑制電極性能降低之觀點而言，有機膦酸含量宜為0.001~0.25質量%，為0.01~0.15質量%則更佳。有機膦酸含量若在上述範圍內，其抑制效果特別是在凸塊電極由焊料形成時相當顯著。
本發明之蝕刻液中，作為過氧化氫、有機酸及有機膦酸以外之成分，宜包含水。作為水，宜藉由蒸留、離子交換處理、濾器處理、各種吸附處理等去除金屬離子或有機雜質、顆粒粒子等，特別是宜為純水、超純水。
本發明之蝕刻液具有選擇性地不蝕刻鎳而蝕刻銅之特徵。藉此，本發明之蝕刻液適合使用在半導體裝置中特別頻繁使用鎳與銅，需選擇性地不蝕刻鎳而蝕刻銅之半導體裝置製造步驟中的蝕刻步驟內。
且本發明之蝕刻液亦具有藉由防止凸塊電極氧化，抑制該電極性能降低，其效果在該電極由焊料形成時相當顯著之特徵。藉此，本發明之蝕刻液宜使用在包含凸塊電極之半導體裝置製造步驟中的蝕刻步驟內，特別是宜使用在該凸塊電極藉由焊料形成之半導體製造步驟中的蝕刻步驟內。
[半導體裝置之製造方法]
本發明之半導體裝置製造方法宜包含使用本發明蝕刻液之蝕刻步驟，該半導體裝置包含凸塊電極。且該蝕刻步驟自有效活用可選擇性地不蝕刻鎳而蝕刻銅之本發明蝕刻液之特徵之觀點而言，其特徵宜為在鎳所構成之構件與銅所構成之構件同時可接觸蝕刻液之狀態下蝕刻該銅所構成之構件。以下更具體地說明本發明之製造方法。
《半導體裝置之製造方法A》
本發明之半導體裝置製造方法第一態樣(以下稱製造方法A。)依序包含種子層形成步驟A1、光阻形成步驟A2、阻障金屬形成步驟A3、焊料層形成步驟A4、使用本發明蝕刻液之蝕刻步驟A5及凸塊電極形成步驟A6。使用圖A(a)~(l)詳細說明本發明之製造方法A。
(步驟A1)
步驟A1係在設有電極之半導體基板上設置包含該電極露出之開口部之絕緣膜，且在該開口部及該絕緣膜上形成種子層之種子層形成步驟。在此，所謂設有電極之半導體基板如圖A(a)所示，在例如矽基板101表面形成包含藉由周知製造方法製造之半導體元件之電子電路，在形成該電子電路之面形成稱為接墊，由例如鋁等導電性材料所構成之電極102。作為導電性材料，除鋁外，可舉例而言宜係添加鈦或銅之鋁合金或銅或銅合金、金等。
在設有此電極102之半導體基板101上(形成該電極之面)形成氧化矽等所構成之絕緣膜103，在該絕緣膜103形成對應電極102之開口部104，俾露出電極102。
接著，如圖A(b)及(c)所示，在開口部104及絕緣膜103上通常藉由濺鍍方式形成種子層。作為形成種子層之金屬，舉例而言宜係鈦、銅等，可如圖A(b)及(c)所示，設置複數此等金屬構成之層，鈦層105或銅層106之層。且自與電極102之密接性或半導體裝置之製作管理之觀點而言，在基板上宜設置鈦層105。
(步驟A2)
步驟A2係光阻形成步驟，形成光阻107，該光阻於包含在該種子層電極上設置處及形成凸塊電極處之區域形成開口，包含露出該種子層之開口部108。首先，如圖A(d)所示，在銅層106上形成光阻107。接著，藉由使該光阻曝光、顯影，如圖A(e)所示，形成包含後述用以形成凸塊電極之開口部108之光阻107。
(步驟A3)
步驟A3係在該開口部108內設置阻障金屬層之阻障金屬形成步驟。通常於步驟A3，如圖A(f)所示，係藉由電解電鍍處理等方法設置鎳層109，該鎳層109、於步驟A1設置之鈦層105及銅層106一併稱為阻障金屬層。該阻障金屬層係為防止在電極102與後述凸塊電極111之間擴散等而設置之層，在與該凸塊電極111接觸之面宜設置藉由鎳或是鎳合金形成之鎳層109。
(步驟A4)
步驟A4如圖A(f)所示，係在鎳層109上設置焊料層110之步驟。焊料層110通常藉由以鈦層105及銅層106為種子層之電解電鍍處理形成，於此階段通常自開口部108突出於光阻107表面，形狀呈香菇型。做為形成該焊料層110之材質，除錫、鉛或此等合金(錫-鉛合金)外，舉例而言宜係錫-銀類合金、錫-銀-銅類合金、錫-銅類合金、錫-鋅類合金、錫-鉍類合金、錫-鋅-鉍類合金等焊接材料。
(步驟A5)
步驟A5係如圖A(h)所示，去除光阻，再如圖A(i)及(j)，更使用本發明之蝕刻液，蝕刻鈦層105及銅層106等種子層中，未由鎳層109或是焊料層110包覆之露出部分之蝕刻步驟。藉由使用本發明之蝕刻液，可選擇性地不蝕刻鎳而蝕刻銅。且如本製造方法，在以焊料形成凸塊電極，特別是焊料包含錫時，藉由使用本發明之蝕刻液，亦可獲得該電極不氧化，性能不降低之效果。
蝕刻對象物接觸蝕刻液之方法中無特別限制，可採用例如以滴入或噴灑等形式使對象物接觸蝕刻液之方法，或使對象物浸漬於蝕刻液之方法等。本發明中，宜採用噴灑蝕刻液以使對象物接觸之方法。
作為蝕刻液之使用溫度，宜在50℃以下，20~50℃更佳，為20~40℃則相當理想，特別是為25~35℃則非常理想。蝕刻液溫度若在50℃以上，蝕刻速度雖上昇但液體穩定性差，蝕刻條件難以保持一定。藉由使蝕刻液溫度在50℃以下，可抑制蝕刻液組成變化至甚小，可獲得穩定之蝕刻速度。且若在20℃以上，蝕刻速度即不會過慢，生產效率不會顯著降低。
如圖A(i)所示，於本蝕刻步驟蝕刻銅層106時，鎳層109側面會暴露於蝕刻液中。在如此時，若使用本發明之蝕刻液，即不會如圖A(l)所示鎳層109受到蝕刻而形成凹陷部112，可選擇性地僅蝕刻銅層106。
(步驟A6)
步驟A6係藉由使焊料層110熔融獲得凸塊電極111之凸塊電極形成步驟。焊料層110之熔融加熱基板以藉由回流處理進行之即可，藉由該回流處理香菇型焊料層110如圖A(k)所示，成為呈球狀之凸塊電極111。
如此，可自包含電極之半導體基板製造包含凸塊電極之半導體裝置。
《半導體裝置之製造方法B》
本發明之半導體裝置製造方法第二態樣(以下稱製造方法B。)依序包含種子層形成步驟B1、光阻(I)形成步驟B2、再配線形成步驟B3、光阻(II)形成步驟B4、凸塊電極形成步驟B5、使用本發明蝕刻液之蝕刻步驟B6。使用圖B(a)~(p)詳細說明本發明之製造方法B。
(步驟B1)
步驟B1係在設有電極之半導體基板上設置包含該電極露出之開口部之絕緣膜，且在該開口部及該絕緣膜上形成種子層之種子層形成步驟，與上述步驟A1相同。
依本步驟，如圖B(a)~(c)所示，在設有電極202之半導體基板201上(形成該電極之面)形成包含對應電極202之開口部204之絕緣膜203，俾露出電極202，在該開口部204及絕緣膜203上作為種子層形成鈦層205及銅層206。
(步驟B2)
步驟B2係光阻(I)形成步驟，形成光阻(I)207，該光阻(I)於包含在該種子層電極上設置處及形成凸塊電極處之區域形成開口，包含露出該種子層之開口部208。首先，如圖A(d)所示，在銅層206上形成光阻(I)207。接著，藉由使該光阻曝光、顯影，如圖A(e)所示，形成光阻(I)207，該光阻(I)207包含開口部208，該開口部208用以形成銜接包含在種子層之電極202上設置處與形成後述之凸塊電極處的區域為止之再配線。
(步驟B3)
步驟B3係於該開口部208設置配線以進行再配線之再配線形 成步驟。藉由此再配線形成步驟，進行在包含電極202之半導體基板201之該電極202上形成配線之再配線之形成。配線使用銅或鎳等材料，如圖B(f)所示，宜包含至少以銅形成之銅層209。且配線通常係藉由對銅或鎳進行電解電鍍處理而設置。
(步驟B4)
步驟B4如圖B(g)及(h)所示，係形成光阻(II)210俾被覆種子層及配線，且藉由曝光、顯影於光阻(II)210形成用以形成凸塊電極之開口部211之光阻(II)形成步驟。此光阻(II)210藉由一般方法設置即可。又，亦可預先去除光阻(I)，再形成光阻(II)210。
(步驟B5)
步驟B5如圖B(i)及(j)所示，係於該光阻(II)210形成凸塊電極處設置開口部211，俾再配線之銅層209露出，於該開口部211形成至少具有一層鎳所構成之鎳層212之凸塊電極之凸塊電極形成步驟。
凸塊電極除形成上述焊料層110之焊接材料外，可使用金、鈀、鎳、銅等，藉由電解電鍍形成之，可以一層或複數層方式形成之。例如圖B(j)，可在設置鎳層212後，設置焊接材料所構成之焊料層213以形成凸塊電極。本發明之製造方法中，形成凸塊電極之層若係鎳層212及焊料層213之組合，即可有效活用本發明之蝕刻液具有之可選擇性地不蝕刻鎳而蝕刻銅之性能，及該電極不氧化，性能不降低之性能。
(步驟B6)
步驟B6如圖B(k)，係使用光阻剝離液去除光阻(I)207及光阻(II)210，再如圖B(l)及(m)所示，更蝕刻鈦層205或銅層206等種子層中，未由如銅層209之配線包覆之露出部分之蝕刻步驟。該蝕刻步驟中，需使用本發明之蝕刻液。藉由使用本發明之蝕刻液，可選擇性地不蝕刻鎳而蝕刻銅。且如本製造方法，在以焊料形成凸塊電極，特別是焊料包含錫時，藉由使用本發明之蝕刻液，亦可獲得該電極不氧化，性能不降低之效果。步驟B6中蝕刻諸條件與步驟A5相同。
如圖B(l)所示，於步驟B6之蝕刻步驟蝕刻銅層206時，鎳層212會暴露於蝕刻液。在如此時，若使用本發明之蝕刻液，即不會如圖B(p)所示鎳層212受到蝕刻而形成凹陷部216，可選擇性地僅蝕刻銅層206。
本發明之製造方法B中，如圖B(n)所示，可更在形成凸塊電極區域以外的部分形成絕緣膜214。該絕緣膜214之形成宜使用環氧樹脂或聚醯亞胺樹脂等絕緣性有機材料等。
且如圖B(o)所示，亦可藉由使於該步驟B5形成之焊料層213熔融，形成凸面狀焊料層215。焊料層213之熔融加熱基板以藉由回流處理進行即可。
藉由本發明製造方法中製造方法B，可獲得經在包含電極之半導體基板該電極上形成配線之再配線，包含凸塊電極之半導體裝置。依此等製造方法，可使用電極間距在150μm以下，或在100μm以下，甚至在50μm以下間距狹窄之半導體基板。且可獲得凸塊電極間距在500μm以下，或在250μm以下，甚至在200μm以下間距狹窄之半導體裝置。因此，藉由本發明之製造方法獲得之半導體裝置可充分對應近年來的小型化或高密度化及多功能化。
實施例
其次雖藉由實施例更詳細地說明本發明，但本發明不因此等例而受到任何限定。
《處理液之調製》
根據表1所示之摻合組成(質量%)，調整於各實施例及比較例使用之蝕刻液。
《評價方法》 評價項目.電鍍外觀(變色)評價
就實施例1~38及比較例1~20，藉由目視以以下基準評價因蝕刻液於處理前後錫-鉛焊料電鍍及錫電鍍外觀(變色)之狀態。
○：變色完全無法確認
△：變色些許存在，但實用上沒問題
×：變色明顯，無法使用
實施例1~38及比較例1~20
將濺鍍銅(銅膜厚度：5000)、錫-鉛焊料電鍍(其含有比例為錫：鉛=6:4)、錫電鍍經成膜之基板在2分鐘期間內浸漬於30℃之表1所示之各實施例及比較例之蝕刻液。
於浸漬後之基板中，就濺鍍銅使用螢光X線分析裝置(「SEA2110L)」，精工盈司電子科技有限公司製)測定其浸漬前後之膜厚變化，計算銅的蝕刻速率(μm/分鐘)。就錫-鉛焊料及錫電鍍，以目視觀察其浸漬前後之外觀，特別是變色狀況，根據上述評價基準評價之。
且將藉由電解電鍍方式使鎳成膜於鋼材(鎳膜厚度：5μm)之基板浸漬於30℃之各實施例及比較例之蝕刻液1小時，測定其浸漬前後之重量，計算蝕刻速率(/分)。顯示此等計算值及評價結果於表1。
【表1】
《評價方法》 評價項目.使用半導體基板之蝕刻評價
使用實施例39~44及比較例21~27之蝕刻液，依A之順序製造半導體裝置。就獲得之半導體裝置，分別以下記基準評價藉由電解電鍍方式設置之鎳層凹陷部、作為種子層設置之銅層蝕刻後殘存狀態，及凸塊電極之變色狀態。
<關於鎳層凹陷部之狀態>
○：鎳層凹陷部完全無法確認
△：鎳層凹陷部些許存在，但實用上沒問題
×：鎳層凹陷部明顯，無法使用
<銅層殘存狀態>
○：蝕刻後，銅層之殘存完全無法確認
△：蝕刻後，銅層之殘存可稍微被確認，但實用上沒問題
×：蝕刻後，銅層之殘存明顯，無法使用
<關於凸塊電極之變色狀態>
○：變色完全無法確認
△：變色些許存在，但實用上沒問題
×：變色明顯，無法使用
實施例39~44及比較例21~27(依製造方法A之半導體裝置之製造)
根據製造方法A(圖A(a)~(k))之順序，製作包含電極及凸塊電極之半導體裝置。在此，為形成焊料層110，使用錫-鉛焊料(含有比例為錫：鉛=6：4)，依圖A(i)~(j)所示之蝕刻步驟，依序使用表2所示之各實施例及比較例之蝕刻液，蝕刻銅層106及鈦層105。此時，蝕刻溫度為30℃，蝕刻時間為表2所示之時間。
就以各實施例及比較例獲得之半導體裝置，將根據上述評價基準評價之結果顯示於表2。
實施例45及比較例28
除不依實施例39及比較例21焊料層110使用錫-鉛焊料(含有比例為錫：鉛=6：4)而代之以錫-銀焊料(銀含量：3質量%)以外，與實施例39及比較例21相同，分別製作實施例45及比較例28之半 導體裝置。
就依各實施例及比較例獲得之半導體裝置，將根據上述評價項目評價之結果顯示於表2。
實施例46~51及比較例29~35(依製造方法B半導體裝置之製造)
根據製造方法B(圖B(a)~(k))之順序，製作包含電極及凸塊電極之半導體裝置。在此，為形成焊料層110使用錫-鉛焊料(含有比例為錫：鉛=6：4)，依圖B(l)~(m)所示之蝕刻步驟，使用表3所示之各實施例及比較例之蝕刻液，依序蝕刻銅層206及鈦層205。此時，蝕刻溫度為30℃，蝕刻時間為表3所示之時間。
就依各實施例及比較例所獲得之半導體裝置，將根據上述評價基準評價之結果顯示於表3。
實施例52及比較例36
除不依實施例46及比較例29焊料層110使用錫-鉛焊料(含有比例為錫：鉛=6:4)而代之以錫-銀焊料(銀含量：3質量%)以外，與實施例46及比較例36相同，分別製作實施例52及比較例36之半導體裝置。
就依各實施例及比較例獲得之半導體裝置，將根據上述評價項目評價之結果顯示於表3。
【表3】
依實施例1~38之結果確認本發明之蝕刻液雖對濺鍍銅具有0.1μm/分鐘以上之高蝕刻速度，但可抑制對電解鎳電鍍之蝕刻速度至甚低，未滿50/分鐘。且關於錫-鉛焊料電鍍及錫電鍍，有機膦酸含量少至未滿0.01質量%時雖可發現些許變色，但實用上沒問題，且於其他實施例，完全未發現變色。
另一方面，過氧化氫含量少至0.5質量%之比較例2及5、枸櫞酸含量少至0.5質量%之比較例3、蘋果酸含量少至0.5質量%之比較例6中，濺鍍銅蝕刻速度低至未滿0.1μm/分鐘。且未包含枸櫞酸或蘋果酸而代之以其他有機酸之比較例9、11及18中，濺鍍銅蝕刻速度低至未滿0.1μm/分鐘。
於未包含有機膦酸之比較例1及4中，在錫-鉛焊料電鍍及錫電鍍上皆發現變色。且即使蝕刻液含有有機膦酸0.05質量%，於作為有機酸不包含枸櫞酸、蘋果酸之比較例7~10及12中，在錫-鉛焊料電鍍或是錫電鍍上亦發現變色。
包含過氧化氫5質量%，作為有機酸未包含枸櫞酸及蘋果酸之比較例8、13及17中，電解鎳電鍍之蝕刻速度在1500/分鐘以上，無法選擇性地蝕刻銅。
包含過氧化氫5質量%，作為有機酸包含酒石酸、戊二酸、伊康酸之各比較例15、19、20中，可獲得與實施例1~38同等之蝕刻性能。然而，使用於此等比較例使用之蝕刻液製作半導體裝置之各比較例25~27中，經確認蝕刻後銅層之殘存明顯，無法使用於半導體裝置之製作。
<產業上利用性>
本發明之蝕刻液用於使用包含電極之半導體基板之半導體裝置製造步驟。在該半導體裝置製造步驟所包含之蝕刻步驟中，蝕刻銅所構成之層之際鎳所構成之層暴露於蝕刻液之情形下，不欲蝕刻該鎳所構成之層時，本發明之蝕刻液特別有效。
101、201‧‧‧矽基板(半導體基板)
102、202‧‧‧電極
103、203、214‧‧‧絕緣膜
104、204‧‧‧開口部
105、205‧‧‧鈦層
106、206、209‧‧‧銅層
107‧‧‧光阻
108、208、211‧‧‧開口部
109‧‧‧鎳層
110、210、213‧‧‧焊料層
111‧‧‧凸塊電極
111‧‧‧焊料層
112、212‧‧‧鎳層
112、216‧‧‧凹陷部
207‧‧‧光阻(I)
210‧‧‧光阻(II)
215‧‧‧凸面狀焊料層
圖1係用以說明包含本發明之凸塊電極之半導體裝置製造方法A，該半導體裝置每一步驟之剖面示意圖(圖A(a)~(g))。
圖2係用以說明包含本發明之凸塊電極之半導體裝置製造方法A，該半導體裝置每一步驟之剖面示意圖(圖A(h)~(l))。
圖3係用以說明包含本發明之凸塊電極之半導體裝置製造方法B，該半導體裝置每一步驟之剖面示意圖(圖B(a)~(h))。
圖4係用以說明包含本發明之凸塊電極之半導體裝置製造方法B，該半導體裝置每一步驟之剖面示意圖(圖B(i)~(p))。
101．．．矽基板(半導體基板)
102．．．電極
103．．．絕緣膜
104．．．開口部
105．．．鈦層
106．．．銅層
107．．．光阻
108．．．開口部
109．．．鎳層
110．．．焊料層

Claims (10)

  1. 一種蝕刻液，可選擇性地不蝕刻鎳而蝕刻銅，用於製造採用具有電極之半導體基板的半導體裝置，該蝕刻液包含過氧化氫、有機酸與有機膦酸，有機酸係選自於枸櫞酸及蘋果酸中至少一種酸，該過氧化氫含量為0.75~10質量%，該有機酸含量為0.75~25質量%，且該有機膦酸含量為0.0005~1質量%。
  2. 如申請專利範圍第1項之蝕刻液，其中，該過氧化氫含量為1.5~10質量%，該有機酸含量為1.5~20質量%，該有機膦酸含量為0.001~0.25質量%。
  3. 如申請專利範圍第1項之蝕刻液，其中，該過氧化氫含量為1.5~5質量%，該有機酸含量為1.5~10質量%，該有機膦酸含量為0.01~0.15質量%。
  4. 如申請專利範圍第1至3項中任一項之蝕刻液，其中，該有機膦酸係選自於二乙烯三胺五亞甲基膦酸、丙二胺四亞甲基膦酸及1-羥基亞乙基-1,1-二膦酸中至少一種酸。
  5. 如申請專利範圍第1至3項中任一項之蝕刻液，其中，該半導體裝置包含藉由焊料形成之凸塊電極。
  6. 如申請專利範圍第1至3項中任一項之蝕刻液，其中，該半導體裝置包含使用銅形成之配線。
  7. 一種半導體裝置之製造方法，可選擇性地不蝕刻鎳而蝕刻銅，包含使用如申請專利範圍第1至6項中任一項之蝕刻液的蝕刻步驟。
  8. 如申請專利範圍第7項之半導體裝置之製造方法，其中，該半導體裝置包含藉由焊料形成之凸塊電極。
  9. 如申請專利範圍第7或8項之半導體裝置之製造方法，其中，包含在具有電極之半導體基板的該電極上形成配線之再配線形成步驟。
  10. 如申請專利範圍第7或8項之半導體裝置之製造方法，其中，該半導體裝置包含使用銅形成之配線。
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US8853701B2 (en) * 2010-04-28 2014-10-07 Sharp Kabushiki Kaisha Semiconductor device, display device, and production method for semiconductor device and display device
JP6101421B2 (ja) * 2010-08-16 2017-03-22 インテグリス・インコーポレーテッド 銅または銅合金用エッチング液
JP5658582B2 (ja) * 2011-01-31 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP5933950B2 (ja) * 2011-09-30 2016-06-15 アドバンスド テクノロジー マテリアルズ，インコーポレイテッド 銅または銅合金用エッチング液
US9012263B1 (en) * 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US10026564B2 (en) * 2014-09-15 2018-07-17 Nantong Memtech Technology Co., Ltd. Precious metal switch contact component and its preparation method
JP6531612B2 (ja) * 2014-11-27 2019-06-19 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
JP6657770B2 (ja) * 2014-11-27 2020-03-04 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
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WO2017188108A1 (ja) * 2016-04-27 2017-11-02 三洋化成工業株式会社 エッチング液及び電子基板の製造方法
JP6285983B2 (ja) * 2016-05-06 2018-02-28 インテグリス・インコーポレーテッド 銅または銅合金用エッチング液
JP6941296B2 (ja) * 2017-09-20 2021-09-29 大日本印刷株式会社 リードフレームおよび半導体装置
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JP2003328159A (ja) * 2002-05-02 2003-11-19 Mitsubishi Gas Chem Co Inc 表面処理剤
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JP4129218B2 (ja) 2003-09-30 2008-08-06 メルテックス株式会社 ウエハ上の銅エッチング液
JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
KR101199533B1 (ko) * 2005-06-22 2012-11-09 삼성디스플레이 주식회사 식각액, 이를 이용하는 배선 형성 방법 및 박막 트랜지스터기판의 제조 방법
DE102005038414A1 (de) 2005-08-12 2007-02-15 Basf Aktiengesellschaft Stabilisierte Ätzlösungen zum Ätzen von Cu- und Cu/Ni-Schicht
US7976723B2 (en) * 2007-05-17 2011-07-12 International Business Machines Corporation Method for kinetically controlled etching of copper
WO2009071351A1 (en) 2007-12-06 2009-06-11 Basf Se A method for chemically-mechanically polishing patterned surfaces composed of metallic and nonmetallic patterned regions
EP2540870A1 (en) * 2007-12-21 2013-01-02 Wako Pure Chemical Industries, Ltd. Etching agent, etching method and liquid for preparing etching agent

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