CN102696097B - 蚀刻液及使用其的半导体装置的制造方法 - Google Patents

蚀刻液及使用其的半导体装置的制造方法 Download PDF

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CN102696097B
CN102696097B CN201080059307.9A CN201080059307A CN102696097B CN 102696097 B CN102696097 B CN 102696097B CN 201080059307 A CN201080059307 A CN 201080059307A CN 102696097 B CN102696097 B CN 102696097B
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semiconductor device
etching solution
acid
copper
quality
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CN102696097A (zh
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细见彰良
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Mitsubishi Gas Chemical Co Inc
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Mitsubishi Gas Chemical Co Inc
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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Abstract

本发明提供在使用了具有电极的半导体基板的半导体装置的制造中使用的、能选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。含有过氧化氢和有机酸和有机膦酸、有机酸为选自柠檬酸及苹果酸中的至少一种、且过氧化氢的含量为0.75~12质量%，有机酸的含量为0.75~25质量%、有机膦酸的含量为0.0005~1质量%的在使用了具有电极的半导体基板的半导体装置的制造中使用的蚀刻液、及使用了这些蚀刻液的半导体装置的制造方法。

Description

蚀刻液及使用其的半导体装置的制造方法
技术领域
本发明涉及在使用了具有电极的半导体基板的半导体装置的制造中使用的、能够选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。
背景技术
近年来，伴随电子设备的小型化的要求，这种设备中使用的半导体装置的小型化、高集成化及多功能化也在加快，连接半导体装置和电子设备的电极有增加的倾向。作为这里使用的半导体装置，多使用在由铝等形成的半导体焊盘上再布线、设置凸块电极的半导体装置。为了同时应对如上所述的半导体装置的小型化及电极数的增加，提出了各种各样的凸块电极的形成方法（例如专利文献1及2）。
这些凸块电极的形成方法中包括设置在半导体焊盘（以下也简称为电极。）上的布线的蚀刻工序，有时必须在不蚀刻布线中使用的镍的条件下蚀刻铜。
更具体而言，专利文献1中公开的凸块电极的形成方法具有如下的蚀刻工序：在设置有由导电性材料构成的电极的基板上设置露出该电极部分的覆膜，进而依次设置通过溅射铜等而形成的基底导电膜、具有从该电极处延伸至形成对应的凸块电极处的开口部的光致抗蚀膜，并且在该开口部通过电镀依次设置铜布线以及镍布线，之后，去除光致抗蚀膜，蚀刻该基底导电膜中未被布线覆盖的部分。该蚀刻工序中，在蚀刻用于形成基底导电膜的铜时，为了确保更高的性能，理想的是不蚀刻通过电镀形成的镍布线。
另外，专利文献2中公开的凸块电极的形成方法具有如下的蚀刻工序：在设置有铝电极的半导体基板上，由钛、铜通过溅射形成晶种层，形成用于形成凸块电极的部分开口的抗蚀层，在该开口处，通过电镀等形成层叠钛、铜、镍等多种金属而成的势垒金属层，进而在其上通过电镀形成成为凸块电极的焊料，之后，去除该抗蚀层，然后蚀刻该晶种层。在该蚀刻工序中，蚀刻用于形成晶种层的钛、铜时，为了确保更高的性能，理想的是，通过不蚀刻用于形成势垒金属层的镍等金属并且防止由焊料形成的凸块电极因蚀刻液导致的氧化，抑制该电极的性能降低。
但是，在专利文献1、专利文献2的蚀刻工序中，没有对该工序中使用的蚀刻液进行充分的研究，可以充分预料到：在蚀刻由铜形成的布线等部件时由镍形成的部件也被蚀刻，或者凸块电极被氧化从而其性能降低。如上所述，伴随半导体装置的小型化、高集成化及多功能化，使用半导体装置的顾客所要求的性能变严格，这时，利用到目前为止的半导体装置的制造方法制造的半导体装置产生不能充分满足该要求性能的情况的倾向变明显。
现有技术文献
专利文献
专利文献1：日本特开平11-195665号公报
专利文献2：日本特开2005-175128号公报
发明内容
发明要解决的问题
本发明是在这样的情况下进行的发明，其目的在于，提供在使用了具有电极的半导体基板的半导体装置的制造中使用的、能选择性蚀刻铜而不蚀刻镍且能防止凸块电极的性能降低的蚀刻液及使用其的半导体装置的制造方法。
用于解决问题的方案
本发明人等为了达成上述目的进行了深入研究，结果发现，通过使用以特定的组成含有过氧化氢和有机酸和有机膦酸、并且使该有机酸为选自特定的羟基酸的柠檬酸及苹果酸中的至少一种的蚀刻液，可以解决该问题。即，本发明提供以下的在使用了具有电极的半导体基板的半导体装置的制造中使用的、能选择性蚀刻铜而不蚀刻镍且能防止凸块电极的性能降低的蚀刻液及使用其的半导体装置的制造方法。
[1]一种在使用了具有电极的半导体基板的半导体装置的制造中使用的蚀刻液，其含有过氧化氢、有机酸和有机膦酸，有机酸为选自柠檬酸及苹果酸中的至少一种，过氧化氢的含量为0.75~12质量%，有机酸的含量为0.75~25质量%，且有机膦酸的含量为0.0005~1质量%。
[2]根据上述1所述的蚀刻液，其中，过氧化氢的含量为1.5~12质量%，有机酸的含量为1.5~20质量%，有机膦酸的含量为0.001~0.25质量%。
[3]根据上述1所述的蚀刻液，其中，过氧化氢的含量为1.5~5质量%，有机酸的含量为1.5~10质量%，有机膦酸的含量为0.01~0.15质量%。
[4]根据上述1~3中任一项所述的蚀刻液，其中，有机膦酸为选自二亚乙基三胺五（亚甲基膦酸）、丙二胺四（亚甲基膦酸）及1-羟基乙叉基-1,1-二膦酸中的至少一种。
[5]根据上述1~4中任一项所述的蚀刻液，其中，半导体装置具有由焊料形成的凸块电极。
[6]根据上述1~5中任一项所述的蚀刻液，其中，半导体装置具有使用铜形成的布线。
[7]一种半导体装置的制造方法，其具有使用上述1~6中任一项所述的蚀刻液的蚀刻工序。
[8]根据上述7所述的半导体装置的制造方法，其中，半导体装置具有由焊料形成的凸块电极。
[9]根据上述7或8所述的半导体装置的制造方法，其具备在具有电极的半导体基板的该电极上形成布线的再布线形成工序。
[10]根据上述7~9中任一项所述的半导体装置的制造方法，其中，半导体装置具有使用铜形成的布线。
发明的效果
根据本发明，能够提供在使用了具有电极的半导体基板的半导体装置的制造工序中使用的、能选择性蚀刻铜而不蚀刻镍且能防止凸块电极的性能降低的蚀刻液及使用其的半导体装置的制造方法。
附图说明
图1是用于说明本发明的具有凸块电极的半导体装置的制造方法A的该半导体装置的每个工序的剖面示意图（图A（a）~（g））。
图2是用于说明本发明的具有凸块电极的半导体装置的制造方法A的该半导体装置的每个工序的剖面示意图（图A（h）~（l））。
图3是用于说明本发明的具有凸块电极的半导体装置的制造方法B的该半导体装置的每个工序的剖面示意图（图B（a）~（h））。
图4是用于说明本发明的具有凸块电极的半导体装置的制造方法B的该半导体装置的每个工序的剖面示意图（图B（i）~（p））。
附图标记说明
101、201：硅基板
102、202：电极
103、203：绝缘膜
104、204：开口部
105、205：钛层
106、206：铜层
107：光致抗蚀层
108、208：开口部
109：镍层
110、213：焊料层
111：凸块电极
112：凹部
114、214：绝缘膜
116：铜层的残渣
207：光致抗蚀层（I）
209：镍层
210：光致抗蚀层（II）
211：开口部
212：镍层
215：凸面状焊料层
216：凹部
具体实施方式
[蚀刻液]
本发明的蚀刻液为如下的液体：在使用了具有电极的半导体基板的半导体装置的制造工序中的蚀刻工序中使用的、以特定的含量含有过氧化氢和有机酸和有机膦酸、且该有机酸为选自特定的羟基酸的柠檬酸及苹果酸中的至少一种。
作为有机膦酸，可以优选列举出：二亚乙基三胺五（亚甲基膦酸）、3,3′-二氨基二丙基胺五（亚甲基膦酸）、亚乙基二胺四（亚甲基膦酸）、丙二胺四（亚甲基膦酸）、双（六亚甲基）三胺五（亚甲基膦酸）、三亚乙基四胺六（亚甲基膦酸）、三（2-氨乙基）胺六（亚甲基膦酸）、三（3-氨丙基）胺六（亚甲基膦酸）、四亚乙基五胺七（亚甲基膦酸）、五亚乙基六胺八（亚甲基膦酸）、六亚甲基四胺八（亚甲基膦酸）、氨甲基膦酸、及羟基乙叉基二膦酸等。这些化合物所具有的膦酰甲基的一部分可以被氢原子、甲基等其它基团置换。另外，这些膦酸系化合物的膦酸基不光可以使用游离的酸，例如铵盐这样的盐也可以同样地使用。
其中，更优选二亚乙基三胺五（亚甲基膦酸）、丙二胺四（亚甲基膦酸）及1-羟基乙叉基-1,1-二膦酸，优选为选自它们中的至少一种。
本发明的蚀刻液中，过氧化氢的含量需要为0.75~12质量%。过氧化氢的含量不足0.75质量%时，不能得到适当的蚀刻速度，大于12质量%时，过氧化氢的管理变困难，过氧化氢的浓度不稳定。另外，从过氧化氢的管理容易、过氧化氢的浓度稳定、并且得到适当的蚀刻速度和良好的蚀刻性能的观点考虑，过氧化氢的含量优选为1.5~12质量%，更优选为1.5~5质量%。
为选自特定的羟基酸的柠檬酸及苹果酸中的至少一种的有机酸的含量需要为0.75~25质量%。有机酸的含量不足0.75质量%或大于25质量%时，不能得到适当的蚀刻速度和蚀刻性能。另外，从得到适当的蚀刻速度和蚀刻性能的观点考虑，有机酸的含量优选为1.5~20质量%，更优选为1.5~10质量%。有机酸的含量在上述范围内时，能够得到适当的蚀刻速度和良好的蚀刻性能。这里，有机酸组合使用柠檬酸和苹果酸时，柠檬酸和苹果酸的含量的总量为有机酸的含量。
另外，有机膦酸的含量需要为0.0005~1质量%。有机膦酸的含量不足0.0005质量%时，不能防止凸块电极因蚀刻液导致的氧化，不能抑制该电极的性能降低，大于1质量%时，Ni会被蚀刻。另外，从抑制凸块电极的氧化、抑制电极性能的降低的观点考虑，有机膦酸的含量优选为0.001~0.25质量%，更优选为0.01~0.15质量%。有机膦酸的含量在上述范围内时，其抑制效果在凸块电极由焊料形成的情况下特别显著。
本发明的蚀刻液中，作为过氧化氢、有机酸、及有机膦酸以外的成分，优选含有水。作为水，优选通过蒸馏、离子交换处理、过滤处理、各种吸附处理等去除了金属离子、有机杂质、颗粒等的水，特别优选纯水、超纯水。
本发明的蚀刻液的特征在于，选择性蚀刻铜而不蚀刻镍。因此，本发明的蚀刻液适宜用于半导体装置的制造工序中的蚀刻工序，特别是使用镍和铜且需要选择性蚀刻铜而不蚀刻镍的半导体装置的制造工序中的蚀刻工序。
另外，本发明的蚀刻液的特征还在于，通过防止凸块电极的氧化，抑制该电极的性能降低，该效果在该电极由焊料形成的情况下较显著。因此，本发明的蚀刻液优选用于具有凸块电极的半导体装置的制造工序中的蚀刻工序，特别优选用于该凸块电极由焊料形成的半导体的制造工序中的蚀刻工序。
[半导体装置的制造方法]
优选的是，本发明的半导体装置的制造方法具有使用本发明的蚀刻液的蚀刻工序，该半导体装置具有凸块电极。另外，该蚀刻工序从有效发挥能选择性蚀刻铜而不蚀刻镍的本发明的蚀刻液的特征的观点来看，优选其特征在于，为由镍形成的部件和由铜形成的部件能同时接触蚀刻液的状态，且蚀刻该由铜形成的部件。以下更具体地说明本发明的制造方法。
《半导体装置的制造方法A》
本发明的半导体装置的制造方法的第一实施方式（以下称为制造方法A。）依次具有：晶种层形成工序A1、光致抗蚀层形成工序A2、势垒金属形成工序A3、焊料层形成工序A4、使用本发明的蚀刻液的蚀刻工序A5、及凸块电极形成工序A6。使用图A（a）~（l）详细地说明本发明的制造方法A。
（工序A1）
工序A1是在设置有电极的半导体基板上设置具有该电极露出的开口部的绝缘膜、进而在该开口部及该绝缘膜上形成晶种层的晶种层形成工序。这里，设置有电极的半导体基板如图A（a）所示，例如在硅基板101的表面形成通过周知的制造方法制造的包含半导体元件的电路，在形成有该电路的面形成被称为焊盘的例如由铝等导电性材料形成的电极102。作为导电性材料，除铝以外，还可以优选列举出添加有钛、铜的铝合金、铜或铜合金、金等。
在该设置有电极102的半导体基板101上（形成有该电极的面）形成由氧化硅等形成的绝缘膜103，在该绝缘膜103上形成与电极102对应的开口部104使得电极102露出。
然后，如图A（b）及（c）所示，在开口部104及绝缘膜103上，通过通常的溅射形成晶种层。作为用于形成晶种层的金属，可优选列举出钛、铜等，可以如图A（b）及（c）所示地设置多层由这些金属形成的层、钛层105、铜层106等层。另外，从与电极102的密合性、半导体装置的制作管理的观点考虑，优选在基板上设置钛层105。
（工序A2）
工序A2是光致抗蚀层形成工序，其使前述晶种层的包含设置在电极上的部位及用于形成凸块电极的部位的区域开口，形成具有该晶种层露出的开口部108的光致抗蚀层107。首先，如图A（d）所示，在铜层106上形成光致抗蚀层107。然后，通过使该光致抗蚀层曝光、显影，如图A（e）所示，形成具有用于形成后述的凸块电极的开口部108的光致抗蚀层107。
（工序A3）
工序A3是在前述开口部108内设置势垒金属层的势垒金属形成工序。通常，在工序A3中，如图A（f）所示，利用电镀处理等方法设置镍层109，将该镍层109、在工序A1中设置的钛层105及铜层106一同称为势垒金属层。该势垒金属层是为了防止电极102与后述的凸块电极111之间的扩散等而设置的层，优选在与该凸块电极111相接的面设置由镍或者镍合金形成的镍层109。
（工序A4）
工序A4是如图A（f）所示在镍层109上设置焊料层110的工序。焊料层110通常通过以钛层105及铜层106为晶种层的电镀处理来形成，在这个阶段，通常从开口部108露出光致抗蚀层107的表面，具有蘑菇型的形状。作为形成该焊料层110的材质，除锡、铅、它们的合金（锡-铅合金）以外，还可以优选列举出：锡-银系合金、锡-银-铜系合金、锡-铜系合金、锡-锌系合金、锡-铋系合金、锡-锌-铋系合金等焊料材料。
（工序A5）
工序A5是蚀刻工序，其中，如图A（h）所示将光致抗蚀层去除之后，进而如图A（i）及（j）所示，使用本发明的蚀刻液蚀刻钛层105及铜层106等晶种层中未被镍层109或者焊料层110覆盖的露出部分。通过使用本发明的蚀刻液，可以选择性蚀刻铜而不蚀刻镍。另外，如本制造方法所示，利用焊料形成凸块电极、特别是焊料包含锡时，通过使用本发明的蚀刻液，还能够得到该电极不会氧化、性能不会降低这样的效果。
使蚀刻液与蚀刻对象物接触的方法没有特别限定，例如可以采用：通过滴下、喷射等形式使蚀刻液与对象物接触的方法；使对象物浸渍在蚀刻液中的方法等。本发明中，优选采用向对象物喷射蚀刻液使它们接触的方法。
作为蚀刻液的使用温度，优选为50℃以下的温度，更优选为20~50℃，进一步优选为20~40℃，特别优选为25~35℃。蚀刻液的温度为50℃以上时，蚀刻速度增大，但液体的稳定性变差，难以使蚀刻条件保持一定。通过使蚀刻液的温度为50℃以下，可以使蚀刻液的组成变化较小，得到稳定的蚀刻速度。另外，为20℃以上时，蚀刻速度不会变得过慢，生产效率不会显著降低。
如图A（i）所示，在本蚀刻工序中蚀刻铜层106时，镍层112的侧面暴露在蚀刻液中。这种情况下，如果使用本发明的蚀刻液，则不会出现图A（l）所示的镍层109被蚀刻而形成凹部112的情况，能够选择性蚀刻仅铜层106。
（工序A6）
工序A6是通过使焊料层110熔融而得到凸块电极111的凸块电极形成工序。焊料层110的熔融通过利用加热基板的回流焊处理来进行即可，通过该回流焊处理，蘑菇型的焊料层111如图A（k）所示成为呈球状的凸块电极111。
由此，可以由具有电极的半导体基板制造具有凸块电极的半导体装置。
《半导体装置的制造方法B》
本发明的半导体装置的制造方法的第二实施方式（以下称为制造方法B。）依次具有：晶种层形成工序B1、光致抗蚀层（I）形成工序B2、再布线形成工序B3、光致抗蚀层（II）形成工序B4、凸块电极形成工序B5、使用本发明的蚀刻液的蚀刻工序B6。使用图B（a）~（p）详细说明本发明的制造方法B。
（工序B1）
工序B1是晶种层形成工序，其在设置有电极的半导体基板上设置具有该电极露出的开口部的绝缘膜，进而在该开口部及该绝缘膜上形成晶种层，与上述工序A1相同。
通过本工序，如图B（a）~（c）所示，在设置有电极202的半导体基板201上（形成有该电极的面）形成具有对应电极202的开口部204的绝缘膜203，使得电极202露出，在该开口部204及绝缘膜203上形成作为晶种层的钛层205及铜层206。
（工序B2）
工序B2是光致抗蚀层（I）形成工序，其使前述晶种层的包含设置在电极上的部位及用于形成凸块电极的部位的区域开口，形成具有该晶种层露出的开口部208的光致抗蚀层（I）207。首先，如图A（d）所示，在铜层206上形成光致抗蚀层（I）207。然后，通过使该光致抗蚀层曝光、显影，如图A（e）所示，形成具有开口部208的光致抗蚀层（I）207，所述开口部208用于形成将晶种层的包含设置在电极202上的部位和后述的用于凸块电极的部位的区域连接的再布线。
（工序B3）
工序B3是在前述开口部208设置布线进行再布线的再布线形成工序。通过该再布线形成工序，进行在具有电极202的半导体基板201的该电极202上形成布线的再布线形成。布线使用铜、镍等材料，优选如图B（f）所示，至少具有由铜形成的铜层209。另外，布线通常通过电镀处理铜、镍来设置。
（工序B4）
工序B4是光致抗蚀层（II）形成工序，其中，如图B（g）及（h）所示，以被覆晶种层及布线的方式形成光致抗蚀层（II）210，进而进行曝光、显影，由此在光致抗蚀层（II）210上形成用于形成凸块电极的开口部211。该光致抗蚀层（II）210利用常规方法设置即可。需要说明的是，也可以在预先去除光致抗蚀层（I）之后，形成光致抗蚀层（II）210。
（工序B5）
工序B5是凸块电极形成工序，其中，如图B（i）及（j）所示，在前述光致抗蚀层（II）210的形成凸块电极的部位，以再布线的铜层209露出的方式设置开口部211，在该开口部211形成具有至少一层由镍形成的镍层212的凸块电极。
凸块电极除形成上述焊料层110的焊料材料以外，可以使用金、钯、镍、铜等通过电镀来形成，可以由一层或多层形成。例如，可以如图A（j）所示，在设置镍层212之后，设置由焊料材料形成的焊料层213，形成凸块电极。本发明的制造方法中，形成凸块电极的层为镍层212及焊料层213的组合时，可以有效地发挥本发明的蚀刻液所具有的能选择性蚀刻铜而不蚀刻镍的性能、及不会使该电极氧化、性能不会降低这样的性能。
（工序B6）
工序B6是蚀刻工序，其中，如图B（k）所示使用抗蚀层剥离液将光致抗蚀层（I）207及光致抗蚀层（II）210去除之后，进而如图B（l）及（m）所示蚀刻钛层205、铜层206等晶种层中未被铜层209这样的布线覆盖的露出部分。该蚀刻工序中，需要使用本发明的蚀刻液。通过使用本发明的蚀刻液，能选择性蚀刻铜而不蚀刻镍。另外，如本制造方法所示，利用焊料形成凸块电极、特别是焊料包含锡时，通过使用本发明的蚀刻液，还能获得该电极不会氧化、性能不会降低的效果。工序B6中的蚀刻的各条件与工序A5相同。
如图B（l）所示，在工序B 6的蚀刻工序中蚀刻铜层206时，镍层212暴露于蚀刻液中。这种情况下，如果使用本发明的蚀刻液，则不会出现图B（p）所示的镍层212被蚀刻而形成凹部216的情况，能选择性地蚀刻仅铜层206。
本发明的制造方法B中，可以如图B（n）所示，进而在形成有凸块电极的区域以外的部分形成绝缘膜214。该绝缘膜214的形成优选使用环氧树脂、聚酰亚胺树脂等绝缘性有机材料等。
进而，也可以如图B（o）所示，通过使在前述工序B 5中形成的焊料层213熔融，形成凸面状焊料层215。焊料层213的熔融通过利用加热基板的回流焊处理进行即可。
本发明的制造方法中，利用制造方法B，能够得到进行了在具有电极的半导体基板的该电极上形成布线的再布线的具有凸块电极的半导体装置。根据这些制造方法，能够使用电极间距为150μm以下、100μm以下、进而50μm以下的窄间距的半导体基板。另外，能够得到凸块电极的间距为500μm以下、250μm以下、进而200μm以下的窄间距的半导体装置。因此，利用本发明的制造方法得到的半导体装置能够充分对应近年来的小型化、高集成化及多功能化。
实施例
以下，通过实施例更详细地说明本发明，但本发明并不受这些例子的任何限定。
《处理液的制备》
按照表1所示的配合组成（质量%），制备各实施例及比较例中使用的蚀刻液。
《评价方法》
评价项目：镀敷的外观（变色）的评价
对实施例1~38及比较例1~20，通过目视，按照以下的基准评价利用蚀刻液处理前后的镀锡-铅焊料及镀锡的外观（变色）的状态。
○：完全没有出现变色
△：出现少许变色，但实用上没有问题
×：变色显著，无法使用
实施例1~38及比较例1~20
将溅射铜（铜膜的厚度：）、镀锡-铅焊料（其含有比为锡：铅＝6：4）、镀锡成膜了的基板在表1所示的各实施例及比较例的蚀刻液中，在30℃下浸渍2分钟。
在浸渍后的基板中，对于溅射铜，使用荧光X射线分析装置（“SEA2110L）”，エスエスアイナノテクノロジー社制造）测定浸渍前后的膜厚变化，计算铜的蚀刻速率（μm/分钟）。对于锡-铅焊料、及镀锡，通过目视观察浸渍前后的外观、尤其是变色情况，按照上述评价基准进行评价。
另外，将在钢材上通过电镀形成有镍膜（镍膜的厚度：5μm）的基板在各实施例及比较例的蚀刻液中，在30℃下浸渍1小时，测定浸渍前后的重量，计算蚀刻速率（/分钟）。将这些计算值及评价的结果示于表1。
[表1]
*1，DTPP：二亚乙基三胺五(亚甲基膦酸)
PDTP：丙二胺四(亚甲基膦酸)
HEDP：1-羟基乙叉基-1，1-二膦酸
《评价方法》
评价项目：使用半导体基板的蚀刻的评价
使用实施例39~44及比较例21~27的蚀刻液，按照A的步骤制造半导体装置。对所得半导体装置，按照下述基准，分别评价通过电镀设置的镍层的凹部、作为晶种层设置的铜层的蚀刻后的残留状态、及凸块电极的变色的状态。
（关于镍层的凹部的状态）
○：完全没有出现镍层的凹部
△：出现少许镍层的凹部，但实用上没有问题
×：镍层的凹部显著，无法使用
（铜层的残留状态）
○：蚀刻后，没有出现铜层的残留
△：蚀刻后，出现少量铜层的残留，但实用上没有问题
×：蚀刻后，铜层的残留显著，无法使用
（关于凸块电极的变色的状态）
○：完全没有出现变色
△：出现少许变色，但实用上没有问题
×：变色显著，无法使用
实施例39~44及比较例21~27（利用制造方法A的半导体装置的制造）
按照制造方法A（图A（a）~（k））的步骤，制作具有电极及凸块电极的半导体装置。这里，焊料层110的形成使用锡-铅焊料（含有比为锡：铅＝6：4），在图A（i）~（j）所示的蚀刻工序中，使用表2所示的各实施例及比较例的蚀刻液，依次进行铜层106及钛层105的蚀刻。此时，蚀刻温度为30℃，蚀刻时间设为表2所示的时间。
对各实施例及比较例中得到的半导体装置，按照上述评价基准进行评价，将结果示于表2。
实施例45及比较例28
将实施例39及比较例21中的焊料层110由锡-铅焊料（含有比为锡：铅＝6：4）替换为锡-银焊料（银的含量：3质量%），除此以外，与实施例39及比较例21同样操作，分别制作实施例45及比较例28的半导体装置。
对各实施例及比较例中得到的半导体装置，按照上述评价项目进行评价，将结果示于表2。
[表2]
*1，在变色的基础上，还出现变形。
实施例46~51及比较例29~35（利用制造方法B的半导体装置的制造）
按照制造方法B（图B（a）~（k））的步骤，制作具有电极及凸块电极的半导体装置。这里，焊料层110的形成中使用锡-铅焊料（含有比为锡：铅＝6：4），在图B（l）~（m）所示的蚀刻工序中，使用表3所示的各实施例及比较例的蚀刻液，依次进行铜层206及钛层205的蚀刻。此时，蚀刻温度为30℃，蚀刻时间设为表3所示的时间。
对各实施例及比较例中得到的半导体装置，按照上述评价基准进行评价，将结果示于表3。
实施例52及比较例36
将实施例46及比较例29中的焊料层210由锡-铅焊料（含有比为锡：铅＝6：4）替换为锡-银焊料（银的含量：3质量%），除此以外，与实施例46及比较例36同样操作，分别制作实施例52及比较例36的半导体装置。
对各实施例及比较例中得到的半导体装置，按照上述评价项目进行评价，将结果示于表3。
[表3]
*1，在变色的基础上，还出现变形。
由实施例1~38的结果可以确认，本发明的蚀刻液尽管对溅射铜具有0.1μm/分钟以上的高蚀刻速度，但电镀镍被抑制在不足/分钟这样的低蚀刻速度。另外，对于镀锡-铅焊料、及镀锡，在有机膦酸的含量较少而不足0.01质量%的情况下，出现少许变色，但实用上不成问题，另外，在其它实施例中，完全没有出现变色。
另一方面，过氧化氢的含量较少而为0.5质量%的比较例2及5、柠檬酸的含量较少而为0.5质量%的比较例3、苹果酸的含量较少而为0.5质量%的比较例6中，溅射铜的蚀刻速度较低，不足0.1μm/分钟。另外，代替柠檬酸、苹果酸而包含其它有机酸的比较例9、11及18中，溅射铜的蚀刻速度也较低而不足0.1μm/分钟。
不含有有机膦酸的比较例1及4中，镀锡-铅焊料、及镀锡均出现变色。另外，为含有0.05质量%有机膦酸的蚀刻液、但不含有柠檬酸、苹果酸作为有机酸的比较例7~10及12中，镀锡-铅焊料、或者镀锡出现变色。
含有5质量%过氧化氢、不含有柠檬酸及苹果酸作为有机酸的比较例8、13及17中，电镀镍的蚀刻速度为/分钟以上，无法选择性蚀刻铜。
含有5质量%过氧化氢、含有酒石酸、戊二酸、衣康酸作为有机酸的各比较例15、19、20中，得到与实施例1~38相同的蚀刻性能。但是，使用这些比较例中使用的蚀刻液制作半导体装置的各比较例25~27中，确认到：蚀刻后的铜层的残留显著，无法在半导体装置的制作中使用。
产业上的可利用性
本发明的蚀刻液在使用了具有电极的半导体基板的半导体装置的制造工序中使用。本发明的蚀刻液在以下情况下特别有效，即，该半导体装置的制造工序所含的蚀刻工序中，在蚀刻由铜形成的层时由镍形成的层暴露在蚀刻液中的情况下，不想蚀刻该由镍形成的层时。

Claims (10)

1.一种在使用了具有电极的半导体基板的半导体装置的制造中使用的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，所述蚀刻液含有过氧化氢、有机酸和有机膦酸，有机酸为选自柠檬酸及苹果酸中的至少一种，过氧化氢的含量为0.75～12质量％，有机酸的含量为0.75～25质量％，且有机膦酸的含量为0.0005～1质量％。
2.根据权利要求1所述的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，其中，所述蚀刻液中的过氧化氢的含量为1.5～12质量％，有机酸的含量为1.5～20质量％，有机膦酸的含量为0.001～0.25质量％。
3.根据权利要求1所述的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，其中，所述蚀刻液中的过氧化氢的含量为1.5～5质量％，有机酸的含量为1.5～10质量％，有机膦酸的含量为0.01～0.15质量％。
4.根据权利要求1～3中任一项所述的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，其中，所述蚀刻液中的有机膦酸为选自二亚乙基三胺五亚甲基膦酸、丙二胺四亚甲基膦酸及1-羟基乙叉基-1,1-二膦酸中的至少一种。
5.根据权利要求1～3中任一项所述的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，其中，半导体装置具有由焊料形成的凸块电极。
6.根据权利要求1～3中任一项所述的蚀刻液的选择性蚀刻铜而不蚀刻镍的用途，其中，半导体装置具有使用铜形成的布线。
7.一种半导体装置的制造方法，其具有使用权利要求1～6中任一项所述的蚀刻液的蚀刻工序。
8.根据权利要求7所述的半导体装置的制造方法，其中，半导体装置具有由焊料形成的凸块电极。
9.根据权利要求7或8所述的半导体装置的制造方法，其具备在具有电极的半导体基板的该电极上形成布线的再布线形成工序。
10.根据权利要求7或8所述的半导体装置的制造方法，其中，半导体装置具有使用铜形成的布线。
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US8853701B2 (en) * 2010-04-28 2014-10-07 Sharp Kabushiki Kaisha Semiconductor device, display device, and production method for semiconductor device and display device
JP6101421B2 (ja) * 2010-08-16 2017-03-22 インテグリス・インコーポレーテッド 銅または銅合金用エッチング液
JP5658582B2 (ja) * 2011-01-31 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP5933950B2 (ja) * 2011-09-30 2016-06-15 アドバンスド テクノロジー マテリアルズ，インコーポレイテッド 銅または銅合金用エッチング液
US9012263B1 (en) * 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US10026564B2 (en) * 2014-09-15 2018-07-17 Nantong Memtech Technology Co., Ltd. Precious metal switch contact component and its preparation method
JP6531612B2 (ja) * 2014-11-27 2019-06-19 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
JP6657770B2 (ja) * 2014-11-27 2020-03-04 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
CN105483813A (zh) * 2015-11-30 2016-04-13 惠州市博美化工制品有限公司 一种铜基剥离剂及其使用方法
JP6713809B2 (ja) * 2016-03-31 2020-06-24 株式会社荏原製作所 基板の製造方法及び基板
WO2017188108A1 (ja) * 2016-04-27 2017-11-02 三洋化成工業株式会社 エッチング液及び電子基板の製造方法
JP6285983B2 (ja) * 2016-05-06 2018-02-28 インテグリス・インコーポレーテッド 銅または銅合金用エッチング液
JP6941296B2 (ja) * 2017-09-20 2021-09-29 大日本印刷株式会社 リードフレームおよび半導体装置
CN111902569B (zh) * 2018-03-26 2022-03-29 三菱瓦斯化学株式会社 蚀刻液
JP7357243B2 (ja) * 2019-04-18 2023-10-06 パナソニックＩｐマネジメント株式会社 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
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JP2003328159A (ja) * 2002-05-02 2003-11-19 Mitsubishi Gas Chem Co Inc 表面処理剤
KR100505328B1 (ko) 2002-12-12 2005-07-29 엘지.필립스 엘시디 주식회사 구리 몰리브덴막에서 몰리브덴 잔사를 제거할 수 있는식각용액 및 그 식각 방법
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JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
KR101199533B1 (ko) 2005-06-22 2012-11-09 삼성디스플레이 주식회사 식각액, 이를 이용하는 배선 형성 방법 및 박막 트랜지스터기판의 제조 방법
DE102005038414A1 (de) * 2005-08-12 2007-02-15 Basf Aktiengesellschaft Stabilisierte Ätzlösungen zum Ätzen von Cu- und Cu/Ni-Schicht
US7976723B2 (en) * 2007-05-17 2011-07-12 International Business Machines Corporation Method for kinetically controlled etching of copper
WO2009071351A1 (en) 2007-12-06 2009-06-11 Basf Se A method for chemically-mechanically polishing patterned surfaces composed of metallic and nonmetallic patterned regions
CN101903988B (zh) * 2007-12-21 2013-07-31 和光纯药工业株式会社 蚀刻剂、蚀刻方法及蚀刻剂制备液

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