WO2010109892A1 - 半導体基板、半導体装置及び半導体基板の製造方法 - Google Patents

半導体基板、半導体装置及び半導体基板の製造方法 Download PDF

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WO2010109892A1
WO2010109892A1 PCT/JP2010/002152 JP2010002152W WO2010109892A1 WO 2010109892 A1 WO2010109892 A1 WO 2010109892A1 JP 2010002152 W JP2010002152 W JP 2010002152W WO 2010109892 A1 WO2010109892 A1 WO 2010109892A1
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Prior art keywords
epitaxial layer
semiconductor substrate
forming step
dopant gas
trench
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PCT/JP2010/002152
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English (en)
French (fr)
Japanese (ja)
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野上彰二
五東仁
柴田巧
山本剛
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Sumco Corp
Denso Corp
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Sumco Corp
Denso Corp
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Priority to CN201080013387.4A priority Critical patent/CN102362336B/zh
Priority to US13/258,268 priority patent/US8501598B2/en
Priority to EP10755694.6A priority patent/EP2413348B1/en
Publication of WO2010109892A1 publication Critical patent/WO2010109892A1/ja
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3444—P-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor substrate.
  • a power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • An example of the structure of the power MOSFET is a super junction structure.
  • the super junction structure is a structure in which n-type layers and p-type layers are alternately formed in a conductive layer connecting a source and a drain.
  • a depletion layer is formed at the interface between the n-type layer and the p-type layer. For this reason, the electric field between the source and the drain is formed not only in the direction from the source to the drain but also in the direction from the n-type layer to the p-type layer. Don't concentrate on a specific part of the layer. Therefore, the super junction structure can obtain high withstand voltage performance.
  • a method for manufacturing a semiconductor substrate of the present invention includes a first epitaxial layer forming step of forming a first epitaxial layer by introducing a dopant gas of the first conductivity type into a first conductivity type semiconductor substrate; A trench forming step of forming a trench in the first epitaxial layer, and a plurality of growths including different growth rates of an epitaxial layer of a second conductivity type different from the first conductivity type in the first epitaxial layer and the trench An epitaxial layer forming step of forming the trench so as to fill the trench using conditions, and making the concentration of the second conductivity type dopant taken into the epitaxial layer constant in each of the plurality of growth conditions.
  • the plurality of growth conditions include a growth temperature of the epitaxial layer, and the growth rate is changed by changing a growth temperature of the epitaxial layer.
  • the plurality of growth conditions include a flow rate of the second conductivity type dopant gas introduced into the epitaxial layer and the trench, and the growth rate is changed by changing a flow rate of the source gas. It is preferable to do.
  • a method for manufacturing a semiconductor substrate of the present invention includes a first epitaxial layer forming step of forming a first epitaxial layer by introducing a dopant gas of the first conductivity type into a first conductivity type semiconductor substrate; A trench forming step of forming a trench in the first epitaxial layer; and a dopant gas of a second conductivity type different from the first conductivity type in an atmosphere at a predetermined first temperature in the first epitaxial layer and the trench.
  • a method for manufacturing a semiconductor substrate of the present invention includes a first epitaxial layer forming step of forming a first epitaxial layer by introducing a dopant gas of the first conductivity type into a first conductivity type semiconductor substrate, A trench forming step of forming a trench in the first epitaxial layer; and a dopant gas of a second conductivity type different from the first conductivity type in an atmosphere at a predetermined first temperature in the first epitaxial layer and the trench.
  • the semiconductor substrate manufacturing method of the present invention includes a first epitaxial layer forming step of forming a first epitaxial layer by introducing the first conductive type dopant gas into the first conductive type semiconductor substrate, A trench forming step of forming a trench in the first epitaxial layer; and a dopant gas of a second conductivity type different from the first conductivity type in an atmosphere at a predetermined first temperature in the first epitaxial layer and the trench.
  • a second epitaxial layer forming step of forming a second epitaxial layer by introducing the first epitaxial gas at a predetermined first dopant gas flow rate in an atmosphere of a second temperature higher than the first temperature in the second epitaxial layer And introducing the second conductivity type dopant gas at a second dopant gas flow rate less than the first dopant gas flow rate to form the trench.
  • a third epitaxial layer forming step of forming a third epitaxial layer is
  • the amount of dopant in the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer is preferably changed by changing the flow rate of the second conductivity type dopant gas.
  • the amount of dopant in the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer is preferably changed by using a plurality of gas cylinders having different concentrations of the dopant gas of the second conductivity type. .
  • One or more of the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer are preferably formed by simultaneously supplying a source gas and a halide gas in the atmosphere. .
  • the dopant amounts of the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer are substantially the same.
  • the flow rate of the halide gas in the atmosphere is larger than that in the second epitaxial layer forming step and the fourth epitaxial layer forming step.
  • the semiconductor substrate of the present invention is a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate.
  • a semiconductor device of the present invention is a semiconductor device using the semiconductor substrate.
  • the present invention it is possible to provide a semiconductor substrate, a semiconductor device, and a method of manufacturing a semiconductor substrate that can easily obtain desired electrical characteristics.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • FIG. 3 is a partial cross-sectional view sequentially showing changes in the cross section of the semiconductor substrate 1 in the method for manufacturing the semiconductor substrate shown in FIG. 2.
  • It is a fragmentary sectional view showing typically one embodiment of a semiconductor device of the present invention. It is a fragmentary sectional view showing typically other embodiments of the semiconductor device of the present invention.
  • FIG. 1 is a partial cross-sectional view schematically showing one embodiment of a semiconductor substrate of the present invention.
  • a first epitaxial layer 11 is formed on a silicon substrate 10, and a plurality of trenches 12 are formed in the first epitaxial layer 11.
  • a second epitaxial layer 13, a third epitaxial layer 14, and a fourth epitaxial layer 15 are sequentially formed in the trench 12.
  • the fourth epitaxial layer 15 is also formed on the first epitaxial layer 11.
  • the silicon substrate 10 is an n + type silicon substrate in which a high concentration n-type dopant is introduced into single crystal silicon.
  • the first epitaxial layer 11 is formed on the silicon substrate 10.
  • the first epitaxial layer 11 is an n-type silicon epitaxial layer into which an n-type dopant having a lower concentration than the silicon substrate 10 is introduced.
  • a plurality of trenches 12 are formed in the first epitaxial layer 11.
  • the bottom surface of the trench 12 is the main surface of the silicon substrate 10.
  • the trench 12 has a substantially quadrangular prism shape.
  • the side surface of the trench 12 is the inner side surface of the first epitaxial layer 11.
  • the second epitaxial layer 13 is formed in the main surface of the first epitaxial layer 11 and in the trench 12.
  • the second epitaxial layer 13 is a p-type silicon epitaxial layer into which a p-type dopant is introduced.
  • the third epitaxial layer 14 is formed on the second epitaxial layer 13.
  • the second epitaxial layer 13 is a p-type silicon epitaxial layer into which a p-type dopant is introduced. Almost the entire portion of the trench 12 remaining is filled with the second epitaxial layer 13 and the third epitaxial layer 14.
  • the fourth epitaxial layer 15 is formed on the main surface of the second epitaxial layer 13 and the main surface of the third epitaxial layer 14 formed on the main surface of the first epitaxial layer 11 and the remaining part of the trench 12 that is not filled. Is formed.
  • the fourth epitaxial layer 15 is a p-type silicon epitaxial layer into which a p-type dopant is introduced.
  • the first epitaxial layer 11 is composed of an n-type epitaxial layer into which a dopant such as P (phosphorus), As (arsenic), Sb (antimony) or the like is introduced.
  • the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are p-type epitaxial layers into which dopants such as B (boron), Ga (gallium), and In (indium) are introduced.
  • the conductivity types of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are different from those of the first epitaxial layer 11.
  • “Different conductivity types” means p-type for n-type or n-type for p-type. Therefore, for example, if the first epitaxial layer 11 is n-type, the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are p-type.
  • the n-type first epitaxial layer 11, the p-type second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are alternately formed on the silicon substrate 10. It has a super junction structure.
  • the width of the first epitaxial layer 11 is H 1 ( ⁇ m)
  • the widths of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are H 2 ( ⁇ m).
  • the concentration is C 1 (cm ⁇ 3 ) and the carrier concentrations of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are C 2 (cm ⁇ 3 )
  • the amount of dopant contained in the first epitaxial layer 11 and the amount of dopant contained in the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are substantially the same. Therefore, a depletion layer is generated from a pn junction formed by the n-type first epitaxial layer 11, the p-type second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15, and the drift region is completely depleted. The withstand voltage performance can be maintained.
  • FIG. 2 is a flowchart showing an embodiment of the method for manufacturing a semiconductor substrate of the present invention.
  • 3A to 3E are partial cross-sectional views sequentially showing changes of the semiconductor substrate 1 in the method of manufacturing the semiconductor substrate shown in FIG.
  • the manufacturing method of the semiconductor substrate of this embodiment includes a first epitaxial layer forming step S1, a trench forming step S2, a second epitaxial layer forming step S3, and a third epitaxial layer forming step S4. And a fourth epitaxial layer forming step S5.
  • a first epitaxial layer forming step S1 a trench forming step S2, a second epitaxial layer forming step S3, and a third epitaxial layer forming step S4.
  • each step (S1 to S5) will be described with reference to FIG.
  • (S1) First Epitaxial Layer Formation Step As shown in FIG. 3A, an n-type dopant gas is introduced onto an n + -type silicon substrate 10 while supplying a source gas, and these source gases and dopants are introduced.
  • the first epitaxial layer 11 is formed in an atmosphere containing a gas.
  • SiH 4 monosilane
  • disilane Si 2 H 6
  • SiH 2 Cl 2 diichlorosilane
  • SiHCl 3 trichlorosilane
  • SiCl 4 sicon tetrachloride
  • the dopant gas examples include phosphine (PH 3 ) and arsine (AsH 3 ) containing phosphorus (P) which is an n-type dopant when an n-type epitaxial layer is formed.
  • phosphine PH 3
  • AsH 3 arsine
  • P phosphorus
  • diborane B 2 H 6
  • boron trichloride BCl 3
  • the source gas and the dopant gas are the same in the second epitaxial layer forming step S3, the third epitaxial layer forming step S4, and the fourth epitaxial layer forming step S5 described later.
  • the means for forming the first epitaxial layer 11, the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 is not particularly limited.
  • CVD chemical vapor deposition
  • PVD phase growth method
  • MBE molecular beam epitaxy method
  • (S2) Trench Formation Step As shown in FIG. 3B, a resist pattern is formed at a predetermined position on the first epitaxial layer 11 formed in the first epitaxial layer formation step S1, using photolithography. Then, a region in the first epitaxial layer 11 where the resist pattern is not formed is etched by, for example, reactive ion etching to form the trench 12. Then, the trench 12 shown in FIG. 3B is obtained by removing the resist pattern.
  • the second epitaxial layer 13 is formed in an atmosphere containing these source gas, halide gas and dopant gas.
  • the temperature in the atmosphere containing the source gas, halide gas and dopant gas is preferably about 950 to 1000 ° C. (predetermined first temperature), and the flow rate of the dopant gas (predetermined first dopant gas flow rate) is 100 to 300 sccm (Standard Cubic Centimeter meter Minute).
  • the dopant amount (first dopant amount) of the second epitaxial layer 13 is preferably 1 ⁇ 10 15 to 1 ⁇ 10 17 (cm ⁇ 3 ).
  • the dopant amount is a value defined by the flow rate of the dopant gas and the concentration of the dopant gas before the dopant gas is taken into the epitaxial layer, and after the dopant gas is taken into the epitaxial layer. Is a value defined by the density of dopant atoms in the crystal lattice of the epitaxial layer.
  • halide gas examples include HCl (hydrogen chloride), Cl 2 (chlorine), F 2 (fluorine), ClF 3 (chlorine trifluoride), HF (hydrogen fluoride), HBr (hydrogen bromide), and the like. Illustrated. The same applies to the halide gas in the third epitaxial layer forming step S4 and the fourth epitaxial layer forming step S5 described later.
  • the halide gas functions as an etching gas in the trench 12. Since the etching rate of the bottom portion of the trench 12 by the halide gas is slower than the etching rate of the opening portion of the trench 12, the formation rate of the epitaxial layer is faster at the bottom portion than the opening portion of the trench 12. Therefore, generation of voids in the second epitaxial layer 13 formed in the trench 12 can be suppressed.
  • (S4) Third Epitaxial Layer Forming Step As shown in FIG. 3D, after passing through the second epitaxial layer forming step S3, the source gas and the halide gas are supplied onto the second epitaxial layer 13 while p.
  • the third epitaxial layer 14 is formed so as to fill the trench 12 in an atmosphere containing these source gas, halide gas and dopant gas by introducing a dopant gas of a type. At this time, the third epitaxial layer 14 is also formed in a portion other than the trench 12 on the second epitaxial layer 13.
  • the temperature in the atmosphere containing the source gas, the halide gas, and the dopant gas is about 900 to 950 ° C.
  • the flow rate of the p-type dopant gas (second dopant gas flow rate) is 110 to 360 sccm, which is higher than the flow rate of the p-type dopant gas in the second epitaxial layer forming step S3.
  • the dopant amount (second dopant amount) of the third epitaxial layer 14 is preferably 1 ⁇ 10 15 to 1 ⁇ 10 17 (cm ⁇ 3 ).
  • the difference between the temperature in the atmosphere in the second epitaxial layer forming step S3 and the temperature in the atmosphere in the third epitaxial layer forming step S4 is preferably 10 ° C. or higher, and more preferably 50 ° C. or higher. preferable. Further, the difference between the flow rate of the p-type dopant gas in the second epitaxial layer formation step S3 and the flow rate of the p-type dopant gas in the third epitaxial layer formation step S4 is preferably 5 sccm or more, more preferably 30 sccm or more. More preferably.
  • the trench 12 is almost entirely filled with the second epitaxial layer 13 and the third epitaxial layer 14 except for a part.
  • the temperature in the atmosphere in the third epitaxial layer forming step S4 is lower than the temperature in the atmosphere in the second epitaxial layer forming step S3. Therefore, generation of voids and crystal defects in the third epitaxial layer 14 can be suppressed.
  • (S5) Fourth Epitaxial Layer Forming Step As shown in FIG. 3E, after passing through the third epitaxial layer forming step S4, on the second epitaxial layer 13 and the third epitaxial layer 14, a source gas, a halide gas, The fourth epitaxial layer 15 is formed in an atmosphere containing these source gas, halide gas and dopant gas while introducing p-type dopant gas.
  • the temperature in the atmosphere containing the source gas, the halide gas, and the dopant gas is about 950 to 1000 ° C. (third temperature), which is higher than the temperature in the atmosphere in the second epitaxial layer forming step S3.
  • the flow rate of the p-type dopant gas (third dopant gas flow rate) is 100 to 300 sccm, which is lower than the flow rate of the p-type dopant gas in the third epitaxial layer forming step S4. Furthermore, the amount of dopant (third amount of dopant) in the fourth epitaxial layer 15 is preferably 1 ⁇ 10 15 to 1 ⁇ 10 17 (cm ⁇ 3 ).
  • the difference between the temperature in the atmosphere in the fourth epitaxial layer forming step S5 and the temperature in the atmosphere in the third epitaxial layer forming step S4 is preferably 10 ° C. or higher, and more preferably 50 ° C. or higher. preferable. Further, the difference between the flow rate of the p-type dopant gas in the fourth epitaxial layer formation step S5 and the flow rate of the p-type dopant gas in the third epitaxial layer formation step S4 is preferably 5 sccm or more, and more than 30 sccm. More preferably.
  • the conductivity type of the silicon substrate 10 and the first epitaxial layer 11 is n-type
  • the conductivity type of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 is p.
  • the present invention is not limited to this.
  • the conductivity types of the silicon substrate 10 and the first epitaxial layer 11 may be p-type
  • the conductivity types of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 may be n-type. .
  • the flow rate of the n-type dopant gas in the third epitaxial layer formation step S4 is smaller than the flow rate of the n-type dopant gas in the second epitaxial layer formation step S3. Further, the flow rate of the n-type dopant gas in the fourth epitaxial layer forming step S5 is larger than the flow rate of the n-type dopant gas in the third epitaxial layer forming step S4.
  • the semiconductor substrate manufacturing method of the present embodiment is different from the first epitaxial layer 11 and the trench 12 in that the p-type second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are different.
  • a plurality of growth conditions including a growth rate are used to fill the trench 12.
  • the semiconductor substrate manufacturing method of the present embodiment has a constant p-type dopant concentration taken into the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 under each of a plurality of growth conditions.
  • the plurality of growth conditions include the growth temperatures of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15.
  • the growth rate described above is changed by changing the growth temperatures of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15.
  • the plurality of growth conditions may include the flow rate of the p-type dopant gas introduced into the trench 12, the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15.
  • the growth rate changes by changing the flow rate of the source gas (silicon source gas).
  • the temperature (about 950 to 1000 ° C.) in the atmosphere of the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5 is the same as the temperature (about 900 to 950 ° C.) of the third epitaxial layer forming step S4. Higher temperature. Therefore, in the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5, the speed of forming the second epitaxial layer 13 and the fourth epitaxial layer 15 is increased, so that the throughput can be improved.
  • the temperature in the atmosphere of the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5 is the temperature in the atmosphere of the third epitaxial layer forming step S4 (about 900 to 950 ° C.). Therefore, the dopant concentration of the third epitaxial layer 14 tends to be lower than the dopant concentrations of the second epitaxial layer 13 and the fourth epitaxial layer 15. Therefore, in order to suppress fluctuations in the dopant concentration, the flow rate of the dopant gas in the third epitaxial layer formation step S4 is higher than the flow rate of the dopant gas in the second epitaxial layer formation step S3 and the fourth epitaxial layer formation step S5. ing.
  • one or more of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are formed by simultaneously supplying a source gas and a halide gas in an atmosphere.
  • the second epitaxial layer 13 and the third epitaxial layer 14 are simultaneously supplied with the source gas and the halide gas in the atmosphere of the second epitaxial layer forming step S3 and the third epitaxial layer forming step S4. It is formed.
  • the flow rate of the halide gas in the atmosphere is larger than in the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5.
  • the dopant concentration or dopant amount of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 is substantially the same.
  • the dopant concentration is substantially the same means that the difference in dopant concentration is within ⁇ 5%.
  • the semiconductor substrate manufacturing method of the present embodiment includes a first epitaxial layer forming step S1 for forming the first epitaxial layer 11, a trench forming step S2 for forming a trench in the first epitaxial layer, the first epitaxial layer 11 and the trench. 12, a second epitaxial layer forming step S3 for forming the second epitaxial layer 13, a third epitaxial layer forming step S4 for forming the third epitaxial layer 14 on the second epitaxial layer 13, a second epitaxial layer, A fourth epitaxial layer forming step S5 for forming a fourth epitaxial layer on the third epitaxial layer;
  • the temperature in the atmosphere of the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5 is higher than the temperature in the atmosphere of the third epitaxial layer forming step S4, and the third epitaxial layer forming step S4.
  • the flow rate of the dopant gas in is higher than the flow rate of the dopant gas in the second epitaxial layer forming step S3 and the fourth epitaxial layer forming step S5.
  • each of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 can be made substantially the same, for example, when the resistivity measurement of the semiconductor substrate 1 is performed.
  • the resistivity of each of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 is substantially the same. That is, according to the semiconductor substrate manufacturing method of the present embodiment, desired electrical characteristics can be obtained. Therefore, for example, a power MOSFET (see FIG. 4 or FIG. 5) manufactured using the semiconductor substrate 1 having the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 of this embodiment has a withstand voltage. Desired electrical characteristics such as performance and on-resistance can be obtained.
  • the semiconductor substrate manufacturing method can achieve the same effects as described above even when the flow rates of the source gas and / or the halogenated gas are changed.
  • the growth temperature is changed in three stages in the second epitaxial layer forming step S3, the third epitaxial layer forming step S4, and the fourth epitaxial layer forming step S5.
  • the semiconductor substrate manufacturing method of the present invention may change the growth temperature of the epitaxial layer in the trench 12 in two stages.
  • the growth temperature of the epitaxial layer is changed from about 950 to 1000 ° C. to about 900 to 950 ° C., or changed from about 900 to 950 ° C. to about 950 to 1000 ° C. Can be.
  • the semiconductor substrate manufacturing method of the present invention may include the first epitaxial layer forming step S1, the trench forming step S2, the second epitaxial layer forming step S3, and the third epitaxial layer forming step S4. Good.
  • the p-type second epitaxial layer 13 is formed in the n-type first epitaxial layer 11 and the trench 12 in a p-type dopant in an atmosphere of about 950 to 1000 ° C.
  • a gas is introduced at a first dopant gas flow rate.
  • the p-type third epitaxial layer 14 is supplied to the second epitaxial layer 13 with the p-type dopant gas in the atmosphere of about 900 to 950 ° C., as the first dopant gas.
  • the trench 12 is formed so as to be filled with the second dopant amount larger than the flow rate.
  • the second epitaxial layer 13 is about In an atmosphere of 950 to 1000 ° C., an n-type dopant gas is introduced into the first epitaxial layer 11 and the trench 12 at a first dopant gas flow rate.
  • the n-type third epitaxial layer 14 is supplied with an n-type dopant gas and a first dopant gas in the second epitaxial layer 13 in an atmosphere of about 900 to 950 ° C.
  • the trench 12 is formed so as to be filled with the second dopant amount smaller than the flow rate.
  • the second epitaxial layer 13 is formed in an atmosphere of about 950 to 1000 ° C.
  • the third epitaxial layer 14 is formed in an atmosphere of about 900 to 950 ° C. where the growth temperature is lower than that of the second epitaxial layer 13.
  • the fourth epitaxial layer 15 is not formed, and the second epitaxial layer 13 and the third epitaxial layer 14 are formed so as to be buried in the trench 12.
  • the second epitaxial layer 13 is formed by using a p-type dopant gas as a first dopant gas in the first epitaxial layer 11 and the trench 12 in an atmosphere of about 900 to 950 ° C. It may be formed by introducing at a flow rate.
  • the third epitaxial layer 14 causes the p-type dopant gas to be added to the second epitaxial layer 13 in an atmosphere of about 950 to 1000 ° C. more than the first dopant gas flow rate.
  • the trench 12 may be formed so as to be introduced at a large second dopant gas flow rate to fill the trench 12.
  • the fourth epitaxial layer 15 is not formed, and the second epitaxial layer 13 and the third epitaxial layer 14 are formed so as to be buried in the trench 12.
  • the second epitaxial layer 13 is about 900 to In an atmosphere of 950 ° C., an n-type dopant gas may be introduced into the first epitaxial layer 11 and the trench 12 at a first dopant gas flow rate.
  • the third epitaxial layer 14 has an n-type dopant gas added to the second epitaxial layer 13 in an atmosphere of about 950 to 1000 ° C. rather than the first dopant gas flow rate.
  • the trench 12 may be formed so as to be introduced with a small second dopant gas flow rate.
  • the fourth epitaxial layer 15 is not formed, and the second epitaxial layer 13 and the third epitaxial layer 14 are formed so as to be buried in the trench 12.
  • the first dopant amount of the second epitaxial layer 13, the second dopant amount of the third epitaxial layer 14, and the third dopant amount of the fourth epitaxial layer 15 described above are p-type or n-type dopant gas. It changes by changing the flow rate. Furthermore, the first dopant amount, the second dopant amount, and the third dopant amount change by using a plurality of gas cylinders having different concentrations of p-type or n-type dopant gas.
  • the growth temperature may be changed in four or more steps without changing the growth temperature in two or three steps, and the growth temperature is continuously changed.
  • an epitaxial layer may be formed in the trench 12.
  • the present invention is not limited to this.
  • the flow rates of the source gas and / or the halogenated gas may be changed.
  • FIG. 4 is a partial cross-sectional view schematically showing one embodiment of a semiconductor device of the present invention.
  • FIG. 5 is a partial cross-sectional view schematically showing another embodiment of the semiconductor device of the present invention.
  • the N-channel power MOSFET 2 includes a silicon substrate 10, a first epitaxial layer 11, a second epitaxial layer 13, a third epitaxial layer 14, a fourth epitaxial layer 15, and a fifth epitaxial layer.
  • a layer 16, a source region 17, an ohmic connection region 18, and a trench insulated gate electrode 19 are provided.
  • the silicon substrate 10 is a drain region.
  • the first epitaxial layer 11 is an n-type epitaxial layer formed on the silicon substrate 10 as described above.
  • the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are p-type epitaxial layers.
  • the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are mutually connected to the first epitaxial layer 11 in the trench 12 formed on the first epitaxial layer 11 and the first epitaxial layer 11 at a predetermined interval. Adjacently formed alternately.
  • the fifth epitaxial layer 16 is a p-type epitaxial layer formed on the fourth epitaxial layer 15.
  • the fifth epitaxial layer 16 functions as a channel formation layer.
  • the fifth epitaxial layer 16 is a p-type epitaxial layer formed on the fourth epitaxial layer 15.
  • the fifth epitaxial layer 16 functions as a channel formation layer.
  • the fifth epitaxial layer 16 is formed on the fourth epitaxial layer 15 after planarizing and polishing the surface of the fourth epitaxial layer.
  • the n-type source region 17 and the p-type ohmic connection region 18 are formed on the fourth epitaxial layer 15.
  • the n-type source region 17 is formed, for example, by ion-implanting an n-type dopant into a p-type epitaxial layer.
  • the p-type ohmic connection region 18 is formed by ion implantation of a p-type dopant, for example.
  • the trench insulated gate electrode 19 is formed through a part of the source region 17, the fifth epitaxial layer 16, the fourth epitaxial layer 15, the third epitaxial layer 14, and the second epitaxial layer 13.
  • the trench 20 penetrating a part of the source region 17, the fifth epitaxial layer 16, the fourth epitaxial layer 15, the third epitaxial layer 14, and the second epitaxial layer 13 is formed. Is done.
  • An insulating film 21 is formed on the bottom and side surfaces of the formed trench 20 using a thermal oxidation method, a CVD method, or the like.
  • the trench insulating gate electrode 19 is made of polycrystalline silicon 22 and is formed on the insulating film 21 so as to fill the trench 20.
  • the amount of dopant in the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 is the same as that of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15. It is constant throughout.
  • the power MOSFET 2 shown in FIG. 5 can be obtained by reversing the conductivity type of each component in the power MOSFET 2 shown in FIG.
  • the semiconductor substrate and the manufacturing method thereof according to the present invention have been described above.
  • the present invention is not limited to the above-described embodiment.
  • the conductivity types of the silicon substrate 10 and the first epitaxial layer 11 are n-type
  • the conductivity types of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 are p-type.
  • the present invention is not limited to this.
  • the conductivity types of the silicon substrate 10 and the first epitaxial layer 11 may be p-type
  • the conductivity types of the second epitaxial layer 13, the third epitaxial layer 14, and the fourth epitaxial layer 15 may be n-type. .
  • the semiconductor substrate using silicon has been described.
  • the present invention is not limited to this.
  • a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN) may be used.
  • the semiconductor substrate 1 shown in FIG. 1 was manufactured by performing the steps S1 to S5 shown in the above-described embodiment. Below, it shows about the temperature in the atmosphere at the time of forming a 2nd epitaxial layer, a 3rd epitaxial layer, and a 4th epitaxial layer, and the flow volume of a dopant.
  • the dopant diborane (B 2 H 6 ) gas having a concentration of 100 ppm was used.
  • the temperature in the atmosphere when forming the second epitaxial layer is 970 ° C., and the flow rate of the dopant gas is 220 sccm.
  • the temperature in the atmosphere when forming the third epitaxial layer is 950 ° C., and the flow rate of the dopant gas is 250 sccm.
  • the temperature in the atmosphere when forming the fourth epitaxial layer is 980 ° C., and the flow rate of the dopant gas is 210 sccm.
  • Example 1 the semiconductor substrate 1 obtained by each process of S1 to S5 was measured for resistivity by a spread resistance measuring device and evaluated for electrical characteristics.
  • the variation in the profile of the resistivity in the thickness direction (for example, maximum value ⁇ minimum value) was ⁇ 2% or less.
  • Comparative Example 1 Compared to Example 1, the flow rate of the dopant gas in the atmosphere in the third epitaxial layer forming step S4 was 220 sccm. The rest is the same as in the first embodiment. In Comparative Example 1, the variation in resistivity profile in the thickness direction was ⁇ 11%.
  • Example 1 has a uniform resistivity profile in the thickness direction. That is, the dopant concentration of each of the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer changes little and becomes substantially the same. Therefore, it can be seen that Example 1 obtained electrical characteristics suitable for manufacturing a MOSFET having a super junction structure.
PCT/JP2010/002152 2009-03-26 2010-03-25 半導体基板、半導体装置及び半導体基板の製造方法 Ceased WO2010109892A1 (ja)

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US13/258,268 US8501598B2 (en) 2009-03-26 2010-03-25 Semiconductor substrate, semiconductor device, and method of producing semiconductor substrate
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JP2015162492A (ja) * 2014-02-26 2015-09-07 豊田合成株式会社 半導体装置の製造方法
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US20120032312A1 (en) 2012-02-09
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US8501598B2 (en) 2013-08-06

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