JP7077252B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7077252B2 JP7077252B2 JP2019033709A JP2019033709A JP7077252B2 JP 7077252 B2 JP7077252 B2 JP 7077252B2 JP 2019033709 A JP2019033709 A JP 2019033709A JP 2019033709 A JP2019033709 A JP 2019033709A JP 7077252 B2 JP7077252 B2 JP 7077252B2
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- 239000004065 semiconductor Substances 0.000 title claims description 137
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000010410 layer Substances 0.000 claims description 102
- 238000000034 method Methods 0.000 claims description 14
- 239000002344 surface layer Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims 1
- 239000011800 void material Substances 0.000 description 20
- 238000009792 diffusion process Methods 0.000 description 17
- 239000012535 impurity Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/02518—Deposited layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Plasma & Fusion (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図2(a)~図6(b)は、実施形態に係る半導体装置1の製造過程を示す模式断面図である。また、図2(a)~図6(b)は、半導体ウェーハ100の断面を表す模式図である。半導体ウェーハ100は、例えば、n形シリコンウェーハである。
Claims (5)
- 第1導電形の第1ウェーハおよび第1導電形の第2ウェーハのそれぞれに、略同一の形状およびサイズの拡張された開口部を有するトレンチを形成する工程と、
前記第1ウェーハの前記トレンチの内部に、前記開口部に位置するスペースを残して、第2導電形の第1半導体層を第1成長条件下で形成する工程と、
前記第2ウェーハの前記トレンチの内部に、前記第1成長条件下で第2導電形の第2半導体層を形成した後、前記開口部に残されたスペースを埋め込んだ第3半導体層を第2成長条件下で形成する工程と、
前記開口部に位置する前記スペースの底に対応する第1レベルであって、前記トレンチの深さ方向の第1レベルと、前記スペースのサイズもしくは形状に基づく前記深さ方向の第2レベルと、を前記第1ウェーハにより得た後に、前記第2ウェーハの前記第3半導体層が設けられた表面側において、前記第2ウェーハの表層を、前記第1レベルと前記第2レベルの間の中間位置の深さに相当する深さまで除去する工程と、
を備えた半導体装置の製造方法。 - 前記第1成長条件は、前記トレンチの内面上に第1成長速度で第2導電形の半導体を成長する第1段階と、前記第1成長速度よりも遅い第2成長速度で第2導電形の半導体を成長する第2段階と、を含む請求項1記載の半導体装置の製造方法。
- 前記第2成長条件は、前記第2成長速度よりも速い成長速度で第2導電形の半導体を成長することを含む請求項2記載の半導体装置の製造方法。
- 前記第2レベルは、前記スペースの開口幅の2分の1にtan54.7°を乗じた値の深さに位置する前記深さ方向のレベルである請求項1~3のいずれか1つに記載の半導体装置の製造方法。
- 前記トレンチは、前記第1ウェーハおよび前記第2ウェーハの上に設けられたマスクを用いた選択エッチングにより形成され、
前記第1半導体層、第2半導体層および前記第3半導体層は、前記第1ウェーハおよび前記第2ウェーハの上に前記マスクを残した状態で形成される請求項1~4のいずれか1つに記載の半導体装置の製造方法。
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US16/550,676 US10804376B2 (en) | 2019-02-27 | 2019-08-26 | Method of manufacturing semiconductor device |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006245269A (ja) | 2005-03-03 | 2006-09-14 | Fujitsu Ltd | 基板研磨方法 |
JP2010182881A (ja) | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体装置の製造方法 |
WO2010109892A1 (ja) | 2009-03-26 | 2010-09-30 | 株式会社Sumco | 半導体基板、半導体装置及び半導体基板の製造方法 |
JP2010225831A (ja) | 2009-03-24 | 2010-10-07 | Toshiba Corp | 半導体装置の製造方法 |
US20170221988A1 (en) | 2016-01-28 | 2017-08-03 | Infineon Technologies Austria Ag | Method of Manufacturing Semiconductor Devices Including Deposition of Crystalline Silicon in Trenches |
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JP2006281384A (ja) | 2005-04-01 | 2006-10-19 | Toshiba Corp | 研磨装置、基板の研磨終点位置検出方法、及び基板の膜厚測定方法 |
JP5072221B2 (ja) | 2005-12-26 | 2012-11-14 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2012156225A (ja) | 2011-01-25 | 2012-08-16 | Toshiba Corp | 半導体装置およびその製造方法 |
JP5556851B2 (ja) | 2011-12-26 | 2014-07-23 | 株式会社デンソー | 半導体装置の製造方法 |
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- 2019-02-27 JP JP2019033709A patent/JP7077252B2/ja active Active
- 2019-08-26 US US16/550,676 patent/US10804376B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006245269A (ja) | 2005-03-03 | 2006-09-14 | Fujitsu Ltd | 基板研磨方法 |
JP2010182881A (ja) | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体装置の製造方法 |
JP2010225831A (ja) | 2009-03-24 | 2010-10-07 | Toshiba Corp | 半導体装置の製造方法 |
WO2010109892A1 (ja) | 2009-03-26 | 2010-09-30 | 株式会社Sumco | 半導体基板、半導体装置及び半導体基板の製造方法 |
US20170221988A1 (en) | 2016-01-28 | 2017-08-03 | Infineon Technologies Austria Ag | Method of Manufacturing Semiconductor Devices Including Deposition of Crystalline Silicon in Trenches |
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JP2020140994A (ja) | 2020-09-03 |
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