WO2010098294A1 - 炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置 Download PDFInfo
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- WO2010098294A1 WO2010098294A1 PCT/JP2010/052667 JP2010052667W WO2010098294A1 WO 2010098294 A1 WO2010098294 A1 WO 2010098294A1 JP 2010052667 W JP2010052667 W JP 2010052667W WO 2010098294 A1 WO2010098294 A1 WO 2010098294A1
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Definitions
- the present invention relates to a silicon carbide semiconductor device used as a power semiconductor device.
- an IGBT or a vertical MOSFET (a MOS structure may be a planar type or a trench type), which is a typical example of a power semiconductor device (power device) having a MOS structure, is, for example, an inverter circuit.
- power devices have a gate insulating film that is much thinner than a field oxide film or the like.
- the vertical MOSFET for power described in Patent Document 1 is a device using Si as a semiconductor substrate material.
- FIGS. 1 and 2 of Patent Document 1 in the adjacent region on the cell region side of the MOSFET adjacent to the peripheral portion (including the gate pad portion) of the MOSFET cell region, Along the line, fine diodes are arranged in at least one row.
- Each of the diodes arranged in a line in the region between the gate pad portion and the MOSFET cell region is shown in FIG. 3 of Patent Document 1 when the MOSFET switches from the ON state to the OFF state.
- holes injected from the P well and the P base into the N-type semiconductor layer on the drain side during forward bias are absorbed.
- Patent Document 1 can prevent the parasitic transistor shown in FIG. 3 of Patent Document 1 from turning on when the MOSFET switches from the forward bias to the reverse bias.
- the P base which is the P well of the MOSFET cell, is electrically connected to the source electrode via the back gate. Yes.
- the drain voltage of the MOSFET cell that is, the drain electrode voltage
- the drain electrode voltage suddenly increases and changes from approximately 0 V to several hundred V.
- a displacement current flows into the P well via the parasitic capacitance existing between the P well and the N ⁇ drain layer.
- This displacement current flows to the source electrode as will be described below, even if the P-well forming the parasitic capacitance with the N ⁇ drain layer is a P-well of the MOSFET cell.
- the area of the cross section of the P well below the gate pad or below the gate finger is compared with the area of the cross section of the P well of the MOSFET cell and the area of the cross section of the P well of the diode cell. Is very big. Therefore, the electric resistance value in the P well below the gate pad or the gate finger is very large compared to the electric resistance value of the P well of the MOSFET cell and the electric resistance value of the P well of the diode cell. become.
- the cross-sectional area of the P-well below the gate pad or the gate finger is much larger than the cross-sectional area of the other P-wells.
- a portion of the P well having a large horizontal distance from a portion (a portion immediately below the contact hole) electrically connected to the source electrode via the contact hole and the field plate has a relatively large potential. It will have. Moreover, this potential increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.
- the gate insulating film is formed on the cell side end portion farthest from the contact hole in the P-well below the gate finger connected to the gate pad. And a gate electrode having a voltage value close to 0V immediately after the MOSFET cell is switched from the ON state to the OFF state, and the cell side end portion of the P well, In some cases, a large electric field is applied to the gate insulating film between the two, and the insulating properties of the gate insulating film are destroyed.
- SiC semiconductor device for example, a vertical MOSFET or IGBT
- SiC silicon carbide
- whose band gap is about three times larger than that of Si, which is a conventional semiconductor substrate material, as a semiconductor substrate material is used as an inverter circuit.
- SiC silicon carbide
- the further high-speed drive of the switching element is calculated
- Patent Document 1 The structural problem pointed out with reference to Patent Document 1 is a problem that can occur in the same manner even if the semiconductor substrate material is replaced with the above SiC from the conventional Si.
- the semiconductor substrate material is SiC, as described above, the fluctuation dV / dt with respect to the time t of the drain voltage V is required to be further increased. The value of the displacement current flowing into the well is further increased.
- the semiconductor substrate material is replaced with SiC
- the following problems emerge. That is, in a switching element using SiC as a semiconductor substrate material, it is difficult to sufficiently reduce the resistance of the semiconductor layer due to a large band gap of SiC compared to a conventional switching element using Si as a semiconductor substrate material. become. For this reason, when SiC is used as the semiconductor substrate material, the value of the parasitic resistance of the P well described above is larger than that of using Si, and the value of the large parasitic resistance is below the gate pad or There is a problem that the potential generated in the P-well below the gate finger is further increased.
- the present invention has been made based on the discovery of such problems and the recognition of the locations where such problems have occurred.
- the main object of the present invention is switching in a SiC semiconductor device functioning as a switching element having a MOS structure. In addition to suppressing the occurrence of dielectric breakdown between the gate electrode and the source electrode at the time of turn-off or turn-off, the switching speed or the charge / discharge speed is improved, thereby reducing the loss.
- a silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a drift layer of a first conductivity type disposed on a main surface of the silicon carbide semiconductor substrate, and an interior of the drift layer from an upper surface of the drift layer. And a second conductivity type well layer, and the second conductivity type semiconductor layer disposed on the upper surface of the well layer.
- the silicon carbide semiconductor device According to the silicon carbide semiconductor device according to the present invention, it is possible to suppress the potential distribution in the well layer of the second conductivity type generated by the displacement current that can be generated at the time of switching, particularly at the time of turn-off, in the direction of reducing the potential distribution.
- the potential difference between the gate electrode and the second conductivity type well layer can be reduced to effectively prevent the breakdown of the gate insulating film, thereby improving the switching speed and extending the lifetime of the device.
- the loss can be reduced as the switching speed is improved, the power consumption (energy saving) of the apparatus can also be promoted.
- SiC semiconductor device As an example of the SiC semiconductor device according to the present embodiment, the structure, manufacturing method, and evaluation of an n-type channel SiC-MOSFET are described below.
- FIG. 1 is a plan view schematically showing an upper surface structure of the SiC-MOSFET according to the present embodiment.
- FIG. 2 is a view showing a longitudinal sectional structure relating to the Y1-Y2 line of the SiC-MOSFET shown in FIG.
- the structural features of the SiC-MOSFET shown in FIG. 1 and FIG. 2 are that the p-type well layer 1 located immediately below the gate electrode pad 11 (the outermost p-type well layer 1OM having the largest cross-sectional area).
- the p-type semiconductor layer 14 is disposed entirely or partially on the upper surface.
- the p-type layer located immediately below the gate electrode pad portion 11 is composed of the p-type well layer 1OM and a composite layer of the p-type semiconductor layer 14 thereon. .
- the resistance of the p-type layer located immediately below the gate electrode pad portion 11 is reduced from the overall viewpoint. Therefore, of the end portion of the p-type well 1OM located immediately below the gate electrode pad portion 11, the end portion on the opposite side to the MOSFET cell region side where a plurality of MOSFET cells each operating as a MOSFET are disposed, and The potential difference or electric resistance between the vicinity and the vicinity of the well contact layer 3 of the p-type well layer 1OM located immediately below the gate electrode pad portion 11 is reduced.
- the value of the voltage applied between the vicinity of the well contact layer 3 of the p-type well layer 1OM located immediately below the gate electrode pad portion 11 and the gate electrode polysilicon layer 7 is significantly reduced.
- the insulating property of the gate insulating film 6 located immediately below the gate electrode polysilicon layer 7 is protected.
- the impurity concentration contained in the p-type semiconductor layer 14 is set to be larger than that of the p-type well layer 1OM located immediately below the gate electrode pad portion 11, and the impurity concentration range is 1 ⁇ 10 19. It is preferably set to cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
- the thickness of the p-type semiconductor layer 14 is preferably set to about 100 nm or more, for example. However, the band gap of the p-type semiconductor layer 14 may be larger, smaller, or the same as that of the p-type well layer 1OM located immediately below the gate electrode pad portion 11.
- the p-type semiconductor layer 14 which is a characteristic portion is structurally and electrically connected to the gate electrode pad portion 11 and is also structurally and electrically connected to each gate electrode polysilicon layer 7. From the standpoint of the function and effect, the p-type well layer 1 (1OM) located immediately below the portion (not shown) is also disposed on the upper surface of the p-type well layer 1 (1OM). That is preferred.
- each reference numeral indicates the following component. That is, 1 is a p-type well layer, 1OM is an outermost p-type well layer (second well layer), 2 is an n-type contact layer, 3 is a well contact layer, 5 is SiC as a base material. 4 is an n-type drift layer disposed on the main surface of the n-type semiconductor substrate 5, 6 is a gate insulating film made of, for example, a silicon oxide film, and 7 is a poly for gate electrode.
- the p-type well layer formed in the MOSFET cell region may be referred to as a first well layer
- the p-type well layer formed in the outer periphery of the MOSFET cell region may be referred to as a second well layer.
- the conductivity type of each semiconductor layer may be reversed.
- the n-type conductivity type is defined as “first conductivity type”
- the p-type becomes “second conductivity type”
- the conductivity type is reversed
- the p-type conductivity type becomes “first conductivity type”.
- the n-type conductivity type is the “second conductivity type”.
- the names of the electrodes other than the gate electrode are also reversed. This also applies to Embodiment 2 and Embodiment 3 described later.
- n-type drift layer 4 made of n-type silicon carbide is formed on the upper surface (main surface) of n-type semiconductor substrate 5 made of silicon carbide by an epitaxial crystal growth method.
- the n-type semiconductor substrate 5 for example, an n-type 4H-silicon carbide substrate is suitable. Further, the n-type drift layer 4 is doped with nitrogen, and the concentration of nitrogen is in the range of 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 . The thickness of the n-type drift layer 4 is preferably in the range of 10 ⁇ m to 15 ⁇ m. Note that phosphorus may be doped instead of nitrogen.
- n-type drift layer 4 After the n-type drift layer 4 is formed, impurities are ion-implanted into portions spaced apart from each other on the upper surface of the n-type drift layer 4 by using a resist (not shown) as a mask to form a pair of p-type wells. Layer 1 is formed in n-type drift layer 4.
- the impurity concentration at that time is in the range of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3
- the thickness of the p-type well layer 1 is in the range of 0.5 ⁇ m to 1.5 ⁇ m.
- the p-type impurity include boron (B) and aluminum (Al).
- impurities are ion-implanted into each p-type well layer 1 to be present in the MOSFET cell region among the plurality of p-type well layers 1, using a resist (not shown) as a mask, An n-type contact layer 2 is formed.
- the impurity concentration at that time is in the range of 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 , and the thickness of the layer 2 is in the range of 0.3 ⁇ m to 0.8 ⁇ m. It is preferable.
- the n-type impurity include phosphorus (P) and nitrogen (N).
- a resist (not shown) is provided around the outermost periphery of the p-type well layer 1 that is located immediately below the gate electrode pad portion 11 in FIG. 2 among the plurality of p-type well layers 1.
- impurities are ion-implanted to form the p-type JTE layer 13, and then the resist is removed.
- the impurity concentration at that time is preferably in the range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 , and the thickness of the layer 13 is in the range of 0.5 ⁇ m to 1.5 ⁇ m. It is preferable to be within.
- the p-type impurity include boron (B) and aluminum (Al).
- impurities are ion-implanted into each of the plurality of p-type well layers 1 using a resist (not shown) as a mask to form the p-type well contact layer 3, and then the resist is removed.
- the impurity concentration is preferably in the range of 1 ⁇ 10 20 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3
- the thickness of the layer 3 is in the range of 0.3 ⁇ m to 0.8 ⁇ m. It is preferable to be within.
- the p-type impurity include boron (B) and aluminum (Al).
- each of the n-type and p-type impurities implanted so far is activated.
- This is a process of electrically activating implanted ions by annealing a wafer at a high temperature using a heat treatment apparatus.
- the n-type channel epitaxial layer may be formed by further depositing n-type SiC by the epitaxial crystal growth method and patterning with a resist (not shown) as a mask.
- the impurity doped in the n-type channel epitaxial layer is nitrogen, the concentration of nitrogen is in the range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 , and the thickness of the n-type channel epitaxial layer is It is preferable that it exists in the range of 0.3 micrometer or more and 0.6 micrometer or less. Note that phosphorus may be doped instead of nitrogen.
- the upper surface of the n-type drift layer 4 is oxidized by thermal oxidation to form an insulating film 6A of SiO 2 film over the entire surface of the wafer, and further, p-type polysilicon is formed by CVD.
- a film 7A is deposited on the insulating film 6A (FIG. 3).
- the p-type polysilicon film 7A is patterned to form a gate insulating film 6 and a gate electrode polysilicon layer 7 thereon as shown in FIG.
- an insulating film 8A such as a TEOS film is formed (FIG. 5), and the insulating film 8A is patterned to form a part of the interlayer insulating film 8 (FIG. 6).
- a p-type polysilicon film 14A is formed by the CVD method (FIG. 7), and the entire upper surface of the outermost p-type well layer 1OM outside the MOSFET cell region or within the plurality of p-type well layers 1 or A p-type semiconductor layer 14 is formed by patterning with a resist mask (not shown) so as to cover a part (FIG. 8). Thereafter, the resist mask is removed.
- the p-type semiconductor layer 14 formed in this step is a single crystal or polycrystalline of SiC, Si, GaAs, GaP, InP, InAs, ZnS, ZnSe, CdS, SiGe, GaN, AlN, BN, or C (diamond). Or you may be comprised from the amorphous semiconductor or these mixtures. Further, the film forming method may be a vapor deposition method or a sputtering method.
- the present invention is characterized in that there are few limitations on the material of the p-type semiconductor layer 14. Note that when the p-type semiconductor layer 14 is made of SiC containing p-type impurities, the heat resistance can be improved.
- the oxide film 12A is patterned with a resist mask (not shown), and the resist mask is removed, so that FIG. 10 shows.
- the field oxide film 12 is formed on the entire upper surface of the p-type semiconductor layer 14.
- a p-type polysilicon film 7B is deposited over the entire surface by CVD (FIG. 11), and then the p-type polysilicon film 7B is patterned to form a gate electrode polysilicon layer 7 on the field oxide film 12. (FIG. 12).
- the gate electrode polysilicon layers 7 are depicted as being separated, but in reality, all the gate electrode polysilicon layers 7 are connected to each other in a mesh pattern.
- an insulating film 8B such as a TEOS film is formed (FIG. 13), and the insulating film 8B is patterned to form an interlayer insulating film 8 (FIG. 14).
- annealing is performed to silicide the nickel and form the well contact layer 3 on which the NiSi layer 9 is formed (FIG. 15).
- a contact hole to the gate electrode polysilicon layer 7 on the field oxide film 12 and a contact hole to the p-type semiconductor layer 14 are formed (FIG. 16), and aluminum is deposited and patterned to form the source electrode 10. And a gate electrode pad portion (gate electrode) 11 are formed (FIG. 17).
- drain electrode 17 of FIG. 2 is formed on the back surface of the n-type semiconductor substrate 5.
- the potential difference distribution between the p-type well layer 1 (1OM) and the gate electrode pad portion (gate electrode) 11 is numerically calculated assuming that the fluctuation dV / dt of the drain voltage with respect to time t is 600 V / 20 nsec.
- the maximum value of the SiC-MOSFET manufactured by the conventional method was 120 V or more, but the maximum value of the SiC-MOSFET manufactured by the manufacturing method of the present embodiment was 60 V or less.
- SiC semiconductor device As an example of the SiC semiconductor device according to the present embodiment, the structure and evaluation of an n-type channel SiC-IGBT will be described below.
- FIG. 18 is a plan view schematically showing the upper surface structure of the SiC-IGBT according to the present embodiment.
- FIG. 19 is a view showing a longitudinal sectional structure relating to the Y1-Y2 line of the SiC-IGBT shown in FIG.
- FIG. 19 is different from the structure shown in FIG. 2 in the p-type semiconductor substrate 15, the emitter electrode 16 and the collector electrode 18, and the same reference numerals denote the same parts. Accordingly, the structure of FIG. 19 is also characterized by the p disposed on the upper surface of the p-type well layer 1 (1OM) located on the outermost periphery having the largest cross-sectional area among the plurality of p-type well layers 1.
- the type semiconductor layer 14 exists.
- FIG. 19 The structure of FIG. 19 is manufactured by the same process as in the first embodiment except that the p-type semiconductor substrate 15 is used instead of the n-type semiconductor substrate 5.
- the p-type substrate 15 for example, a p-type 4H-silicon carbide substrate is suitable.
- the p-type semiconductor layer 14 is disposed entirely or partially on the upper surface of the outermost peripheral p-type well layer 1 (corresponding to 1OM). However, as an example of partial arrangement, it may be arranged in a comb shape.
- the p-type semiconductor layer 14 is arranged in a comb shape will be described with reference to FIGS.
- FIG. 20 is a partial plan view when the configuration above the n-type drift layer 4 is omitted.
- the p-type well layers 1 and 1OM formed in the upper layer portion of the n-type drift layer 4 and the p-type well layer 1 are shown.
- N-type contact layer 2 formed in the upper layer portion
- p-type well contact layer 3 formed in the upper layer portion of p-type well layer 1OM
- p-type well contact layer formed in the upper layer portion of p-type well layer 1 3.
- the p-type well layer 1 has a quadrangular planar shape, and a configuration in which the n-type contact layer 2 and the p-type well contact layer 3 are formed concentrically on the surface thereof has a gap in the surface of the n-type drift layer 4.
- a plurality of the arrays are formed in parallel.
- this arrangement is referred to as an arrangement of the p-type well contact layer 3.
- FIG. 21 is a partial plan view showing a gate electrode polysilicon layer 7 (referred to as a lower polysilicon layer) formed on the n-type drift layer 4, according to the formation position of the p-type well contact layer 3.
- a rectangular opening OP for exposing the p-type well contact layer 3 is provided.
- a notch NP1 is provided at a position corresponding to the p-type well contact layer 3 provided in the p-type well layer 1OM.
- FIG. 22 is a partial plan view showing the p-type semiconductor layer 14 formed in a comb-teeth shape.
- the p-type semiconductor layer 14 extends along the direction of the p-type well contact layer 3 in the direction opposite to the arrangement.
- the mold semiconductor layer 14 extends to form a plurality of comb teeth. Note that the p-type semiconductor layer 14 extends along the arrangement direction of the comb teeth so as to connect the arrangement of the comb teeth at one end of the comb teeth.
- FIG. 23 is a partial plan view showing a polysilicon layer 7 for gate electrodes (referred to as an upper polysilicon layer) formed on the interlayer insulating film 8, and a p-type well contact layer provided on the p-type well layer 1OM.
- a notch NP ⁇ b> 2 is provided at a position corresponding to 3.
- FIGS. 24, 25, and 26 Cross-sectional views taken along lines a-a ′, b-b ′, and c-c ′ shown in FIGS. 20 to 23 are shown in FIGS. 24, 25, and 26. Also, the position of the A-A ′ line shown in FIGS. 20 to 23 corresponds to the position of the line L shown in FIGS.
- an electric field concentration region is formed at the junction surface between the p-type well layer 1OM and the p-type semiconductor layer 14. That is, in FIG. 22, the corner portion CN exists in a portion corresponding to the space between the comb teeth, so that an electric field concentration region is formed on the joint surface near the corner portion CN. As a result, the injection of holes from the p-type semiconductor layer 14 to the p-type well layer 1OM is promoted.
- SiC semiconductor device As an example of the SiC semiconductor device according to the present embodiment, the structure, manufacturing method, and evaluation of an n-type channel SiC-MOSFET are described below.
- FIG. 27 is a view showing a longitudinal sectional structure relating to the Y1-Y2 line of the SiC-MOSFET shown in FIG.
- the configuration shown in FIG. 27 is an example in which the p-type semiconductor layer 14 is formed in a part of the outermost p-type well layer 1OM outside the MOSFET cell region.
- the p-type semiconductor layer 14 is not formed on the p-type well layer 1OM but is formed in the upper layer portion of the p-type well layer 1OM. This is different from the n-type channel SiC-MOSFET of the first embodiment shown in FIG. For this reason, until the p-type well contact layer 3 is formed, it is formed through the same process as that of the n-type channel SiC-MOSFET described in the first embodiment.
- a method for manufacturing the SiC-MOSFET according to the present embodiment will be described with reference to the longitudinal sectional views of FIGS.
- the p-type well contact layer 3 is formed in the plurality of p-type well layers 1, all or one of the upper surfaces of the outermost p-type well layers 1 OM outside the MOSFET cell region in the plurality of p-type well layers 1.
- a p-type impurity is ion-implanted into the portion using a resist (not shown) as a mask to form a p-type semiconductor layer 14, and then the resist is removed.
- the impurity concentration in this ion implantation is preferably in the range of 1 ⁇ 10 20 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 , and the thickness of the layer 3 is 0.3 ⁇ m to 0.8 ⁇ m. It is preferable to be within the following range.
- Examples of the p-type impurity include boron (B) and aluminum (Al).
- the formation of the p-type semiconductor layer 14 may be performed simultaneously with the formation of the p-type well contact layer 3.
- each of the n-type and p-type impurities implanted so far is activated.
- This is a process of electrically activating implanted ions by annealing a wafer at a high temperature using a heat treatment apparatus.
- the n-type channel epitaxial layer may be formed by depositing n-type SiC by an epitaxial crystal growth method and patterning with a resist (not shown) as a mask.
- the impurity doped in the n-type channel epitaxial layer is nitrogen, the concentration of nitrogen is in the range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 , and the thickness of the n-type channel epitaxial layer is It is preferable that it exists in the range of 0.3 micrometer or more and 0.6 micrometer or less. Note that phosphorus may be doped instead of nitrogen.
- an insulating film such as a TEOS film is formed, and the insulating film is patterned to extend from the p-type well layer 1OM beyond the JTE layer 13 to the outer periphery as shown in FIG.
- the existing field oxide film 12 is formed.
- the upper surface of the n-type drift layer 4 is oxidized by a thermal oxidation method to form an insulating film 6A such as a SiO 2 film over the entire surface of the wafer.
- an insulating film 6A such as a SiO 2 film
- a p-type polysilicon film 7A is deposited on the entire surface of the wafer by CVD.
- the p-type polysilicon film 7A and the insulating film 6A are patterned to form the gate insulating film 6 and the gate electrode polysilicon layer 7 thereon in the MOSFET cell region, as shown in FIG. In this patterning, the p-type polysilicon film 7A extending beyond the JTE layer 13 to the outer periphery is also removed.
- an insulating film such as a TEOS film is formed, and the insulating film is patterned to form an interlayer insulating film 8 shown in FIG.
- the interlayer insulating film 8 covers the gate insulating film 6 and the polysilicon layer 7 for the gate electrode, and is for the gate electrode above the p-type well contact layer 3, a part of the p-type semiconductor layer 14 and the p-type semiconductor layer 14.
- the upper part of the polysilicon layer 7 is patterned to be an opening.
- the nickel layer is silicided and a NiSi layer 9 is formed on the p-type well contact layer 3 and on the p-type semiconductor layer 14 exposed at the bottom of the opening, as shown in FIG.
- a drain electrode 17 is formed on the back surface of the n-type semiconductor substrate 5.
- the potential difference distribution between the p-type well layer 1 (1OM) and the gate electrode pad portion (gate electrode) 11 is numerically calculated assuming that the fluctuation dV / dt of the drain voltage with respect to time t is 600 V / 20 nsec.
- the maximum value of the SiC-MOSFET manufactured by the conventional method was 120 V or more, but the maximum value of the SiC-MOSFET manufactured by the manufacturing method of the present embodiment was 55 V or less.
- the p-type semiconductor layer 14 is formed in the upper layer portion of the p-type well layer 1OM, and thus is similarly formed in the upper layer portion of the p-type well layer 1OM.
- the p-type well contact layer 3 and the p-type semiconductor layer 14 may be integrated.
- FIG. 34 shows such a configuration. As shown in FIG. 34, the p-type semiconductor layer 14 extends to the vicinity of the MOSFET cell region, and the edge thereof is connected to the source electrode 10.
- the p-type semiconductor layer 14 is disposed entirely or partially on the upper surface of the outermost p-type well layer 1 (corresponding to 1OM). However, as an example of partial arrangement, it may be arranged in a comb shape.
- the p-type semiconductor layer 14 is arranged in a comb shape will be described with reference to FIGS.
- FIG. 35 is a partial plan view when the configuration above n-type drift layer 4 is omitted.
- P-type well layers 1 and 1OM formed in the upper layer portion of n-type drift layer 4 and p-type well layer 1 are shown.
- the p-type well layer 1 has a quadrangular planar shape, and a configuration in which the n-type contact layer 2 and the p-type well contact layer 3 are formed concentrically on the surface thereof has a gap in the surface of the n-type drift layer 4.
- a plurality of the arrays are formed in parallel.
- this arrangement is referred to as an arrangement of the p-type well contact layer 3.
- the p-type semiconductor layer 14 formed in a comb-teeth shape extends in the direction opposite to the arrangement along the direction of the arrangement of the p-type well contact layers 3 to form a plurality of comb teeth. Yes. Note that the p-type semiconductor layer 14 extends along the arrangement direction of the comb teeth so as to connect the arrangement of the comb teeth at one end of the comb teeth.
- FIG. 36 is a partial plan view showing the polysilicon layer 7 for the gate electrode, and a rectangular opening OP for exposing the p-type well contact layer 3 is provided in accordance with the position where the p-type well contact layer 3 is formed. It has been. Also, a plurality of similar openings OP are provided at intervals at positions corresponding to the p-type well contact layer 3 provided in the p-type well layer 1OM.
- FIGS. 37, 38 and 39 Cross-sectional views taken along lines a-a ', b-b' and c-c 'shown in FIGS. 35 and 36 are shown in FIGS. 37, 38 and 39, respectively. Further, the position of the A-A ′ line shown in FIGS. 35 and 36 corresponds to the position of the line L shown in FIGS. 37 to 39.
- an electric field concentration region is formed at the junction surface between the p-type well layer 1OM and the p-type semiconductor layer 14. That is, in FIG. 35, the corner portion CN exists at a portion corresponding to the space between the comb teeth, so that an electric field concentration region is formed on the joint surface near the corner portion CN. As a result, the injection of holes from the p-type semiconductor layer 14 to the p-type well layer 1OM is promoted.
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Abstract
Description
従来法により作製されたSiC-MOSFETにおいては、スイッチング速度を上げていくと、ゲートパッド部下方乃至はゲートフィンガー部下方に位置するp型ウエル層1の電圧分布が大きくなり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態の製造方法により作製されたSiC-MOSFETでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、ゲート電極用パッド部11の下方に位置するp型ウエル層1(1OM)内を変位電流が流れる際の電圧降下による当該p型ウエル層1(1OM)の電圧分布が抑制乃至は低減されることがわかる。
従来法により作製されたSiC-IGBTにおいては、スイッチング速度を上げていくと、電圧降下による最外周のp型ウエル層の電圧分布が100V以上になり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態により作製されたSiC-IGBTでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、電圧降下による最外周のp型ウエル層1OMの電圧分布が抑えられることがわかる。この条件下でのp型ウエル層1OMとゲート電極用パッド部11間の電位差分布を、数値計算により見積もったところ、従来法で作製されるSiC-IGBTでは最大値が100V以上であったが、本実施の形態により作製されるSiC-IGBTでは最大値が50V以下であった。
以上説明した本発明に係る実施の形態1および2においては、最外周のp型ウエル層1(1OMに相当)の上面上に、全面的または部分的にp型半導体層14が配設されているという説明を行ったが、部分的に配設する例としては、櫛歯状に配設しても良い。以下、図20~図26を用いて、p型半導体層14を櫛歯状に配設する例を説明する。
従来法により作製されたSiC-MOSFETにおいては、スイッチング速度を上げていくと、ゲートパッド部下方乃至はゲートフィンガー部下方に位置するp型ウエル層1の電圧分布が大きくなり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態の製造方法により作製されたSiC-MOSFETでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、ゲート電極用パッド部11の下方に位置するp型ウエル層1(1OM)内を変位電流が流れる際の電圧降下による当該p型ウエル層1(1OM)の電圧分布が抑制乃至は低減されることがわかる。
以上、本発明の実施の形態を詳細に開示し記述したが、以上の記述は本発明の適用可能な局面を例示したものであって、本発明はこれに限定されるものではない。すなわち、記述した局面に対する様々な修正や変形例を、この発明の範囲から逸脱することの無い範囲内で考えることが可能である。
以上説明した実施の形態3のn型チャネルSiC―MOSFETは、p型半導体層14をp型ウエル層1OMの上層部内に形成するので、同じようにp型ウエル層1OMの上層部内に形成されたp型ウエルコンタクト層3とp型半導体層14とを一体化しても良い。
以上説明した実施の形態3のn型チャネルSiC―MOSFETにおいては、最外周のp型ウエル層1(1OMに相当)の上面上に、全面的または部分的にp型半導体層14が配設されているという説明を行ったが、部分的に配設する例としては、櫛歯状に配設しても良い。以下、図35~図39を用いて、p型半導体層14を櫛歯状に配設する例を説明する。
Claims (9)
- 炭化珪素半導体基板(5)と、
前記炭化珪素半導体基板の主面上に配設された第1導電型のドリフト層(4)と、
前記ドリフト層の上面より前記ドリフト層の内部にまで配設された第2導電型のウエル層(1,1OM)と、
前記ウエル層の上面上に配設された前記第2導電型の半導体層(14)とを、備えたことを特徴とする、炭化珪素半導体装置。 - 請求項1記載の炭化珪素半導体装置であって、
前記ウエル層は、
それぞれが半導体素子として動作するセルが複数形成されたセル領域に配設される第1のウエル層(1)と、前記セル領域の周縁部に配設される第2のウエル層(1OM)とを含み、
前記半導体層は、前記第2のウエル層上に配設されることを特徴とする、炭化珪素半導体装置。 - 請求項2記載の炭化珪素半導体装置であって、
ゲート電極用パッド部(11)が、前記第2のウエル層および前記半導体層の直上に配設されていることを特徴とする、炭化珪素半導体装置。 - 請求項1乃至3の何れかに記載の炭化珪素半導体装置であって、
前記半導体層は、Si、GaAs、GaP、InP、InAs、ZnS、ZnSe、CdS、SiGe、GaN、AlN、BN若しくはダイヤモンド、の単結晶、多結晶あるいはアモルファス半導体、またはこれらの混合物で構成されることを特徴とする、炭化珪素半導体装置。 - 請求項1乃至3の何れかに記載の炭化珪素半導体装置であって、
前記半導体層は、第2導電型の炭化珪素で構成されることを特徴とする、炭化珪素半導体装置。 - 請求項1乃至3の何れかに記載の炭化珪素半導体装置であって、
前記半導体層は、前記第2のウエル層の上に部分的に形成されたことを特徴とする、炭化珪素半導体装置。 - 請求項6に記載の炭化珪素半導体装置であって、
前記半導体層は、前記第2のウエル層上に平面視形状が櫛歯状に形成されたことを特徴とする、炭化珪素半導体装置。 - 炭化珪素半導体基板(5)と、
前記炭化珪素半導体基板の主面上に配設された第1導電型のドリフト層(4)と、
前記ドリフト層の上面より前記ドリフト層の内部にまで配設された第2導電型のウエル層(1,1OM)と、
前記ウエル層の上層部に配設された前記第2導電型の半導体層(14)とを、備えたことを特徴とする、炭化珪素半導体装置。 - 請求項8記載の炭化珪素半導体装置であって、
前記ウエル層は、
それぞれが半導体素子として動作するセルが複数形成されたセル領域に配設される第1のウエル層(1)と、前記セル領域の周縁部に配設される第2のウエル層(1OM)とを含み、
前記半導体層は、前記第2のウエル層の上層部に配設されることを特徴とする、炭化珪素半導体装置。
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JP2011501583A JP5528424B2 (ja) | 2009-02-24 | 2010-02-23 | 炭化珪素半導体装置 |
DE112010000882.5T DE112010000882B4 (de) | 2009-02-24 | 2010-02-23 | Siliziumkarbid-Halbleitervorrichtung |
US14/245,539 US10418444B2 (en) | 2009-02-24 | 2014-04-04 | Silicon carbide semiconductor device |
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US14/245,539 Division US10418444B2 (en) | 2009-02-24 | 2014-04-04 | Silicon carbide semiconductor device |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04229661A (ja) * | 1990-06-08 | 1992-08-19 | Nippondenso Co Ltd | 絶縁ゲート型バイポーラトランジスタおよびその製造方法 |
JPH05198816A (ja) * | 1991-09-27 | 1993-08-06 | Nec Corp | 半導体装置 |
JP2002076337A (ja) * | 2000-09-01 | 2002-03-15 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
JP2003023158A (ja) * | 2001-07-06 | 2003-01-24 | Toshiba Corp | 高耐圧半導体装置 |
WO2006123458A1 (ja) * | 2005-05-19 | 2006-11-23 | Mitsubishi Denki Kabushiki Kaisha | 半導体装置及びその製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0541523A (ja) | 1991-08-05 | 1993-02-19 | Oki Electric Ind Co Ltd | 半導体装置 |
US5686750A (en) | 1991-09-27 | 1997-11-11 | Koshiba & Partners | Power semiconductor device having improved reverse recovery voltage |
JPH05160407A (ja) * | 1991-12-09 | 1993-06-25 | Nippondenso Co Ltd | 縦型絶縁ゲート型半導体装置およびその製造方法 |
JPH08102495A (ja) | 1994-09-30 | 1996-04-16 | Toshiba Corp | 半導体装置 |
JP3559971B2 (ja) | 2001-12-11 | 2004-09-02 | 日産自動車株式会社 | 炭化珪素半導体装置およびその製造方法 |
DE10217610B4 (de) * | 2002-04-19 | 2005-11-03 | Infineon Technologies Ag | Metall-Halbleiter-Kontakt, Halbleiterbauelement, integrierte Schaltungsanordnung und Verfahren |
JP3637330B2 (ja) * | 2002-05-16 | 2005-04-13 | 株式会社東芝 | 半導体装置 |
US7071537B2 (en) * | 2002-05-17 | 2006-07-04 | Ixys Corporation | Power device having electrodes on a top surface thereof |
US7221010B2 (en) * | 2002-12-20 | 2007-05-22 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
JP4432332B2 (ja) | 2003-03-06 | 2010-03-17 | サンケン電気株式会社 | 半導体素子及びその製造方法 |
WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
EP1935019A1 (en) * | 2005-10-12 | 2008-06-25 | Spinnaker Semiconductor, Inc. | A cmos device with zero soft error rate |
JP2008112857A (ja) * | 2006-10-30 | 2008-05-15 | Nec Electronics Corp | 半導体集積回路装置 |
JP4367508B2 (ja) * | 2007-03-13 | 2009-11-18 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP4286877B2 (ja) * | 2007-03-13 | 2009-07-01 | Okiセミコンダクタ株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP4793293B2 (ja) | 2007-03-16 | 2011-10-12 | 日産自動車株式会社 | 炭化珪素半導体装置及びその製造方法 |
WO2010098294A1 (ja) * | 2009-02-24 | 2010-09-02 | 三菱電機株式会社 | 炭化珪素半導体装置 |
-
2010
- 2010-02-23 WO PCT/JP2010/052667 patent/WO2010098294A1/ja active Application Filing
- 2010-02-23 DE DE112010000882.5T patent/DE112010000882B4/de active Active
- 2010-02-23 US US13/146,812 patent/US8723259B2/en active Active
- 2010-02-23 JP JP2011501583A patent/JP5528424B2/ja active Active
-
2014
- 2014-04-04 US US14/245,539 patent/US10418444B2/en active Active
- 2014-04-15 JP JP2014083483A patent/JP5781191B2/ja active Active
-
2019
- 2019-07-30 US US16/525,820 patent/US10886372B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04229661A (ja) * | 1990-06-08 | 1992-08-19 | Nippondenso Co Ltd | 絶縁ゲート型バイポーラトランジスタおよびその製造方法 |
JPH05198816A (ja) * | 1991-09-27 | 1993-08-06 | Nec Corp | 半導体装置 |
JP2002076337A (ja) * | 2000-09-01 | 2002-03-15 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
JP2003023158A (ja) * | 2001-07-06 | 2003-01-24 | Toshiba Corp | 高耐圧半導体装置 |
WO2006123458A1 (ja) * | 2005-05-19 | 2006-11-23 | Mitsubishi Denki Kabushiki Kaisha | 半導体装置及びその製造方法 |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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WO2014083942A1 (ja) | 2012-11-28 | 2014-06-05 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2014107419A (ja) * | 2012-11-28 | 2014-06-09 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置およびその製造方法 |
US9450060B2 (en) | 2012-11-28 | 2016-09-20 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a silicon carbide semiconductor device |
US9716157B2 (en) | 2012-11-28 | 2017-07-25 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
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WO2015049923A1 (ja) * | 2013-10-04 | 2015-04-09 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
US9543429B2 (en) | 2013-10-04 | 2017-01-10 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
WO2015193965A1 (ja) * | 2014-06-17 | 2015-12-23 | 株式会社日立製作所 | 半導体装置、パワーモジュール、電力変換装置、鉄道車両、および半導体装置の製造方法 |
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US10707341B2 (en) | 2016-08-25 | 2020-07-07 | Mitsubishi Electric Corporation | Semiconductor device |
DE112017004237T5 (de) | 2016-08-25 | 2019-05-09 | Mitsubishi Electric Corporation | Halbleitereinheit |
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JP2021005740A (ja) * | 2016-12-28 | 2021-01-14 | 3−5 パワー エレクトロニクス ゲゼルシャフト ミット ベシュレンクテル ハフツング3−5 Power Electronics GmbH | Igbt半導体構造 |
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JP2018110231A (ja) * | 2016-12-28 | 2018-07-12 | 3−5 パワー エレクトロニクス ゲゼルシャフト ミット ベシュレンクテル ハフツング3−5 Power Electronics GmbH | Igbt半導体構造 |
US11171226B2 (en) | 2016-12-28 | 2021-11-09 | 3-5 Power Electronics GmbH | GaAS based IGBT semiconductor structure |
WO2018155566A1 (ja) * | 2017-02-24 | 2018-08-30 | 三菱電機株式会社 | 炭化珪素半導体装置および電力変換装置 |
US10991822B2 (en) | 2017-02-24 | 2021-04-27 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device having a conductive layer formed above a bottom surface of a well region so as not to be in ohmic connection with the well region and power converter including the same |
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JP2019197914A (ja) * | 2019-07-18 | 2019-11-14 | 三菱電機株式会社 | 半導体装置 |
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Also Published As
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JP5528424B2 (ja) | 2014-06-25 |
US20140299888A1 (en) | 2014-10-09 |
JP5781191B2 (ja) | 2015-09-16 |
US10418444B2 (en) | 2019-09-17 |
US20190355821A1 (en) | 2019-11-21 |
DE112010000882T5 (de) | 2012-06-14 |
US10886372B2 (en) | 2021-01-05 |
JPWO2010098294A1 (ja) | 2012-08-30 |
US8723259B2 (en) | 2014-05-13 |
JP2014150279A (ja) | 2014-08-21 |
US20110278599A1 (en) | 2011-11-17 |
DE112010000882B4 (de) | 2015-03-19 |
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