WO2010093158A3 - 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 - Google Patents
지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 Download PDFInfo
- Publication number
- WO2010093158A3 WO2010093158A3 PCT/KR2010/000780 KR2010000780W WO2010093158A3 WO 2010093158 A3 WO2010093158 A3 WO 2010093158A3 KR 2010000780 W KR2010000780 W KR 2010000780W WO 2010093158 A3 WO2010093158 A3 WO 2010093158A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- locked loop
- receiving apparatus
- recovery unit
- delay locked
- clock recovery
- Prior art date
Links
- 238000011084 recovery Methods 0.000 title abstract 3
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201080001351.4A CN101999144B (zh) | 2009-02-13 | 2010-02-09 | 基于延迟锁定回路具有时钟回复单元的接收器 |
JP2010550615A JP5579625B2 (ja) | 2009-02-13 | 2010-02-09 | 遅延同期ループを基礎としたクロック復元部が具備された受信部装置 |
US12/920,550 US8611484B2 (en) | 2009-02-13 | 2010-02-09 | Receiver having clock recovery unit based on delay locked loop |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2009-0011727 | 2009-02-13 | ||
KR1020090011727A KR101169210B1 (ko) | 2009-02-13 | 2009-02-13 | 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010093158A2 WO2010093158A2 (ko) | 2010-08-19 |
WO2010093158A3 true WO2010093158A3 (ko) | 2010-10-28 |
Family
ID=42562171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2010/000780 WO2010093158A2 (ko) | 2009-02-13 | 2010-02-09 | 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8611484B2 (ko) |
JP (1) | JP5579625B2 (ko) |
KR (1) | KR101169210B1 (ko) |
CN (1) | CN101999144B (ko) |
TW (1) | TWI452838B (ko) |
WO (1) | WO2010093158A2 (ko) |
Families Citing this family (25)
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KR101125504B1 (ko) * | 2010-04-05 | 2012-03-21 | 주식회사 실리콘웍스 | 클럭 신호가 임베딩된 단일 레벨의 데이터 전송을 이용한 디스플레이 구동 시스템 |
KR101681782B1 (ko) * | 2010-09-02 | 2016-12-02 | 엘지디스플레이 주식회사 | 액정표시장치 |
CN102769430B (zh) * | 2011-05-04 | 2015-03-18 | 智原科技股份有限公司 | 时钟产生方法、无参考频率接收器以及无晶体振荡器系统 |
KR101978937B1 (ko) * | 2012-03-16 | 2019-05-15 | 주식회사 실리콘웍스 | 전원 잡음에 둔감한 표시장치용 소스 드라이버 |
US8797075B2 (en) * | 2012-06-25 | 2014-08-05 | Intel Corporation | Low power oversampling with reduced-architecture delay locked loop |
US8779815B2 (en) | 2012-06-25 | 2014-07-15 | Intel Corporation | Low power oversampling with delay locked loop implementation |
KR101327221B1 (ko) * | 2012-07-06 | 2013-11-11 | 주식회사 실리콘웍스 | 클럭생성기, 데이터 수신부 및 마스터 클럭신호 복원방법 |
TWI567705B (zh) * | 2012-12-27 | 2017-01-21 | 天鈺科技股份有限公司 | 顯示裝置及其驅動方法、時序控制電路的資料處理及輸出方法 |
US9881579B2 (en) * | 2013-03-26 | 2018-01-30 | Silicon Works Co., Ltd. | Low noise sensitivity source driver for display apparatus |
KR102112089B1 (ko) * | 2013-10-16 | 2020-06-04 | 엘지디스플레이 주식회사 | 표시장치와 그 구동 방법 |
TWI547102B (zh) | 2014-08-08 | 2016-08-21 | 瑞昱半導體股份有限公司 | 多通道時序回復裝置 |
JP6468763B2 (ja) * | 2014-09-08 | 2019-02-13 | ラピスセミコンダクタ株式会社 | データ処理装置 |
KR102167139B1 (ko) * | 2014-09-17 | 2020-10-19 | 엘지디스플레이 주식회사 | 표시장치 |
KR102303914B1 (ko) * | 2015-03-06 | 2021-09-17 | 주식회사 실리콘웍스 | 디스플레이 신호 전송 장치 및 방법 |
JP6883377B2 (ja) * | 2015-03-31 | 2021-06-09 | シナプティクス・ジャパン合同会社 | 表示ドライバ、表示装置及び表示ドライバの動作方法 |
KR102366952B1 (ko) | 2015-07-14 | 2022-02-23 | 주식회사 엘엑스세미콘 | 지연고정루프 기반의 클럭 복원 장치 및 이를 구비한 수신 장치 |
KR102273191B1 (ko) * | 2017-09-08 | 2021-07-06 | 삼성전자주식회사 | 스토리지 장치 및 그것의 데이터 트레이닝 방법 |
KR101930532B1 (ko) | 2017-09-26 | 2018-12-19 | 주식회사 티엘아이 | 능동적이며 안정적으로 클락 데이터를 복원하는 클락 복원 회로 |
KR102518935B1 (ko) * | 2018-07-03 | 2023-04-17 | 주식회사 엘엑스세미콘 | 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버 |
KR102507862B1 (ko) * | 2018-07-09 | 2023-03-08 | 주식회사 엘엑스세미콘 | 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버 |
JP7224831B2 (ja) * | 2018-09-28 | 2023-02-20 | キヤノン株式会社 | 撮像装置 |
KR102621926B1 (ko) * | 2018-11-05 | 2024-01-08 | 주식회사 엘엑스세미콘 | 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버 |
KR20220087752A (ko) * | 2020-12-18 | 2022-06-27 | 주식회사 엘엑스세미콘 | 데이터 구동 회로 및 그의 클럭 복원 방법과 디스플레이 장치 |
CN113886300B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种总线接口的时钟数据自适应恢复系统及芯片 |
CN116343637A (zh) * | 2023-03-17 | 2023-06-27 | 惠科股份有限公司 | 驱动电路、驱动方法和显示装置 |
Citations (5)
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KR19980058222A (ko) * | 1996-12-30 | 1998-09-25 | 구자홍 | 데이타 통신장치의 클럭주파수 및 위상 복원회로 |
KR20030052667A (ko) * | 2001-12-21 | 2003-06-27 | 주식회사 하이닉스반도체 | 지연 고정 루프 회로 |
KR20080011834A (ko) * | 2006-07-31 | 2008-02-11 | 삼성전자주식회사 | 지연 동기 루프 회로 및 클럭 신호 발생 방법 |
JP2008072597A (ja) * | 2006-09-15 | 2008-03-27 | Ricoh Co Ltd | 遅延ロックループ回路 |
KR20080066327A (ko) * | 2007-01-12 | 2008-07-16 | 삼성전자주식회사 | 클럭 임베디드 신호를 이용한 직렬 통신 방법 및 장치 |
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KR100986041B1 (ko) | 2008-10-20 | 2010-10-07 | 주식회사 실리콘웍스 | 클럭 신호가 임베딩된 단일 레벨 신호 전송을 이용한 디스플레이 구동 시스템 |
-
2009
- 2009-02-13 KR KR1020090011727A patent/KR101169210B1/ko active IP Right Grant
-
2010
- 2010-01-28 TW TW099102481A patent/TWI452838B/zh active
- 2010-02-09 US US12/920,550 patent/US8611484B2/en active Active
- 2010-02-09 CN CN201080001351.4A patent/CN101999144B/zh active Active
- 2010-02-09 JP JP2010550615A patent/JP5579625B2/ja active Active
- 2010-02-09 WO PCT/KR2010/000780 patent/WO2010093158A2/ko active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR19980058222A (ko) * | 1996-12-30 | 1998-09-25 | 구자홍 | 데이타 통신장치의 클럭주파수 및 위상 복원회로 |
KR20030052667A (ko) * | 2001-12-21 | 2003-06-27 | 주식회사 하이닉스반도체 | 지연 고정 루프 회로 |
KR20080011834A (ko) * | 2006-07-31 | 2008-02-11 | 삼성전자주식회사 | 지연 동기 루프 회로 및 클럭 신호 발생 방법 |
JP2008072597A (ja) * | 2006-09-15 | 2008-03-27 | Ricoh Co Ltd | 遅延ロックループ回路 |
KR20080066327A (ko) * | 2007-01-12 | 2008-07-16 | 삼성전자주식회사 | 클럭 임베디드 신호를 이용한 직렬 통신 방법 및 장치 |
Also Published As
Publication number | Publication date |
---|---|
TW201115925A (en) | 2011-05-01 |
CN101999144B (zh) | 2014-05-28 |
KR101169210B1 (ko) | 2012-07-27 |
WO2010093158A2 (ko) | 2010-08-19 |
JP5579625B2 (ja) | 2014-08-27 |
JP2011514560A (ja) | 2011-05-06 |
US8611484B2 (en) | 2013-12-17 |
CN101999144A (zh) | 2011-03-30 |
US20110286562A1 (en) | 2011-11-24 |
TWI452838B (zh) | 2014-09-11 |
KR20100092562A (ko) | 2010-08-23 |
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