WO2010093158A3 - 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 - Google Patents

지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 Download PDF

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Publication number
WO2010093158A3
WO2010093158A3 PCT/KR2010/000780 KR2010000780W WO2010093158A3 WO 2010093158 A3 WO2010093158 A3 WO 2010093158A3 KR 2010000780 W KR2010000780 W KR 2010000780W WO 2010093158 A3 WO2010093158 A3 WO 2010093158A3
Authority
WO
WIPO (PCT)
Prior art keywords
locked loop
receiving apparatus
recovery unit
delay locked
clock recovery
Prior art date
Application number
PCT/KR2010/000780
Other languages
English (en)
French (fr)
Other versions
WO2010093158A2 (ko
Inventor
전현규
문용환
Original Assignee
(주)실리콘웍스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)실리콘웍스 filed Critical (주)실리콘웍스
Priority to JP2010550615A priority Critical patent/JP5579625B2/ja
Priority to US12/920,550 priority patent/US8611484B2/en
Priority to CN201080001351.4A priority patent/CN101999144B/zh
Publication of WO2010093158A2 publication Critical patent/WO2010093158A2/ko
Publication of WO2010093158A3 publication Critical patent/WO2010093158A3/ko

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery

Abstract

본 발명은 디스플레이 구동 시스템의 수신부 장치에 관한 것으로서, 보다 상세하게는 수신부에서 위상고정루프(PLL : Phase Locked Loop) 구조를 배제하여 레퍼런스 클럭(Reference clock)을 생성하기 위한 별도의 발진기 없이 지연고정루프(DLL : Delay Locked Loop) 구조만으로 구현된 클럭 복원부를 이용하여 데이터 신호 사이에 동일한 크기로 임베딩된 클럭 신호를 복원할 수 있게 한 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치에 관한 것이다.
PCT/KR2010/000780 2009-02-13 2010-02-09 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치 WO2010093158A2 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010550615A JP5579625B2 (ja) 2009-02-13 2010-02-09 遅延同期ループを基礎としたクロック復元部が具備された受信部装置
US12/920,550 US8611484B2 (en) 2009-02-13 2010-02-09 Receiver having clock recovery unit based on delay locked loop
CN201080001351.4A CN101999144B (zh) 2009-02-13 2010-02-09 基于延迟锁定回路具有时钟回复单元的接收器

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090011727A KR101169210B1 (ko) 2009-02-13 2009-02-13 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치
KR10-2009-0011727 2009-02-13

Publications (2)

Publication Number Publication Date
WO2010093158A2 WO2010093158A2 (ko) 2010-08-19
WO2010093158A3 true WO2010093158A3 (ko) 2010-10-28

Family

ID=42562171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/000780 WO2010093158A2 (ko) 2009-02-13 2010-02-09 지연고정루프 기반의 클럭 복원부가 구비된 수신부 장치

Country Status (6)

Country Link
US (1) US8611484B2 (ko)
JP (1) JP5579625B2 (ko)
KR (1) KR101169210B1 (ko)
CN (1) CN101999144B (ko)
TW (1) TWI452838B (ko)
WO (1) WO2010093158A2 (ko)

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KR101681782B1 (ko) * 2010-09-02 2016-12-02 엘지디스플레이 주식회사 액정표시장치
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KR102112089B1 (ko) * 2013-10-16 2020-06-04 엘지디스플레이 주식회사 표시장치와 그 구동 방법
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KR102167139B1 (ko) * 2014-09-17 2020-10-19 엘지디스플레이 주식회사 표시장치
KR102303914B1 (ko) * 2015-03-06 2021-09-17 주식회사 실리콘웍스 디스플레이 신호 전송 장치 및 방법
JP6883377B2 (ja) * 2015-03-31 2021-06-09 シナプティクス・ジャパン合同会社 表示ドライバ、表示装置及び表示ドライバの動作方法
KR102366952B1 (ko) 2015-07-14 2022-02-23 주식회사 엘엑스세미콘 지연고정루프 기반의 클럭 복원 장치 및 이를 구비한 수신 장치
KR102273191B1 (ko) * 2017-09-08 2021-07-06 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
KR101930532B1 (ko) 2017-09-26 2018-12-19 주식회사 티엘아이 능동적이며 안정적으로 클락 데이터를 복원하는 클락 복원 회로
KR102518935B1 (ko) * 2018-07-03 2023-04-17 주식회사 엘엑스세미콘 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버
KR102507862B1 (ko) * 2018-07-09 2023-03-08 주식회사 엘엑스세미콘 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버
JP7224831B2 (ja) * 2018-09-28 2023-02-20 キヤノン株式会社 撮像装置
KR102621926B1 (ko) * 2018-11-05 2024-01-08 주식회사 엘엑스세미콘 인터페이스신호에서 임베디드클럭을 복원하는 클럭복원장치 및 소스드라이버
KR20220087752A (ko) * 2020-12-18 2022-06-27 주식회사 엘엑스세미콘 데이터 구동 회로 및 그의 클럭 복원 방법과 디스플레이 장치
CN113886300A (zh) * 2021-09-23 2022-01-04 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片

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Also Published As

Publication number Publication date
TWI452838B (zh) 2014-09-11
CN101999144A (zh) 2011-03-30
US20110286562A1 (en) 2011-11-24
KR20100092562A (ko) 2010-08-23
KR101169210B1 (ko) 2012-07-27
CN101999144B (zh) 2014-05-28
WO2010093158A2 (ko) 2010-08-19
JP5579625B2 (ja) 2014-08-27
US8611484B2 (en) 2013-12-17
TW201115925A (en) 2011-05-01
JP2011514560A (ja) 2011-05-06

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