WO2010070826A1 - 貫通電極の形成方法及び半導体装置 - Google Patents
貫通電極の形成方法及び半導体装置 Download PDFInfo
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Abstract
Description
前記電極に向けて他方の面から前記層間絶縁膜まで通じる貫通穴を前記半導体基板に形成する第1工程と、
前記貫通穴の側面及び底面並びに前記他方の面に絶縁膜を形成する第2工程と、
前記底面に形成された前記絶縁膜と前記電極上の前記層間絶縁膜とをエッチング加工することで前記電極のうち一方の面側の表面を露出させる第3工程と、
前記半導体基板の前記他方の面、並びに、前記貫通穴の側面及び底面に金属層をそれぞれ形成して前記貫通電極を形成し、前記貫通電極により、前記第3工程で露出させた前記電極と前記金属層とを接続させる第4工程と、
を備える貫通電極の形成方法を提供する。
(B+C)/A<E/D
であることを特徴とする第1の態様に記載の貫通電極の形成方法を提供する。
前記貫通電極と前記半導体基板との間でかつ前記貫通穴内に配置されて前記貫通電極と前記半導体基板とを絶縁する絶縁膜と、
前記一方の面に配置されて前記電極と前記半導体基板とを絶縁し、かつ、前記貫通電極に接触する層間絶縁膜とを備える、ことを特徴とする半導体装置を提供する。
まず、第1工程S1(図2参照)は、図4A,図4B,図4Cにそれぞれ示す3工程で構成されている。
その後、図4Dに示すように、第2工程S2(図2参照)で、貫通穴6内の底面及び側面、並びに、半導体基板1の貫通穴6の開口側の表面(半導体基板1の反対側の面(他方の面)1b)に、CVDにより絶縁膜4をそれぞれ形成する。一例として、貫通穴6の開口側の表面1bの絶縁膜4(図4Dの4a参照)の厚さは3μm、貫通穴6の底面の絶縁膜4(図4Dの4b参照)の厚さは0.2μmである。通常、前記CVD処理では、貫通穴6内にTEOS(Tetraethoxysilane)のラジカルが到達する確率が低くなるので、図5Aに示すように、貫通穴6内の底面の絶縁膜4(図5Aの4b参照)の厚さよりも、半導体基板1の貫通穴6の開口側の表面1bの絶縁膜4(図5Aの4a参照)の厚さのほうが厚くなるように堆積させる。そのため、貫通穴6内の開口側の表面1bの付近の貫通穴6の側面に付着する絶縁膜4(図5Aの4c参照)の厚さは、半導体基板1の貫通穴6の開口側の表面1bの絶縁膜4(図5Aの4a参照)の厚さとほぼ同等であり、貫通穴6の開口側の表面1bから貫通穴6の底面にかけて徐々に少なくなる。そして、貫通穴6の底面付近の側面に付着する絶縁膜4(図5Aの4c参照)の厚さは、貫通穴6の底面に付着する絶縁膜4(図5Aの4b参照)の厚さとほぼ同じになる。なお、図19Dは、概略図示であって、この説明とは寸法的には異なって図示されている。
次いで、図4Eに示すように、第3工程S3(図2参照)で、貫通穴6の側面の絶縁膜4(図4Eの4c参照)をエッチングしないように、貫通穴6の底面の絶縁膜4(図4Dの4b参照)の部分(一例として、厚さ0.2μmの部分)の全て及び半導体基板1の貫通穴6の開口側の表面1bの絶縁膜4(図4Dの4a参照)の一部をドライエッチングにより除去し、貫通穴6の底面においてパッド電極5の下面側のチタンを露出させる。すなわち、半導体基板1に形成された貫通穴6の底面からパッド電極5までに存在する、貫通穴6の底面の絶縁膜4(図4Dの4b参照)と層間絶縁膜2とを同時にエッチング加工する。これにより、半導体基板1に形成された貫通穴6の底面からパッド電極5までの絶縁膜4bと層間絶縁膜2とをエッチングで除去することにより、貫通穴6をさらに層間絶縁膜2内にまで延ばし、半導体基板1の前記一方の面1aの前記電極5を前記貫通穴6の前記底面に露出させる。通常、平行平板型ドライエッチング装置を用いた場合、ドライエッチング装置の真空容器内の圧力が高いため、平均自由行程が短く、イオン又はラジカルの衝突が頻繁に発生するため、絶縁膜4及び層間絶縁膜2のエッチングに寄与するイオン及びラジカルが貫通穴6内に到達することが困難である。そのため、貫通穴6内の底面の絶縁膜4及び層間絶縁膜2のエッチングレートが、貫通穴6の開口側の表面1bの絶縁膜4(図4Dの4a参照)のエッチングレートよりも著しく低くなり、貫通穴6内の底面の絶縁膜4及び層間絶縁膜2をエッチング除去する前に、表面1bの絶縁膜4がなくなってしまう。
言い換えれば、この関係式が成立するように、パッド電極5の下の層間絶縁膜2の厚さCと、第2工程S2のCVDの半導体基板1の他方の面1bの絶縁膜4(図4Dの4a参照)の厚さA及び貫通穴6の底面の絶縁膜4(図4Dの4b参照)の厚さBと、第3工程S3のドライエッチング工程における半導体基板1の他方の面1bの絶縁膜4(図4Dの4a参照)のエッチング速度D及び貫通穴6の底面の絶縁膜4(図4Dの4b参照)と前記層間絶縁膜2の厚さCとのエッチング速度Eを設定する。前記式1を満たした厚さ及びドライエッチング条件で加工することによって、図5Bに示すような断面構造の貫通穴6及び絶縁膜4を得ることができる。
E/D=300nm/分/400nm/分=0.75
0.4<0.75
これにより、この実施例では、式1が成立している。
次いで、第3工程S3に続く第4工程S4(図2参照)では、スパッタ法により金属膜を貫通穴6の内部に付着させるため、まず、第5工程S5のめっきのためのシード層32を形成する(図4F参照)。一例として、貫通電極3の電極材料として銅を用いるため、銅のシード層32を形成する。また、シード層32の密着層31の一例としてチタンを用いることができる。貫通穴6の底面に付着するチタンの密着層31の厚さの一例としては50nm程度である。よって、チタンより構成する密着層31を、まず、貫通穴6の側面及び底面及び貫通穴6の開口側の半導体基板1の他方の面1bにスパッタ法により形成する。その後、密着層31の上にシード層32をスパッタ法により形成する。
次いで、第5工程S5(図2参照)で、前記チタンの密着層31及び銅のシード層32にそれぞれ電流を流すことによって、銅の電解めっきを行い、貫通穴6の内部及び他方の面1bに銅を成長させて、銅の導電層32aを形成する(図4Gの32a参照)。この結果、半導体基板1の他方の面1bに金属層31,32,32aを形成するとともに、貫通穴6の側面及び底面とに金属層31,32,32aを形成して貫通電極3を形成し、貫通電極3により、第3工程S3で露出させた半導体基板1の一方の面1aの電極5と半導体基板1の他方の面1bの金属層31,32,32aとを接続させる。
次いで、第6工程S6(図2参照)で、半導体基板1の反対側の面1bに形成された銅の導電層32aに対して回路形成を行うためのレジストマスク33を形成する。すなわち、銅の導電層32aにレジストマスク33を全面に塗布したのち(図4H参照)、回路形成不要部分を露光し、現像により露光された部分を除去し、残ったレジストマスク33aをベーキングして、回路形成部分にのみレジストマスク33aを形成する(図4I参照)。その後、エッチングにより、レジストマスク33aで覆われていない部分の導電層32aを除去する(図4J参照)。
Claims (10)
- 半導体基板の一方の面に層間絶縁膜が形成されかつ前記層間絶縁膜に能動素子を含む電子回路が配置され、前記電子回路に接続されると共に前記一方の面上に設けられた電極と、前記半導体基板の他方の面側に形成された導電層とを貫通電極で接続する貫通電極の形成方法において、
前記電極に向けて他方の面から前記層間絶縁膜まで通じる貫通穴を前記半導体基板に形成する第1工程と、
前記貫通穴の側面及び底面並びに前記他方の面に絶縁膜を形成する第2工程と、
前記底面に形成された前記絶縁膜と前記電極上の前記層間絶縁膜とをエッチング加工することで前記電極のうち一方の面側の表面を露出させる第3工程と、
前記半導体基板の前記他方の面、並びに、前記貫通穴の側面及び底面に金属層をそれぞれ形成して前記貫通電極を形成し、前記貫通電極により、前記第3工程で露出させた前記電極と前記金属層とを接続させる第4工程と、
を備える貫通電極の形成方法。 - 前記第2工程において前記他方の面に形成する前記絶縁膜の厚さAと前記貫通穴の前記底面に形成する前記絶縁膜の厚さBと、前記一方の面の前記層間絶縁膜の厚さCと、前記第3工程において前記他方の面の前記絶縁膜を前記エッチングで除去するときのエッチング速度Dと、前記第2工程で形成された前記貫通穴の前記底面の前記絶縁膜と前記層間絶縁膜の厚さCをエッチングするときの平均のエッチング速度Eとの関係が、
(B+C)/A<E/D
である請求項1に記載の貫通電極の形成方法。 - 前記第1工程において、貫通穴形成時に、前記他方の面の貫通電極形成部分以外の部分を覆うレジストマスクを前記他方の面に配置し、前記レジストマスクで覆われていない前記貫通電極形成部分の前記半導体基板に前記貫通穴を形成し、その後、前記レジストマスクを前記他方の面から除去する請求項1又は2に記載の貫通電極の形成方法。
- 前記第1工程及び前記第2工程において、洗浄工程を含む請求項1又は2に記載の貫通電極の形成方法。
- 前記第3工程は、第2工程で形成した前記貫通穴の前記底面の前記絶縁膜と前記貫通穴の前記底面と前記電極との間にある前記層間絶縁膜をドライエッチングにより加工して、前記貫通穴の前記底面の前記絶縁膜と前記貫通穴の前記底面と前記電極との間にある前記層間絶縁膜とを除去して前記貫通穴をさらに前記層間絶縁膜内にまで延ばし、前記一方の面の前記電極を前記貫通穴の前記底面に露出させる請求項1又は2に記載の貫通電極の形成方法。
- 前記第2工程において、前記絶縁膜を形成するとき、熱CVD、プラズマCVD、常圧CVD、及び、TEOSCVDのうちのいずれかを使用する請求項1又は2に記載の貫通電極の形成方法。
- 前記第3工程のエッチングをドライエッチングで行うとともに、前記貫通穴の前記底面の前記絶縁膜及び前記一方の面にありかつ前記貫通穴の前記底面と前記電極との間にある前記層間絶縁膜とを前記ドライエッチングで加工するとき、高密度プラズマ源である、誘導結合プラズマ、ヘリコンプラズマ、電子サイクロトロン共鳴プラズマ、VHFプラズマ源のいずれか1つを使用してドライエッチング用のプラズマを発生させる請求項5に記載の貫通電極の形成方法。
- 前記第3工程のエッチングをドライエッチングで行うとき、前記半導体基板を配置するドライエッチング用真空容器内に導入するドライエッチング用ガス圧力が5Pa以下である請求項5に記載の貫通電極の形成方法。
- 前記請求項1又は2に記載の前記貫通電極の形成方法により形成された貫通電極を有する前記半導体基板で構成される半導体装置。
- 半導体基板の一方の面に層間絶縁膜が形成されかつ前記層間絶縁膜に能動素子を含む電子回路が配置され、前記電子回路に接続されると共に前記一方の面上に設けられた電極と、前記半導体基板の他方の面側に形成された導電層とを貫通電極で接続する半導体装置において、
前記貫通電極と前記半導体基板との間でかつ前記貫通穴内に配置されて前記貫通電極と前記半導体基板とを絶縁する絶縁膜と、
前記一方の面に配置されて前記電極と前記半導体基板とを絶縁し、かつ、前記貫通電極に接触する層間絶縁膜とを備える、半導体装置。
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CN2009801151097A CN102017099A (zh) | 2008-12-17 | 2009-12-01 | 贯通电极的形成方法及半导体装置 |
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